Diff: freq_counter.cpp

Revision:

1:fd2e1c853ab6

Parent:

0:83661d0d09c0

Child:

2:54c05b0a117a

--- a/freq_counter.cpp	Sun Oct 19 06:44:51 2014 +0000
+++ b/freq_counter.cpp	Tue Oct 21 03:44:46 2014 +0000
@@ -7,7 +7,7 @@
  *  http://mbed.org/users/kenjiArai/
  *      Addition and Modification
  *      started: October   18th, 2014
- *      Revised: October   19th, 2014
+ *      Revised: October   21st, 2014
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
@@ -33,6 +33,22 @@
     LPC_TIM2->CTCR = 1;             // 4)Count on riging edge Cap3[0]
     LPC_TIM2->CCR  = 0;             // 5)Input Capture Disabled
     LPC_TIM2->TCR  = 1;             // 6)Counter Start (bit1<=0,bit0<=1)
+#elif defined(TARGET_NUCLEO_F401RE)
+    // PA0 -> Counter frequency input pin as Timer2 TI1
+    GPIOA->AFR[0] &= 0xfffffff0;
+    GPIOA->AFR[0] |= GPIO_AF1_TIM2;
+    GPIOA->MODER &= ~(GPIO_MODER_MODER0);
+    GPIOA->MODER |= 0x2;
+    // Initialize Timer2(32bit) for an external up counter mode
+    RCC->APB1ENR |= ((uint32_t)0x00000001);
+    TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));  // count_up + div by 1
+    TIM2->ARR = 0xFFFFFFFF;
+    TIM2->PSC = 0x0000;
+    TIM2->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1F;   // input filter
+    TIM2->CCER = TIM_CCER_CC1P;     // positive edge
+    TIM2->SMCR &= (uint16_t)~(TIM_SMCR_SMS | TIM_SMCR_TS | TIM_SMCR_ECE);
+    TIM2->SMCR |= (uint16_t)(TIM_TS_TI1FP1 | TIM_SMCR_SMS); // external mode 1
+    TIM2->CR1 |= TIM_CR1_CEN;   //Enable the TIM Counter
 #else
 #error "No support for this CPU"
 #endif
@@ -46,6 +62,11 @@
     wait(gate_time);                // Gate time for count
     freq = LPC_TIM2->TC;
     return freq;
+#elif defined(TARGET_NUCLEO_F401RE)
+    TIM2->CNT = 0;
+    wait(gate_time);                // Gate time for count
+    freq = TIM2->CNT;
+    return freq;
 #else
 #error "No support for this CPU"
 #endif