Kenji Arai / fc_GPS1PPS_f746_f4xx

Frequency counter library only for DISCO-F746NG & NucleoF411RE +F446RE

Dependencies:   RingBuff

Dependents:   FreqCntr_GPS1PPS_F746F4xx_w_recipro Freq_Cntr_GPS1PPS_F746NG_GUI

Fork of Frq_cuntr_full by Kenji Arai

fc_hw_f746.h@6:be7123d400ae, 2016-11-16 (annotated)

Committer:
kenjiArai
Date:
Wed Nov 16 13:15:35 2016 +0000
Revision:
6:be7123d400ae
Parent:
5:783b039f9119 
Frequency counter library using GPS 1PPS signal

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 5:783b039f9119 1 /*
kenjiArai 5:783b039f9119 2 * mbed Library / Frequency Counter using GPS 1PPS gate pulse
kenjiArai 5:783b039f9119 3 * Frequency Counter Hardware relataed program
kenjiArai 5:783b039f9119 4 * Only for ST DISCO-F746NG
kenjiArai 5:783b039f9119 5 *
kenjiArai 5:783b039f9119 6 * Re-started: October 5th, 2016 Change board -> DISCO-F746NG
kenjiArai 5:783b039f9119 7 * Re-started: October 17th, 2016 Separate common & HW related part
kenjiArai 5:783b039f9119 8 * Revised: November 13th, 2016
kenjiArai 5:783b039f9119 9 *
kenjiArai 5:783b039f9119 10 */
kenjiArai 5:783b039f9119 11
kenjiArai 5:783b039f9119 12 #if defined(TARGET_STM32F746NG)
kenjiArai 5:783b039f9119 13
kenjiArai 5:783b039f9119 14 // Following ring buffers are very big!! 4096 x 8(bytes) x 2(buff) = 64KB
kenjiArai 5:783b039f9119 15 RingBuff<uint64_t> fdt_buffer; // RinBuffer for TIM8+4
kenjiArai 5:783b039f9119 16 freq_one fdt; // frequency data in pack (interrupt)
kenjiArai 5:783b039f9119 17 RingBuff<uint64_t> onepps_buf; // RinBuffer for TIM2
kenjiArai 5:783b039f9119 18 freq_one onepps_dt; // frequency data in pack (interrupt)
kenjiArai 5:783b039f9119 19
kenjiArai 5:783b039f9119 20 //------------------------------------------------------------------------------
kenjiArai 5:783b039f9119 21 // Initialize TIM2 and TIM8+4
kenjiArai 5:783b039f9119 22 //------------------------------------------------------------------------------
kenjiArai 5:783b039f9119 23 // Initialize TIM8 & TIM4 as 32bit counter (TIM8(Low 16bit) + TIM4(High 16bit))
kenjiArai 5:783b039f9119 24 // TIM8 clock input is unkown freq.(measuring freq.) and TIM4 is slave counter
kenjiArai 5:783b039f9119 25 // 1PPS gate signal connected both TIM8 IC2, TIM4 IC3 (& TIM2 IC3)
kenjiArai 5:783b039f9119 26 void FRQ_CUNTR::initialize_TIMxPy(void)
kenjiArai 5:783b039f9119 27 {
kenjiArai 5:783b039f9119 28 // Timer8 input max freq.= 108MHz (@SystemCoreClock = 216MHz)
kenjiArai 5:783b039f9119 29 // PC6 -> Unkown frequency input pin as Timer8 CH1/TI1
kenjiArai 5:783b039f9119 30 RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN);
kenjiArai 5:783b039f9119 31 GPIOC->AFR[0] &= 0xf0ffffff;
kenjiArai 5:783b039f9119 32 GPIOC->AFR[0] |= GPIO_AF3_TIM8 << 24; // 6bit x 4
kenjiArai 5:783b039f9119 33 GPIOC->MODER &= ~(GPIO_MODER_MODER6); // AF
kenjiArai 5:783b039f9119 34 GPIOC->MODER |= GPIO_MODER_MODER6_1; // alternate function mode
kenjiArai 5:783b039f9119 35 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR6); // PU
kenjiArai 5:783b039f9119 36 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR6_0; // Pull-up mode
kenjiArai 5:783b039f9119 37 // Initialize Timer8(16bit) for an external up counter mode
kenjiArai 5:783b039f9119 38 RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;
kenjiArai 5:783b039f9119 39 // count_up + div by 1
kenjiArai 5:783b039f9119 40 TIM8->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));
kenjiArai 5:783b039f9119 41 // update request only by overflow
kenjiArai 5:783b039f9119 42 TIM8->CR1 |= (uint16_t)TIM_CR1_URS;
kenjiArai 5:783b039f9119 43 TIM8->ARR = 0xffff; // Use 16bit full
kenjiArai 5:783b039f9119 44 TIM8->CCER = 0; // Reset all
kenjiArai 5:783b039f9119 45 // input filter + input select
kenjiArai 5:783b039f9119 46 TIM8->CCMR1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S);
kenjiArai 5:783b039f9119 47 TIM8->CCMR1 |= TIM_CCMR1_CC1S_0; // CC1 channel = TI1
kenjiArai 5:783b039f9119 48 // external mode 1
kenjiArai 5:783b039f9119 49 TIM8->SMCR &= ~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);
kenjiArai 5:783b039f9119 50 // ECE must be ZERO!!!!
kenjiArai 5:783b039f9119 51 TIM8->SMCR |= ( TIM_TS_TI1FP1 | TIM_SLAVEMODE_EXTERNAL1);
kenjiArai 5:783b039f9119 52 TIM8->CR2 &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS);
kenjiArai 5:783b039f9119 53 TIM8->CR2 |= (uint16_t)TIM_CR2_MMS_1; // TRGO update
kenjiArai 5:783b039f9119 54 TIM8->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 5:783b039f9119 55 // PC7 -> Input Capture pin as Timer8 IC2
kenjiArai 5:783b039f9119 56 GPIOC->AFR[0] &= 0x0fffffff;
kenjiArai 5:783b039f9119 57 GPIOC->AFR[0] |= GPIO_AF3_TIM8 << 28; // 7bit x 4
kenjiArai 5:783b039f9119 58 GPIOC->MODER &= ~(GPIO_MODER_MODER7); // AF
kenjiArai 5:783b039f9119 59 GPIOC->MODER |= GPIO_MODER_MODER7_1; // alternate function mode
kenjiArai 5:783b039f9119 60 GPIOC->PUPDR &= ~(GPIO_PUPDR_PUPDR7); // PU
kenjiArai 5:783b039f9119 61 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_0; // Pull-up mode
kenjiArai 5:783b039f9119 62 // Initialize Timer8 IC2
kenjiArai 5:783b039f9119 63 TIM8->CCER &= (uint16_t)~TIM_CCER_CC2E; // Disable the CC2
kenjiArai 5:783b039f9119 64 // input filter + input select
kenjiArai 5:783b039f9119 65 TIM8->CCMR1 &= ~(TIM_CCMR1_IC2F | TIM_CCMR1_CC2S);
kenjiArai 5:783b039f9119 66 TIM8->CCMR1 |= TIM_CCMR1_CC2S_0;
kenjiArai 5:783b039f9119 67 // positive edge
kenjiArai 5:783b039f9119 68 TIM8->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
kenjiArai 5:783b039f9119 69 TIM8->CCER |= (uint16_t)TIM_CCER_CC2E; // enable capture
kenjiArai 5:783b039f9119 70 // Initialize Timer4(16bit) as slave counter of TIM8
kenjiArai 5:783b039f9119 71 // TIM8 overflow event -> ITR3 as Timer4 clock
kenjiArai 5:783b039f9119 72 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
kenjiArai 5:783b039f9119 73 TIM4->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));
kenjiArai 5:783b039f9119 74 // only counter overflow for interrupt
kenjiArai 5:783b039f9119 75 TIM4->CR1 |= (uint16_t)TIM_CR1_URS;
kenjiArai 5:783b039f9119 76 // Up counter uses from 0 to max(32bit)
kenjiArai 5:783b039f9119 77 TIM4->ARR = 0xffff; // Use 16bit full
kenjiArai 5:783b039f9119 78 TIM4->CCER = 0; // Reset all
kenjiArai 5:783b039f9119 79 // external mode 1
kenjiArai 5:783b039f9119 80 TIM4->SMCR &= ~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS);
kenjiArai 5:783b039f9119 81 TIM4->SMCR |= (TIM_TS_ITR3); // Set Internal Triger 3 (ITR3)
kenjiArai 5:783b039f9119 82 TIM4->SMCR |= (TIM_SLAVEMODE_EXTERNAL1); // ECE must be ZERO!!!!
kenjiArai 5:783b039f9119 83 TIM4->CR2 &= (uint16_t)~(TIM_CR2_TI1S | TIM_CR2_MMS);
kenjiArai 5:783b039f9119 84 TIM4->CR2 |= (uint16_t)TIM_CR2_MMS_1; // TRGO update
kenjiArai 5:783b039f9119 85 TIM4->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 5:783b039f9119 86 // PB8 -> Input Capture pin as Timer4 IC3
kenjiArai 5:783b039f9119 87 GPIOB->AFR[1] &= 0xfffffff0;
kenjiArai 5:783b039f9119 88 GPIOB->AFR[1] |= GPIO_AF2_TIM4 << 0; // (8-8)bit x 4
kenjiArai 5:783b039f9119 89 GPIOB->MODER &= ~(GPIO_MODER_MODER8); // AF
kenjiArai 5:783b039f9119 90 GPIOB->MODER |= GPIO_MODER_MODER8_1; // alternate function mode
kenjiArai 5:783b039f9119 91 GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR8); // PU
kenjiArai 5:783b039f9119 92 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR8_0; // Pull-up mode
kenjiArai 5:783b039f9119 93 // Initialize Timer4 IC3
kenjiArai 5:783b039f9119 94 TIM4->CCER &= (uint16_t)~TIM_CCER_CC3E;
kenjiArai 5:783b039f9119 95 TIM4->CCMR2 &= ~(TIM_CCMR2_CC3S | TIM_CCMR2_IC3F);
kenjiArai 5:783b039f9119 96 TIM4->CCMR2 |= TIM_CCMR2_CC3S_0;
kenjiArai 5:783b039f9119 97 // positive edge
kenjiArai 5:783b039f9119 98 TIM4->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
kenjiArai 5:783b039f9119 99 TIM4->CCER |= (uint16_t)TIM_CCER_CC3E; // enable capture
kenjiArai 5:783b039f9119 100 // Up counter based on gate time period
kenjiArai 5:783b039f9119 101 time_count = 0;
kenjiArai 5:783b039f9119 102 // Only for Debug purpose
kenjiArai 5:783b039f9119 103 PRINTF("\r\n// Timer8(16bit high(max106MHz) clock)\r\n");
kenjiArai 5:783b039f9119 104 PRINTF("// and Timer4(16bit low clock) combined up counter\r\n");
kenjiArai 5:783b039f9119 105 PRINTF("// Set GPIO for Timer8&4\r\n");
kenjiArai 5:783b039f9119 106 // PB
kenjiArai 5:783b039f9119 107 PRINTF("// PB8 -> Input Capture pin as Timer4 CH3/TI3\r\n");
kenjiArai 5:783b039f9119 108 PRINTF("GPIOB->AFRL 0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]);
kenjiArai 5:783b039f9119 109 PRINTF("GPIOB->AFRH 0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]);
kenjiArai 5:783b039f9119 110 PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER);
kenjiArai 5:783b039f9119 111 PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR);
kenjiArai 5:783b039f9119 112 PRINTF("GPIOB->OTYPER 0x%08x:0x%08x\r\n",&GPIOB->OTYPER, GPIOB->OTYPER);
kenjiArai 5:783b039f9119 113 PRINTF("GPIOB->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOB->OSPEEDR, GPIOB->OSPEEDR);
kenjiArai 5:783b039f9119 114 // PC
kenjiArai 5:783b039f9119 115 PRINTF("// PC6 -> unkown frequency input pin as Timer8 CH1/TI1\r\n");
kenjiArai 5:783b039f9119 116 PRINTF("// PC7 -> Input Capture pin as Timer8 CH2/TI2\r\n");
kenjiArai 5:783b039f9119 117 PRINTF("GPIOC->AFRL 0x%08x:0x%08x\r\n",&GPIOC->AFR[0], GPIOC->AFR[0]);
kenjiArai 5:783b039f9119 118 PRINTF("GPIOC->AFRH 0x%08x:0x%08x\r\n",&GPIOC->AFR[1], GPIOC->AFR[1]);
kenjiArai 5:783b039f9119 119 PRINTF("GPIOC->MODER 0x%08x:0x%08x\r\n",&GPIOC->MODER, GPIOC->MODER);
kenjiArai 5:783b039f9119 120 PRINTF("GPIOC->PUPDR 0x%08x:0x%08x\r\n",&GPIOC->PUPDR, GPIOC->PUPDR);
kenjiArai 5:783b039f9119 121 PRINTF("GPIOC->OTYPER 0x%08x:0x%08x\r\n",&GPIOC->OTYPER, GPIOC->OTYPER);
kenjiArai 5:783b039f9119 122 PRINTF("GPIOC->OSPEEDR 0x%08x:0x%08x\r\n",&GPIOC->OSPEEDR, GPIOC->OSPEEDR);
kenjiArai 5:783b039f9119 123 // TIM8
kenjiArai 5:783b039f9119 124 PRINTF("// PC6 -> Timer8(16bit) for an external up counter mode\r\n");
kenjiArai 5:783b039f9119 125 PRINTF("// PC7 -> Timer8 IC2\r\n");
kenjiArai 5:783b039f9119 126 PRINTF("TIM8->CR1 0x%08x:0x%08x\r\n",&TIM8->CR1, TIM8->CR1);
kenjiArai 5:783b039f9119 127 PRINTF("TIM8->CR2 0x%08x:0x%08x\r\n",&TIM8->CR2, TIM8->CR2);
kenjiArai 5:783b039f9119 128 PRINTF("TIM8->ARR 0x%08x:0x%08x\r\n",&TIM8->ARR, TIM8->ARR);
kenjiArai 5:783b039f9119 129 PRINTF("TIM8->PSC 0x%08x:0x%08x\r\n",&TIM8->PSC, TIM8->PSC);
kenjiArai 5:783b039f9119 130 PRINTF("TIM8->CCMR1 0x%08x:0x%08x\r\n",&TIM8->CCMR1, TIM8->CCMR1);
kenjiArai 5:783b039f9119 131 PRINTF("TIM8->CCMR2 0x%08x:0x%08x\r\n",&TIM8->CCMR2, TIM8->CCMR2);
kenjiArai 5:783b039f9119 132 PRINTF("TIM8->CCER 0x%08x:0x%08x\r\n",&TIM8->CCER, TIM8->CCER);
kenjiArai 5:783b039f9119 133 PRINTF("TIM8->SMCR 0x%08x:0x%08x\r\n",&TIM8->SMCR, TIM8->SMCR);
kenjiArai 5:783b039f9119 134 PRINTF("TIM8->DIER 0x%08x:0x%08x\r\n",&TIM8->DIER, TIM8->DIER);
kenjiArai 5:783b039f9119 135 // TIM4
kenjiArai 5:783b039f9119 136 PRINTF("// PB8 -> Timer4 IC3\r\n");
kenjiArai 5:783b039f9119 137 PRINTF("TIM4->CR1 0x%08x:0x%08x\r\n",&TIM4->CR1, TIM4->CR1);
kenjiArai 5:783b039f9119 138 PRINTF("TIM4->CR2 0x%08x:0x%08x\r\n",&TIM4->CR2, TIM4->CR2);
kenjiArai 5:783b039f9119 139 PRINTF("TIM4->ARR 0x%08x:0x%08x\r\n",&TIM4->ARR, TIM4->ARR);
kenjiArai 5:783b039f9119 140 PRINTF("TIM4->PSC 0x%08x:0x%08x\r\n",&TIM4->PSC, TIM4->PSC);
kenjiArai 5:783b039f9119 141 PRINTF("TIM4->CCMR1 0x%08x:0x%08x\r\n",&TIM4->CCMR1, TIM4->CCMR1);
kenjiArai 5:783b039f9119 142 PRINTF("TIM4->CCMR2 0x%08x:0x%08x\r\n",&TIM4->CCMR2, TIM4->CCMR2);
kenjiArai 5:783b039f9119 143 PRINTF("TIM4->CCER 0x%08x:0x%08x\r\n",&TIM4->CCER, TIM4->CCER);
kenjiArai 5:783b039f9119 144 PRINTF("TIM4->SMCR 0x%08x:0x%08x\r\n",&TIM4->SMCR, TIM4->SMCR);
kenjiArai 5:783b039f9119 145 // Interrupt Timer4 IC3 (NOT Timer8 IC2) & Overflow
kenjiArai 5:783b039f9119 146 timxpy_ready_flg = 0;
kenjiArai 5:783b039f9119 147 timxpy_cnt_data = 0;
kenjiArai 5:783b039f9119 148 sw_ovrflw_timxpy = 0;
kenjiArai 5:783b039f9119 149 TIM8->SR = 0; // clear all IC/OC flag
kenjiArai 5:783b039f9119 150 TIM4->SR = 0; // clear all IC/OC flag
kenjiArai 5:783b039f9119 151 TIM4->DIER = 0; // Reset all interrupt flag
kenjiArai 5:783b039f9119 152 TIM4->DIER = TIM_DIER_CC3IE + TIM_DIER_UIE;
kenjiArai 5:783b039f9119 153 NVIC_SetVector(TIM4_IRQn, (uint32_t)irq_ic_TIMxPy);
kenjiArai 5:783b039f9119 154 NVIC_ClearPendingIRQ(TIM4_IRQn);
kenjiArai 5:783b039f9119 155 NVIC_EnableIRQ(TIM4_IRQn);
kenjiArai 5:783b039f9119 156 PRINTF("TIM4->DIER 0x%08x:0x%08x\r\n\r\n",&TIM4->DIER, TIM4->DIER);
kenjiArai 5:783b039f9119 157 PRINTF("RCC->APB1ENR 0x%08x:0x%08x\r\n\r\n",&RCC->APB1ENR, RCC->APB1ENR);
kenjiArai 5:783b039f9119 158 }
kenjiArai 5:783b039f9119 159
kenjiArai 5:783b039f9119 160 // Initialize TIM2
kenjiArai 5:783b039f9119 161 // IC3->PB10 for GPS 1pps signal
kenjiArai 5:783b039f9119 162 // IC1->PA15 for Reciprocal frequency counting mode (Interrupt)
kenjiArai 5:783b039f9119 163 void FRQ_CUNTR::initialize_TIMz(void)
kenjiArai 5:783b039f9119 164 {
kenjiArai 5:783b039f9119 165 // Initialize Timer2(32bit) for an internal(108MHz) up counter mode
kenjiArai 5:783b039f9119 166 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
kenjiArai 5:783b039f9119 167 // count_up + div by 1
kenjiArai 5:783b039f9119 168 TIM2->CR1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS | TIM_CR1_CKD));
kenjiArai 5:783b039f9119 169 // only counter overflow for interrupt
kenjiArai 5:783b039f9119 170 TIM2->CR1 |= (uint16_t)TIM_CR1_URS;
kenjiArai 5:783b039f9119 171 // Up counter uses from 0 to max(32bit)
kenjiArai 5:783b039f9119 172 TIM2->ARR = 0xffffffff;
kenjiArai 5:783b039f9119 173 TIM2->PSC = 0x0000; // 1/1
kenjiArai 5:783b039f9119 174 TIM2->CCER = 0; // Reset all
kenjiArai 5:783b039f9119 175 // input filter + input select
kenjiArai 5:783b039f9119 176 TIM2->CCMR1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S);
kenjiArai 5:783b039f9119 177 TIM2->CCMR1 |= TIM_CCMR1_CC1S_0;
kenjiArai 5:783b039f9119 178 TIM2->SMCR = 0; // Internal clock
kenjiArai 5:783b039f9119 179 TIM2->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter
kenjiArai 5:783b039f9119 180 // PA15 -> Input Capture pin as Timer2 IC1
kenjiArai 5:783b039f9119 181 GPIOA->AFR[1] &= 0x0fffffff;
kenjiArai 5:783b039f9119 182 GPIOA->AFR[1] |= GPIO_AF1_TIM2 << 28; // 15-8 = 7bit x 4
kenjiArai 5:783b039f9119 183 GPIOA->MODER &= ~(GPIO_MODER_MODER15); // AF
kenjiArai 5:783b039f9119 184 GPIOA->MODER |= GPIO_MODER_MODER15_1; // alternate function mode
kenjiArai 5:783b039f9119 185 GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR15); // PU
kenjiArai 5:783b039f9119 186 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR15_0; // Pull-up mode
kenjiArai 5:783b039f9119 187 // Initialize Timer2 IC1
kenjiArai 5:783b039f9119 188 // input filter + input select
kenjiArai 5:783b039f9119 189 TIM2->CCMR1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S);
kenjiArai 5:783b039f9119 190 TIM2->CCMR1 |= (TIM_CCMR1_CC1S_0 + TIM_CCMR1_IC1F_1); // filter = fCLK/4
kenjiArai 5:783b039f9119 191 // positive edge
kenjiArai 5:783b039f9119 192 TIM2->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
kenjiArai 5:783b039f9119 193 TIM2->CCER |= (uint16_t)TIM_CCER_CC1E; // enable capture
kenjiArai 5:783b039f9119 194 // PB10 -> Input Capture pin as Timer2 IC3 for Reciprocal
kenjiArai 5:783b039f9119 195 GPIOB->AFR[1] &= 0xfffff0ff;
kenjiArai 5:783b039f9119 196 GPIOB->AFR[1] |= GPIO_AF1_TIM2 << 8; // 10-8 = 2bit x 4
kenjiArai 5:783b039f9119 197 GPIOB->MODER &= ~(GPIO_MODER_MODER10); // AF
kenjiArai 5:783b039f9119 198 GPIOB->MODER |= GPIO_MODER_MODER10_1; // alternate function mode
kenjiArai 5:783b039f9119 199 GPIOB->PUPDR &= ~(GPIO_PUPDR_PUPDR10); // PU
kenjiArai 5:783b039f9119 200 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR10_0; // Pull-up mode
kenjiArai 5:783b039f9119 201 // Initialize Timer2 IC3
kenjiArai 5:783b039f9119 202 TIM2->CCER &= (uint16_t)~TIM_CCER_CC3E; // Disable the CC
kenjiArai 5:783b039f9119 203 TIM2->CCMR2 &= ~(TIM_CCMR2_IC3F | TIM_CCMR2_CC3S);
kenjiArai 5:783b039f9119 204 //TIM2->CCMR2 |= TIM_CCMR2_CC3S_0; // filter none
kenjiArai 5:783b039f9119 205 TIM2->CCMR2 |= (TIM_CCMR2_CC3S_0 + TIM_CCMR2_IC3F_1); // filter = fCLK/4
kenjiArai 5:783b039f9119 206 // positive edge
kenjiArai 5:783b039f9119 207 TIM2->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
kenjiArai 5:783b039f9119 208 TIM2->CCER |= (uint16_t)TIM_CCER_CC3E; // enable capture
kenjiArai 5:783b039f9119 209 // Up counter based on gate time period
kenjiArai 5:783b039f9119 210 time_count_onepps = 0;
kenjiArai 5:783b039f9119 211 // Only for Debug purpose
kenjiArai 5:783b039f9119 212 // PA
kenjiArai 5:783b039f9119 213 PRINTF("\r\n// Timer2(32bit) for an internal up counter mode\r\n");
kenjiArai 5:783b039f9119 214 PRINTF("// Set GPIO for Timer2\r\n");
kenjiArai 5:783b039f9119 215 PRINTF("// PA15 -> Input Capture pin as Timer2 CH1/TI1\r\n");
kenjiArai 5:783b039f9119 216 PRINTF("GPIOA->AFRL 0x%08x:0x%08x\r\n",&GPIOA->AFR[0], GPIOA->AFR[0]);
kenjiArai 5:783b039f9119 217 PRINTF("GPIOA->AFRH 0x%08x:0x%08x\r\n",&GPIOA->AFR[1], GPIOA->AFR[1]);
kenjiArai 5:783b039f9119 218 PRINTF("GPIOA->MODER 0x%08x:0x%08x\r\n",&GPIOA->MODER, GPIOA->MODER);
kenjiArai 5:783b039f9119 219 PRINTF("GPIOA->PUPDR 0x%08x:0x%08x\r\n",&GPIOA->PUPDR, GPIOA->PUPDR);
kenjiArai 5:783b039f9119 220 // PB
kenjiArai 5:783b039f9119 221 PRINTF("// PB10 -> Input Capture pin as Timer2 CH3/TI3\r\n");
kenjiArai 5:783b039f9119 222 PRINTF("GPIOB->AFRL 0x%08x:0x%08x\r\n",&GPIOB->AFR[0], GPIOB->AFR[0]);
kenjiArai 5:783b039f9119 223 PRINTF("GPIOB->AFRH 0x%08x:0x%08x\r\n",&GPIOB->AFR[1], GPIOB->AFR[1]);
kenjiArai 5:783b039f9119 224 PRINTF("GPIOB->MODER 0x%08x:0x%08x\r\n",&GPIOB->MODER, GPIOB->MODER);
kenjiArai 5:783b039f9119 225 PRINTF("GPIOB->PUPDR 0x%08x:0x%08x\r\n",&GPIOB->PUPDR, GPIOB->PUPDR);
kenjiArai 5:783b039f9119 226 // TIM2
kenjiArai 5:783b039f9119 227 PRINTF("// PA15 -> Timer2 IC1\r\n");
kenjiArai 5:783b039f9119 228 PRINTF("// PB10 -> Timer2 IC3\r\n");
kenjiArai 5:783b039f9119 229 PRINTF("TIM2->CR1 0x%08x:0x%08x\r\n",&TIM2->CR1, TIM2->CR1);
kenjiArai 5:783b039f9119 230 PRINTF("TIM2->CR2 0x%08x:0x%08x\r\n",&TIM2->CR2, TIM2->CR2);
kenjiArai 5:783b039f9119 231 PRINTF("TIM2->ARR 0x%08x:0x%08x\r\n",&TIM2->ARR, TIM2->ARR);
kenjiArai 5:783b039f9119 232 PRINTF("TIM2->PSC 0x%08x:0x%08x\r\n",&TIM2->PSC, TIM2->PSC);
kenjiArai 5:783b039f9119 233 PRINTF("TIM2->CCMR1 0x%08x:0x%08x\r\n",&TIM2->CCMR1, TIM2->CCMR1);
kenjiArai 5:783b039f9119 234 PRINTF("TIM2->CCMR2 0x%08x:0x%08x\r\n",&TIM2->CCMR2, TIM2->CCMR2);
kenjiArai 5:783b039f9119 235 PRINTF("TIM2->CCER 0x%08x:0x%08x\r\n",&TIM2->CCER, TIM2->CCER);
kenjiArai 5:783b039f9119 236 PRINTF("TIM2->SMCR 0x%08x:0x%08x\r\n",&TIM2->SMCR, TIM2->SMCR);
kenjiArai 5:783b039f9119 237 // Interrupt Timer2 IC4(disable at this moment) & Overflow
kenjiArai 5:783b039f9119 238 timz_cnt_data = 0;
kenjiArai 5:783b039f9119 239 sw_ovrflw_timz = 0;
kenjiArai 5:783b039f9119 240 TIM2->SR = 0; // clear all IC/OC flag
kenjiArai 5:783b039f9119 241 TIM2->DIER = 0; // Disable all interrupt
kenjiArai 5:783b039f9119 242 TIM2->DIER = TIM_DIER_UIE; // set only overflow
kenjiArai 5:783b039f9119 243 NVIC_SetVector(TIM2_IRQn, (uint32_t)irq_ic_TIMz);
kenjiArai 5:783b039f9119 244 NVIC_ClearPendingIRQ(TIM2_IRQn);
kenjiArai 5:783b039f9119 245 NVIC_EnableIRQ(TIM2_IRQn);
kenjiArai 5:783b039f9119 246 PRINTF("TIM2->DIER 0x%08x:0x%08x\r\n\r\n",&TIM2->DIER, TIM2->DIER);
kenjiArai 5:783b039f9119 247 }
kenjiArai 5:783b039f9119 248
kenjiArai 5:783b039f9119 249 //------------------------------------------------------------------------------
kenjiArai 5:783b039f9119 250 // Reciprocal measuremt
kenjiArai 5:783b039f9119 251 //------------------------------------------------------------------------------
kenjiArai 5:783b039f9119 252 void FRQ_CUNTR::start_action(void)
kenjiArai 5:783b039f9119 253 {
kenjiArai 5:783b039f9119 254 __disable_irq();
kenjiArai 5:783b039f9119 255 TIM2->SR &= ~TIM_SR_CC1IF; // clear IC flag
kenjiArai 5:783b039f9119 256 TIM2->DIER |= TIM_DIER_CC1IE; // Enable IC1
kenjiArai 5:783b039f9119 257 __enable_irq();
kenjiArai 5:783b039f9119 258 }
kenjiArai 5:783b039f9119 259
kenjiArai 5:783b039f9119 260 //------------------------------------------------------------------------------
kenjiArai 5:783b039f9119 261 // Frequency check for test & debug purpose
kenjiArai 5:783b039f9119 262 //------------------------------------------------------------------------------
kenjiArai 5:783b039f9119 263 // Read TIM8(+TIM4) Input frequency
kenjiArai 5:783b039f9119 264 uint32_t FRQ_CUNTR::debug_read_input_frequency(double gatetime)
kenjiArai 5:783b039f9119 265 {
kenjiArai 5:783b039f9119 266 TIM8->CR1 &= ~(uint16_t)TIM_CR1_CEN; // disable the TIM8 Counter
kenjiArai 5:783b039f9119 267 TIM4->CNT = 0;
kenjiArai 5:783b039f9119 268 TIM8->CNT = 0;
kenjiArai 5:783b039f9119 269 TIM8->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM8 Counter
kenjiArai 5:783b039f9119 270 wait(gatetime); // Gate time for count
kenjiArai 5:783b039f9119 271 TIM8->CR1 &= ~(uint16_t)TIM_CR1_CEN; // disable the TIM8 Counter
kenjiArai 5:783b039f9119 272 uint32_t freq = (TIM4->CNT << 16) + TIM8->CNT;
kenjiArai 5:783b039f9119 273 TIM8->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM8 Counter
kenjiArai 5:783b039f9119 274 PRINTF("Input freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq, gatetime);
kenjiArai 5:783b039f9119 275 return freq; // read counter
kenjiArai 5:783b039f9119 276 }
kenjiArai 5:783b039f9119 277
kenjiArai 5:783b039f9119 278 // Read TIM2 Clock frequency
kenjiArai 5:783b039f9119 279 uint32_t FRQ_CUNTR::debug_read_base_clock_frequency(double gatetime)
kenjiArai 5:783b039f9119 280 {
kenjiArai 5:783b039f9119 281 TIM2->CNT = 0;
kenjiArai 5:783b039f9119 282 wait(gatetime); // Gate time for count
kenjiArai 5:783b039f9119 283 uint32_t freq = TIM2->CNT; // read counter
kenjiArai 5:783b039f9119 284 PRINTF("Clock Counter=%10d, gate= %4.2f [Sec]\r\n", freq, gatetime);
kenjiArai 5:783b039f9119 285 return freq; // return counter data
kenjiArai 5:783b039f9119 286 }
kenjiArai 5:783b039f9119 287
kenjiArai 5:783b039f9119 288 // Dump all buffered data
kenjiArai 5:783b039f9119 289 void FRQ_CUNTR::debug_printf_all_buffer(void)
kenjiArai 5:783b039f9119 290 {
kenjiArai 5:783b039f9119 291 fdt_buffer.debug_print_all_buffer();
kenjiArai 5:783b039f9119 292 }
kenjiArai 5:783b039f9119 293
kenjiArai 5:783b039f9119 294 //------------------------------------------------------------------------------
kenjiArai 5:783b039f9119 295 // Interrupt Handlers
kenjiArai 5:783b039f9119 296 //------------------------------------------------------------------------------
kenjiArai 5:783b039f9119 297 // GPS 1PPS signal interrupt (connected to TIM4 IC3, TIM8 IC2 and TIM2 IC3)
kenjiArai 5:783b039f9119 298 // TIM4 IC3 Interrupt control
kenjiArai 5:783b039f9119 299 void irq_ic_TIMxPy(void)
kenjiArai 5:783b039f9119 300 {
kenjiArai 5:783b039f9119 301 // IC3 (GPS 1PPS)
kenjiArai 5:783b039f9119 302 if (TIM4->SR & TIM_SR_CC3IF){
kenjiArai 5:783b039f9119 303 TIM8->SR &= ~TIM_SR_CC2IF; // clear IC flag
kenjiArai 5:783b039f9119 304 TIM4->SR &= ~TIM_SR_CC3IF; // clear IC flag
kenjiArai 5:783b039f9119 305 TIM2->SR &= ~TIM_SR_CC3IF; // clear IC flag
kenjiArai 5:783b039f9119 306 timxpy_cnt_data = (TIM4->CCR3 << 16) + TIM8->CCR2; // 16+16 bit
kenjiArai 5:783b039f9119 307 timxpy_ready_flg = 1;
kenjiArai 5:783b039f9119 308 timz_cnt_data = TIM2->CCR3; // 32 bit
kenjiArai 5:783b039f9119 309 // data saves into the ring buffer / Unknown Freq.
kenjiArai 5:783b039f9119 310 fdt.freq_dt = timxpy_cnt_data;
kenjiArai 5:783b039f9119 311 fdt.f_sw_dt = sw_ovrflw_timxpy;
kenjiArai 5:783b039f9119 312 fdt.t_cnt = ++time_count;
kenjiArai 5:783b039f9119 313 fdt_buffer.ring_put_dt(fdt.f_1sec_dt);
kenjiArai 5:783b039f9119 314 // data saves into the ring buffer / F746 internal clock
kenjiArai 5:783b039f9119 315 onepps_dt.freq_dt = timz_cnt_data;
kenjiArai 5:783b039f9119 316 onepps_dt.f_sw_dt = sw_ovrflw_timz;
kenjiArai 5:783b039f9119 317 onepps_dt.t_cnt = ++time_count_onepps;
kenjiArai 5:783b039f9119 318 onepps_buf.ring_put_dt(onepps_dt.f_1sec_dt);
kenjiArai 5:783b039f9119 319 #if ACTIVE_LED_TIMX
kenjiArai 5:783b039f9119 320 irq_led1 = !irq_led1;
kenjiArai 5:783b039f9119 321 #endif // ACTIVE_LED
kenjiArai 5:783b039f9119 322 }
kenjiArai 5:783b039f9119 323 // TIM4 overflow
kenjiArai 5:783b039f9119 324 if (TIM4->SR & TIM_SR_UIF){
kenjiArai 5:783b039f9119 325 TIM4->SR &= ~TIM_SR_UIF;
kenjiArai 5:783b039f9119 326 ++sw_ovrflw_timxpy;
kenjiArai 5:783b039f9119 327 }
kenjiArai 5:783b039f9119 328 }
kenjiArai 5:783b039f9119 329
kenjiArai 5:783b039f9119 330 // Reciprocal data (TIM2 IC1)
kenjiArai 5:783b039f9119 331 void irq_ic_TIMz(void)
kenjiArai 5:783b039f9119 332 {
kenjiArai 5:783b039f9119 333 // IC1 (for reciprocal measurement)
kenjiArai 5:783b039f9119 334 if (TIM2->SR & TIM_SR_CC1IF){
kenjiArai 5:783b039f9119 335 TIM2->SR &= ~TIM_SR_CC1IF; // clear IC flag
kenjiArai 5:783b039f9119 336 uint32_t data = TIM2->CCR1;
kenjiArai 5:783b039f9119 337 if (recipro_step == 0){ // start measuring
kenjiArai 5:783b039f9119 338 recipro_start = data;
kenjiArai 5:783b039f9119 339 recipro_step = 1;
kenjiArai 5:783b039f9119 340 } else if (recipro_step == 1){ // stop
kenjiArai 5:783b039f9119 341 TIM2->DIER &= ~TIM_DIER_CC1IE; // disable IC4 interrupt
kenjiArai 5:783b039f9119 342 recipro_stop = data;
kenjiArai 5:783b039f9119 343 recipro_step = 2;
kenjiArai 5:783b039f9119 344 } else { // jsut in case
kenjiArai 5:783b039f9119 345 TIM2->DIER &= ~TIM_DIER_CC1IE; // disable IC4 interrupt
kenjiArai 5:783b039f9119 346 recipro_step = 0;
kenjiArai 5:783b039f9119 347 }
kenjiArai 5:783b039f9119 348 #if ACTIVE_LED_TIMZ
kenjiArai 5:783b039f9119 349 irq_led1 = !irq_led1;
kenjiArai 5:783b039f9119 350 #endif // ACTIVE_LED
kenjiArai 5:783b039f9119 351 }
kenjiArai 5:783b039f9119 352 // TIM2 overflow
kenjiArai 5:783b039f9119 353 if (TIM2->SR & TIM_SR_UIF){ // 32bit counter overflow
kenjiArai 5:783b039f9119 354 TIM2->SR &= ~TIM_SR_UIF;
kenjiArai 5:783b039f9119 355 ++sw_ovrflw_timz;
kenjiArai 5:783b039f9119 356 }
kenjiArai 5:783b039f9119 357 }
kenjiArai 5:783b039f9119 358
kenjiArai 5:783b039f9119 359 #endif // defined(TARGET_STM32F746NG)