mon_hw_STM32.cpp

00001 /*
00002  * mbed Application program for the ST NUCLEO Board
00003  * Monitor program Ver.3 for only for STM32F401RE,F411RE & STM32L152RE
00004  *
00005  *  Copyright (c) 2010-2015 Kenji Arai / JH1PJL
00006  *  http://www.page.sannet.ne.jp/kenjia/index.html
00007  *  http://mbed.org/users/kenjiArai/
00008  *      Started:  May        9th, 2010
00009  *      Created:  May       15th, 2010
00010  *          release as "monitor_01" http://mbed.org/users/kenjiArai/code/monitor_01/
00011  *      Spareted: June      25th, 2014      mon() & mon_hw()
00012  *      restart:  July      12th, 2014
00013  *      Revised:  April     25th, 2015      Bug fix ('o' command) pointed out by Topi Makinen
00014  *      Revised:  April     26th, 2015      Change Port output speed (set High speed)
00015  *
00016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
00017  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00018  * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
00019  * DAMAGES OR OTHER  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00020  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00021  */
00022 
00023 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_L152RE)
00024 
00025 //  Include ---------------------------------------------------------------------------------------
00026 #include "mbed.h"
00027 #include "mon_hw_config.h"
00028 #include "mon_hw_common.h"
00029 #include "mon_hw_STM32.h"
00030 
00031 //  Object ----------------------------------------------------------------------------------------
00032 
00033 //  Definition ------------------------------------------------------------------------------------
00034 // USB Frequency
00035 #define USB_FREQ_H          48100000
00036 #define USB_FREQ_L          47900000
00037 
00038 //  RAM -------------------------------------------------------------------------------------------
00039 uint32_t SystemFrequency;
00040 uint8_t quitflag;
00041 
00042 uint32_t reg_save0, reg_save1, reg_save2, reg_save3, reg_save4, reg_save5, reg_save6;
00043 
00044 //  ROM / Constant data ---------------------------------------------------------------------------
00045 #if defined(TARGET_NUCLEO_F401RE)
00046 char *const mon_msg =
00047     "HW monitor only for mbed Nucleo F401RE created on UTC:"__DATE__"("__TIME__")";
00048 
00049 #if USE_MEM
00050 const uint32_t mem_range[][2] = {   // Memory access range
00051     { 0x08000000, 0x0807ffff },     // On-chip Flash memory, 512KB Flash
00052     { 0x1fff0000, 0x1fff7a0f },     // System memory
00053     { 0x1fffc000, 0x1fffc007 },     // Option bytes
00054     { 0x20000000, 0x20017fff },     // Main Embedded SRAM, 96KB SRAM
00055     { 0x40000000, 0x5003ffff }      // IO area
00056 };
00057 #endif // USE_MEM
00058 #elif defined(TARGET_NUCLEO_F411RE)
00059 char *const mon_msg =
00060     "HW monitor only for mbed Nucleo F411RE created on UTC:"__DATE__"("__TIME__")";
00061 
00062 #if USE_MEM
00063 const uint32_t mem_range[][2] = {   // Memory access range
00064     { 0x08000000, 0x0807ffff },     // On-chip Flash memory, 512KB Flash
00065     { 0x1fff0000, 0x1fff7a0f },     // System memory
00066     { 0x1fffc000, 0x1fffc007 },     // Option bytes
00067     { 0x20000000, 0x2001ffff },     // Main Embedded SRAM, 128KB SRAM
00068     { 0x40000000, 0x5003ffff }      // IO area
00069 };
00070 #endif // USE_MEM
00071 #elif defined(TARGET_NUCLEO_L152RE)
00072 char *const mon_msg =
00073     "HW monitor only for mbed Nucleo L152RE created on UTC:"__DATE__"("__TIME__")";
00074 
00075 #if USE_MEM
00076 const uint32_t mem_range[][2] = {   // Memory access range
00077     { 0x08000000, 0x0807ffff },     // On-chip Flash memory, 512KB Flash
00078     { 0x08080000, 0x08083fff },     // EEPROM, 16KB
00079     { 0x1ff00000, 0x1ff01fff },     // System memory
00080     { 0x1ff80000, 0x1ff8009f },     // Option bytes
00081     { 0x20000000, 0x20013fff },     // Main Embedded SRAM, 32KB SRAM
00082     { 0x40000000, 0x400267ff }      // IO area
00083 };
00084 #endif // USE_MEM
00085 #endif
00086 
00087 char *const hmsg0 = "m  - Entry Memory Mode";
00088 char *const hmsg1 = "m>? -> Aditinal functions can see by ?";
00089 char *const hmsg2 = "r  - Entry Register Mode";
00090 char *const hmsg3 = "r>? -> Aditinal functions can see by ?";
00091 char *const hmsg4 = "s  - System Clock -> sf, System / CPU information -> sc";
00092 char *const hmsg5 = "q  - Quit (back to called routine)";
00093 char *const hmsg6 = "p  - Entry Port Mode";
00094 char *const hmsg7 = "p>? -> Aditinal functions can see by ?";
00095 
00096 char *const mrmsg0 = "Enter Register Mode u,i,s,t,a,d,l,w,c & ? for help";
00097 #if (USE_UART==1) || (USE_SPI==1) || (USE_I2C == 1)
00098 char *const mrmsg1 = "------";
00099 char *const mrmsg2 = "USART";
00100 //
00101 char *const mrmsg4 = "I2C";
00102 //
00103 char *const mrmsg6 = "SPI";
00104 //
00105 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
00106 char *const mrmsg3 = "Enter u1,u2,u6 and u* for all";
00107 char *const mrmsg5 = "Enter i1,i2,i3 and i* for all";
00108 char *const mrmsg7 = "Enter s1,s2,s3,s4 and s* for all";
00109 #elif defined(TARGET_NUCLEO_L152RE)
00110 char *const mrmsg3 = "Enter u1,u2,u3,u5 and u* for all";
00111 char *const mrmsg5 = "Enter i1,i2 and i* for all";
00112 char *const mrmsg7 = "Enter s1,s2,s3 and s* for all";
00113 #endif
00114 #endif  // (USE_UART==1) || (USE_SPI==1) || (USE_I2C == 1)
00115 char *const mrmsg8 = "Return to All Mode";
00116 
00117 //-------------------------------------------------------------------------------------------------
00118 //  Control Program
00119 //-------------------------------------------------------------------------------------------------
00120 // No function
00121 static void not_yet_impliment( void )
00122 {
00123     PRINTF("Not implimented yet");
00124     put_rn();
00125 }
00126 
00127 // No function
00128 #if (USE_MEM==0)||(USE_PORT==0)||(USE_UART==0)||(USE_SPI==0)||(USE_I2C==0)||(USE_SYS==0)
00129 static void not_select( void )
00130 {
00131     PRINTF("Not select the function (refer mon_hw_config.h)");
00132     put_rn();
00133 }
00134 #endif
00135 
00136 //  Help Massage
00137 void hw_msg_hlp ( void )
00138 {
00139     PRINTF(mon_msg);
00140     put_rn();
00141     PRINTF(hmsg0);
00142     put_rn();
00143     PRINTF(hmsg1);
00144     put_rn();
00145     PRINTF(hmsg6);
00146     put_rn();
00147     PRINTF(hmsg7);
00148     put_rn();
00149     PRINTF(hmsg2);
00150     put_rn();
00151     PRINTF(hmsg3);
00152     put_rn();
00153     PRINTF(hmsg4);
00154     put_rn();
00155     PRINTF(hmsg5);
00156     put_rn();
00157 }
00158 
00159 #if USE_MEM
00160 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
00161 char *const rmsg0 = "FLASH    ";
00162 char *const rmsg1 = "SYS-Mem  ";
00163 char *const rmsg2 = "OPTION   ";
00164 char *const rmsg3 = "SRAM     ";
00165 char *const rmsg4 = "IO       ";
00166 #elif defined(TARGET_NUCLEO_L152RE)
00167 char *const rmsg0 = "FLASH    ";
00168 char *const rmsg1 = "EEPROM   ";
00169 char *const rmsg2 = "SYS-Mem  ";
00170 char *const rmsg3 = "OPTION   ";
00171 char *const rmsg4 = "SRAM     ";
00172 char *const rmsg5 = "IO       ";
00173 #endif
00174 
00175 #include "mon_hw_mem.h"
00176 #endif   // USE_MEM
00177 
00178 
00179 //  Show 16bit register contents
00180 void reg_print(uint16_t size, uint16_t reg)
00181 {
00182     uint16_t i, j, k, n;
00183 
00184     i = j = k = n = 0;
00185     switch (size) {
00186         case SIZE8:
00187             PRINTF(rgmsg0);
00188             put_rn();
00189             i = 8;
00190             n = 0x80;
00191             break;
00192         case SIZE16:
00193             PRINTF("%s%s", rgmsg1, rgmsg0);
00194             put_rn();
00195             i = 16;
00196             n = 0x8000;
00197             break;
00198         case SIZE32:
00199             PRINTF("0x%08x", reg);
00200             return;
00201         default :
00202             ;
00203     }
00204     PUTC(' ');
00205     for (; i>0; i--) {
00206         k = n >> (size-i);
00207         j = reg & k;
00208         if (j) {
00209             PUTC('1');
00210         } else {
00211             PUTC('0');
00212         }
00213         PUTC(' ');
00214         PUTC(' ');
00215     }
00216     PRINTF("  (0x%04x)", reg);
00217 }
00218 
00219 #if USE_I2C
00220 void i2c_reg( I2C_TypeDef* I2Cx )
00221 {
00222     uint16_t reg;
00223 
00224     put_rn();
00225     reg = I2Cx->CR1;
00226     reg_print( SIZE32, reg );
00227     PRINTF( rnmsg0 );
00228     PRINTF( imsg2 );
00229     put_rn();
00230     reg = I2Cx->CR2;
00231     reg_print( SIZE32, reg );
00232     PRINTF( rnmsg1 );
00233     PRINTF( imsg2 );
00234     put_rn();
00235     reg = I2Cx->SR1;
00236     reg_print( SIZE32, reg );
00237     PRINTF( rnmsg5 );
00238     PRINTF( imsg3 );
00239     put_rn();
00240     reg = I2Cx->SR2;
00241     reg_print( SIZE32, reg );
00242     PRINTF( rnmsg6 );
00243     PRINTF( imsg3 );
00244     put_rn();
00245     reg = I2Cx->DR;
00246     reg_print( SIZE32, reg );
00247     PRINTF( rnmsg2 );
00248     PRINTF( imsg4 );
00249     put_rn();
00250     reg = I2Cx->OAR1;
00251     reg_print( SIZE32, reg );
00252     PRINTF( rnmsg7 );
00253     PRINTF( imsg6 );
00254     put_rn();
00255     reg = I2Cx->OAR2;
00256     reg_print( SIZE32, reg );
00257     PRINTF( rnmsg8 );
00258     PRINTF( imsg6 );
00259     put_rn();
00260     reg = I2Cx->CCR;
00261     reg_print( SIZE32, reg );
00262     PRINTF( rnmsg9 );
00263     PRINTF( imsg7 );
00264     put_rn();
00265     reg = I2Cx->TRISE;
00266     reg_print( SIZE32, reg );
00267     PRINTF( rnmsg10 );
00268     PRINTF( imsg8 );
00269     put_rn();
00270 }
00271 #endif  // USE_I2C
00272 
00273 #if USE_SPI
00274 void spi_reg( SPI_TypeDef* SPIx )
00275 {
00276     uint16_t reg;
00277 
00278     put_rn();
00279     reg = SPIx->CR1;
00280     reg_print( SIZE32, reg );
00281     PRINTF( rnmsg0 );
00282     PRINTF( imsg2 );
00283     put_rn();
00284     reg = SPIx->CR2;
00285     reg_print( SIZE32, reg );
00286     PRINTF( rnmsg1 );
00287     PRINTF( imsg2 );
00288     put_rn();
00289     reg = SPIx->SR;
00290     reg_print( SIZE32, reg );
00291     PRINTF( rnmsg3 );
00292     PRINTF( imsg3 );
00293     put_rn();
00294     reg = SPIx->DR;
00295     reg_print( SIZE32, reg );
00296     PRINTF( rnmsg2 );
00297     PRINTF( imsg4 );
00298     put_rn();
00299 }
00300 #endif  // USE_SPI
00301 
00302 #if USE_UART
00303 void usart_reg( USART_TypeDef* USARTx )
00304 {
00305     uint16_t reg;
00306 
00307     put_rn();
00308     reg = USARTx->SR;
00309     reg_print( SIZE32, reg );
00310     PRINTF( rnmsg3 );
00311     PRINTF( imsg3 );
00312     put_rn();
00313     reg = USARTx->DR;
00314     reg_print( SIZE32, reg );
00315     PRINTF( rnmsg2 );
00316     PRINTF( imsg4 );
00317     put_rn();
00318     reg = USARTx->BRR;
00319     reg_print( SIZE32, reg );
00320     PRINTF( rnmsg4 );
00321     PRINTF( imsg5 );
00322     put_rn();
00323     reg = USARTx->CR1;
00324     reg_print( SIZE32, reg );
00325     PRINTF( rnmsg0 );
00326     PRINTF( imsg2 );
00327     put_rn();
00328     reg = USARTx->CR2;
00329     reg_print( SIZE32, reg );
00330     PRINTF( rnmsg1 );
00331     PRINTF( imsg2 );
00332     put_rn();
00333 }
00334 #endif  // USE_UART
00335 
00336 #if USE_PORT
00337 void rpt_port_one( GPIO_TypeDef* GPIOx )
00338 {
00339     uint32_t i;
00340 
00341     PRINTF( " " );
00342     i = GPIOx->MODER;
00343     PRINTF( "0x%08x",i );
00344     i = GPIOx->OTYPER;
00345     PRINTF( " 0x%04x",i );
00346     i = GPIOx->OSPEEDR;
00347     PRINTF( "  0x%08x",i );
00348     i = GPIOx->PUPDR;
00349     PRINTF( " 0x%08x",i );
00350     i = GPIOx->IDR;
00351     PRINTF( " 0x%04x",i );
00352     i = GPIOx->ODR;
00353     PRINTF( " 0x%04x",i );
00354     put_rn();
00355 }
00356 
00357 void rpt_port( void )
00358 {
00359     PRINTF( pnmsg0 );
00360     PRINTF( pnmsg1 );
00361     put_rn();
00362     PRINTF( pnmsga );
00363     rpt_port_one( GPIOA );
00364     PRINTF( pnmsgb );
00365     rpt_port_one( GPIOB );
00366     PRINTF( pnmsgc );
00367     rpt_port_one( GPIOC );
00368     PRINTF( pnmsgd );
00369     rpt_port_one( GPIOD );
00370     PRINTF( pnmsge );
00371     rpt_port_one( GPIOE );
00372     PRINTF( pnmsgh );
00373     rpt_port_one( GPIOH );
00374 }
00375 
00376 void port_inf_one( char *ptr )
00377 {
00378     GPIO_TypeDef* GPIOx;
00379     uint32_t i,j;
00380     uint32_t pinpos;
00381 
00382     GPIOx = 0;
00383     PRINTF( pnmsg2 );
00384     switch ( *ptr ) {
00385         case 'a':
00386             GPIOx = GPIOA;
00387             PUTC( 'A' );
00388             break;
00389         case 'b':
00390             GPIOx = GPIOB;
00391             PUTC( 'B' );
00392             break;
00393         case 'c':
00394             GPIOx = GPIOC;
00395             PUTC( 'C' );
00396             break;
00397         case 'd':
00398             GPIOx = GPIOD;
00399             PUTC( 'D' );
00400             break;
00401         case 'e':
00402             GPIOx = GPIOE;
00403             PUTC( 'E' );
00404             break;
00405         case 'h':
00406             GPIOx = GPIOH;
00407             PUTC( 'H' );
00408             break;
00409     }
00410     i = GPIOx->MODER;
00411     put_rn();
00412     PRINTF( "-->Mode Reg.  (0x%08x)",i );
00413     put_rn();
00414     for ( pinpos = 0x00; pinpos < 16; pinpos++ ) {
00415         j = GPIO_MODER_MODER0 & (i >> (pinpos * 2));
00416         switch (j) {
00417             case GPIO_Mode_IN:
00418                 PRINTF( "%2d= in", pinpos );
00419                 break;
00420             case GPIO_Mode_OUT:
00421                 PRINTF( "%2d=out", pinpos );
00422                 break;
00423             case GPIO_Mode_AF:
00424                 PRINTF( "%2d=alt", pinpos );
00425                 break;
00426             case GPIO_Mode_AN:
00427                 PRINTF( "%2d=ana", pinpos );
00428                 break;
00429             default:
00430                 break;
00431         }
00432         if ( (pinpos == 3) && (*ptr == 'h') ) {
00433             break;
00434         } else {
00435             if ( pinpos == 7 ) {
00436                 put_rn();
00437             } else if ( pinpos == 15 ) {
00438                 ;
00439             } else {
00440                 PRINTF(", ");
00441             }
00442         }
00443     }
00444     i = GPIOx->OTYPER;
00445     put_rn();
00446     PRINTF( "%s type 1=push-pull, 0= open-drain", pnmsg4 );
00447     put_rn();
00448     reg_print( SIZE32,i);
00449     i = GPIOx->OSPEEDR;
00450     PRINTF( "%s speed [MHz] (0x%08x)", pnmsg4, i );
00451     put_rn();
00452     for ( pinpos = 0x00; pinpos < 16; pinpos++ ) {
00453         j = GPIO_OSPEEDER_OSPEEDR0 & (i >> (pinpos * 2));
00454         switch (j) {
00455             case GPIO_Speed_400KHz:
00456                 PRINTF( "%2d=0.4", pinpos );
00457                 break;
00458             case GPIO_Speed_2MHz:
00459                 PRINTF( "%2d=  2", pinpos );
00460                 break;
00461             case GPIO_Speed_10MHz:
00462                 PRINTF( "%2d= 10", pinpos );
00463                 break;
00464             case GPIO_Speed_40MHz:
00465                 PRINTF( "%2d= 40", pinpos );
00466                 break;
00467             default:
00468                 break;
00469         }
00470         if ( (pinpos == 3) && (*ptr == 'h') ) {
00471             break;
00472         } else {
00473             if ( pinpos == 7 ) {
00474                 put_rn();
00475             } else if ( pinpos == 15) {
00476                 ;
00477             } else {
00478                 PRINTF(", ");
00479             }
00480         }
00481     }
00482     i = GPIOx->PUPDR;
00483     put_rn();
00484     PRINTF( "-->Pullup(pup)/down(pdn) none(no)(0x%08x)",i );
00485     put_rn();
00486     for ( pinpos = 0x00; pinpos < 16; pinpos++ ) {
00487         j = GPIO_PUPDR_PUPDR0 & (i >> (pinpos * 2));
00488         switch (j) {
00489             case GPIO_PuPd_NOPULL:
00490                 PRINTF( "%2d= no", pinpos );
00491                 break;
00492             case GPIO_PuPd_UP:
00493                 PRINTF( "%2d=pup", pinpos );
00494                 break;
00495             case GPIO_PuPd_DOWN:
00496                 PRINTF( "%2d=pdn", pinpos );
00497                 break;
00498             default:
00499                 break;
00500         }
00501         if ( (pinpos == 3) && (*ptr == 'h') ) {
00502             break;
00503         } else {
00504             if ( pinpos == 7 ) {
00505                 put_rn();
00506             } else if ( pinpos == 15 ) {
00507                 ;
00508             } else {
00509                 PRINTF(", ");
00510             }
00511         }
00512     }
00513     put_rn();
00514     PRINTF( "%s %s", pnmsg5, pnmsg6);
00515     i = GPIOx->IDR;
00516     reg_print( SIZE32,i);
00517     put_rn();
00518     PRINTF( "%s %s", pnmsg4, pnmsg6);
00519     i = GPIOx->ODR;
00520     reg_print( SIZE32,i);
00521     put_rn();
00522 }
00523 #endif  // USE_PORT
00524 
00525 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
00526 void port_mco1_mco2_set(uint8_t n)
00527 {
00528     GPIO_TypeDef* GPIOx = 0;
00529     uint32_t temp = 0x00;
00530 
00531     if (n == 0){    // Just save the original setting
00532         // PA8 -> MCO_1
00533         GPIOx = GPIOA;
00534         reg_save0 = GPIOx->AFR[8 >> 3];
00535         reg_save1 = GPIOx->MODER;
00536         reg_save2 = GPIOx->OSPEEDR;
00537         GPIOx = GPIOC;
00538         reg_save3 = GPIOx->AFR[9 >> 3];
00539         reg_save4 = GPIOx->MODER;
00540         reg_save5 = GPIOx->OSPEEDR;
00541         reg_save6 = RCC->CFGR;
00542     } else {
00543         // PA8 -> MCO_1
00544         GPIOx = GPIOA;
00545         temp = ((uint32_t)(GPIO_AF0_MCO) << (((uint32_t)8 & (uint32_t)0x07) * 4)) ;
00546         GPIOx->AFR[8 >> 3] &= ~((uint32_t)0xf << ((uint32_t)(8 & (uint32_t)0x07) * 4)) ;
00547         GPIOx->AFR[8 >> 3] |= temp;
00548         GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (8 * 2));
00549         GPIOx->MODER |= (0x2 << (8 * 2));
00550         GPIOx->OSPEEDR |= (0x03 << (8 * 2)); // High speed
00551         // PC9 -> MCO_2
00552         GPIOx = GPIOC;
00553         temp = ((uint32_t)(GPIO_AF0_MCO) << (((uint32_t)9 & (uint32_t)0x07) * 4)) ;
00554         GPIOx->AFR[9 >> 3] &= ~((uint32_t)0xf << ((uint32_t)(9 & (uint32_t)0x07) * 4)) ;
00555         GPIOx->AFR[9 >> 3] |= temp;
00556         GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (9 * 2));
00557         GPIOx->MODER |= (0x2 << (9 * 2));
00558         GPIOx->OSPEEDR |= (0x03 << (9 * 2)); // High speed
00559         // Select output clock source
00560         RCC->CFGR &= 0x009fffff;
00561         if (n == 1){
00562             // MC0_1 output HSE 1/4, MCO_2 output SYSCLK 1/4
00563             //             MCO2          MCO2PRE       MCO1PRE       MCO1
00564             RCC->CFGR |= (0x0 << 30) + (0x6 << 27) + (0x6 << 24) + (0x3 << 22);
00565         } else {
00566             // MC0_1 output HSE 1/1, MCO_2 output SYSCLK 1/2
00567             //             MCO2          MCO2PRE       MCO1PRE       MCO1
00568             RCC->CFGR |= (0x0 << 30) + (0x4 << 27) + (0x0 << 24) + (0x3 << 22);
00569         }
00570     }
00571 }
00572 
00573 void port_mco1_mco2_recover(void)
00574 {
00575     GPIO_TypeDef* GPIOx = 0;
00576 
00577     // PA8 -> MCO_1
00578     GPIOx = GPIOA;
00579     GPIOx->AFR[8 >> 3] = reg_save0;
00580     GPIOx->MODER = reg_save1;
00581     GPIOx->OSPEEDR = reg_save2;
00582     // PC9 -> MCO_2
00583     GPIOx = GPIOC;
00584     GPIOx->AFR[9 >> 3] = reg_save3;
00585     GPIOx->MODER = reg_save4;
00586     GPIOx->OSPEEDR = reg_save5;
00587     // MC0_1 & MCO_2
00588     RCC->CFGR = reg_save6;
00589 }
00590 #endif      // defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
00591 
00592 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
00593 void cpu_inf( char *ptr )
00594 {
00595     uint32_t m1 = 0, m2 = 0, m3 = 0, m4 = 0, m5 = 0;
00596 
00597     switch (*ptr++) {
00598         case 'f' :  // sc - show system clock frequency
00599             m1 = RCC->CR;
00600             PRINTF( "CR       = 0x%08x", m1 );
00601             put_rn();
00602             m1 = RCC->PLLCFGR;
00603             PRINTF( "PLLCFGR  = 0x%08x", m1 );
00604             put_rn();
00605             m1 = RCC->CFGR;
00606             PRINTF( "CFGR     = 0x%08x", m1 );
00607             put_rn();
00608             m1 = RCC->CIR;
00609             PRINTF( "CIR      = 0x%08x", m1 );
00610             put_rn();
00611             m1 = RCC->AHB1RSTR;
00612             PRINTF( "AHB1RSTR = 0x%08x", m1 );
00613             put_rn();
00614             m1 = RCC->APB2RSTR;
00615             PRINTF( "APB2RSTR = 0x%08x", m1 );
00616             put_rn();
00617             m1 = RCC->APB1RSTR;
00618             PRINTF( "APB1RSTR = 0x%08x", m1 );
00619             put_rn();
00620             m1 = RCC->AHB1ENR;
00621             PRINTF( "AHB1ENR  = 0x%08x", m1 );
00622             put_rn();
00623             m1 = RCC->APB2ENR;
00624             PRINTF( "APB2ENR  = 0x%08x", m1 );
00625             put_rn();
00626             m1 = RCC->APB2LPENR;
00627             PRINTF( "APB2LPENR= 0x%08x", m1 );
00628             put_rn();
00629             m1 = RCC->APB1LPENR;
00630             PRINTF( "APB1LPENR= 0x%08x", m1 );
00631             put_rn();
00632             m1 = RCC->CSR;
00633             PRINTF( "CSR      = 0x%08x", m1 );
00634             put_rn();
00635             PRINTF(cmsg11);
00636             put_rn();
00637             m1 = PWR->CR;
00638             PRINTF( "CR       = 0x%08x", m1 );
00639             put_rn();
00640             m1 = PWR->CSR;
00641             PRINTF( "CSR      = 0x%08x", m1 );
00642             put_rn();
00643             put_rn();
00644         case 'F' :  // sF - show system clock frequency
00645             m1 = RCC->CFGR & RCC_CFGR_SWS;  /* Get SYSCLK source */
00646             switch (m1) {
00647                 case 0x00:  // HSI used as system clock
00648                     PRINTF( "%s, %s%dHz", cmsg2, cmsg1,HSI_VALUE );
00649                     m2 = HSI_VALUE;
00650                     break;
00651                 case 0x04:  // HSE used as system clock
00652                     PRINTF( "%s, %s%dHz", cmsg3, cmsg1, HSE_VALUE );
00653                     m2 = HSE_VALUE;
00654                     break;
00655                 case 0x08:  // PLL used as system clock
00656                     PRINTF("fVCO = fPLL-in x (PLLN/PLLM), fPLL-out = fVCO/PLLP, fUSB-out = fVCO/PLLQ");
00657                     put_rn();
00658                     m5 = (RCC->PLLCFGR >> 6) & 0x1ff;   // PLLN
00659                     m1 = RCC->PLLCFGR & 0x3f;           // PLLM
00660                     PRINTF( "%s PLLN=%d, PLLM=%d", cmsg4, m5, m1 );
00661                     put_rn();
00662                     m3 = (RCC->PLLCFGR >> 22) & 0x1;    // Clock source
00663                     if (m3 == 0) {
00664                         // HSI oscillator clock selected as PLL clock source
00665                         m2 = (HSI_VALUE * (m5 / m1));
00666                         PRINTF( "%s, RC=%dHz", cmsg2, HSI_VALUE );
00667                     } else {
00668                         // HSE selected
00669                         m2 = (((HSE_VALUE) * m5) / m1);
00670                         if ((RCC->CR >> 18) & 0x01) {  // check HSEBYP bit
00671                             // HSE(not Xtal) selected as PLL clock source
00672                             PRINTF( "Use HSE(not Xtal but External Clock)=%dHz", HSE_VALUE );
00673                         } else {
00674                             // HSE(Xtal) selected as PLL clock source
00675                             PRINTF( "%s, Xtal=%dHz", cmsg3, HSE_VALUE );
00676                         }
00677                     }
00678                     put_rn();
00679                     PRINTF("PLL/Base   %s%dHz", cmsg1, m2);
00680                     put_rn();
00681                     m3 = (RCC->PLLCFGR >> 16) & 0x03;  // PLLP
00682                     switch (m3) {
00683                         case 0:
00684                             m3 = 2;
00685                             break;
00686                         case 1:
00687                             m3 = 4;
00688                             break;
00689                         case 2:
00690                             m3 = 6;
00691                             break;
00692                         case 3:
00693                             m3 = 8;
00694                             break;
00695                     }
00696                     m4 = (RCC->PLLCFGR >> 24) & 0x0f;  // PLLQ
00697                     PRINTF("%s PLLP=%d, PLLQ=%d", cmsg4, m3, m4);
00698                     put_rn();
00699                     PRINTF("PLL/System %s%dHz", cmsg1, m2/m3);
00700                     put_rn();
00701                     PRINTF("PLL/USB    %s%dHz", cmsg1, m2/m4);
00702                     m2 = m2/m4;
00703                     if ((m2 > USB_FREQ_H) || (m2 <USB_FREQ_L)) {
00704                         PRINTF(" -> USB Freq. is out of range!");
00705                     }
00706                     put_rn();
00707                     break;
00708                 default:    // Not come here
00709                     PRINTF( cmsg5 );
00710                     break;
00711             }
00712             put_rn();
00713             PRINTF( "SYSCLK %s%dHz", cmsg6, HAL_RCC_GetSysClockFreq());
00714             put_rn();
00715             PRINTF( "HCLK   %s%dHz", cmsg6, HAL_RCC_GetHCLKFreq());
00716             put_rn();
00717             PRINTF( "PCLK1  %s%dHz", cmsg6, HAL_RCC_GetPCLK1Freq());
00718             put_rn();
00719             PRINTF( "PCLK2  %s%dHz", cmsg6, HAL_RCC_GetPCLK2Freq());
00720             put_rn();
00721             put_rn();
00722             // Check RTC Clock
00723             PRINTF("RTC Clock");
00724             put_rn();
00725             m1 = (RCC->BDCR >> 8) & 0x03;
00726             switch (m1) {
00727                 case 0: // no clock
00728                     PRINTF(cmsg7);
00729                     break;
00730                 case 1: // LSE
00731                     PRINTF(cmsg8);
00732                     break;
00733                 case 2: // LSI
00734                     PRINTF("%s 17 to 47, typ.32KHz", cmsg9);
00735                     break;
00736                 case 3: // HSE
00737                     PRINTF( cmsg10 );
00738                     m2 = (RCC->PLLCFGR >> 16) & 0x1f;   // RTCPRE
00739                     m3 = HSE_VALUE / m2;
00740                     PRINTF("%s%dHz", cmsg6, m3);
00741                     put_rn();
00742                     break;
00743                 default:    // Not come here
00744                     PRINTF(cmsg5);
00745                     break;
00746             }
00747             put_rn();
00748             put_rn();
00749             break;
00750         case 'c' :      // sc - show system CPU information
00751             m1 = SCB->CPUID;
00752             m2 = ( m1 >> 24 );
00753             if ( m2 == 0x41 ) {
00754                 PRINTF( "CPU = ARM " );
00755             } else {
00756                 PRINTF( "CPU = NOT ARM " );
00757             }
00758             m2 = ( m1 >> 4 ) & 0xfff;
00759             if ( m2 == 0xc24 ) {
00760                 PRINTF( "Cortex-M4" );
00761             } else {
00762                 PRINTF( "NOT Cortex-M4" );
00763             }
00764             put_rn();
00765             m2 = ( m1 >> 20 ) & 0x0f;
00766             PRINTF( "Variant:%x", m2 );
00767             put_rn();
00768             m2 = m1 & 0x7;
00769             PRINTF( "Revision:%x", m2 );
00770             put_rn();
00771             PRINTF( "CPU ID: 0x%08x", m1 );
00772             put_rn();
00773             m1 = DBGMCU->IDCODE;
00774             PRINTF( "DBG ID: 0x%08x", m1 );
00775             put_rn();
00776             // unique ID
00777             // http://waijung.aimagin.com/index.htm?stm32f4_uidread.htm
00778             m1 = *(__IO uint32_t *)((uint32_t)0x1FFF7A10);
00779             PRINTF("Unique device ID(94bits):(1) 0x%08x ", m1);
00780             m1 = *(__IO uint32_t *)((uint32_t)0x1FFF7A14);
00781             PRINTF("(2) 0x%08x ", m1);
00782             m1 = *(__IO uint32_t *)((uint32_t)0x1FFF7A18);
00783             PRINTF( "(3) 0x%08x", m1 );
00784             put_rn();
00785             break;
00786         case '?' :
00787         default:
00788             PRINTF( "sc - System CPU information" );
00789             put_rn();
00790             PRINTF( "sf - System Clock" );
00791             put_rn();
00792     }
00793 }
00794 #elif defined(TARGET_NUCLEO_L152RE)
00795 
00796 static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
00797 
00798 void cpu_inf( char *ptr )
00799 {
00800     uint32_t m1, m2, m3, m4, m5;
00801 
00802     switch (*ptr++) {
00803         case 'f' :  // sc - show system clock frequency
00804             m1 = RCC->CR;
00805             PRINTF( "CR       = 0x%08x", m1 );
00806             put_rn();
00807             m1 = RCC->ICSCR;
00808             PRINTF( "ICSCR    = 0x%08x", m1 );
00809             put_rn();
00810             m1 = RCC->CFGR;
00811             PRINTF( "CFGR     = 0x%08x", m1 );
00812             put_rn();
00813             m1 = RCC->CIR;
00814             PRINTF( "CIR      = 0x%08x", m1 );
00815             put_rn();
00816             m1 = RCC->AHBRSTR;
00817             PRINTF( "AHBRSTR  = 0x%08x", m1 );
00818             put_rn();
00819             m1 = RCC->APB2RSTR;
00820             PRINTF( "APB2RSTR = 0x%08x", m1 );
00821             put_rn();
00822             m1 = RCC->APB1RSTR;
00823             PRINTF( "APB1RSTR = 0x%08x", m1 );
00824             put_rn();
00825             m1 = RCC->AHBENR;
00826             PRINTF( "AHBENR   = 0x%08x", m1 );
00827             put_rn();
00828             m1 = RCC->APB2ENR;
00829             PRINTF( "APB2ENR  = 0x%08x", m1 );
00830             put_rn();
00831             m1 = RCC->APB2LPENR;
00832             PRINTF( "APB2LPENR= 0x%08x", m1 );
00833             put_rn();
00834             m1 = RCC->APB1LPENR;
00835             PRINTF( "APB1LPENR= 0x%08x", m1 );
00836             put_rn();
00837             m1 = RCC->CSR;
00838             PRINTF( "CSR      = 0x%08x", m1 );
00839             put_rn();
00840             PRINTF( cmsg11 );
00841             put_rn();
00842             m1 = PWR->CR;
00843             PRINTF( "CR       = 0x%08x", m1 );
00844             put_rn();
00845             m1 = PWR->CSR;
00846             PRINTF( "CSR      = 0x%08x", m1 );
00847             put_rn();
00848             put_rn();
00849         case 'F' :  // sF - show system clock frequency
00850             m1 = RCC->CFGR & RCC_CFGR_SWS;  /* Get SYSCLK source */
00851             switch (m1) {
00852                 case 0x00:  // MSI used as system clock
00853                     m4 = ( RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
00854                     m2 = (32768 * (1 << (m4 + 1)));
00855                     PRINTF( "%s, %s%dHz", cmsg0, cmsg1, m2);
00856                     break;
00857                 case 0x04:  // HSI used as system clock
00858                     PRINTF( "%s, %s%dHz", cmsg2, cmsg1,HSI_VALUE );
00859                     m2 = HSI_VALUE;
00860                     break;
00861                 case 0x08:  // HSE used as system clock
00862                     PRINTF( "%s, %s%dHz", cmsg3, cmsg1, HSE_VALUE );
00863                     m2 = HSE_VALUE;
00864                     break;
00865                 case 0x0C:  // PLL used as system clock
00866                     // Get PLL clock source and multiplication factor
00867                     m5 = RCC->CFGR & RCC_CFGR_PLLMUL;
00868                     m1 = RCC->CFGR & RCC_CFGR_PLLDIV;
00869                     m5 = PLLMulTable[(m5 >> 18)];
00870                     m1 = (m1 >> 22) + 1;
00871                     PRINTF( "%s Mul=%d, Div=%d", cmsg4, m5, m1 );
00872                     put_rn();
00873                     m3 = RCC->CFGR & RCC_CFGR_PLLSRC;
00874                     if ( m3 == 0x00 ) {
00875                         // HSI oscillator clock selected as PLL clock source
00876                         m2 = (((HSI_VALUE) * m5) / m1);
00877                         PRINTF( "%s, RC=%dHz", cmsg2, HSI_VALUE );
00878                     } else {
00879                         // HSE selected
00880                         m2 = (((HSE_VALUE) * m5) / m1);
00881                         if ((RCC->CR >> 18) & 0x01) {  // check HSEBYP bit
00882                             // HSE(not Xtal) selected as PLL clock source
00883                             PRINTF( "Use HSE(not Xtal but External Clock)=%dHz", HSE_VALUE );
00884                         } else {
00885                             // HSE(Xtal) selected as PLL clock source
00886                             PRINTF( "%s, Xtal=%dHz", cmsg3, HSE_VALUE );
00887                         }
00888                     }
00889                     put_rn();
00890                     PRINTF( "PLL %s%dHz", cmsg1, m2 );
00891                     put_rn();
00892                     break;
00893                 default:    // Not come here
00894                     PRINTF( cmsg5 );
00895                     break;
00896             }
00897             put_rn();
00898             PRINTF( "SYSCLK %s%dHz", cmsg6, HAL_RCC_GetSysClockFreq() );
00899             put_rn();
00900             PRINTF( "HCLK   %s%dHz", cmsg6, HAL_RCC_GetHCLKFreq() );
00901             put_rn();
00902             PRINTF( "PCLK1  %s%dHz", cmsg6, HAL_RCC_GetPCLK1Freq() );
00903             put_rn();
00904             PRINTF( "PCLK2  %s%dHz", cmsg6, HAL_RCC_GetPCLK2Freq() );
00905             put_rn();
00906             put_rn();
00907             m1 = RCC->CSR & RCC_CSR_RTCSEL;
00908             // Check RTC & LCD Clock
00909             PRINTF("RTC/LCD Clock");
00910             put_rn();
00911             switch (m1) {
00912                 case RCC_CSR_RTCSEL_NOCLOCK:
00913                     PRINTF( cmsg7 );
00914                     break;
00915                 case RCC_CSR_RTCSEL_LSE:
00916                     PRINTF( cmsg8 );
00917                     break;
00918                 case RCC_CSR_RTCSEL_LSI:
00919                     PRINTF("%s 26 to 56, typ.38KHz", cmsg9);
00920                     break;
00921                 case RCC_CSR_RTCSEL_HSE:
00922                     PRINTF( cmsg10 );
00923                     break;
00924                 default:    // Not come here
00925                     PRINTF( cmsg5 );
00926                     break;
00927             }
00928             put_rn();
00929             put_rn();
00930             break;
00931         case 'c' :      // sc - show system CPU information
00932             m1 = SCB->CPUID;
00933             m2 = ( m1 >> 24 );
00934             if ( m2 == 0x41 ) {
00935                 PRINTF( "CPU = ARM " );
00936             } else {
00937                 PRINTF( "CPU = NOT ARM " );
00938             }
00939             m2 = ( m1 >> 4 ) & 0xfff;
00940             if ( m2 == 0xc23 ) {
00941                 PRINTF( "Cortex-M3" );
00942             } else {
00943                 PRINTF( "NOT Cortex-M3" );
00944             }
00945             put_rn();
00946             m2 = ( m1 >> 20 ) & 0x0f;
00947             PRINTF( "Variant:%x", m2 );
00948             put_rn();
00949             m2 = m1 & 0x7;
00950             PRINTF( "Revision:%x", m2 );
00951             put_rn();
00952             PRINTF( "CPU ID: 0x%08x", m1 );
00953             put_rn();
00954             m1 = DBGMCU->IDCODE;
00955             PRINTF( "DBG ID: 0x%08x", m1 );
00956             put_rn();
00957             // unique ID
00958             // http://false.ekta.is/2013/09/stm32-unique-id-register-not-so-unique/
00959             m1 = *(__IO uint32_t *)((uint32_t)0x1FF80050);
00960             PRINTF("Unique device ID(94bits):(1) 0x%08x ", m1);
00961             m1 = *(__IO uint32_t *)((uint32_t)0x1FF80054);
00962             PRINTF("(2) 0x%08x ", m1);
00963             m1 = *(__IO uint32_t *)((uint32_t)0x1FF80058);
00964             PRINTF( "(3) 0x%08x", m1 );
00965             put_rn();
00966             break;
00967         case '?' :
00968         default:
00969             PRINTF( "sc - System CPU information" );
00970             put_rn();
00971             PRINTF( "sf - System Clock" );
00972             put_rn();
00973     }
00974 }
00975 #endif  // Select CPU
00976 
00977 //-------------------------------------------------------------------------------------------------
00978 //  Monitor Main Program
00979 //-------------------------------------------------------------------------------------------------
00980 int mon_hw(void)
00981 {
00982     char *ptr;
00983 
00984     put_r();
00985     PRINTF("%s [Help:'?' key]", mon_msg);
00986     put_rn();
00987     for (;;) {
00988         put_r();
00989         PUTC('>');
00990         ptr = linebuf;
00991         get_line(ptr, buf_size);
00992         put_r();
00993         switch (*ptr++) {
00994                 //-----------------------------------------------------------------------------------------
00995                 //    Memory
00996                 //-----------------------------------------------------------------------------------------
00997             case 'm' :
00998 #if USE_MEM
00999                 mem_inf(ptr);
01000                 put_rn();
01001 #else
01002                 not_select();
01003 #endif   // USE_MEM
01004                 break;
01005                 //-----------------------------------------------------------------------------------------
01006                 //    Register
01007                 //-----------------------------------------------------------------------------------------
01008             case 'r' :
01009                 put_r();
01010                 PRINTF(mrmsg0);
01011                 put_rn();
01012                 quitflag = 0;
01013                 for (; quitflag != 0xff;) {
01014                     PRINTF("r>");
01015                     ptr = linebuf;
01016                     get_line(ptr, buf_size);
01017                     put_r();
01018                     switch(*ptr++) {
01019                         case 'u' :
01020 #if USE_UART
01021                             switch(*ptr++) {
01022                                 case '1' :
01023                                     PRINTF("%s%s1%s", mrmsg1,mrmsg2,mrmsg1);
01024                                     usart_reg(USART1);
01025                                     break;
01026                                 case '2' :
01027                                     PRINTF("%s%s2%s", mrmsg1,mrmsg2,mrmsg1);
01028                                     usart_reg(USART2);
01029                                     break;
01030 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
01031                                 case '6' :
01032                                     PRINTF("%s%s6%s", mrmsg1,mrmsg2,mrmsg1);
01033                                     usart_reg(USART6);
01034                                     break;
01035 #elif defined(TARGET_NUCLEO_L152RE)
01036                                 case '3' :
01037                                     PRINTF("%s%s3%s", mrmsg1,mrmsg2,mrmsg1);
01038                                     usart_reg(USART3);
01039                                     break;
01040                                 case '5' :
01041                                     PRINTF("%s%s5%s", mrmsg1,mrmsg2,mrmsg1);
01042                                     usart_reg(UART5);
01043                                     break;
01044 #endif
01045                                 case '*' :
01046                                     PRINTF( "%s & UART", mrmsg2 );
01047                                     put_rn();
01048                                     PRINTF("%s%s1%s", mrmsg1,mrmsg2,mrmsg1);
01049                                     usart_reg(USART1);
01050                                     PRINTF("%s%s2%s", mrmsg1,mrmsg2,mrmsg1);
01051                                     usart_reg(USART2);
01052 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
01053                                     PRINTF("%s%s6%s", mrmsg1,mrmsg2,mrmsg1);
01054                                     usart_reg(USART6);
01055 #elif defined(TARGET_NUCLEO_L152RE)
01056                                     PRINTF("%s%s3%s", mrmsg1,mrmsg2,mrmsg1);
01057                                     usart_reg(USART3);
01058                                     PRINTF("%s%s5%s", mrmsg1,mrmsg2,mrmsg1);
01059                                     usart_reg(UART5);
01060 #endif
01061                                     break;
01062                                 case '?' :
01063                                 default:
01064                                     PRINTF( mrmsg3 );
01065                                     put_rn();
01066                             }
01067 #else
01068                             not_select();
01069 #endif // USE_UART
01070                             break;
01071                         case 'i' :
01072 #if USE_I2C
01073                             switch(*ptr++) {
01074                                 case '1' :
01075                                     PRINTF("%s%s1%s", mrmsg1,mrmsg4,mrmsg1);
01076                                     i2c_reg( I2C1 );
01077                                     break;
01078                                 case '2' :
01079                                     PRINTF("%s%s2%s", mrmsg1,mrmsg4,mrmsg1);;
01080                                     i2c_reg( I2C2 );
01081                                     break;
01082 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
01083                                 case '3' :
01084                                     PRINTF("%s%s3%s", mrmsg1,mrmsg4,mrmsg1);;
01085                                     i2c_reg( I2C3 );
01086                                     break;
01087 #endif
01088                                 case '*' :
01089                                     PRINTF(mrmsg4);
01090                                     put_rn();
01091                                     PRINTF("%s%s1%s", mrmsg1,mrmsg4,mrmsg1);
01092                                     i2c_reg( I2C1 );
01093                                     PRINTF("%s%s2%s", mrmsg1,mrmsg4,mrmsg1);
01094                                     i2c_reg( I2C2 );
01095 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
01096                                     PRINTF("%s%s3%s", mrmsg1,mrmsg4,mrmsg1);;
01097                                     i2c_reg( I2C3 );
01098 #endif
01099                                     break;
01100                                 case '?' :
01101                                 default:
01102                                     PRINTF(mrmsg5);
01103                                     put_rn();
01104                             }
01105 #else
01106                             not_select();
01107 #endif // USE_I2C
01108                             break;
01109                         case 's' :
01110 #if USE_SPI
01111                             switch(*ptr++) {
01112                                 case '1' :
01113                                     PRINTF("%s%s1%s", mrmsg1,mrmsg6,mrmsg1);
01114                                     spi_reg( SPI1 );
01115                                     break;
01116                                 case '2' :
01117                                     PRINTF("%s%s2%s", mrmsg1,mrmsg6,mrmsg1);
01118                                     spi_reg( SPI2 );
01119                                     break;
01120                                 case '3' :
01121                                     PRINTF("%s%s3%s", mrmsg1,mrmsg6,mrmsg1);
01122                                     spi_reg( SPI3 );
01123                                     break;
01124 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
01125                                 case '4' :
01126                                     PRINTF("%s%s4%s", mrmsg1,mrmsg6,mrmsg1);
01127                                     spi_reg( SPI4 );
01128                                     break;
01129 #endif
01130                                 case '*' :
01131                                     PRINTF(mrmsg6);
01132                                     put_rn();
01133                                     PRINTF("%s%s1%s", mrmsg1,mrmsg6,mrmsg1);
01134                                     spi_reg( SPI1 );
01135                                     PRINTF("%s%s2%s", mrmsg1,mrmsg6,mrmsg1);
01136                                     spi_reg( SPI2 );
01137                                     PRINTF("%s%s3%s", mrmsg1,mrmsg6,mrmsg1);
01138                                     spi_reg( SPI3 );
01139 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
01140                                     PRINTF("%s%s4%s", mrmsg1,mrmsg6,mrmsg1);
01141                                     spi_reg( SPI4 );
01142 #endif
01143                                     break;
01144                                 case '?' :
01145                                 default:
01146                                     PRINTF(mrmsg7);
01147                                     put_rn();
01148                             }
01149 #else
01150                             not_select();
01151 #endif // USE_SPI
01152                             break;
01153                         case 't' :      //
01154                             not_yet_impliment();
01155                             break;
01156                         case 'a' :      //
01157                             not_yet_impliment();
01158                             break;
01159                         case 'd' :      //
01160                             not_yet_impliment();
01161                             break;
01162                         case 'w' :      //
01163                             not_yet_impliment();
01164                             break;
01165                         case 'l' :        //
01166                             not_yet_impliment();
01167                             break;
01168                         case 'c' :      //
01169                             not_yet_impliment();
01170                             break;
01171                         case 'x' :      //
01172                             not_yet_impliment();
01173                             break;
01174                         case 'y' :      //
01175                             not_yet_impliment();
01176                             break;
01177                         case '?' :
01178                             PRINTF("u - USART");
01179                             put_rn();
01180                             PRINTF("i - I2C");
01181                             put_rn();
01182                             PRINTF("s - SPI");
01183                             put_rn();
01184                             PRINTF("t - TIMER");
01185                             put_rn();
01186                             PRINTF("a - ADC");
01187                             put_rn();
01188                             PRINTF("d - DAC");
01189                             put_rn();
01190                             PRINTF("l - LDC");
01191                             put_rn();
01192                             PRINTF("w - WWDG");
01193                             put_rn();
01194                             PRINTF("c - COMP");
01195                             put_rn();
01196                             break;
01197                         case 'q' :        // quit
01198                             quitflag = 0xff;
01199                             break;
01200                         default:
01201                             PUTC('?');
01202                             put_rn();
01203                     }
01204                 }
01205                 PRINTF(mrmsg8);
01206                 put_rn();
01207                 break;
01208                 //-----------------------------------------------------------------------------------------
01209                 //    Port
01210                 //-----------------------------------------------------------------------------------------
01211             case 'p' :
01212 #if USE_PORT
01213                 put_r();
01214                 PRINTF("Enter port a,b,c,d,e,h & * ? for help");
01215                 put_rn();
01216                 quitflag = 0;
01217                 for (; quitflag != 0xff;) {
01218                     PRINTF("p>");
01219                     ptr = linebuf;
01220                     get_line(ptr, buf_size);
01221                     put_r();
01222                     switch(*ptr) {
01223                         case 'a' :
01224                         case 'b' :
01225                         case 'c' :
01226                         case 'd' :
01227                         case 'e' :
01228                         case 'h' :
01229                             port_inf_one(ptr);
01230                             break;
01231                         case '*' :
01232                             rpt_port();
01233                             break;
01234                         case '?' :
01235                             PRINTF("port a,b,c,d,e,h & *");
01236                             put_rn();
01237                             break;
01238                         case 'q' :        // quit
01239                             quitflag = 0xff;
01240                             break;
01241                         default:
01242                             PUTC('?');
01243                             put_rn();
01244                     }
01245                 }
01246                 PRINTF(mrmsg8);
01247                 put_rn();
01248 #else
01249                 not_select();
01250 #endif // USE_PORT
01251                 break;
01252                 //-----------------------------------------------------------------------------------------
01253                 //    System
01254                 //-----------------------------------------------------------------------------------------
01255             case 's' :    // System related information
01256 #if USE_SYS
01257                 cpu_inf(ptr);
01258 #else
01259                 not_select();
01260 #endif   // USE_SYS
01261                 break;
01262                 //-----------------------------------------------------------------------------------------
01263                 //    Help
01264                 //-----------------------------------------------------------------------------------------
01265             case '?' :
01266                 hw_msg_hlp();
01267                 break;
01268                 //-----------------------------------------------------------------------------------------
01269                 //    Return to main routine
01270                 //-----------------------------------------------------------------------------------------
01271             case 'q' :        // Quit
01272                 put_r();
01273                 PRINTF("Return to monitor");
01274                 put_rn();
01275                 return 0;
01276                 //-----------------------------------------------------------------------------------------
01277                 //    Special command for DEBUG
01278                 //-----------------------------------------------------------------------------------------
01279             case 'x' :
01280                 not_yet_impliment();
01281                 break;
01282                 //-----------------------------------------------------------------------------------------
01283                 //    no support
01284                 //-----------------------------------------------------------------------------------------
01285             default:
01286                 PUTC('?');
01287                 put_rn();
01288                 break;
01289         }
01290     }
01291 }
01292 #endif  // defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_L152RE)