mon_hw_LPC1114.cpp

00001 /*
00002  * mbed Application program for the mbed LPC1114FN28
00003  * Monitor program Ver.3 for only for LPC1114FN28
00004  *
00005  *  Copyright (c) 2010-2014 Kenji Arai / JH1PJL
00006  *  http://www.page.sannet.ne.jp/kenjia/index.html
00007  *  http://mbed.org/users/kenjiArai/
00008  *      Created:  May       15th, 2010
00009  *          release as "monitor_01" http://mbed.org/users/kenjiArai/code/monitor_01/
00010  *      Spareted: June      25th, 2014      mon() & mon_hw()
00011  *      Revised:  Nobember   2nd, 2014
00012  *
00013  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
00014  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
00015  * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
00016  * DAMAGES OR OTHER  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00017  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00018  */
00019 
00020 #if defined(TARGET_LPC1114)
00021 
00022 //  Include ---------------------------------------------------------------------------------------
00023 #include "mbed.h"
00024 #include "mon_hw_config.h"
00025 #include "mon_hw_common.h"
00026 
00027 //  Object ----------------------------------------------------------------------------------------
00028 
00029 //  Definition ------------------------------------------------------------------------------------
00030 // Define clocks
00031 #define __XTAL              (12000000UL)    // Oscillator frequency
00032 #define __SYS_OSC_CLK       (    __XTAL)    // Main oscillator frequency
00033 #define __IRC_OSC_CLK       (12000000UL)    // Internal RC oscillator frequency
00034 
00035 //  RAM -------------------------------------------------------------------------------------------
00036 uint32_t SystemFrequency;
00037 
00038 //  ROM / Constant data ---------------------------------------------------------------------------
00039 #if USE_MEM
00040 //  Memory range data
00041 const uint32_t mem_range[][2] = {          // Memory access range
00042     { 0x00000000, 0x00007fff },            // On-chip non-volatile memory     //32KB Flash memory
00043     { 0x10000000, 0x10000fff },            // On-chip SRAM                    //4KB local RAM
00044     { 0x1fff0000, 0x1fff3fff },            // Boot ROM                        //16KB Boot ROM
00045     { 0x40000000, 0x4007ffff },            // IO area
00046     { 0x50000000, 0x501fffff }             // IO area
00047 };
00048 #endif  // USE_MEM
00049 
00050 char *const mon_msg = "HW monitor only for mbed LPC1114FN28 created on "__DATE__","__TIME__"";
00051 
00052 char *const xmsg0 = "Not implimented yet";
00053 
00054 char *const hmsg0 = "m  - Entry Memory Mode";
00055 char *const hmsg1 = "m>? -> Help ";
00056 char *const hmsg2 = "r  - Show PORT,I2C,SPI,UART & other Reg.";
00057 char *const hmsg3 = "r>? -> Help";
00058 char *const hmsg4 = "sf - System Clock";
00059 char *const hmsg5 = "sc - System / CPU information";
00060 char *const hmsg6 = "x  - Special command for Debug";
00061 char *const hmsg7 = "q  - Quit (back to called routine)";
00062 
00063 #if (USE_PORT==0)||(USE_UART==0)||(USE_SPI==0)||(USE_I2C==0)
00064 char *const io_port_name0 = "PIO0_";
00065 char *const io_port_name1 = "PIO1_";
00066 char *const iomsg0 = "Func->select ";
00067 char *const iomsg1 = "IO";
00068 char *const iomsg2 = "Reserved";
00069 char *const iomsg30 = "B0_MAT";
00070 char *const iomsg31 = "B1_MAT";
00071 char *const iomsg4 = "Std/F-md I2C";
00072 char *const iomsg5 = "func. R";
00073 char *const iomsg6 = "D-Mode";
00074 char *const iomsg7 = "A-Mode";
00075 #endif
00076 
00077 //  Calculate CPU System Clock Frequency /refrence: system_LPCxx.c
00078 char *const fmsg0 = "Internal RC Oscillator";
00079 char *const fmsg1 = "Xtal Osc Clock";
00080 char *const fmsg2 = "Watch dog Osc Clock";
00081 char *const fmsg3 = "with PLL";
00082 char *const fmsg4 = "System Clock =";
00083 char *const fmsg5 = "PLL Post divider ratio =";
00084 char *const fmsg6 = "feedback devider =";
00085 char *const fmsg7 = "NO Clock ?!";
00086 
00087 #if (USE_UART==1) || (USE_SPI==1) || (USE_I2C == 1)
00088 char *const imsg2 = "-->Control Reg.";
00089 char *const imsg3 = "-->Status Reg.";
00090 char *const imsg4 = "-->Data Reg.";
00091 char *const imsg5 = "-->Clock control Reg.";
00092 #endif
00093 
00094 //  Function prototypes ---------------------------------------------------------------------------
00095 
00096 //-------------------------------------------------------------------------------------------------
00097 //  Control Program
00098 //-------------------------------------------------------------------------------------------------
00099 // No function
00100 void not_yet_impliment( void )
00101 {
00102     PRINTF(xmsg0);
00103     put_rn();
00104 }
00105 
00106 // No function
00107 #if (USE_MEM==0)||(USE_PORT==0)||(USE_UART==0)||(USE_SPI==0)||(USE_I2C==0)||(USE_SYS==0)
00108 void not_select( void )
00109 {
00110     PRINTF("Not select the function (refer mon_hw_config.h)");
00111     put_rn();
00112 }
00113 #endif
00114 
00115 //  Help Massage
00116 void msg_hlp_hw (void)
00117 {
00118     PRINTF(mon_msg);
00119     put_rn();
00120     PRINTF(hmsg0);
00121     put_rn();
00122     PRINTF(hmsg1);
00123     put_rn();
00124     PRINTF(hmsg2);
00125     put_rn();
00126     PRINTF(hmsg3);
00127     put_rn();
00128     PRINTF(hmsg4);
00129     put_rn();
00130     PRINTF(hmsg5);
00131     put_rn();
00132     PRINTF(hmsg6);
00133     put_rn();
00134     PRINTF(hmsg7);
00135     put_rn();
00136 }
00137 
00138 #if USE_MEM
00139 char *const rmsg0 = "FLASH     ";
00140 char *const rmsg1 = "SRAM      ";
00141 char *const rmsg2 = "Boot ROM  ";
00142 char *const rmsg3 = "IO Area0  ";
00143 char *const rmsg4 = "IO Area1  ";
00144 
00145 #include "mon_hw_mem.h"
00146 #endif   // USE_MEM
00147 
00148 //  Show 16bit register contents
00149 void reg_print(uint16_t size, uint16_t reg)
00150 {
00151     uint16_t i, j, k, n;
00152 
00153     if (size == 8) {
00154         PRINTF(" 7, 6, 5, 4, 3, 2, 1, 0");
00155         put_rn();
00156         i = 8;
00157         n = 0x80;
00158     } else if (size == 16) {
00159         PRINTF( "15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0" );
00160         put_rn();
00161         i = 16;
00162         n = 0x8000;
00163     } else {
00164         PRINTF("0x%08x", reg);
00165         return;
00166     }
00167     PUTC(' ');
00168     for (; i>0; i--) {
00169         k = n >> (size-i);
00170         j = reg & k;
00171         if (j) {
00172             PUTC('1');
00173         } else {
00174             PUTC('0');
00175         }
00176         PUTC(' ');
00177         PUTC(' ');
00178     }
00179     PRINTF("  (0x%04x)", reg);
00180 }
00181 
00182 #if USE_PORT
00183 void io_mode(uint32_t reg)
00184 {
00185     PRINTF("MODE->");
00186     switch (reg) {
00187         case 0:
00188             PRINTF("Inactive");
00189             break;
00190         case 1:
00191             PRINTF("P-DWN");
00192             break;
00193         case 2:
00194             PRINTF("P-UP");
00195             break;
00196         case 3:
00197             PRINTF("Repeater");
00198             break;
00199     }
00200 }
00201 
00202 void io_hys(uint32_t reg)
00203 {
00204     PRINTF("HIS->");
00205     switch (reg) {
00206         case 0:
00207             PRINTF("Dis");
00208             break;
00209         case 1:
00210             PRINTF("Ena");
00211             break;
00212     }
00213 }
00214 
00215 void io_od(uint32_t reg)
00216 {
00217     PRINTF("OD->");
00218     switch (reg) {
00219         case 0:
00220             PRINTF("no OD");
00221             break;
00222         case 1:
00223             PRINTF("OD");
00224             break;
00225     }
00226 }
00227 
00228 void io_mode_hys_od(uint32_t reg)
00229 {
00230     io_mode ((reg >>  3) & 0x3);
00231     put_lin();
00232     io_hys (( reg >>  5) & 0x1);
00233     put_lin();
00234     io_od (( reg >> 10) & 0x1);
00235 }
00236 
00237 // I/O Config IO0_x
00238 void io_config0(void)
00239 {
00240     uint32_t r0;
00241 
00242     // P0_0
00243     r0 = LPC_IOCON->RESET_PIO0_0;
00244     PRINTF("RESET_%s0(dp23)", io_port_name0);
00245     put_spc(1);
00246     reg_print( SIZE_X, r0 );
00247     put_spc(2);
00248     PRINTF( iomsg0 );
00249     if ((r0 & 0x7) == 0) {
00250         PRINTF("RESET");
00251     } else {
00252         PRINTF( iomsg1 );
00253     }
00254     put_lin();
00255     io_mode_hys_od( r0 );
00256     put_rn();
00257     // P0_1
00258     r0 = LPC_IOCON->PIO0_1;
00259     PRINTF("%s1(dp24)", io_port_name0);
00260     put_spc(3);
00261     reg_print( SIZE_X, r0 );
00262     put_spc(2);
00263     PRINTF( iomsg0 );
00264     switch (r0 & 0x7) {
00265         case 0:
00266             PRINTF(iomsg1);
00267             break;
00268         case 1:
00269             PRINTF("CLKOUT");
00270             break;
00271         case 2:
00272             PRINTF("32%s2", iomsg30);
00273             break;
00274     }
00275     put_lin();
00276     io_mode_hys_od(r0);
00277     put_rn();
00278     // P0_2
00279     r0 = LPC_IOCON->PIO0_2;
00280     PRINTF("%s2(dp25)",io_port_name0);
00281     put_spc(3);
00282     reg_print(SIZE_X, r0);
00283     put_spc(2);
00284     PRINTF(iomsg0);
00285     switch (r0 & 0x7) {
00286         case 0:
00287             PRINTF(iomsg1);
00288             break;
00289         case 1:
00290             PRINTF("SSEL0");
00291             break;
00292         case 2:
00293             PRINTF("16B0_CAP0");
00294             break;
00295     }
00296     put_lin();
00297     io_mode_hys_od(r0);
00298     put_rn();
00299     // P0_3
00300     r0 = LPC_IOCON->PIO0_3;
00301     PRINTF("%s3(dp26)",io_port_name0);
00302     put_spc(3);
00303     reg_print(SIZE_X, r0);
00304     put_spc(2);
00305     PRINTF(iomsg0);
00306     switch (r0 & 0x7) {
00307         case 0:
00308             PRINTF(iomsg1);
00309             break;
00310     }
00311     put_lin();
00312     io_mode_hys_od(r0);
00313     put_rn();
00314     // P0_4
00315     r0 = LPC_IOCON->PIO0_4;
00316     PRINTF("%s4(dp27)",io_port_name0);
00317     put_spc(3);
00318     reg_print(SIZE_X, r0);
00319     put_spc(2);
00320     PRINTF(iomsg0);
00321     switch (r0 & 0x7) {
00322         case 0:
00323             PRINTF(iomsg1);
00324             break;
00325         case 1:
00326             PRINTF("SCL");
00327             break;
00328     }
00329     put_lin();
00330     switch (( r0 >> 8 ) & 0x3) {
00331         case 0:
00332             PRINTF(iomsg4);
00333             break;
00334         case 1:
00335             PRINTF(iomsg1);
00336             break;
00337         case 2:
00338             PRINTF("Fast md");
00339             break;
00340         case 3:
00341             PRINTF(iomsg2);
00342             break;
00343     }
00344     put_rn();
00345     // P0_5
00346     r0 = LPC_IOCON->PIO0_5;
00347     PRINTF("%s5(dp5)",io_port_name0);
00348     put_spc(4);
00349     reg_print(SIZE_X, r0);
00350     put_spc(2);
00351     PRINTF(iomsg0);
00352     switch (r0 & 0x7) {
00353         case 0:
00354             PRINTF(iomsg1);
00355             break;
00356         case 1:
00357             PRINTF("SDA");
00358             break;
00359     }
00360     put_lin();
00361     switch ( ( r0 >> 8 ) & 0x3 ) {
00362         case 0:
00363             PRINTF(iomsg4);
00364             break;
00365         case 1:
00366             PRINTF(iomsg1);
00367             break;
00368         case 2:
00369             PRINTF("Fast md");
00370             break;
00371         case 3:
00372             PRINTF(iomsg2);
00373             break;
00374     }
00375     put_rn();
00376     // P0_6
00377     r0 = LPC_IOCON->PIO0_6;
00378     PRINTF("%s6(dp6)", io_port_name0);
00379     put_spc(4);
00380     reg_print(SIZE_X, r0);
00381     put_spc(2);
00382     PRINTF(iomsg0);
00383     switch (r0 & 0x7) {
00384         case 0:
00385             PRINTF(iomsg1);
00386             break;
00387         case 1:
00388             PRINTF(iomsg2);
00389             break;
00390         case 2:
00391             PRINTF("SCK0");
00392             break;
00393     }
00394     put_lin();
00395     io_mode_hys_od(r0);
00396     put_rn();
00397     // P0_7
00398     r0 = LPC_IOCON->PIO0_7;
00399     PRINTF("%s7(dp28)", io_port_name0);
00400     put_spc(3);
00401     reg_print(SIZE_X, r0);
00402     put_spc(2);
00403     PRINTF(iomsg0);
00404     switch (r0 & 0x7) {
00405         case 0:
00406             PRINTF(iomsg1);
00407             break;
00408         case 1:
00409             PRINTF("CTS");
00410             break;
00411     }
00412     put_lin();
00413     io_mode_hys_od(r0);
00414     put_rn();
00415     // P0_8
00416     r0 = LPC_IOCON->PIO0_8;
00417     PRINTF("%s8(dp1)", io_port_name0);
00418     put_spc(4);
00419     reg_print(SIZE_X, r0);
00420     put_spc(2);
00421     PRINTF(iomsg0);
00422     switch (r0 & 0x7) {
00423         case 0:
00424             PRINTF(iomsg1);
00425             break;
00426         case 1:
00427             PRINTF("MISO0");
00428             break;
00429         case 2:
00430             PRINTF("16%s0", iomsg30);
00431             break;
00432     }
00433     put_lin();
00434     io_mode_hys_od(r0);
00435     put_rn();
00436     // P0_9
00437     r0 = LPC_IOCON->PIO0_9;
00438     PRINTF("%s9(dp2)", io_port_name0);
00439     put_spc(4);
00440     reg_print(SIZE_X, r0);
00441     put_spc(2);
00442     PRINTF(iomsg0);
00443     switch (r0 & 0x7) {
00444         case 0:
00445             PRINTF(iomsg1);
00446             break;
00447         case 1:
00448             PRINTF("MOSI0");
00449             break;
00450         case 2:
00451             PRINTF("16%s1", iomsg30);
00452             break;
00453     }
00454     put_lin();
00455     io_mode_hys_od(r0);
00456     put_rn();
00457     // P0_10
00458     r0 = LPC_IOCON->SWCLK_PIO0_10;
00459     PRINTF("SWCLK_%s10(dp3)", io_port_name0);
00460     put_spc(1);
00461     reg_print(SIZE_X, r0);
00462     put_spc(2);
00463     PRINTF(iomsg0);
00464     switch (r0 & 0x7) {
00465         case 0:
00466             PRINTF("SWCLK");
00467             break;
00468         case 1:
00469             PRINTF(iomsg1);
00470             break;
00471         case 2:
00472             PRINTF("SCK0");
00473             break;
00474         case 3:
00475             PRINTF("16%s2", iomsg30);
00476             break;
00477     }
00478     put_lin();
00479     io_mode_hys_od(r0);
00480     put_rn();
00481     // P0_11
00482     r0 = LPC_IOCON->R_PIO0_11;
00483     PRINTF("R_%s11(dp4)", io_port_name0);
00484     put_spc(1);
00485     reg_print(SIZE_X, r0);
00486     put_spc(2);
00487     PRINTF( iomsg0 );
00488     switch ( r0 & 0x7 ) {
00489         case 0:
00490             PRINTF(iomsg5);
00491             break;
00492         case 1:
00493             PRINTF(iomsg1);
00494             break;
00495         case 2:
00496             PRINTF("AD0");
00497             break;
00498         case 3:
00499             PRINTF("32%s3", iomsg30);
00500             break;
00501     }
00502     put_lin();
00503     io_mode_hys_od(r0);
00504     if ( r0 & 0x80 ) {
00505         PRINTF(", %s", iomsg6);
00506     } else {
00507         PRINTF(", %s", iomsg7);
00508     }
00509     put_rn();
00510 }
00511 
00512 // I/O Config IO1_x
00513 void io_config1(void)
00514 {
00515     uint32_t r0;
00516 
00517     // P1_0
00518     r0 = LPC_IOCON->R_PIO1_0;
00519     PRINTF("R_%s0(dp9)", io_port_name1);
00520     put_spc(2);
00521     reg_print(SIZE_X, r0);
00522     put_spc(2);
00523     PRINTF( iomsg0 );
00524     switch ( r0 & 0x7 ) {
00525         case 0:
00526             PRINTF(iomsg5);
00527             break;
00528         case 1:
00529             PRINTF(iomsg1);
00530             break;
00531         case 2:
00532             PRINTF("AD1");
00533             break;
00534         case 3:
00535             PRINTF("32B1_CAP0");
00536             break;
00537     }
00538     io_mode_hys_od(r0);
00539     if (r0 & 0x80) {
00540         PRINTF(", %s", iomsg6);
00541     } else {
00542         PRINTF(", %s", iomsg7);
00543     }
00544     put_rn();
00545     // P1_1
00546     r0 = LPC_IOCON->R_PIO1_1;
00547     PRINTF("R_%s1(dp10)", io_port_name1);
00548     put_spc(1);
00549     reg_print(SIZE_X, r0);
00550     put_spc(2);
00551     PRINTF(iomsg0);
00552     switch (r0 & 0x7) {
00553         case 0:
00554             PRINTF(iomsg5);
00555             break;
00556         case 1:
00557             PRINTF(iomsg1);
00558             break;
00559         case 2:
00560             PRINTF("AD2");
00561             break;
00562         case 3:
00563             PRINTF("32%s0", iomsg31);
00564             break;
00565     }
00566     io_mode_hys_od(r0);
00567     if (r0 & 0x80) {
00568         PRINTF(", %s", iomsg6);
00569     } else {
00570         PRINTF(", %s", iomsg7);
00571     }
00572     put_rn();
00573     // P1_2
00574     r0 = LPC_IOCON->R_PIO1_2;
00575     PRINTF("R_%s2(dp11)", io_port_name1);
00576     put_spc(1);
00577     reg_print(SIZE_X, r0);
00578     put_spc(2);
00579     PRINTF(iomsg0);
00580     switch (r0 & 0x7) {
00581         case 0:
00582             PRINTF(iomsg5);
00583             break;
00584         case 1:
00585             PRINTF(iomsg1);
00586             break;
00587         case 2:
00588             PRINTF("AD3");
00589             break;
00590         case 3:
00591             PRINTF("32%s1", iomsg31);
00592             break;
00593     }
00594     io_mode_hys_od( r0 );
00595     if (r0 & 0x80) {
00596         PRINTF(", %s", iomsg6);
00597     } else {
00598         PRINTF(", %s", iomsg7);
00599     }
00600     put_rn();
00601     // P1_3
00602     r0 = LPC_IOCON->SWDIO_PIO1_3;
00603     PRINTF("SWDIO_%s3(dp12)",io_port_name1);
00604     put_spc(1);
00605     reg_print(SIZE_X, r0);
00606     put_spc(3);
00607     PRINTF(iomsg0);
00608     switch (r0 & 0x7) {
00609         case 0:
00610             PRINTF("SWDIO");
00611             break;
00612         case 1:
00613             PRINTF(iomsg1);
00614             break;
00615         case 2:
00616             PRINTF("AD4");
00617             break;
00618         case 3:
00619             PRINTF("32%s2", iomsg31);
00620             break;
00621     }
00622     io_mode_hys_od(r0);
00623     if (r0 & 0x80) {
00624         PRINTF(", %s", iomsg6);
00625     } else {
00626         PRINTF(", %s", iomsg7);
00627     }
00628     put_rn();
00629     // P1_4
00630     r0 = LPC_IOCON->PIO1_4;
00631     PRINTF("%s4(dp13)",io_port_name1);
00632     put_spc(3);
00633     reg_print(SIZE_X, r0);
00634     put_spc(2);
00635     PRINTF( iomsg0 );
00636     switch (r0 & 0x7) {
00637         case 0:
00638             PRINTF(iomsg1);
00639             break;
00640         case 1:
00641             PRINTF("AD5");
00642             break;
00643         case 2:
00644             PRINTF("32%s3", iomsg31);
00645             break;
00646     }
00647     put_lin();
00648     io_mode_hys_od(r0);
00649     put_rn();
00650     // P1_5
00651     r0 = LPC_IOCON->PIO1_5;
00652     PRINTF("%s5(dp14)",io_port_name1);
00653     put_spc(3);
00654     reg_print(SIZE_X, r0);
00655     put_spc(2);
00656     PRINTF(iomsg0);
00657     switch (r0 & 0x7) {
00658         case 0:
00659             PRINTF(iomsg1);
00660             break;
00661         case 1:
00662             PRINTF("RTS");
00663             break;
00664         case 2:
00665             PRINTF("32B0_CAP0");
00666             break;
00667     }
00668     put_lin();
00669     io_mode_hys_od(r0);
00670     put_rn();
00671     // P1_6
00672     r0 = LPC_IOCON->PIO1_6;
00673     PRINTF("%s6(dp15)", io_port_name1);
00674     put_spc(3);
00675     reg_print(SIZE_X, r0);
00676     put_spc(2);
00677     PRINTF(iomsg0);
00678     switch (r0 & 0x7) {
00679         case 0:
00680             PRINTF(iomsg1);
00681             break;
00682         case 1:
00683             PRINTF("RXD");
00684             break;
00685         case 2:
00686             PRINTF( "32%s0", iomsg30 );
00687             break;
00688     }
00689     put_lin();
00690     io_mode_hys_od( r0 );
00691     put_rn();
00692     // P1_7
00693     r0 = LPC_IOCON->PIO1_7;
00694     PRINTF("%s7(dp16)", io_port_name1);
00695     put_spc(3);
00696     reg_print(SIZE_X, r0);
00697     put_spc(2);
00698     PRINTF(iomsg0);
00699     switch (r0 & 0x7) {
00700         case 0:
00701             PRINTF(iomsg1);
00702             break;
00703         case 1:
00704             PRINTF("TXD");
00705             break;
00706         case 2:
00707             PRINTF("32%s1", iomsg30);
00708             break;
00709     }
00710     put_lin();
00711     io_mode_hys_od(r0);
00712     put_rn();
00713     // P1_8
00714     r0 = LPC_IOCON->PIO1_8;
00715     PRINTF("%s8(dp17)", io_port_name1);
00716     put_spc(3);
00717     reg_print(SIZE_X, r0);
00718     put_spc(2);
00719     PRINTF(iomsg0);
00720     switch (r0 & 0x7) {
00721         case 0:
00722             PRINTF(iomsg1);
00723             break;
00724         case 1:
00725             PRINTF("32%s1", iomsg30);
00726             break;
00727     }
00728     put_lin();
00729     io_mode_hys_od(r0);
00730     put_rn();
00731     // P1_9
00732     r0 = LPC_IOCON->PIO1_9;
00733     PRINTF("%s9(dp18)", io_port_name1);
00734     put_spc(3);
00735     reg_print(SIZE_X, r0);
00736     put_spc(2);
00737     PRINTF(iomsg0);
00738     switch (r0 & 0x7) {
00739         case 0:
00740             PRINTF(iomsg1);
00741             break;
00742         case 1:
00743             PRINTF("16%s0", iomsg31);
00744             break;
00745         case 2:
00746             PRINTF("MOSI1");
00747             break;
00748     }
00749     put_lin();
00750     io_mode_hys_od(r0);
00751     put_rn();
00752 }
00753 #endif  // USE_PORT
00754 
00755 #if USE_SPI
00756 void spi_reg(int no)
00757 {
00758     uint32_t n, r0, r1 ,r2, r3, r4, r5, r6, r7, r8;
00759 
00760     if (no == SPI_0) {
00761         n = 0;
00762         r0 = LPC_SSP0->CR1;
00763         r1 = LPC_SSP0->DR;
00764         r2 = LPC_SSP0->SR;
00765         r3 = LPC_SSP0->CPSR;
00766         r4 = LPC_SSP0->IMSC;
00767         r5 = LPC_SSP0->RIS;
00768         r6 = LPC_SSP0->MIS;
00769         r7 = LPC_SSP0->ICR;
00770         r8 = LPC_SSP0->CR0;
00771     } else if (no == SPI_1) {
00772         n = 1;
00773         r0 = LPC_SSP1->CR1;
00774         r1 = LPC_SSP1->DR;
00775         r2 = LPC_SSP1->SR;
00776         r3 = LPC_SSP1->CPSR;
00777         r4 = LPC_SSP1->IMSC;
00778         r5 = LPC_SSP1->RIS;
00779         r6 = LPC_SSP1->MIS;
00780         r7 = LPC_SSP1->ICR;
00781         r8 = LPC_SSP1->CR0;
00782     } else {
00783         return;
00784     }
00785     PRINTF("Show SSP%1d(SPI%1d) Registers", n, n);
00786     put_rn();
00787     PRINTF("CR0");
00788     PRINTF(imsg2);
00789     reg_print(SIZE8, r8);
00790     put_rn();
00791     PRINTF("CR1");
00792     PRINTF(imsg2);
00793     reg_print(SIZE8, r0);
00794     put_rn();
00795     PRINTF("DR");
00796     PRINTF(imsg4);
00797     reg_print(SIZE8, r1);
00798     put_rn();
00799     PRINTF("SR");
00800     PRINTF(imsg3);
00801     reg_print(SIZE8, r2);
00802     put_rn();
00803     PRINTF("CPSR");
00804     PRINTF(imsg5);
00805     reg_print(SIZE8, r3);
00806     put_rn();
00807     PRINTF("IMSC");
00808     PRINTF(imsg2);
00809     reg_print(SIZE8, r4);
00810     put_rn();
00811     PRINTF("RIS");
00812     PRINTF(imsg3);
00813     reg_print(SIZE8, r5);
00814     put_rn();
00815     PRINTF("MIS");
00816     PRINTF(imsg3);
00817     reg_print(SIZE8, r6);
00818     put_rn();
00819     PRINTF("ICR");
00820     PRINTF(imsg2);
00821     reg_print(SIZE8, r7);
00822     put_rn();
00823 }
00824 #endif  //USE_SPI
00825 
00826 #if USE_UART
00827 void uart_reg(void)
00828 {
00829     uint32_t r0,r1,r2,r3,r4,r5,r6;
00830 
00831     // clear LCR[DLAB] to read registers
00832     LPC_UART->LCR &= ~(1 << 7);
00833     r0 = LPC_UART->RBR;
00834     r1 = LPC_UART->IER;
00835     r2 = LPC_UART->IIR;
00836     r3 = LPC_UART->TER;
00837     // set LCR[DLAB] to enable writing to divider registers
00838     LPC_UART->LCR |= (1 << 7);
00839     r4 = LPC_UART->DLL;
00840     r5 = LPC_UART->DLM;
00841     r6 = LPC_UART->FDR;
00842     // clear LCR[DLAB]
00843     LPC_UART->LCR &= ~(1 << 7);
00844     // Print each register
00845     PRINTF("Show UART Registers");
00846     put_rn();
00847     PRINTF("RBR");
00848     PRINTF(imsg4);
00849     reg_print(SIZE8, r0);
00850     put_rn();
00851     PRINTF("THR--Write only");
00852     PRINTF(imsg4);
00853     put_rn();
00854     PRINTF("DLL");
00855     PRINTF(imsg2);
00856     reg_print(SIZE8, r4);
00857     put_rn();
00858     PRINTF("DLM");
00859     PRINTF(imsg2);
00860     reg_print(SIZE8, r5);
00861     put_rn();
00862     PRINTF("IER");
00863     PRINTF(imsg2);
00864     reg_print(SIZE8, r1);
00865     put_rn();
00866     PRINTF("IIR");
00867     PRINTF(imsg2);
00868     reg_print(SIZE8, r2);
00869     put_rn();
00870     PRINTF("FCR--Write only");
00871     PRINTF(imsg2);
00872     put_rn();
00873     PRINTF("LCR,MCR,MSR,SCR,ACR--Not support");
00874     put_rn();
00875     PRINTF("FDR");
00876     PRINTF(imsg2);
00877     reg_print(SIZE8, r6);
00878     put_rn();
00879     PRINTF("TER");
00880     PRINTF(imsg3);
00881     reg_print(SIZE8, r3);
00882     put_rn();
00883     PRINTF("RS485CTRL,485ADRMATCH,485DLY--Not support");
00884     put_rn();
00885 }
00886 #endif  //USE_UART
00887 
00888 //#if USE_SYS
00889 void cpu_inf (void)
00890 {
00891     unsigned long m1, m2;
00892 
00893     m1 = SCB->CPUID;
00894     m2 = (m1 >> 24);
00895     if (m2 == 0x41) {
00896         put_r();
00897         PRINTF("CPU = ARM ");
00898     } else {
00899         put_r();
00900         PRINTF("CPU = NOT ARM ");
00901     }
00902     m2 = (m1 >> 4) & 0xfff;
00903     if (m2 == 0xc23) {
00904         PRINTF("Cortex-M3");
00905         put_rn();
00906     } else if (m2 == 0xc20) {
00907         PRINTF("Cortex-M0");
00908         put_rn();
00909     } else {
00910         PRINTF("NOT Cortex-M3,M0");
00911         put_rn();
00912     }
00913     m2 = (m1 >> 20) & 0x0f;
00914     PRINTF("Variant:%x", m2);
00915     put_rn();
00916     m2 = m1 & 0x7;
00917     PRINTF("Revision:%x", m2);
00918     put_rn();
00919 #if 0
00920     // unique ID
00921     // http://nemuisan.blog.bai.ne.jp/?eid=192845
00922     m1 = *(__IO uint32_t *)((uint32_t)0x1FFF7A22);
00923     PRINTF("Unique device ID(94bits):(1) 0x%08x ", m1);
00924     m1 = *(__IO uint32_t *)((uint32_t)0x1FFF7A26);
00925     PRINTF("(2) 0x%08x ", m1);
00926     m1 = *(__IO uint32_t *)((uint32_t)0x1FFF7A2A);
00927     PRINTF( "(3) 0x%08x", m1 );
00928     put_rn();
00929 //    m1 = DBGMCU->IDCODE;
00930 //    PRINTF( "DBG ID: 0x%08x", m1 );
00931 #endif
00932 }
00933 
00934 //  Calculate CPU System Clock Frequency
00935 void get_freq(int pr)
00936 {
00937     uint32_t wdt_osc = 0, pll_fct0 = 0, pll_fct1 = 0;
00938 
00939     // Determine clock frequency according to clock register values
00940     switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
00941         case 0:
00942             wdt_osc =  400000;
00943             break;
00944         case 1:
00945             wdt_osc =  500000;
00946             break;
00947         case 2:
00948             wdt_osc =  800000;
00949             break;
00950         case 3:
00951             wdt_osc = 1100000;
00952             break;
00953         case 4:
00954             wdt_osc = 1400000;
00955             break;
00956         case 5:
00957             wdt_osc = 1600000;
00958             break;
00959         case 6:
00960             wdt_osc = 1800000;
00961             break;
00962         case 7:
00963             wdt_osc = 2000000;
00964             break;
00965         case 8:
00966             wdt_osc = 2200000;
00967             break;
00968         case 9:
00969             wdt_osc = 2400000;
00970             break;
00971         case 10:
00972             wdt_osc = 2600000;
00973             break;
00974         case 11:
00975             wdt_osc = 2700000;
00976             break;
00977         case 12:
00978             wdt_osc = 2900000;
00979             break;
00980         case 13:
00981             wdt_osc = 3100000;
00982             break;
00983         case 14:
00984             wdt_osc = 3200000;
00985             break;
00986         case 15:
00987             wdt_osc = 3400000;
00988             break;
00989     }
00990     wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
00991     put_r();
00992     switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
00993         case 0:                             // Internal RC oscillator
00994             SystemCoreClock = __IRC_OSC_CLK;
00995             if(pr) {
00996                 PRINTF("%s = %dHz", fmsg0, SystemCoreClock);
00997             }
00998             break;
00999         case 1:                             // Input Clock to System PLL
01000             switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
01001                 case 0:                         // Internal RC oscillator
01002                     SystemCoreClock = __IRC_OSC_CLK;
01003                     if(pr) {
01004                         PRINTF("%s = %dHz", fmsg0, SystemCoreClock);
01005                     }
01006                     break;
01007                 case 1:                         // System oscillator
01008                     SystemCoreClock = __SYS_OSC_CLK;
01009                     if(pr) {
01010                         PRINTF("%s = %dHz", fmsg1, SystemCoreClock );
01011                     }
01012                     break;
01013                 case 2:                         // WDT Oscillator
01014                     SystemCoreClock = wdt_osc;
01015                     if(pr) {
01016                         PRINTF("%s = %dHz", fmsg2, wdt_osc );
01017                     }
01018                     break;
01019                 case 3:                         // Reserved
01020                     SystemCoreClock = 0;
01021                     if(pr) {
01022                         PRINTF(fmsg7);
01023                     }
01024                     break;
01025             }
01026             break;
01027         case 2:                             // WDT Oscillator
01028             SystemCoreClock = wdt_osc;
01029             if(pr) {
01030                 PRINTF("%s = %dHz", fmsg2, wdt_osc );
01031             }
01032             break;
01033         case 3:                             // System PLL Clock Out
01034             switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
01035                 case 0:                         // Internal RC oscillator
01036                     if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
01037                         SystemCoreClock = __IRC_OSC_CLK;
01038                         if(pr) {
01039                             PRINTF("%s = %dHz", fmsg0, SystemCoreClock);
01040                         }
01041                     } else {
01042                         pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1;
01043                         pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL;
01044                         SystemCoreClock = __IRC_OSC_CLK *  pll_fct0;
01045                         if(pr) {
01046                             PRINTF("Use Internal RC = %dHz", __IRC_OSC_CLK);
01047                             put_rn();
01048                             PRINTF("%s %s = %dHz", fmsg0, fmsg3, SystemCoreClock);
01049                             put_rn();
01050                             PRINTF("%s %d, %s %d", fmsg5, pll_fct1, fmsg6, pll_fct0);
01051                         }
01052                     }
01053                     break;
01054                 case 1:                         // System oscillator
01055                     if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
01056                         SystemCoreClock = __SYS_OSC_CLK;
01057                         if(pr) {
01058                             PRINTF("%s = %dHz", fmsg1, SystemCoreClock );
01059                         }
01060                     } else {
01061                         pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1;
01062                         pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL;
01063                         SystemCoreClock = __SYS_OSC_CLK * pll_fct0;
01064                         if(pr) {
01065                             PRINTF("Use XTAL = %dHz", __XTAL);
01066                             put_rn();
01067                             PRINTF("%s %s = %dHz", fmsg1, fmsg3, SystemCoreClock);
01068                             put_rn();
01069                             PRINTF("%s %d, %s %d", fmsg5, pll_fct1, fmsg6, pll_fct0);
01070                         }
01071                     }
01072                     break;
01073                 case 2:                         // WDT Oscillator
01074                     if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
01075                         SystemCoreClock = wdt_osc;
01076                         if(pr) {
01077                             PRINTF("%s = %dHz", fmsg2, wdt_osc );
01078                         }
01079                     } else {
01080                         pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1;
01081                         pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL;
01082                         SystemCoreClock = wdt_osc *  pll_fct0;
01083                         if(pr) {
01084                             PRINTF("Use WDT OSC = %dHz", wdt_osc);
01085                             put_rn();
01086                             PRINTF("%s %s = %dHz", fmsg2, fmsg3, SystemCoreClock);
01087                             put_rn();
01088                             PRINTF("%s %d, %s %d", fmsg5, pll_fct1, fmsg6, pll_fct0);
01089                         }
01090                     }
01091                     break;
01092                 case 3:                         // Reserved
01093                     SystemCoreClock = 0;
01094                     if(pr) {
01095                         PRINTF("fmsg7");
01096                     }
01097                     break;
01098             }
01099             break;
01100     }
01101     SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
01102     if(pr) {
01103         put_rn();
01104         PRINTF("%s %dHz", fmsg4, SystemCoreClock);
01105         put_rn();
01106     }
01107 }
01108 //#endif  //USE_SYS
01109 
01110 #if USE_I2C
01111 void i2c_io_reg (void)
01112 {
01113     uint32_t r0;
01114 
01115     PRINTF("<Show IO Pin>");
01116     put_rn();
01117     // P0_4
01118     r0 = LPC_IOCON->PIO0_4;
01119     reg_print(SIZE_X, r0);
01120     put_spc(2);
01121     PRINTF("%s4(dp27)",io_port_name0);
01122     put_spc(2);
01123     PRINTF(iomsg0);
01124     switch (r0 & 0x7) {
01125         case 0:
01126             PRINTF(iomsg1);
01127             break;
01128         case 1:
01129             PRINTF("SCL");
01130             break;
01131     }
01132     put_lin();
01133     switch (( r0 >> 8 ) & 0x3) {
01134         case 0:
01135             PRINTF(iomsg4);
01136             break;
01137         case 1:
01138             PRINTF(iomsg1);
01139             break;
01140         case 2:
01141             PRINTF("Fast md");
01142             break;
01143         case 3:
01144             PRINTF(iomsg2);
01145             break;
01146     }
01147     put_rn();
01148     // P0_5
01149     r0 = LPC_IOCON->PIO0_5;
01150     reg_print( SIZE_X, r0 );
01151     put_spc(2);
01152     PRINTF("%s5(dp5)",io_port_name0);
01153     put_spc(3);
01154     PRINTF(iomsg0);
01155     switch (r0 & 0x7) {
01156         case 0:
01157             PRINTF(iomsg1);
01158             break;
01159         case 1:
01160             PRINTF("SDA");
01161             break;
01162     }
01163     put_lin();
01164     switch ((r0 >> 8 ) & 0x3) {
01165         case 0:
01166             PRINTF(iomsg4);
01167             break;
01168         case 1:
01169             PRINTF(iomsg1);
01170             break;
01171         case 2:
01172             PRINTF("Fast md");
01173             break;
01174         case 3:
01175             PRINTF(iomsg2);
01176             break;
01177     }
01178     put_rn();
01179 }
01180 
01181 void i2c_reg (void)
01182 {
01183     uint32_t r0,r1,r2,r3,r4,r5,r6,r7;
01184 
01185     r0 = LPC_I2C->CONSET;
01186     r1 = LPC_I2C->STAT;
01187     r2 = LPC_I2C->DAT;
01188     r3 = LPC_I2C->SCLH;
01189     r4 = LPC_I2C->SCLL;
01190     r5 = LPC_I2C->CONCLR;
01191     r6 = LPC_I2C->MMCTRL;
01192     r7 = LPC_I2C->DATA_BUFFER;
01193 
01194     PRINTF("<Show I2C Registers>");
01195     put_rn();
01196     reg_print(SIZE8, r0);
01197     put_spc(2);
01198     PRINTF("CONSET");
01199     PRINTF(imsg2);
01200     put_rn();
01201     reg_print(SIZE8, r1);
01202     put_spc(2);
01203     PRINTF("STAT");
01204     PRINTF(imsg3);
01205     put_rn();
01206     reg_print(SIZE8, r2);
01207     put_spc(2);
01208     PRINTF("DAT");
01209     PRINTF(imsg4);
01210     put_rn();
01211     put_spc(2);
01212     PRINTF("ADR0--Not support");
01213     put_rn();
01214     reg_print(SIZE8, r3);
01215     put_spc(2);
01216     PRINTF("SCLH");
01217     PRINTF(imsg2);
01218     put_rn();
01219     reg_print(SIZE8, r4);
01220     put_spc(2);
01221     PRINTF("SCLL");
01222     PRINTF(imsg2);
01223     put_rn();
01224     reg_print(SIZE8, r5);
01225     put_spc(2);
01226     PRINTF("CONCLR");
01227     PRINTF(imsg2);
01228     put_rn();
01229     reg_print(SIZE8, r6);
01230     put_spc(2);
01231     PRINTF("MMCTRL");
01232     PRINTF(imsg2);
01233     put_rn();
01234     put_spc(2);
01235     PRINTF("ADR1,2,3--Not support");
01236     put_rn();
01237     reg_print(SIZE8, r7);
01238     put_spc(2);
01239     PRINTF("DATA_BUFFER");
01240     PRINTF(imsg5);
01241     put_rn();
01242     put_spc(2);
01243     PRINTF("MASK0,1,2,3--Not support");
01244     put_rn();
01245 }
01246 
01247 void i2c_freq (void)
01248 {
01249     uint32_t r0,r1;
01250 
01251     r0 = LPC_I2C->SCLH;
01252     r1 = LPC_I2C->SCLL;
01253     get_freq(0);
01254     PRINTF("<I2C Status>");
01255     put_rn();
01256     PRINTF("Freq. = I2CPCLK/(SCLH+SCLL) = %d/(%d+%d) = %d Hz",
01257            SystemCoreClock, r0, r1, SystemCoreClock/(r0+r1));
01258     put_rn();
01259     r0 = LPC_I2C->CONSET;
01260     PRINTF("I2C I/F ");
01261     if ( r0 & 0x40 ) {
01262         PRINTF("Enabled");
01263     } else {
01264         PRINTF("disabled");
01265     }
01266     put_rn();
01267 }
01268 #endif
01269 
01270 //-------------------------------------------------------------------------------------------------
01271 //  Monitor Main Program
01272 //-------------------------------------------------------------------------------------------------
01273 int mon_hw (void)
01274 {
01275     char *ptr;
01276 
01277     put_r();
01278     PRINTF("%s [Help:'?' key]", mon_msg);
01279     put_rn();
01280 #if USE_SYS
01281     get_freq(0);
01282 #endif      //USE_SYS
01283     for (;;) {
01284         put_r();
01285         PUTC('>');
01286         ptr = linebuf;
01287         get_line(ptr, buf_size);
01288         switch (*ptr++) {
01289                 //---------------------------------------------------------------------------------
01290                 //    Memory
01291                 //---------------------------------------------------------------------------------
01292             case 'm' :
01293 #if USE_MEM
01294                 mem_inf(ptr);
01295                 put_rn();
01296                 break;
01297 #else
01298                 not_select();
01299 #endif   // USE_MEM
01300                 //---------------------------------------------------------------------------------
01301                 //    Register
01302                 //---------------------------------------------------------------------------------
01303             case 'r' :
01304                 uint8_t  r_flg;
01305                 put_r();
01306                 PRINTF("Reg. Mode p,u,i,s,t,a,d,l,w,c & ?");
01307                 put_rn();
01308                 r_flg = 0;
01309                 for (; r_flg != 0xff;) {
01310                     PRINTF("r>");
01311                     ptr = linebuf;
01312                     get_line(ptr, buf_size);
01313                     put_r();
01314                     switch(*ptr++) {
01315                         case 'p' :
01316 #if USE_PORT
01317                             put_r();
01318                             switch(*ptr++) {
01319                                 case '0' :
01320                                     io_config0();
01321                                     break;
01322                                 case '1' :
01323                                     io_config1();
01324                                     break;
01325                                 case '*' :
01326                                     io_config0();
01327                                     put_rn();
01328                                     io_config1();
01329                                     break;
01330                                 case '?' :
01331                                 default:
01332                                     PRINTF("Enter p0,p1 and p* for all");
01333                                     put_rn();
01334                             }
01335 #else
01336                             not_select();
01337 #endif // USE_PORT
01338                             break;
01339                         case 'u' :
01340 #if USE_UART
01341                             uart_reg();
01342 #else
01343                             not_select();
01344 #endif // USE_UART
01345                             break;
01346                         case 'i' :
01347 #if USE_I2C
01348                             put_r();
01349                             i2c_io_reg();
01350                             i2c_reg();
01351                             i2c_freq();
01352 #else
01353                             not_select();
01354 #endif // USE_I2C
01355                             break;
01356                         case 's' :
01357 #if USE_SPI
01358                             switch(*ptr++) {
01359                                 case '0' :
01360                                     spi_reg(SPI_0);
01361                                     break;
01362                                 case '1' :
01363                                     spi_reg(SPI_1);
01364                                     break;
01365                                 case '*' :
01366                                     spi_reg(SPI_0);
01367                                     put_rn();
01368                                     spi_reg( SPI_1 );
01369                                     break;
01370                                 case '?' :
01371                                 default:
01372                                     PRINTF("Enter s0,s1 and s* for all");
01373                                     put_rn();
01374                             }
01375 #else
01376                             not_select();
01377 #endif // USE_SPI
01378                             break;
01379                         case 't' :      //
01380                             not_yet_impliment();
01381                             break;
01382                         case 'a' :      //
01383                             not_yet_impliment();
01384                             break;
01385                         case 'd' :      //
01386                             not_yet_impliment();
01387                             break;
01388                         case 'w' :      //
01389                             not_yet_impliment();
01390                             break;
01391                         case 'l' :        //
01392                             not_yet_impliment();
01393                             break;
01394                         case 'c' :      //
01395                             not_yet_impliment();
01396                             break;
01397                         case 'x' :      //
01398                             not_yet_impliment();
01399                             break;
01400                         case 'y' :      //
01401                             not_yet_impliment();
01402                             break;
01403                         case 'q' :        // quit
01404                             r_flg = 0xff;
01405                             break;
01406                         case '?' :
01407                             PRINTF("p - I/O Pin Config");
01408                             put_rn();
01409                             PRINTF("u - UART");
01410                             put_rn();
01411                             PRINTF("i - I2C");
01412                             put_rn();
01413                             PRINTF("s - SPI");
01414                             put_rn();
01415                             PRINTF("t - TIMER");
01416                             put_rn();
01417                             PRINTF("a - ADC");
01418                             put_rn();
01419                             PRINTF("d - DAC");
01420                             put_rn();
01421                             PRINTF("l - LDC");
01422                             put_rn();
01423                             PRINTF("w - WWDG");
01424                             put_rn();
01425                             PRINTF("c - COMP");
01426                             put_rn();
01427                             PRINTF("q - Exit mode");
01428                             put_rn();
01429                             break;
01430                         default:
01431                             PUTC('?');
01432                             put_rn();
01433                     }
01434                 }
01435                 PRINTF("Return to All Mode");
01436                 put_rn();
01437                 break;
01438                 //---------------------------------------------------------------------------------
01439                 //    System
01440                 //---------------------------------------------------------------------------------
01441             case 's' :    // System related information
01442 #if USE_SYS
01443                 switch (*ptr++) {
01444                     case 'f' :    // sc - show system clock frequency
01445                         get_freq(1);
01446                         break;
01447                     case 'c' :    // sc - show system CPU information
01448                         cpu_inf();
01449                         break;
01450                     case '?' :
01451                     default:
01452                         put_r();
01453                         PRINTF("sc - System CPU information");
01454                         put_rn();
01455                         PRINTF("sf - System Clock");
01456                         put_rn();
01457                         break;
01458                 }
01459 #else
01460                 not_select();
01461 #endif   // USE_SYS
01462                 break;
01463                 //---------------------------------------------------------------------------------
01464                 //    Help
01465                 //---------------------------------------------------------------------------------
01466             case '?' :
01467                 put_r();
01468                 msg_hlp_hw();
01469                 break;
01470                 //---------------------------------------------------------------------------------
01471                 //    Return to main routine
01472                 //---------------------------------------------------------------------------------
01473             case 'q' :        // Quit
01474                 PRINTF("\rReturn to monitor ");
01475                 return 0;
01476                 //---------------------------------------------------------------------------------
01477                 //    Special command for DEBUG
01478                 //---------------------------------------------------------------------------------
01479             case 'x' :
01480                 not_yet_impliment();
01481                 break;
01482                 //---------------------------------------------------------------------------------
01483                 //    no support
01484                 //---------------------------------------------------------------------------------
01485             default:
01486                 PUTC('?');
01487                 put_rn();
01488                 break;
01489         }
01490     }
01491 }
01492 
01493 #endif  // defined(TARGET_LPC1114)