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#include <si5351a.h>

Public Member Functions
	SI5351A (PinName p_sda, PinName p_scl, uint32_t base_clk_freq, uint8_t xtal_cap=SI5351_CRYSTAL_LOAD_8PF, uint8_t drive_current=SI5351_CLK_DRIVE_STRENGTH_2MA)
	Configure data pin.
	SI5351A (I2C &p_i2c, uint32_t base_clk_freq, uint8_t xtal_cap=SI5351_CRYSTAL_LOAD_8PF, uint8_t drive_current=SI5351_CLK_DRIVE_STRENGTH_2MA)
	Configure data pin (with other devices on I2C line)
uint32_t	set_frequency (uint8_t channel, uint32_t freq)
	Set frequency.
uint32_t	shift_freq (uint8_t channel, int32_t diff)
	shift frequency after setting frequency (Range: 750KHz to 100MHz )
uint32_t	read_freq (uint8_t channel)
	read frequency
void	f_compensation (uint32_t target_f, uint32_t measured_f)
	compensation frequency
void	all_reset (void)
	reset Si5351A all registers
void	debug_reg_print (void)
	debug / print registers
void	debug_current_config (void)
	debug / check registers and shows current configlation
void	debug_example_clock (void)
	debug / set CLK0: 120.00MHz, CLK1: 12.00MHz, CLK2: 13.56MHz as demonstration purpose for hardware check (@25MHz Xtal)
Protected Member Functions
double	si5351_setupMultisynth (uint8_t output, uint8_t pllSource, uint32_t div, uint32_t num, uint32_t denom, uint8_t factor)
	Configures the Multisynth divider, which determines the output clock frequency based on the specified PLL input.
void	si5351_setupPLL (uint8_t pll, uint8_t mult, uint32_t num, uint32_t denom)
	Sets the multiplier for the specified PLL.

Detailed Description

Silicon Laboratories Inc.

Si5351A

 #include "mbed.h"
 #include "si5351a.h"

 I2C i2c(I2C_SDA, I2C_SCL);       // communication with Si5351A
 SI5351 clk(i2c, 25000000UL);     // Base clock = 25MHz

 int main() {
   clk.set_frequency(SI5351_CLK0, 10000000);   // CLK0=10MHz
   while(true) {
      wait(1000);
   }
 }

 // ---------  CAUTION & RESTRICTION -----------------------------------------
 // 1) SETTING METHOD
 // 2.6KHz~100MHz: fixed PLL(around 900 or around 600MHz), fractional divider
 // 100~150MHz: fractional PLL 600-900MHz, fixed divider 6
 // 150~200MHz: fractional PLL 600-900MHz, fixed divider 4
 //
 // 2) RESOURCE USAGE
 // PLLA -> only for CLK0 (You can change freqency any time to any value.)
 // PLLB -> use for bothe CLK1 & CLK2
 // If you set a freq. less than 100MHz,
 //    You can change both CLK1 & CLK2 independently.
 // Over 100MHz, you may have a trouble becase need to change PLLB freq.
 //
 // 3) DISCONTINUITY
 // If you use multiple output, you will lose output signal when you change
 //   the output frequency even not specific CLKn during I2C acccess. 
 // --------------------------------------------------------------------------

Definition at line 159 of file si5351a.h.

Constructor & Destructor Documentation

SI5351A	(	PinName	p_sda,
		PinName	p_scl,
		uint32_t	base_clk_freq,
		uint8_t	xtal_cap = `SI5351_CRYSTAL_LOAD_8PF`,
		uint8_t	drive_current = `SI5351_CLK_DRIVE_STRENGTH_2MA`
	)

Configure data pin.

Parameters:

data	SDA and SCL pins
External	base clock frequency
Internal	capacitor value (10pF, 8pF & 6pF/ Default 8pF)
Output	current drive strength(Default 2mA) same value CLK0,1,2

Definition at line 46 of file si5351a.cpp.

SI5351A	(	I2C &	p_i2c,
		uint32_t	base_clk_freq,
		uint8_t	xtal_cap = `SI5351_CRYSTAL_LOAD_8PF`,
		uint8_t	drive_current = `SI5351_CLK_DRIVE_STRENGTH_2MA`
	)

Configure data pin (with other devices on I2C line)

Parameters:

I2C	previous definition
External	base clock frequency
Internal	capacitor value (10pF, 8pF & 6pF/ Default 8pF)
Output	current drive strength(Default 2mA) same value CLK0,1,2

Definition at line 59 of file si5351a.cpp.

Member Function Documentation

void all_reset ( void )

reset Si5351A all registers

Parameters:

none

Returns:: none

Definition at line 316 of file si5351a.cpp.

void debug_current_config ( void )

debug / check registers and shows current configlation

Parameters:

none

Returns:: none (but print on console)

Definition at line 839 of file si5351a.cpp.

void debug_example_clock ( void )

debug / set CLK0: 120.00MHz, CLK1: 12.00MHz, CLK2: 13.56MHz as demonstration purpose for hardware check (@25MHz Xtal)

Parameters:

none

Returns:: none

Definition at line 1094 of file si5351a.cpp.

void debug_reg_print ( void )

debug / print registers

Parameters:

none

Returns:: none (but print on console)

Definition at line 819 of file si5351a.cpp.

void f_compensation	(	uint32_t	target_f,
		uint32_t	measured_f
	)

compensation frequency

Parameters:

Target	freuency (setting value)
Measured	freuency (actual value)

Returns:: none

Definition at line 293 of file si5351a.cpp.

uint32_t read_freq ( uint8_t channel )

read frequency

Parameters:

select channel CLK0=0, CLK1=1, CLK2=2

Returns:: output frequency

Definition at line 282 of file si5351a.cpp.

uint32_t set_frequency	(	uint8_t	channel,
		uint32_t	freq
	)

Set frequency.

Parameters:

output	channel CLK0=0, CLK1=1, CLK2=2
target	frequency (unit = Hz)

Returns:: output frequency

Definition at line 77 of file si5351a.cpp.

uint32_t shift_freq	(	uint8_t	channel,
		int32_t	diff
	)

shift frequency after setting frequency (Range: 750KHz to 100MHz )

Parameters:

desired	channel CLK0=0, CLK1=1, CLK2=2
sift(+/-)	frequency (unit = Hz)

Returns:: output frequency

Definition at line 178 of file si5351a.cpp.

double si5351_setupMultisynth	(	uint8_t	output,
		uint8_t	pllSource,
		uint32_t	div,
		uint32_t	num,
		uint32_t	denom,
		uint8_t	factor
	)		`[protected]`

Configures the Multisynth divider, which determines the output clock frequency based on the specified PLL input.

Parameters:

output	The output channel to use (0..2)
pllSource	The PLL input source to use, which must be one of: SI5351_PLL_A SI5351_PLL_B
div	The integer divider for the Multisynth output. If pure integer values are used, this value must be one of: SI5351_MULTISYNTH_DIV_4 SI5351_MULTISYNTH_DIV_6 SI5351_MULTISYNTH_DIV_8 If fractional output is used, this value must be between 8 and 900.
num	The 20-bit numerator for fractional output (0..1,048,575). Set this to '0' for integer output.
denom	The 20-bit denominator for fractional output (1..1,048,575). Set this to '1' or higher to avoid divide by zero errors.

Clock Configuration

The multisynth dividers are applied to the specified PLL output, and are used to reduce the PLL output to a valid range (500kHz to 160MHz). The relationship can be seen in this formula, where fVCO is the PLL output frequency and MSx is the multisynth divider: fOUT = fVCO / MSx Valid multisynth dividers are 4, 6, or 8 when using integers, or any fractional values between 8 + 1/1,048,575 and 900 + 0/1

The following formula is used for the fractional mode divider: a + b / c a = The integer value, which must be 4, 6 or 8 in integer mode (MSx_INT=1) or 6..1800 in fractional mode (MSx_INT=0). b = The fractional numerator (0..1,048,575) c = The fractional denominator (1..1,048,575)

Note:: Try to use integers whenever possible to avoid clock jitter; For output frequencies > 150MHz, you must set the divider to 4 and adjust to PLL to generate the frequency (for example a PLL of 640 to generate a 160MHz output clock). This is not yet supported in the driver, which limits frequencies to 500kHz .. 150MHz.; For frequencies below 500kHz (down to 8kHz) Rx_DIV must be used, but this isn't currently implemented in the driver.

Definition at line 600 of file si5351a.cpp.

void si5351_setupPLL	(	uint8_t	pll,
		uint8_t	mult,
		uint32_t	num,
		uint32_t	denom
	)		`[protected]`

Sets the multiplier for the specified PLL.

Parameters:

pll	The PLL to configure, which must be one of the following: SI5351_PLL_A SI5351_PLL_B
mult	The PLL integer multiplier (must be between 15 and 90)
num	The 20-bit numerator for fractional output (0..1,048,575). Set this to '0' for integer output.
denom	The 20-bit denominator for fractional output (1..1,048,575). Set this to '1' or higher to avoid divider by zero errors.

Configuration

fVCO is the PLL output, and must be between 600..900MHz, where: fVCO = fXTAL * (a+(b/c)) fXTAL = the crystal input frequency a = an integer between 15 and 90 b = the fractional numerator (0..1,048,575) c = the fractional denominator (1..1,048,575) NOTE: Try to use integers whenever possible to avoid clock jitter (only use the a part, setting b to '0' and c to '1'). See: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf

Definition at line 451 of file si5351a.cpp.

Type:	Library
Created:	01 Jan 2017
Imports:	87
Forks:	0
Commits:	5
Dependents:	6
Dependencies:	0
Followers:	6

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Detailed Description

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Member Function Documentation

Clock Configuration

Configuration

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SI5351A Class Reference

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Detailed Description

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Member Function Documentation

Clock Configuration

Configuration

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