Silicon Laboratories Inc. Si5351A-B-GT I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR
Dependents: clockGenerator Check_Si5351A_Clock_generator t2d Thing2Do ... more
Test program:
/users/kenjiArai/code/Check_Si5351A_Clock_generator/
si5351a.h@4:8c63d15c8c2e, 2017-08-23 (annotated)
- Committer:
- kenjiArai
- Date:
- Wed Aug 23 09:53:16 2017 +0000
- Revision:
- 4:8c63d15c8c2e
- Parent:
- 3:af2d99cfb3f0
countermeasure for NonCopyable
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
kenjiArai | 0:47b9bfa03730 | 1 | /* |
kenjiArai | 0:47b9bfa03730 | 2 | * mbed Library / Silicon Laboratories Inc. Si5351A-B-GT |
kenjiArai | 0:47b9bfa03730 | 3 | * I2C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR |
kenjiArai | 0:47b9bfa03730 | 4 | * https://www.silabs.com/products/ |
kenjiArai | 0:47b9bfa03730 | 5 | * timing/clock-generator/si535x/pages/Si5351A-B-GM.aspx |
kenjiArai | 0:47b9bfa03730 | 6 | * |
kenjiArai | 0:47b9bfa03730 | 7 | * Checked on Nucleo-F411RE & F401RE mbed board |
kenjiArai | 0:47b9bfa03730 | 8 | * |
kenjiArai | 0:47b9bfa03730 | 9 | * Original & Reference program: |
kenjiArai | 0:47b9bfa03730 | 10 | * 1) |
kenjiArai | 0:47b9bfa03730 | 11 | * https://github.com/adafruit/Adafruit_Si5351_Library |
kenjiArai | 0:47b9bfa03730 | 12 | * see original source (bottom part of si5351a.cpp file) |
kenjiArai | 0:47b9bfa03730 | 13 | * Software License Agreement (BSD License) |
kenjiArai | 0:47b9bfa03730 | 14 | * Copyright (c) 2014, Adafruit Industries All rights reserved. |
kenjiArai | 0:47b9bfa03730 | 15 | * 2) |
kenjiArai | 0:47b9bfa03730 | 16 | * https://gist.github.com/edy555/f1ee7ef44fe4f5c6f7618ac4cbbe66fb |
kenjiArai | 0:47b9bfa03730 | 17 | * made by TT@Hokkaido-san (edy555) |
kenjiArai | 0:47b9bfa03730 | 18 | * http://ttrftech.tumblr.com/ |
kenjiArai | 0:47b9bfa03730 | 19 | * http://ttrftech.tumblr.com/post/150247113216/ |
kenjiArai | 0:47b9bfa03730 | 20 | * si5351a-configuration-how-to-and-signal-quality |
kenjiArai | 0:47b9bfa03730 | 21 | * |
kenjiArai | 0:47b9bfa03730 | 22 | * Modified by Kenji Arai / JH1PJL |
kenjiArai | 0:47b9bfa03730 | 23 | * http://www.page.sannet.ne.jp/kenjia/index.html |
kenjiArai | 0:47b9bfa03730 | 24 | * http://mbed.org/users/kenjiArai/ |
kenjiArai | 0:47b9bfa03730 | 25 | * |
kenjiArai | 0:47b9bfa03730 | 26 | * Started: December 24th, 2016 |
kenjiArai | 4:8c63d15c8c2e | 27 | * Revised: August 23rd, 2017 |
kenjiArai | 0:47b9bfa03730 | 28 | * |
kenjiArai | 0:47b9bfa03730 | 29 | */ |
kenjiArai | 0:47b9bfa03730 | 30 | |
kenjiArai | 3:af2d99cfb3f0 | 31 | #ifndef MBED_SI5351A |
kenjiArai | 3:af2d99cfb3f0 | 32 | #define MBED_SI5351A |
kenjiArai | 3:af2d99cfb3f0 | 33 | |
kenjiArai | 3:af2d99cfb3f0 | 34 | #if 0 // Range extend mode -> set 1 |
kenjiArai | 3:af2d99cfb3f0 | 35 | #define RANGE_EXTENDED |
kenjiArai | 3:af2d99cfb3f0 | 36 | #endif |
kenjiArai | 3:af2d99cfb3f0 | 37 | #if defined(RANGE_EXTENDED) |
kenjiArai | 3:af2d99cfb3f0 | 38 | #warning "Si5351A PLL range is only 600MHz to 900MHz." |
kenjiArai | 3:af2d99cfb3f0 | 39 | #warning "If you use RANGE_EXTENDED mode, PLL sets 250MHz to 1.3GHz." |
kenjiArai | 3:af2d99cfb3f0 | 40 | #warning "This causes high possibility to make a \ |
kenjiArai | 3:af2d99cfb3f0 | 41 | PARMANENT DAMAGE for the chip!!!!!" |
kenjiArai | 3:af2d99cfb3f0 | 42 | #warning "Don't use this mode!!!" |
kenjiArai | 3:af2d99cfb3f0 | 43 | #endif |
kenjiArai | 0:47b9bfa03730 | 44 | |
kenjiArai | 0:47b9bfa03730 | 45 | ////////////// ADDRESS ///////////////////////////////////////////////////////// |
kenjiArai | 0:47b9bfa03730 | 46 | // 7bit address = 0b1100000(0x60) -> 8bit = 0b11000000(0xc0) |
kenjiArai | 0:47b9bfa03730 | 47 | // -> Fixed adddress (No other choises) |
kenjiArai | 0:47b9bfa03730 | 48 | #define SI5351_I2C_ADDR (0x60<<1) |
kenjiArai | 0:47b9bfa03730 | 49 | |
kenjiArai | 0:47b9bfa03730 | 50 | ////////////// REGISTER DEFINITION ///////////////////////////////////////////// |
kenjiArai | 0:47b9bfa03730 | 51 | #define SI5351_REG_3_OUTPUT_ENABLE_CONTROL 3 |
kenjiArai | 0:47b9bfa03730 | 52 | #define SI5351_REG_16_CLK0_CONTROL 16 |
kenjiArai | 0:47b9bfa03730 | 53 | #define SI5351_REG_17_CLK1_CONTROL 17 |
kenjiArai | 0:47b9bfa03730 | 54 | #define SI5351_REG_18_CLK2_CONTROL 18 |
kenjiArai | 0:47b9bfa03730 | 55 | #define SI5351_REG_26_PLL_A 26 |
kenjiArai | 0:47b9bfa03730 | 56 | #define SI5351_REG_34_PLL_B 34 |
kenjiArai | 0:47b9bfa03730 | 57 | #define SI5351_REG_42_MULTISYNTH0 42 |
kenjiArai | 0:47b9bfa03730 | 58 | #define SI5351_REG_44_MULTISYNTH0_P3 44 |
kenjiArai | 0:47b9bfa03730 | 59 | #define SI5351_REG_50_MULTISYNTH1 50 |
kenjiArai | 0:47b9bfa03730 | 60 | #define SI5351_REG_52_MULTISYNTH1_P3 52 |
kenjiArai | 0:47b9bfa03730 | 61 | #define SI5351_REG_58_MULTISYNTH2 58 |
kenjiArai | 3:af2d99cfb3f0 | 62 | #define SI5351_REG_60_MULTISYNTH2_P3 60 |
kenjiArai | 0:47b9bfa03730 | 63 | #define SI5351_REG_177_PLL_RESET 177 |
kenjiArai | 0:47b9bfa03730 | 64 | #define SI5351_REG_183_CRYSTAL_LOAD 183 |
kenjiArai | 0:47b9bfa03730 | 65 | |
kenjiArai | 0:47b9bfa03730 | 66 | ////////////// Configration //////////////////////////////////////////////////// |
kenjiArai | 0:47b9bfa03730 | 67 | // PLLn |
kenjiArai | 0:47b9bfa03730 | 68 | #define SI5351_PLL_A 0 |
kenjiArai | 0:47b9bfa03730 | 69 | #define SI5351_PLL_B 1 |
kenjiArai | 0:47b9bfa03730 | 70 | // CLKn |
kenjiArai | 0:47b9bfa03730 | 71 | #define SI5351_CLK0 0 |
kenjiArai | 0:47b9bfa03730 | 72 | #define SI5351_CLK1 1 |
kenjiArai | 0:47b9bfa03730 | 73 | #define SI5351_CLK2 2 |
kenjiArai | 0:47b9bfa03730 | 74 | // REG_44_MULTISYNTH0, REG_52_MULTISYNTH1, REG_60_MULTISYNTH2 |
kenjiArai | 0:47b9bfa03730 | 75 | #define SI5351_R_DIV_1 (0<<4) |
kenjiArai | 0:47b9bfa03730 | 76 | #define SI5351_R_DIV_2 (1<<4) |
kenjiArai | 0:47b9bfa03730 | 77 | #define SI5351_R_DIV_4 (2<<4) |
kenjiArai | 0:47b9bfa03730 | 78 | #define SI5351_R_DIV_8 (3<<4) |
kenjiArai | 0:47b9bfa03730 | 79 | #define SI5351_R_DIV_16 (4<<4) |
kenjiArai | 0:47b9bfa03730 | 80 | #define SI5351_R_DIV_32 (5<<4) |
kenjiArai | 0:47b9bfa03730 | 81 | #define SI5351_R_DIV_64 (6<<4) |
kenjiArai | 0:47b9bfa03730 | 82 | #define SI5351_R_DIV_128 (7<<4) |
kenjiArai | 0:47b9bfa03730 | 83 | #define SI5351_DIVBY4 (3<<2) |
kenjiArai | 0:47b9bfa03730 | 84 | // REG_16_CLK0_CONTROL, REG_17_CLK1_CONTROL, REG_18_CLK2_CONTROL |
kenjiArai | 0:47b9bfa03730 | 85 | #define SI5351_CLK_POWERDOWN (1<<7) |
kenjiArai | 0:47b9bfa03730 | 86 | #define SI5351_CLK_INTEGER_MODE (1<<6) |
kenjiArai | 0:47b9bfa03730 | 87 | #define SI5351_CLK_PLL_SELECT_B (1<<5) |
kenjiArai | 0:47b9bfa03730 | 88 | #define SI5351_CLK_INVERT (1<<4) |
kenjiArai | 0:47b9bfa03730 | 89 | #define SI5351_CLK_INPUT_MASK (3<<2) |
kenjiArai | 0:47b9bfa03730 | 90 | #define SI5351_CLK_INPUT_XTAL (0<<2) |
kenjiArai | 0:47b9bfa03730 | 91 | #define SI5351_CLK_INPUT_CLKIN (1<<2) |
kenjiArai | 0:47b9bfa03730 | 92 | #define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2) |
kenjiArai | 0:47b9bfa03730 | 93 | #define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2) |
kenjiArai | 0:47b9bfa03730 | 94 | #define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0) |
kenjiArai | 0:47b9bfa03730 | 95 | #define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0) |
kenjiArai | 0:47b9bfa03730 | 96 | #define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0) |
kenjiArai | 0:47b9bfa03730 | 97 | #define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0) |
kenjiArai | 0:47b9bfa03730 | 98 | #define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0) |
kenjiArai | 0:47b9bfa03730 | 99 | // REG_177_PLL_RESET |
kenjiArai | 0:47b9bfa03730 | 100 | #define SI5351_PLL_RESET_B (1<<7) |
kenjiArai | 0:47b9bfa03730 | 101 | #define SI5351_PLL_RESET_A (1<<5) |
kenjiArai | 0:47b9bfa03730 | 102 | // REG_183_CRYSTAL_LOAD |
kenjiArai | 0:47b9bfa03730 | 103 | #define SI5351_CRYSTAL_LOAD_6PF (1<<6) |
kenjiArai | 0:47b9bfa03730 | 104 | #define SI5351_CRYSTAL_LOAD_8PF (2<<6) |
kenjiArai | 0:47b9bfa03730 | 105 | #define SI5351_CRYSTAL_LOAD_10PF (3<<6) |
kenjiArai | 0:47b9bfa03730 | 106 | |
kenjiArai | 0:47b9bfa03730 | 107 | // Frequency |
kenjiArai | 3:af2d99cfb3f0 | 108 | #define FREQ_900MHZ (900000000UL) |
kenjiArai | 3:af2d99cfb3f0 | 109 | #define FREQ_600MHZ (600000000UL) |
kenjiArai | 3:af2d99cfb3f0 | 110 | #define FREQ_200MHZ (200000000UL) |
kenjiArai | 0:47b9bfa03730 | 111 | #define FREQ_150MHZ (150000000UL) |
kenjiArai | 3:af2d99cfb3f0 | 112 | #define FREQ_110MHZ (110000000UL) |
kenjiArai | 0:47b9bfa03730 | 113 | #define FREQ_1MHZ (1000000UL) |
kenjiArai | 0:47b9bfa03730 | 114 | #define FREQ_450KHZ (450000UL) |
kenjiArai | 0:47b9bfa03730 | 115 | #define FREQ_75KHZ (75000UL) |
kenjiArai | 0:47b9bfa03730 | 116 | #define FREQ_20KHZ (20000UL) |
kenjiArai | 0:47b9bfa03730 | 117 | |
kenjiArai | 0:47b9bfa03730 | 118 | typedef enum { // Operating mode |
kenjiArai | 0:47b9bfa03730 | 119 | CLK_OUT_NOT_USED = 0, CLK_OUT_FIXEDPLL, CLK_OUT_FIXEDDIV |
kenjiArai | 0:47b9bfa03730 | 120 | } OperatingMode; |
kenjiArai | 0:47b9bfa03730 | 121 | |
kenjiArai | 0:47b9bfa03730 | 122 | /** Silicon Laboratories Inc. Si5351A |
kenjiArai | 0:47b9bfa03730 | 123 | * |
kenjiArai | 0:47b9bfa03730 | 124 | * @code |
kenjiArai | 0:47b9bfa03730 | 125 | * #include "mbed.h" |
kenjiArai | 0:47b9bfa03730 | 126 | * #include "si5351a.h" |
kenjiArai | 0:47b9bfa03730 | 127 | * |
kenjiArai | 0:47b9bfa03730 | 128 | * I2C i2c(I2C_SDA, I2C_SCL); // communication with Si5351A |
kenjiArai | 0:47b9bfa03730 | 129 | * SI5351 clk(i2c, 25000000UL); // Base clock = 25MHz |
kenjiArai | 0:47b9bfa03730 | 130 | * |
kenjiArai | 0:47b9bfa03730 | 131 | * int main() { |
kenjiArai | 0:47b9bfa03730 | 132 | * clk.set_frequency(SI5351_CLK0, 10000000); // CLK0=10MHz |
kenjiArai | 0:47b9bfa03730 | 133 | * while(true) { |
kenjiArai | 0:47b9bfa03730 | 134 | * wait(1000); |
kenjiArai | 0:47b9bfa03730 | 135 | * } |
kenjiArai | 0:47b9bfa03730 | 136 | * } |
kenjiArai | 0:47b9bfa03730 | 137 | * |
kenjiArai | 0:47b9bfa03730 | 138 | * // --------- CAUTION & RESTRICTION ----------------------------------------- |
kenjiArai | 0:47b9bfa03730 | 139 | * // 1) SETTING METHOD |
kenjiArai | 3:af2d99cfb3f0 | 140 | * // 2.6KHz~100MHz: fixed PLL(around 900 or around 600MHz), fractional divider |
kenjiArai | 3:af2d99cfb3f0 | 141 | * // 100~150MHz: fractional PLL 600-900MHz, fixed divider 6 |
kenjiArai | 3:af2d99cfb3f0 | 142 | * // 150~200MHz: fractional PLL 600-900MHz, fixed divider 4 |
kenjiArai | 0:47b9bfa03730 | 143 | * // |
kenjiArai | 0:47b9bfa03730 | 144 | * // 2) RESOURCE USAGE |
kenjiArai | 0:47b9bfa03730 | 145 | * // PLLA -> only for CLK0 (You can change freqency any time to any value.) |
kenjiArai | 0:47b9bfa03730 | 146 | * // PLLB -> use for bothe CLK1 & CLK2 |
kenjiArai | 0:47b9bfa03730 | 147 | * // If you set a freq. less than 100MHz, |
kenjiArai | 0:47b9bfa03730 | 148 | * // You can change both CLK1 & CLK2 independently. |
kenjiArai | 0:47b9bfa03730 | 149 | * // Over 100MHz, you may have a trouble becase need to change PLLB freq. |
kenjiArai | 0:47b9bfa03730 | 150 | * // |
kenjiArai | 0:47b9bfa03730 | 151 | * // 3) DISCONTINUITY |
kenjiArai | 0:47b9bfa03730 | 152 | * // If you use multiple output, you will lose output signal when you change |
kenjiArai | 0:47b9bfa03730 | 153 | * // the output frequency even not specific CLKn during I2C acccess. |
kenjiArai | 0:47b9bfa03730 | 154 | * // -------------------------------------------------------------------------- |
kenjiArai | 0:47b9bfa03730 | 155 | * |
kenjiArai | 0:47b9bfa03730 | 156 | * @endcode |
kenjiArai | 0:47b9bfa03730 | 157 | */ |
kenjiArai | 0:47b9bfa03730 | 158 | |
kenjiArai | 0:47b9bfa03730 | 159 | class SI5351A |
kenjiArai | 0:47b9bfa03730 | 160 | { |
kenjiArai | 0:47b9bfa03730 | 161 | public: |
kenjiArai | 0:47b9bfa03730 | 162 | /** Configure data pin |
kenjiArai | 0:47b9bfa03730 | 163 | * @param data SDA and SCL pins |
kenjiArai | 0:47b9bfa03730 | 164 | * @param External base clock frequency |
kenjiArai | 0:47b9bfa03730 | 165 | * @param Internal capacitor value (10pF, 8pF & 6pF/ Default 8pF) |
kenjiArai | 0:47b9bfa03730 | 166 | * @param Output current drive strength(Default 2mA) same value CLK0,1,2 |
kenjiArai | 0:47b9bfa03730 | 167 | */ |
kenjiArai | 0:47b9bfa03730 | 168 | SI5351A(PinName p_sda, PinName p_scl, |
kenjiArai | 0:47b9bfa03730 | 169 | uint32_t base_clk_freq, |
kenjiArai | 0:47b9bfa03730 | 170 | uint8_t xtal_cap = SI5351_CRYSTAL_LOAD_8PF, |
kenjiArai | 0:47b9bfa03730 | 171 | uint8_t drive_current = SI5351_CLK_DRIVE_STRENGTH_2MA |
kenjiArai | 0:47b9bfa03730 | 172 | ); |
kenjiArai | 0:47b9bfa03730 | 173 | |
kenjiArai | 0:47b9bfa03730 | 174 | /** Configure data pin (with other devices on I2C line) |
kenjiArai | 0:47b9bfa03730 | 175 | * @param I2C previous definition |
kenjiArai | 0:47b9bfa03730 | 176 | * @param External base clock frequency |
kenjiArai | 0:47b9bfa03730 | 177 | * @param Internal capacitor value (10pF, 8pF & 6pF/ Default 8pF) |
kenjiArai | 0:47b9bfa03730 | 178 | * @param Output current drive strength(Default 2mA) same value CLK0,1,2 |
kenjiArai | 0:47b9bfa03730 | 179 | */ |
kenjiArai | 0:47b9bfa03730 | 180 | SI5351A(I2C& p_i2c, |
kenjiArai | 0:47b9bfa03730 | 181 | uint32_t base_clk_freq, |
kenjiArai | 0:47b9bfa03730 | 182 | uint8_t xtal_cap = SI5351_CRYSTAL_LOAD_8PF, |
kenjiArai | 0:47b9bfa03730 | 183 | uint8_t drive_current = SI5351_CLK_DRIVE_STRENGTH_2MA |
kenjiArai | 0:47b9bfa03730 | 184 | ); |
kenjiArai | 0:47b9bfa03730 | 185 | |
kenjiArai | 0:47b9bfa03730 | 186 | /** Set frequency |
kenjiArai | 0:47b9bfa03730 | 187 | * @param output channel CLK0=0, CLK1=1, CLK2=2 |
kenjiArai | 0:47b9bfa03730 | 188 | * @param target frequency (unit = Hz) |
kenjiArai | 0:47b9bfa03730 | 189 | * @return output frequency |
kenjiArai | 0:47b9bfa03730 | 190 | */ |
kenjiArai | 0:47b9bfa03730 | 191 | uint32_t set_frequency(uint8_t channel, uint32_t freq); |
kenjiArai | 0:47b9bfa03730 | 192 | |
kenjiArai | 0:47b9bfa03730 | 193 | /** shift frequency after setting frequency (Range: 750KHz to 100MHz ) |
kenjiArai | 0:47b9bfa03730 | 194 | * @param desired channel CLK0=0, CLK1=1, CLK2=2 |
kenjiArai | 0:47b9bfa03730 | 195 | * @param sift(+/-) frequency (unit = Hz) |
kenjiArai | 0:47b9bfa03730 | 196 | * @return output frequency |
kenjiArai | 0:47b9bfa03730 | 197 | */ |
kenjiArai | 0:47b9bfa03730 | 198 | uint32_t shift_freq(uint8_t channel, int32_t diff); |
kenjiArai | 0:47b9bfa03730 | 199 | |
kenjiArai | 0:47b9bfa03730 | 200 | /** read frequency |
kenjiArai | 0:47b9bfa03730 | 201 | * @param select channel CLK0=0, CLK1=1, CLK2=2 |
kenjiArai | 0:47b9bfa03730 | 202 | * @return output frequency |
kenjiArai | 0:47b9bfa03730 | 203 | */ |
kenjiArai | 0:47b9bfa03730 | 204 | uint32_t read_freq(uint8_t channel); |
kenjiArai | 0:47b9bfa03730 | 205 | |
kenjiArai | 2:8fe745836ea6 | 206 | /** compensation frequency |
kenjiArai | 2:8fe745836ea6 | 207 | * @param Target freuency (setting value) |
kenjiArai | 2:8fe745836ea6 | 208 | * @param Measured freuency (actual value) |
kenjiArai | 2:8fe745836ea6 | 209 | * @return none |
kenjiArai | 2:8fe745836ea6 | 210 | */ |
kenjiArai | 2:8fe745836ea6 | 211 | void f_compensation(uint32_t target_f, uint32_t measured_f); |
kenjiArai | 0:47b9bfa03730 | 212 | |
kenjiArai | 0:47b9bfa03730 | 213 | /** reset Si5351A all registers |
kenjiArai | 0:47b9bfa03730 | 214 | * @param none |
kenjiArai | 0:47b9bfa03730 | 215 | * @return none |
kenjiArai | 0:47b9bfa03730 | 216 | */ |
kenjiArai | 0:47b9bfa03730 | 217 | void all_reset(void); |
kenjiArai | 0:47b9bfa03730 | 218 | |
kenjiArai | 3:af2d99cfb3f0 | 219 | //--------------- Debug interface ------------------------------------------ |
kenjiArai | 0:47b9bfa03730 | 220 | |
kenjiArai | 0:47b9bfa03730 | 221 | /** debug / print registers |
kenjiArai | 0:47b9bfa03730 | 222 | * @param none |
kenjiArai | 0:47b9bfa03730 | 223 | * @return none (but print on console) |
kenjiArai | 0:47b9bfa03730 | 224 | */ |
kenjiArai | 0:47b9bfa03730 | 225 | void debug_reg_print(void); |
kenjiArai | 0:47b9bfa03730 | 226 | |
kenjiArai | 0:47b9bfa03730 | 227 | /** debug / check registers and shows current configlation |
kenjiArai | 0:47b9bfa03730 | 228 | * @param none |
kenjiArai | 0:47b9bfa03730 | 229 | * @return none (but print on console) |
kenjiArai | 0:47b9bfa03730 | 230 | */ |
kenjiArai | 0:47b9bfa03730 | 231 | void debug_current_config(void); |
kenjiArai | 0:47b9bfa03730 | 232 | |
kenjiArai | 0:47b9bfa03730 | 233 | /** debug / set CLK0: 120.00MHz, CLK1: 12.00MHz, CLK2: 13.56MHz |
kenjiArai | 0:47b9bfa03730 | 234 | * as demonstration purpose for hardware check (@25MHz Xtal) |
kenjiArai | 0:47b9bfa03730 | 235 | * @param none |
kenjiArai | 0:47b9bfa03730 | 236 | * @return none |
kenjiArai | 3:af2d99cfb3f0 | 237 | */ |
kenjiArai | 0:47b9bfa03730 | 238 | void debug_example_clock(void); |
kenjiArai | 0:47b9bfa03730 | 239 | |
kenjiArai | 0:47b9bfa03730 | 240 | protected: |
kenjiArai | 4:8c63d15c8c2e | 241 | I2C *_i2c_p; |
kenjiArai | 4:8c63d15c8c2e | 242 | I2C &_i2c; |
kenjiArai | 0:47b9bfa03730 | 243 | |
kenjiArai | 0:47b9bfa03730 | 244 | uint32_t gcd(uint32_t x, uint32_t y); |
kenjiArai | 0:47b9bfa03730 | 245 | void si5351_read(const uint8_t *buf); |
kenjiArai | 0:47b9bfa03730 | 246 | void si5351_write(uint8_t reg, uint8_t dat); |
kenjiArai | 0:47b9bfa03730 | 247 | void si5351_bulk_write(const uint8_t *buf, uint8_t len); |
kenjiArai | 0:47b9bfa03730 | 248 | double si5351_set_frequency_fixeddiv( |
kenjiArai | 0:47b9bfa03730 | 249 | uint8_t channel, |
kenjiArai | 0:47b9bfa03730 | 250 | uint32_t pll, |
kenjiArai | 0:47b9bfa03730 | 251 | uint32_t freq, |
kenjiArai | 0:47b9bfa03730 | 252 | uint32_t div); |
kenjiArai | 0:47b9bfa03730 | 253 | double si5351_set_frequency_fixedpll( |
kenjiArai | 0:47b9bfa03730 | 254 | uint8_t channel, |
kenjiArai | 0:47b9bfa03730 | 255 | uint32_t pll, |
kenjiArai | 0:47b9bfa03730 | 256 | uint32_t pllfreq, |
kenjiArai | 0:47b9bfa03730 | 257 | uint32_t freq, |
kenjiArai | 0:47b9bfa03730 | 258 | uint8_t factor); |
kenjiArai | 0:47b9bfa03730 | 259 | double si5351_setupMultisynth( |
kenjiArai | 0:47b9bfa03730 | 260 | uint8_t output, |
kenjiArai | 0:47b9bfa03730 | 261 | uint8_t pllSource, |
kenjiArai | 0:47b9bfa03730 | 262 | uint32_t div, |
kenjiArai | 0:47b9bfa03730 | 263 | uint32_t num, |
kenjiArai | 0:47b9bfa03730 | 264 | uint32_t denom, |
kenjiArai | 0:47b9bfa03730 | 265 | uint8_t factor); |
kenjiArai | 0:47b9bfa03730 | 266 | void si5351_setupPLL( |
kenjiArai | 0:47b9bfa03730 | 267 | uint8_t pll, |
kenjiArai | 0:47b9bfa03730 | 268 | uint8_t mult, |
kenjiArai | 0:47b9bfa03730 | 269 | uint32_t num, |
kenjiArai | 0:47b9bfa03730 | 270 | uint32_t denom); |
kenjiArai | 3:af2d99cfb3f0 | 271 | void si5351_set_PLL_input_condition(uint32_t freq); |
kenjiArai | 0:47b9bfa03730 | 272 | void si5351_reset_pll(void); |
kenjiArai | 0:47b9bfa03730 | 273 | void si5351_enable_output(void); |
kenjiArai | 0:47b9bfa03730 | 274 | void si5351_disable_output(void); |
kenjiArai | 0:47b9bfa03730 | 275 | void si5351_disable_all_output(void); |
kenjiArai | 0:47b9bfa03730 | 276 | void si5351_init(void); |
kenjiArai | 0:47b9bfa03730 | 277 | void put_dump(const uint8_t *buff, uint8_t ofs, uint8_t cnt); |
kenjiArai | 0:47b9bfa03730 | 278 | void prnt_reg(uint8_t offset, uint8_t n); |
kenjiArai | 0:47b9bfa03730 | 279 | void reg_16_17_18(uint8_t dt); |
kenjiArai | 0:47b9bfa03730 | 280 | void reg_pll_8bytes(uint8_t *buf); |
kenjiArai | 0:47b9bfa03730 | 281 | void reg_mltisyc_8bytes(uint8_t *buf); |
kenjiArai | 0:47b9bfa03730 | 282 | |
kenjiArai | 0:47b9bfa03730 | 283 | private: |
kenjiArai | 0:47b9bfa03730 | 284 | uint8_t addr; // Chip I2C address |
kenjiArai | 0:47b9bfa03730 | 285 | uint32_t base_freq; // Xtal oscilation freq. |
kenjiArai | 0:47b9bfa03730 | 286 | uint8_t x_cap; // Internal capacitor value |
kenjiArai | 0:47b9bfa03730 | 287 | uint8_t drv_current; // Output current drive strength |
kenjiArai | 3:af2d99cfb3f0 | 288 | uint8_t pll_n; // PLL div number (PLL_N) |
kenjiArai | 3:af2d99cfb3f0 | 289 | uint32_t pll_freq; // XTAL * pll_n |
kenjiArai | 0:47b9bfa03730 | 290 | uint32_t plla_freq; // Calculated freq of PLLA |
kenjiArai | 0:47b9bfa03730 | 291 | uint32_t pllb_freq; // Calculated freq of PLLB |
kenjiArai | 2:8fe745836ea6 | 292 | double compensation; // Compensation data |
kenjiArai | 0:47b9bfa03730 | 293 | // Setting frequency |
kenjiArai | 0:47b9bfa03730 | 294 | double clk0_freq; |
kenjiArai | 0:47b9bfa03730 | 295 | double clk1_freq; |
kenjiArai | 0:47b9bfa03730 | 296 | double clk2_freq; |
kenjiArai | 0:47b9bfa03730 | 297 | // operating mode |
kenjiArai | 0:47b9bfa03730 | 298 | uint8_t clk0_state; |
kenjiArai | 0:47b9bfa03730 | 299 | uint8_t clk1_state; |
kenjiArai | 0:47b9bfa03730 | 300 | uint8_t clk2_state; |
kenjiArai | 0:47b9bfa03730 | 301 | |
kenjiArai | 0:47b9bfa03730 | 302 | }; // class SI5351A |
kenjiArai | 0:47b9bfa03730 | 303 | |
kenjiArai | 0:47b9bfa03730 | 304 | #endif // MBED_SI5351A |