Kenji Arai / Frq_cuntr_Nucleo-F746ZG

Frequency counter library using GPS 1PPS signal and temperature controlled 50MHz Base clock. Ported from F411 Frequency Counter.

Dependencies:   RingBuff

Dependents:   Frequency_Cntr_1PPS_F746ZG

Fork of Frq_cuntr_full by Kenji Arai

Please refer following.
/users/kenjiArai/notebook/frequency-counters/

frq_cuntr_full.h@0:bfdc6ed58a06, 2014-11-22 (annotated)

Committer:
kenjiArai
Date:
Sat Nov 22 04:01:41 2014 +0000
Revision:
0:bfdc6ed58a06
Child:
1:102230f2879d
Frequency Counter program using GPS 1PPS signal compensation. Only for  ST Nucleo F411RE.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 0:bfdc6ed58a06 1 /*
kenjiArai 0:bfdc6ed58a06 2 * mbed Application program / Frequency Counter with GPS 1PPS Compensation
kenjiArai 0:bfdc6ed58a06 3 * Frequency Counter Hardware relataed program
kenjiArai 0:bfdc6ed58a06 4 *
kenjiArai 0:bfdc6ed58a06 5 * Copyright (c) 2014 Kenji Arai / JH1PJL
kenjiArai 0:bfdc6ed58a06 6 * http://www.page.sannet.ne.jp/kenjia/index.html
kenjiArai 0:bfdc6ed58a06 7 * http://mbed.org/users/kenjiArai/
kenjiArai 0:bfdc6ed58a06 8 * Additional functions and modification
kenjiArai 0:bfdc6ed58a06 9 * started: October 18th, 2014
kenjiArai 0:bfdc6ed58a06 10 * Revised: Nobember 22nd, 2014
kenjiArai 0:bfdc6ed58a06 11 *
kenjiArai 0:bfdc6ed58a06 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
kenjiArai 0:bfdc6ed58a06 13 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
kenjiArai 0:bfdc6ed58a06 14 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
kenjiArai 0:bfdc6ed58a06 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
kenjiArai 0:bfdc6ed58a06 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
kenjiArai 0:bfdc6ed58a06 17 */
kenjiArai 0:bfdc6ed58a06 18
kenjiArai 0:bfdc6ed58a06 19 #ifndef MBED_FRQ_CUNTR
kenjiArai 0:bfdc6ed58a06 20 #define MBED_FRQ_CUNTR
kenjiArai 0:bfdc6ed58a06 21
kenjiArai 0:bfdc6ed58a06 22 #include "mbed.h"
kenjiArai 0:bfdc6ed58a06 23
kenjiArai 0:bfdc6ed58a06 24 namespace Frequency_counter
kenjiArai 0:bfdc6ed58a06 25 {
kenjiArai 0:bfdc6ed58a06 26 #define DEBUG // use Communication with PC(UART)
kenjiArai 0:bfdc6ed58a06 27 #define IRQ_DRIVE
kenjiArai 0:bfdc6ed58a06 28 //#define BASE_EXTERNAL_CLOCK
kenjiArai 0:bfdc6ed58a06 29
kenjiArai 0:bfdc6ed58a06 30 #if defined(BASE_EXTERNAL_CLOCK)
kenjiArai 0:bfdc6ed58a06 31 #define CNT_UPPER (0xffffffff - 100)
kenjiArai 0:bfdc6ed58a06 32 #define CNT_LOWER (0 + 100)
kenjiArai 0:bfdc6ed58a06 33 //#define CNT_UPPER (30000000 + 1000000)
kenjiArai 0:bfdc6ed58a06 34 //#define CNT_LOWER (30000000 - 1000000)
kenjiArai 0:bfdc6ed58a06 35 #else
kenjiArai 0:bfdc6ed58a06 36 #define CNT_UPPER (0xffffffff - 100)
kenjiArai 0:bfdc6ed58a06 37 #define CNT_LOWER (0 + 100)
kenjiArai 0:bfdc6ed58a06 38 //#define CNT_UPPER (100000000 - 100000)
kenjiArai 0:bfdc6ed58a06 39 //#define CNT_LOWER (100000000 + 100000)
kenjiArai 0:bfdc6ed58a06 40 #endif
kenjiArai 0:bfdc6ed58a06 41
kenjiArai 0:bfdc6ed58a06 42 #if defined(BASE_EXTERNAL_CLOCK)
kenjiArai 0:bfdc6ed58a06 43 #define ONE_SECOND_COUNT 0xe4e1c0
kenjiArai 0:bfdc6ed58a06 44 #else
kenjiArai 0:bfdc6ed58a06 45 #define ONE_SECOND_COUNT 0x2faf080
kenjiArai 0:bfdc6ed58a06 46 #endif
kenjiArai 0:bfdc6ed58a06 47
kenjiArai 0:bfdc6ed58a06 48 #define CNT_BF_SIZE 120
kenjiArai 0:bfdc6ed58a06 49
kenjiArai 0:bfdc6ed58a06 50 //#if defined(IRQ_DRIVE)
kenjiArai 0:bfdc6ed58a06 51 // 1PPS data
kenjiArai 0:bfdc6ed58a06 52 extern uint32_t onepps_cnt[CNT_BF_SIZE];
kenjiArai 0:bfdc6ed58a06 53 extern uint32_t onepps_num;
kenjiArai 0:bfdc6ed58a06 54 extern uint64_t onepps_cnt_avarage;
kenjiArai 0:bfdc6ed58a06 55 extern uint8_t onepps_buf_full;
kenjiArai 0:bfdc6ed58a06 56 extern uint8_t onepps_ready_flg;
kenjiArai 0:bfdc6ed58a06 57 // TIM2
kenjiArai 0:bfdc6ed58a06 58 extern uint8_t tim2_ready_flg;
kenjiArai 0:bfdc6ed58a06 59 extern uint32_t tim2_cnt_data;
kenjiArai 0:bfdc6ed58a06 60 extern uint32_t tim2_old_cnt_data;
kenjiArai 0:bfdc6ed58a06 61 // TIM3+4
kenjiArai 0:bfdc6ed58a06 62 extern uint8_t tim3p4_ready_flg;
kenjiArai 0:bfdc6ed58a06 63 extern uint32_t tim3p4_cnt_data;
kenjiArai 0:bfdc6ed58a06 64 extern uint32_t tim3p4_old_cnt_data;
kenjiArai 0:bfdc6ed58a06 65
kenjiArai 0:bfdc6ed58a06 66 // TIM2 IC2 Interrupt control
kenjiArai 0:bfdc6ed58a06 67 void irq_ic2_TIM2(void);
kenjiArai 0:bfdc6ed58a06 68 // TIM3 IC2 Interrupt control (same signal connected to TIM4 IC1)
kenjiArai 0:bfdc6ed58a06 69 void irq_ic2_TIM3P4(void);
kenjiArai 0:bfdc6ed58a06 70
kenjiArai 0:bfdc6ed58a06 71 class FRQ_CUNTR
kenjiArai 0:bfdc6ed58a06 72 {
kenjiArai 0:bfdc6ed58a06 73 public:
kenjiArai 0:bfdc6ed58a06 74
kenjiArai 0:bfdc6ed58a06 75 FRQ_CUNTR(PinName f_in);
kenjiArai 0:bfdc6ed58a06 76
kenjiArai 0:bfdc6ed58a06 77 void initialize_Freq_counter(void);
kenjiArai 0:bfdc6ed58a06 78
kenjiArai 0:bfdc6ed58a06 79 // Read TIM2 captured counter value
kenjiArai 0:bfdc6ed58a06 80 uint32_t read_ic2_counter_TIM2(void);
kenjiArai 0:bfdc6ed58a06 81
kenjiArai 0:bfdc6ed58a06 82 // Check TIM2 IC2 status
kenjiArai 0:bfdc6ed58a06 83 uint32_t check_ic2_status_TIM2(void);
kenjiArai 0:bfdc6ed58a06 84
kenjiArai 0:bfdc6ed58a06 85 // Read TIM3+4(as 32bit) captured counter value
kenjiArai 0:bfdc6ed58a06 86 uint32_t read_ic2_counter_TIM3P4(void);
kenjiArai 0:bfdc6ed58a06 87
kenjiArai 0:bfdc6ed58a06 88 // Check TIM3 IC2 & TIM4 IC1 status
kenjiArai 0:bfdc6ed58a06 89 uint32_t check_ic2_status_TIM3P4(void);
kenjiArai 0:bfdc6ed58a06 90
kenjiArai 0:bfdc6ed58a06 91 // Avarage measued data GPS 1PPS by 50MHz Internal Clock
kenjiArai 0:bfdc6ed58a06 92 void avarage_1pps(void);
kenjiArai 0:bfdc6ed58a06 93
kenjiArai 0:bfdc6ed58a06 94 // Frequency check for test purpose
kenjiArai 0:bfdc6ed58a06 95 uint32_t read_frequency_TIM2(float gate_time);
kenjiArai 0:bfdc6ed58a06 96 uint32_t read_frequency_TIM3P4(float gate_time);
kenjiArai 0:bfdc6ed58a06 97
kenjiArai 0:bfdc6ed58a06 98 // Clock output for test purpose
kenjiArai 0:bfdc6ed58a06 99 void port_mco1_mco2_set(uint8_t select);
kenjiArai 0:bfdc6ed58a06 100
kenjiArai 0:bfdc6ed58a06 101 protected:
kenjiArai 0:bfdc6ed58a06 102 DigitalIn _pin;
kenjiArai 0:bfdc6ed58a06 103
kenjiArai 0:bfdc6ed58a06 104 // Initialize TIM2
kenjiArai 0:bfdc6ed58a06 105 // Internal clock (50MHz) and IC2 for GPS 1pps signal measurement
kenjiArai 0:bfdc6ed58a06 106 void initialize_TIM2(void);
kenjiArai 0:bfdc6ed58a06 107
kenjiArai 0:bfdc6ed58a06 108 // Initialize TIM3 and TIM4 as 32bit counter (TIM3(16bit) + TIM4(16bit))
kenjiArai 0:bfdc6ed58a06 109 // TIM3 clock input is unkown freq.(measuring freq.) and TIM4 is slave counter
kenjiArai 0:bfdc6ed58a06 110 // 1sec gate signal connected both TIM3 IC2 and TIM4 IC1
kenjiArai 0:bfdc6ed58a06 111 void initialize_TIM3P4(void);
kenjiArai 0:bfdc6ed58a06 112
kenjiArai 0:bfdc6ed58a06 113 private:
kenjiArai 0:bfdc6ed58a06 114 #if defined(IRQ_DRIVE)
kenjiArai 0:bfdc6ed58a06 115 // 1PPS data
kenjiArai 0:bfdc6ed58a06 116 uint32_t onepps_cnt[CNT_BF_SIZE];
kenjiArai 0:bfdc6ed58a06 117 uint32_t onepps_num;
kenjiArai 0:bfdc6ed58a06 118 uint64_t onepps_cnt_avarage;
kenjiArai 0:bfdc6ed58a06 119 uint8_t onepps_buf_full;
kenjiArai 0:bfdc6ed58a06 120 uint8_t onepps_ready_flg;
kenjiArai 0:bfdc6ed58a06 121 #endif
kenjiArai 0:bfdc6ed58a06 122 };
kenjiArai 0:bfdc6ed58a06 123 } // Frequency_counter
kenjiArai 0:bfdc6ed58a06 124
kenjiArai 0:bfdc6ed58a06 125 #endif // MBED_FRQ_CUNTR