Frequency counter library using GPS 1PPS signal and temperature controlled 50MHz Base clock. Ported from F411 Frequency Counter.
Dependents: Frequency_Cntr_1PPS_F746ZG
Fork of Frq_cuntr_full by
Please refer following.
/users/kenjiArai/notebook/frequency-counters/
Diff: frq_cuntr_full.cpp
- Revision:
- 3:339307e1dc0d
- Parent:
- 2:194f82ad3041
- Child:
- 4:9d3b3f0a3882
--- a/frq_cuntr_full.cpp Sun Dec 21 12:14:46 2014 +0000 +++ b/frq_cuntr_full.cpp Tue Dec 23 23:26:49 2014 +0000 @@ -8,7 +8,7 @@ * http://mbed.org/users/kenjiArai/ * Additional functions and modification * started: October 18th, 2014 - * Revised: December 21st, 2014 + * Revised: December 24th, 2014 * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE @@ -83,7 +83,7 @@ } } #if defined(DEBUG) -// debug_led = !debug_led; + debug_led = !debug_led; #endif } } @@ -96,7 +96,7 @@ tim3p4_cnt_data = (TIM4->CCR1 << 16) + TIM3->CCR2; tim3p4_ready_flg = 1; #if defined(DEBUG) -// debug_led = !debug_led; + debug_led = !debug_led; #endif } @@ -145,17 +145,22 @@ ex_clock_freq = ex_clock; ex_clk_base = (uint32_t)(ex_clock_freq * 1000000); // MHz->Hz clk_hi_const = (uint32_t)(ex_clock_freq * 1000000 * 0.04); // 40mS -// uint32_t err = (uint32_t)(ex_clock_freq * 1000000 * 0.00001); // 10ppm error range - uint32_t err = (uint32_t)(ex_clock_freq * 1000000 * 0.1); +#if defined(CLOCK_DIVIDED_BY_2) + uint32_t err = (uint32_t)(ex_clock_freq * 1000000 * 0.00001); // 10ppm error range +#else + uint32_t err = (uint32_t)(ex_clock_freq * 1000000 * 0.1); // error range +#endif clk_upper_limit = ex_clk_base + err; clk_lower_limit = ex_clk_base - err; + PRINTF("EXTERNAL Clock mode\r\n"); #else - ex_clock_freq = 100; // Internal 100MHz + ex_clock_freq = 100; // Internal 100MHz ex_clk_base = 100000000; // MHz->Hz clk_hi_const = 4000000; // 40mS - uint32_t err = 100; // 10ppm error range + uint32_t err = 10000; // error range clk_upper_limit = ex_clk_base + err; clk_lower_limit = ex_clk_base - err; + PRINTF("INTERNAL Clock mode\r\n"); #endif } @@ -186,7 +191,7 @@ { uint32_t diff = tim2_cnt_data - tim2_old_cnt_data; if ((diff > clk_upper_limit) || (diff < clk_lower_limit)) { -// PRINTF("IC0 %d %d %d \r\n", diff, clk_upper_limit, clk_lower_limit); + PRINTF("IC0 %d %d %d \r\n", diff, clk_upper_limit, clk_lower_limit); gps_ready = 0; return 0; } else { @@ -210,24 +215,28 @@ total += (uint64_t)onepps_cnt[i]; } onepps_cnt_avarage = total / CNT_BF_SIZE; -// PRINTF("buf"); + PRINTF("buf"); } else { for (uint32_t i = 0; i < onepps_num; i++) { total += (uint64_t)onepps_cnt[i]; } onepps_cnt_avarage = total / onepps_num; -// PRINTF("not"); + PRINTF("not"); } -// PRINTF(" full, num= %3d , 1PPS/new= %9d\r\n", onepps_num, onepps_newest); + PRINTF(" full, num= %3d , 1PPS/new= %9d\r\n", onepps_num, onepps_newest); +#if defined(BASE_EXTERNAL_CLOCK) #if defined(ONEPPS_AVE) return onepps_cnt_avarage; #else return onepps_newest; #endif +#else + return onepps_newest; +#endif } // Check GPS condition -uint8_t FRQ_CUNTR::gps_status(void) +uint8_t FRQ_CUNTR::status_gps(void) { return gps_ready; } @@ -294,7 +303,7 @@ TIM2->CNT = 0; wait(gate_time); // Gate time for count freq = TIM2->CNT; // read counter -// PRINTF("Clock freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq, gate_time); + PRINTF("Clock freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq, gate_time); return freq; // return counter data } @@ -310,7 +319,7 @@ freq0 = TIM3->CNT; freq1 = TIM4->CNT; freq0 = (freq1 << 16) + freq0; -// PRINTF("Input freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq0, gate_time); + PRINTF("Input freq.=%10d [Hz], gate= %4.2f [Sec]\r\n", freq0, gate_time); return freq0; // read counter } @@ -344,17 +353,17 @@ // MC01 output HSE 1/1, MCO2 output SYSCLK 1/1 // MCO2 MCO2PRE MCO1PRE MCO1 RCC->CFGR |= (0x0 << 30) + (0x0 << 27) + (0x0 << 24) + (0x2 << 21); -// PRINTF("Set MCO1(PA8):HSE/1, MCO2(PC9):SYSCLK/1\r\n"); + PRINTF("Set MCO1(PA8):HSE/1, MCO2(PC9):SYSCLK/1\r\n"); } else if (select == 2) { // MC01 output HSE 1/2, MCO2 output SYSCLK 1/2 // MCO2 MCO2PRE MCO1PRE MCO1 RCC->CFGR |= (0x0 << 30) + (0x4 << 27) + (0x4 << 24) + (0x2 << 21); -// PRINTF("Set MCO1(PA8):HSE/2, MCO2(PC9):SYSCLK/2\r\n"); + PRINTF("Set MCO1(PA8):HSE/2, MCO2(PC9):SYSCLK/2\r\n"); } else { // select = 4 and other wrong order // MC01 output HSE 1/4, MCO2 output SYSCLK 1/4 // MCO2 MCO2PRE MCO1PRE MCO1 RCC->CFGR |= (0x0 << 30) + (0x6 << 27) + (0x6 << 24) + (0x2 << 21); -// PRINTF("Set MCO1(PA8):HSE/4, MCO2(PC9):SYSCLK/4\r\n"); + PRINTF("Set MCO1(PA8):HSE/4, MCO2(PC9):SYSCLK/4\r\n"); } } @@ -372,7 +381,7 @@ void FRQ_CUNTR::initialize_TIM2(void) { #if defined(BASE_EXTERNAL_CLOCK) - // PA0 -> Counter frequency input pin as Timer2 CH1/TI1 + // PA0 -> Counter frequency input pin as Timer2 CH1/ETR RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN); GPIOA->AFR[0] &= 0xfffffff0; GPIOA->AFR[0] |= GPIO_AF1_TIM2; @@ -390,8 +399,11 @@ TIM2->CCMR1 &= (uint16_t)~(TIM_CCMR1_IC1F | TIM_CCMR1_CC1S); // input filter + input select TIM2->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0; TIM2->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NE | TIM_CCER_CC1NP); // positive edge - TIM2->SMCR &= (uint16_t)~(TIM_SMCR_ECE | TIM_SMCR_TS | TIM_SMCR_SMS); // external mode 1 - TIM2->SMCR |= (uint16_t)( TIM_TS_TI1FP1 | TIM_SLAVEMODE_EXTERNAL1); // ECE must be ZERO!!!! +#if defined(CLOCK_DIVIDED_BY_2) + TIM2->SMCR = (uint16_t)(TIM_SMCR_ECE| TIM_SMCR_ETPS_0 | TIM_SMCR_TS); // clock/2 !! +#else + TIM2->SMCR = (uint16_t)(TIM_SMCR_ECE| TIM_SMCR_TS); // clock/1 !! +#endif TIM2->CR1 |= (uint16_t)TIM_CR1_CEN; // Enable the TIM Counter #else // Initialize Timer2(32bit) for an internal up counter mode @@ -438,7 +450,7 @@ oc_hi_time = oc_set_time0; oc_lo_time = oc_set_time1; TIM2->CCR3 = TIM2->CNT + oc_hi_time;// Set the Capture Compare Register value -#if 0 +#if 1 // Only for Debug purpose BAUD(9600); // PA @@ -547,7 +559,7 @@ TIM4->CCMR1 |= (uint16_t)TIM_CCMR1_CC1S_0; TIM4->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); // positive edge TIM4->CCER |= (uint16_t)TIM_CCER_CC1E; // enable capture -#if 0 +#if 1 // Only for Debug purpose // PB PRINTF("// PB6 -> Input Capture pin as Timer4 CH1/TI1\r\n"); @@ -604,7 +616,7 @@ //--------------------------------------------------------------------------------------- void FRQ_CUNTR::debug_printf_internal_data(void) { -#if 0 +#if 1 PRINTF("Debug information\r\n"); PRINTF("gate_time %f\r\n", gate_time); PRINTF("ex_clock_freq %f\r\n", ex_clock_freq);