shunpei kataoka / nRF51822

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of nRF51822 by Shuta Nakamae

source/nordic-sdk/components/device/nrf51.h@498:d72c7e78ee13, 2015-12-02 (annotated)

Committer:
rgrover1
Date:
Wed Dec 02 10:32:52 2015 +0000
Revision:
498:d72c7e78ee13
Parent:
496:08bd8a46630b 
Synchronized with git rev a583502f

Author: Liyou Zhou

Update files to nrf51 sdk 8.1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rgrover1 496:08bd8a46630b 1 /*
rgrover1 496:08bd8a46630b 2 * Copyright (c) Nordic Semiconductor ASA
rgrover1 496:08bd8a46630b 3 * All rights reserved.
rgrover1 496:08bd8a46630b 4 *
rgrover1 496:08bd8a46630b 5 * Redistribution and use in source and binary forms, with or without modification,
rgrover1 496:08bd8a46630b 6 * are permitted provided that the following conditions are met:
rgrover1 496:08bd8a46630b 7 *
rgrover1 496:08bd8a46630b 8 * 1. Redistributions of source code must retain the above copyright notice, this
rgrover1 496:08bd8a46630b 9 * list of conditions and the following disclaimer.
rgrover1 496:08bd8a46630b 10 *
rgrover1 496:08bd8a46630b 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
rgrover1 496:08bd8a46630b 12 * list of conditions and the following disclaimer in the documentation and/or
rgrover1 496:08bd8a46630b 13 * other materials provided with the distribution.
rgrover1 496:08bd8a46630b 14 *
rgrover1 496:08bd8a46630b 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
rgrover1 496:08bd8a46630b 16 * contributors to this software may be used to endorse or promote products
rgrover1 496:08bd8a46630b 17 * derived from this software without specific prior written permission.
rgrover1 496:08bd8a46630b 18 *
rgrover1 496:08bd8a46630b 19 *
rgrover1 496:08bd8a46630b 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
rgrover1 496:08bd8a46630b 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
rgrover1 496:08bd8a46630b 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
rgrover1 496:08bd8a46630b 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
rgrover1 496:08bd8a46630b 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
rgrover1 496:08bd8a46630b 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
rgrover1 496:08bd8a46630b 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
rgrover1 496:08bd8a46630b 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
rgrover1 496:08bd8a46630b 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
rgrover1 496:08bd8a46630b 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
rgrover1 496:08bd8a46630b 30 *
rgrover1 496:08bd8a46630b 31 */
rgrover1 496:08bd8a46630b 32
rgrover1 496:08bd8a46630b 33 #ifndef NRF51_H
rgrover1 496:08bd8a46630b 34 #define NRF51_H
rgrover1 496:08bd8a46630b 35
rgrover1 496:08bd8a46630b 36 #ifdef __cplusplus
rgrover1 496:08bd8a46630b 37 extern "C" {
rgrover1 496:08bd8a46630b 38 #endif
rgrover1 496:08bd8a46630b 39
rgrover1 496:08bd8a46630b 40
rgrover1 496:08bd8a46630b 41 /* ------------------------- Interrupt Number Definition ------------------------ */
rgrover1 496:08bd8a46630b 42
rgrover1 496:08bd8a46630b 43 typedef enum {
rgrover1 496:08bd8a46630b 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
rgrover1 496:08bd8a46630b 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
rgrover1 496:08bd8a46630b 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
rgrover1 496:08bd8a46630b 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
rgrover1 496:08bd8a46630b 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
rgrover1 496:08bd8a46630b 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
rgrover1 496:08bd8a46630b 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
rgrover1 496:08bd8a46630b 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
rgrover1 498:d72c7e78ee13 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
rgrover1 496:08bd8a46630b 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
rgrover1 496:08bd8a46630b 54 RADIO_IRQn = 1, /*!< 1 RADIO */
rgrover1 496:08bd8a46630b 55 UART0_IRQn = 2, /*!< 2 UART0 */
rgrover1 496:08bd8a46630b 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
rgrover1 496:08bd8a46630b 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
rgrover1 496:08bd8a46630b 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
rgrover1 496:08bd8a46630b 59 ADC_IRQn = 7, /*!< 7 ADC */
rgrover1 496:08bd8a46630b 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
rgrover1 496:08bd8a46630b 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
rgrover1 496:08bd8a46630b 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
rgrover1 496:08bd8a46630b 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
rgrover1 496:08bd8a46630b 64 TEMP_IRQn = 12, /*!< 12 TEMP */
rgrover1 496:08bd8a46630b 65 RNG_IRQn = 13, /*!< 13 RNG */
rgrover1 496:08bd8a46630b 66 ECB_IRQn = 14, /*!< 14 ECB */
rgrover1 496:08bd8a46630b 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
rgrover1 496:08bd8a46630b 68 WDT_IRQn = 16, /*!< 16 WDT */
rgrover1 496:08bd8a46630b 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
rgrover1 496:08bd8a46630b 70 QDEC_IRQn = 18, /*!< 18 QDEC */
rgrover1 496:08bd8a46630b 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
rgrover1 496:08bd8a46630b 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
rgrover1 496:08bd8a46630b 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
rgrover1 496:08bd8a46630b 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
rgrover1 496:08bd8a46630b 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
rgrover1 496:08bd8a46630b 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
rgrover1 496:08bd8a46630b 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
rgrover1 496:08bd8a46630b 78 } IRQn_Type;
rgrover1 496:08bd8a46630b 79
rgrover1 496:08bd8a46630b 80
rgrover1 496:08bd8a46630b 81 /** @addtogroup Configuration_of_CMSIS
rgrover1 496:08bd8a46630b 82 * @{
rgrover1 496:08bd8a46630b 83 */
rgrover1 496:08bd8a46630b 84
rgrover1 496:08bd8a46630b 85
rgrover1 496:08bd8a46630b 86 /* ================================================================================ */
rgrover1 496:08bd8a46630b 87 /* ================ Processor and Core Peripheral Section ================ */
rgrover1 496:08bd8a46630b 88 /* ================================================================================ */
rgrover1 496:08bd8a46630b 89
rgrover1 496:08bd8a46630b 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
rgrover1 496:08bd8a46630b 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
rgrover1 496:08bd8a46630b 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
rgrover1 496:08bd8a46630b 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
rgrover1 496:08bd8a46630b 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
rgrover1 496:08bd8a46630b 95 /** @} */ /* End of group Configuration_of_CMSIS */
rgrover1 496:08bd8a46630b 96
rgrover1 496:08bd8a46630b 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
rgrover1 498:d72c7e78ee13 98 #include "system_nrf51.h" /*!< nrf51 System */
rgrover1 496:08bd8a46630b 99
rgrover1 496:08bd8a46630b 100
rgrover1 496:08bd8a46630b 101 /* ================================================================================ */
rgrover1 496:08bd8a46630b 102 /* ================ Device Specific Peripheral Section ================ */
rgrover1 496:08bd8a46630b 103 /* ================================================================================ */
rgrover1 496:08bd8a46630b 104
rgrover1 496:08bd8a46630b 105
rgrover1 496:08bd8a46630b 106 /** @addtogroup Device_Peripheral_Registers
rgrover1 496:08bd8a46630b 107 * @{
rgrover1 496:08bd8a46630b 108 */
rgrover1 496:08bd8a46630b 109
rgrover1 496:08bd8a46630b 110
rgrover1 496:08bd8a46630b 111 /* ------------------- Start of section using anonymous unions ------------------ */
rgrover1 496:08bd8a46630b 112 #if defined(__CC_ARM)
rgrover1 496:08bd8a46630b 113 #pragma push
rgrover1 496:08bd8a46630b 114 #pragma anon_unions
rgrover1 496:08bd8a46630b 115 #elif defined(__ICCARM__)
rgrover1 496:08bd8a46630b 116 #pragma language=extended
rgrover1 496:08bd8a46630b 117 #elif defined(__GNUC__)
rgrover1 496:08bd8a46630b 118 /* anonymous unions are enabled by default */
rgrover1 496:08bd8a46630b 119 #elif defined(__TMS470__)
rgrover1 496:08bd8a46630b 120 /* anonymous unions are enabled by default */
rgrover1 496:08bd8a46630b 121 #elif defined(__TASKING__)
rgrover1 496:08bd8a46630b 122 #pragma warning 586
rgrover1 496:08bd8a46630b 123 #else
rgrover1 496:08bd8a46630b 124 #warning Not supported compiler type
rgrover1 496:08bd8a46630b 125 #endif
rgrover1 496:08bd8a46630b 126
rgrover1 496:08bd8a46630b 127
rgrover1 496:08bd8a46630b 128 typedef struct {
rgrover1 496:08bd8a46630b 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
rgrover1 496:08bd8a46630b 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
rgrover1 496:08bd8a46630b 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
rgrover1 496:08bd8a46630b 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
rgrover1 496:08bd8a46630b 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
rgrover1 496:08bd8a46630b 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
rgrover1 496:08bd8a46630b 135 } AMLI_RAMPRI_Type;
rgrover1 496:08bd8a46630b 136
rgrover1 496:08bd8a46630b 137 typedef struct {
rgrover1 496:08bd8a46630b 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
rgrover1 496:08bd8a46630b 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
rgrover1 496:08bd8a46630b 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
rgrover1 496:08bd8a46630b 141 } SPIM_PSEL_Type;
rgrover1 496:08bd8a46630b 142
rgrover1 496:08bd8a46630b 143 typedef struct {
rgrover1 496:08bd8a46630b 144 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 496:08bd8a46630b 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
rgrover1 496:08bd8a46630b 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
rgrover1 496:08bd8a46630b 147 } SPIM_RXD_Type;
rgrover1 496:08bd8a46630b 148
rgrover1 496:08bd8a46630b 149 typedef struct {
rgrover1 496:08bd8a46630b 150 __IO uint32_t PTR; /*!< Data pointer. */
rgrover1 496:08bd8a46630b 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
rgrover1 496:08bd8a46630b 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
rgrover1 496:08bd8a46630b 153 } SPIM_TXD_Type;
rgrover1 496:08bd8a46630b 154
rgrover1 496:08bd8a46630b 155 typedef struct {
rgrover1 496:08bd8a46630b 156 __O uint32_t EN; /*!< Enable channel group. */
rgrover1 496:08bd8a46630b 157 __O uint32_t DIS; /*!< Disable channel group. */
rgrover1 496:08bd8a46630b 158 } PPI_TASKS_CHG_Type;
rgrover1 496:08bd8a46630b 159
rgrover1 496:08bd8a46630b 160 typedef struct {
rgrover1 496:08bd8a46630b 161 __IO uint32_t EEP; /*!< Channel event end-point. */
rgrover1 496:08bd8a46630b 162 __IO uint32_t TEP; /*!< Channel task end-point. */
rgrover1 496:08bd8a46630b 163 } PPI_CH_Type;
rgrover1 496:08bd8a46630b 164
rgrover1 496:08bd8a46630b 165
rgrover1 496:08bd8a46630b 166 /* ================================================================================ */
rgrover1 496:08bd8a46630b 167 /* ================ POWER ================ */
rgrover1 496:08bd8a46630b 168 /* ================================================================================ */
rgrover1 496:08bd8a46630b 169
rgrover1 496:08bd8a46630b 170
rgrover1 496:08bd8a46630b 171 /**
rgrover1 496:08bd8a46630b 172 * @brief Power Control. (POWER)
rgrover1 496:08bd8a46630b 173 */
rgrover1 496:08bd8a46630b 174
rgrover1 496:08bd8a46630b 175 typedef struct { /*!< POWER Structure */
rgrover1 496:08bd8a46630b 176 __I uint32_t RESERVED0[30];
rgrover1 496:08bd8a46630b 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
rgrover1 496:08bd8a46630b 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
rgrover1 496:08bd8a46630b 179 __I uint32_t RESERVED1[34];
rgrover1 496:08bd8a46630b 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
rgrover1 496:08bd8a46630b 181 __I uint32_t RESERVED2[126];
rgrover1 496:08bd8a46630b 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 184 __I uint32_t RESERVED3[61];
rgrover1 496:08bd8a46630b 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
rgrover1 496:08bd8a46630b 186 __I uint32_t RESERVED4[9];
rgrover1 496:08bd8a46630b 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
rgrover1 496:08bd8a46630b 188 __I uint32_t RESERVED5[53];
rgrover1 496:08bd8a46630b 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
rgrover1 496:08bd8a46630b 190 __I uint32_t RESERVED6[3];
rgrover1 496:08bd8a46630b 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
rgrover1 496:08bd8a46630b 192 __I uint32_t RESERVED7[2];
rgrover1 496:08bd8a46630b 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
rgrover1 496:08bd8a46630b 194 register. */
rgrover1 496:08bd8a46630b 195 __I uint32_t RESERVED8;
rgrover1 496:08bd8a46630b 196 __IO uint32_t RAMON; /*!< Ram on/off. */
rgrover1 496:08bd8a46630b 197 __I uint32_t RESERVED9[7];
rgrover1 496:08bd8a46630b 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
rgrover1 496:08bd8a46630b 199 is a retained register. */
rgrover1 496:08bd8a46630b 200 __I uint32_t RESERVED10[3];
rgrover1 496:08bd8a46630b 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
rgrover1 496:08bd8a46630b 202 __I uint32_t RESERVED11[8];
rgrover1 496:08bd8a46630b 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
rgrover1 496:08bd8a46630b 204 __I uint32_t RESERVED12[291];
rgrover1 496:08bd8a46630b 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
rgrover1 496:08bd8a46630b 206 } NRF_POWER_Type;
rgrover1 496:08bd8a46630b 207
rgrover1 496:08bd8a46630b 208
rgrover1 496:08bd8a46630b 209 /* ================================================================================ */
rgrover1 496:08bd8a46630b 210 /* ================ CLOCK ================ */
rgrover1 496:08bd8a46630b 211 /* ================================================================================ */
rgrover1 496:08bd8a46630b 212
rgrover1 496:08bd8a46630b 213
rgrover1 496:08bd8a46630b 214 /**
rgrover1 496:08bd8a46630b 215 * @brief Clock control. (CLOCK)
rgrover1 496:08bd8a46630b 216 */
rgrover1 496:08bd8a46630b 217
rgrover1 496:08bd8a46630b 218 typedef struct { /*!< CLOCK Structure */
rgrover1 496:08bd8a46630b 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
rgrover1 496:08bd8a46630b 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
rgrover1 496:08bd8a46630b 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
rgrover1 496:08bd8a46630b 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
rgrover1 496:08bd8a46630b 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
rgrover1 496:08bd8a46630b 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
rgrover1 496:08bd8a46630b 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
rgrover1 496:08bd8a46630b 226 __I uint32_t RESERVED0[57];
rgrover1 496:08bd8a46630b 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
rgrover1 496:08bd8a46630b 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
rgrover1 496:08bd8a46630b 229 __I uint32_t RESERVED1;
rgrover1 496:08bd8a46630b 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
rgrover1 496:08bd8a46630b 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
rgrover1 496:08bd8a46630b 232 __I uint32_t RESERVED2[124];
rgrover1 496:08bd8a46630b 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 235 __I uint32_t RESERVED3[63];
rgrover1 496:08bd8a46630b 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
rgrover1 496:08bd8a46630b 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
rgrover1 496:08bd8a46630b 238 __I uint32_t RESERVED4;
rgrover1 496:08bd8a46630b 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
rgrover1 496:08bd8a46630b 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
rgrover1 496:08bd8a46630b 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
rgrover1 496:08bd8a46630b 242 triggered. */
rgrover1 496:08bd8a46630b 243 __I uint32_t RESERVED5[62];
rgrover1 496:08bd8a46630b 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
rgrover1 496:08bd8a46630b 245 __I uint32_t RESERVED6[7];
rgrover1 496:08bd8a46630b 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
rgrover1 496:08bd8a46630b 247 __I uint32_t RESERVED7[5];
rgrover1 496:08bd8a46630b 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
rgrover1 496:08bd8a46630b 249 } NRF_CLOCK_Type;
rgrover1 496:08bd8a46630b 250
rgrover1 496:08bd8a46630b 251
rgrover1 496:08bd8a46630b 252 /* ================================================================================ */
rgrover1 496:08bd8a46630b 253 /* ================ MPU ================ */
rgrover1 496:08bd8a46630b 254 /* ================================================================================ */
rgrover1 496:08bd8a46630b 255
rgrover1 496:08bd8a46630b 256
rgrover1 496:08bd8a46630b 257 /**
rgrover1 496:08bd8a46630b 258 * @brief Memory Protection Unit. (MPU)
rgrover1 496:08bd8a46630b 259 */
rgrover1 496:08bd8a46630b 260
rgrover1 496:08bd8a46630b 261 typedef struct { /*!< MPU Structure */
rgrover1 496:08bd8a46630b 262 __I uint32_t RESERVED0[330];
rgrover1 496:08bd8a46630b 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
rgrover1 496:08bd8a46630b 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
rgrover1 496:08bd8a46630b 265 __I uint32_t RESERVED1[52];
rgrover1 496:08bd8a46630b 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
rgrover1 496:08bd8a46630b 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
rgrover1 496:08bd8a46630b 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
rgrover1 496:08bd8a46630b 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
rgrover1 496:08bd8a46630b 270 } NRF_MPU_Type;
rgrover1 496:08bd8a46630b 271
rgrover1 496:08bd8a46630b 272
rgrover1 496:08bd8a46630b 273 /* ================================================================================ */
rgrover1 496:08bd8a46630b 274 /* ================ PU ================ */
rgrover1 496:08bd8a46630b 275 /* ================================================================================ */
rgrover1 496:08bd8a46630b 276
rgrover1 496:08bd8a46630b 277
rgrover1 496:08bd8a46630b 278 /**
rgrover1 496:08bd8a46630b 279 * @brief Patch unit. (PU)
rgrover1 496:08bd8a46630b 280 */
rgrover1 496:08bd8a46630b 281
rgrover1 496:08bd8a46630b 282 typedef struct { /*!< PU Structure */
rgrover1 496:08bd8a46630b 283 __I uint32_t RESERVED0[448];
rgrover1 496:08bd8a46630b 284 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
rgrover1 496:08bd8a46630b 285 __I uint32_t RESERVED1[24];
rgrover1 496:08bd8a46630b 286 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
rgrover1 496:08bd8a46630b 287 __I uint32_t RESERVED2[24];
rgrover1 496:08bd8a46630b 288 __IO uint32_t PATCHEN; /*!< Patch enable register. */
rgrover1 496:08bd8a46630b 289 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
rgrover1 496:08bd8a46630b 290 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
rgrover1 496:08bd8a46630b 291 } NRF_PU_Type;
rgrover1 496:08bd8a46630b 292
rgrover1 496:08bd8a46630b 293
rgrover1 496:08bd8a46630b 294 /* ================================================================================ */
rgrover1 496:08bd8a46630b 295 /* ================ AMLI ================ */
rgrover1 496:08bd8a46630b 296 /* ================================================================================ */
rgrover1 496:08bd8a46630b 297
rgrover1 496:08bd8a46630b 298
rgrover1 496:08bd8a46630b 299 /**
rgrover1 496:08bd8a46630b 300 * @brief AHB Multi-Layer Interface. (AMLI)
rgrover1 496:08bd8a46630b 301 */
rgrover1 496:08bd8a46630b 302
rgrover1 496:08bd8a46630b 303 typedef struct { /*!< AMLI Structure */
rgrover1 496:08bd8a46630b 304 __I uint32_t RESERVED0[896];
rgrover1 496:08bd8a46630b 305 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
rgrover1 496:08bd8a46630b 306 } NRF_AMLI_Type;
rgrover1 496:08bd8a46630b 307
rgrover1 496:08bd8a46630b 308
rgrover1 496:08bd8a46630b 309 /* ================================================================================ */
rgrover1 496:08bd8a46630b 310 /* ================ RADIO ================ */
rgrover1 496:08bd8a46630b 311 /* ================================================================================ */
rgrover1 496:08bd8a46630b 312
rgrover1 496:08bd8a46630b 313
rgrover1 496:08bd8a46630b 314 /**
rgrover1 496:08bd8a46630b 315 * @brief The radio. (RADIO)
rgrover1 496:08bd8a46630b 316 */
rgrover1 496:08bd8a46630b 317
rgrover1 496:08bd8a46630b 318 typedef struct { /*!< RADIO Structure */
rgrover1 496:08bd8a46630b 319 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
rgrover1 496:08bd8a46630b 320 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
rgrover1 496:08bd8a46630b 321 __O uint32_t TASKS_START; /*!< Start radio. */
rgrover1 496:08bd8a46630b 322 __O uint32_t TASKS_STOP; /*!< Stop radio. */
rgrover1 496:08bd8a46630b 323 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
rgrover1 496:08bd8a46630b 324 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
rgrover1 496:08bd8a46630b 325 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
rgrover1 496:08bd8a46630b 326 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
rgrover1 496:08bd8a46630b 327 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
rgrover1 496:08bd8a46630b 328 __I uint32_t RESERVED0[55];
rgrover1 496:08bd8a46630b 329 __IO uint32_t EVENTS_READY; /*!< Ready event. */
rgrover1 496:08bd8a46630b 330 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
rgrover1 496:08bd8a46630b 331 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
rgrover1 496:08bd8a46630b 332 __IO uint32_t EVENTS_END; /*!< End event. */
rgrover1 496:08bd8a46630b 333 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
rgrover1 496:08bd8a46630b 334 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
rgrover1 496:08bd8a46630b 335 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
rgrover1 496:08bd8a46630b 336 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
rgrover1 496:08bd8a46630b 337 sample is ready for readout at the RSSISAMPLE register. */
rgrover1 496:08bd8a46630b 338 __I uint32_t RESERVED1[2];
rgrover1 498:d72c7e78ee13 339 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
rgrover1 496:08bd8a46630b 340 __I uint32_t RESERVED2[53];
rgrover1 496:08bd8a46630b 341 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
rgrover1 496:08bd8a46630b 342 __I uint32_t RESERVED3[64];
rgrover1 496:08bd8a46630b 343 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 344 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 345 __I uint32_t RESERVED4[61];
rgrover1 496:08bd8a46630b 346 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
rgrover1 496:08bd8a46630b 347 __I uint32_t CD; /*!< Carrier detect. */
rgrover1 496:08bd8a46630b 348 __I uint32_t RXMATCH; /*!< Received address. */
rgrover1 496:08bd8a46630b 349 __I uint32_t RXCRC; /*!< Received CRC. */
rgrover1 496:08bd8a46630b 350 __I uint32_t DAI; /*!< Device address match index. */
rgrover1 496:08bd8a46630b 351 __I uint32_t RESERVED5[60];
rgrover1 496:08bd8a46630b 352 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
rgrover1 496:08bd8a46630b 353 __IO uint32_t FREQUENCY; /*!< Frequency. */
rgrover1 496:08bd8a46630b 354 __IO uint32_t TXPOWER; /*!< Output power. */
rgrover1 496:08bd8a46630b 355 __IO uint32_t MODE; /*!< Data rate and modulation. */
rgrover1 496:08bd8a46630b 356 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
rgrover1 496:08bd8a46630b 357 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
rgrover1 496:08bd8a46630b 358 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
rgrover1 496:08bd8a46630b 359 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
rgrover1 496:08bd8a46630b 360 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
rgrover1 496:08bd8a46630b 361 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
rgrover1 496:08bd8a46630b 362 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
rgrover1 496:08bd8a46630b 363 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
rgrover1 496:08bd8a46630b 364 __IO uint32_t CRCCNF; /*!< CRC configuration. */
rgrover1 496:08bd8a46630b 365 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
rgrover1 496:08bd8a46630b 366 __IO uint32_t CRCINIT; /*!< CRC initial value. */
rgrover1 496:08bd8a46630b 367 __IO uint32_t TEST; /*!< Test features enable register. */
rgrover1 496:08bd8a46630b 368 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
rgrover1 496:08bd8a46630b 369 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
rgrover1 496:08bd8a46630b 370 __I uint32_t RESERVED6;
rgrover1 496:08bd8a46630b 371 __I uint32_t STATE; /*!< Current radio state. */
rgrover1 496:08bd8a46630b 372 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
rgrover1 496:08bd8a46630b 373 __I uint32_t RESERVED7[2];
rgrover1 496:08bd8a46630b 374 __IO uint32_t BCC; /*!< Bit counter compare. */
rgrover1 496:08bd8a46630b 375 __I uint32_t RESERVED8[39];
rgrover1 496:08bd8a46630b 376 __IO uint32_t DAB[8]; /*!< Device address base segment. */
rgrover1 496:08bd8a46630b 377 __IO uint32_t DAP[8]; /*!< Device address prefix. */
rgrover1 496:08bd8a46630b 378 __IO uint32_t DACNF; /*!< Device address match configuration. */
rgrover1 496:08bd8a46630b 379 __I uint32_t RESERVED9[56];
rgrover1 496:08bd8a46630b 380 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
rgrover1 496:08bd8a46630b 381 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
rgrover1 496:08bd8a46630b 382 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
rgrover1 496:08bd8a46630b 383 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
rgrover1 496:08bd8a46630b 384 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
rgrover1 496:08bd8a46630b 385 __I uint32_t RESERVED10[561];
rgrover1 496:08bd8a46630b 386 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 387 } NRF_RADIO_Type;
rgrover1 496:08bd8a46630b 388
rgrover1 496:08bd8a46630b 389
rgrover1 496:08bd8a46630b 390 /* ================================================================================ */
rgrover1 496:08bd8a46630b 391 /* ================ UART ================ */
rgrover1 496:08bd8a46630b 392 /* ================================================================================ */
rgrover1 496:08bd8a46630b 393
rgrover1 496:08bd8a46630b 394
rgrover1 496:08bd8a46630b 395 /**
rgrover1 496:08bd8a46630b 396 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
rgrover1 496:08bd8a46630b 397 */
rgrover1 496:08bd8a46630b 398
rgrover1 496:08bd8a46630b 399 typedef struct { /*!< UART Structure */
rgrover1 496:08bd8a46630b 400 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
rgrover1 496:08bd8a46630b 401 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
rgrover1 496:08bd8a46630b 402 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
rgrover1 496:08bd8a46630b 403 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
rgrover1 496:08bd8a46630b 404 __I uint32_t RESERVED0[3];
rgrover1 496:08bd8a46630b 405 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
rgrover1 496:08bd8a46630b 406 __I uint32_t RESERVED1[56];
rgrover1 496:08bd8a46630b 407 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
rgrover1 496:08bd8a46630b 408 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
rgrover1 496:08bd8a46630b 409 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
rgrover1 496:08bd8a46630b 410 __I uint32_t RESERVED2[4];
rgrover1 496:08bd8a46630b 411 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
rgrover1 496:08bd8a46630b 412 __I uint32_t RESERVED3;
rgrover1 496:08bd8a46630b 413 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
rgrover1 496:08bd8a46630b 414 __I uint32_t RESERVED4[7];
rgrover1 496:08bd8a46630b 415 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
rgrover1 498:d72c7e78ee13 416 __I uint32_t RESERVED5[111];
rgrover1 496:08bd8a46630b 417 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 418 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 498:d72c7e78ee13 419 __I uint32_t RESERVED6[93];
rgrover1 496:08bd8a46630b 420 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
rgrover1 498:d72c7e78ee13 421 __I uint32_t RESERVED7[31];
rgrover1 496:08bd8a46630b 422 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
rgrover1 498:d72c7e78ee13 423 __I uint32_t RESERVED8;
rgrover1 496:08bd8a46630b 424 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
rgrover1 496:08bd8a46630b 425 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
rgrover1 496:08bd8a46630b 426 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
rgrover1 496:08bd8a46630b 427 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
rgrover1 496:08bd8a46630b 428 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
rgrover1 496:08bd8a46630b 429 Once read the character is consumed. If read when no character
rgrover1 496:08bd8a46630b 430 available, the UART will stop working. */
rgrover1 496:08bd8a46630b 431 __O uint32_t TXD; /*!< TXD register. */
rgrover1 498:d72c7e78ee13 432 __I uint32_t RESERVED9;
rgrover1 496:08bd8a46630b 433 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
rgrover1 498:d72c7e78ee13 434 __I uint32_t RESERVED10[17];
rgrover1 496:08bd8a46630b 435 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
rgrover1 498:d72c7e78ee13 436 __I uint32_t RESERVED11[675];
rgrover1 496:08bd8a46630b 437 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 438 } NRF_UART_Type;
rgrover1 496:08bd8a46630b 439
rgrover1 496:08bd8a46630b 440
rgrover1 496:08bd8a46630b 441 /* ================================================================================ */
rgrover1 496:08bd8a46630b 442 /* ================ SPI ================ */
rgrover1 496:08bd8a46630b 443 /* ================================================================================ */
rgrover1 496:08bd8a46630b 444
rgrover1 496:08bd8a46630b 445
rgrover1 496:08bd8a46630b 446 /**
rgrover1 496:08bd8a46630b 447 * @brief SPI master 0. (SPI)
rgrover1 496:08bd8a46630b 448 */
rgrover1 496:08bd8a46630b 449
rgrover1 496:08bd8a46630b 450 typedef struct { /*!< SPI Structure */
rgrover1 496:08bd8a46630b 451 __I uint32_t RESERVED0[66];
rgrover1 496:08bd8a46630b 452 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
rgrover1 496:08bd8a46630b 453 __I uint32_t RESERVED1[126];
rgrover1 496:08bd8a46630b 454 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 455 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 456 __I uint32_t RESERVED2[125];
rgrover1 496:08bd8a46630b 457 __IO uint32_t ENABLE; /*!< Enable SPI. */
rgrover1 496:08bd8a46630b 458 __I uint32_t RESERVED3;
rgrover1 496:08bd8a46630b 459 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 496:08bd8a46630b 460 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 496:08bd8a46630b 461 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 496:08bd8a46630b 462 __I uint32_t RESERVED4;
rgrover1 496:08bd8a46630b 463 __I uint32_t RXD; /*!< RX data. */
rgrover1 496:08bd8a46630b 464 __IO uint32_t TXD; /*!< TX data. */
rgrover1 496:08bd8a46630b 465 __I uint32_t RESERVED5;
rgrover1 496:08bd8a46630b 466 __IO uint32_t FREQUENCY; /*!< SPI frequency */
rgrover1 496:08bd8a46630b 467 __I uint32_t RESERVED6[11];
rgrover1 496:08bd8a46630b 468 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 496:08bd8a46630b 469 __I uint32_t RESERVED7[681];
rgrover1 496:08bd8a46630b 470 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 471 } NRF_SPI_Type;
rgrover1 496:08bd8a46630b 472
rgrover1 496:08bd8a46630b 473
rgrover1 496:08bd8a46630b 474 /* ================================================================================ */
rgrover1 496:08bd8a46630b 475 /* ================ TWI ================ */
rgrover1 496:08bd8a46630b 476 /* ================================================================================ */
rgrover1 496:08bd8a46630b 477
rgrover1 496:08bd8a46630b 478
rgrover1 496:08bd8a46630b 479 /**
rgrover1 496:08bd8a46630b 480 * @brief Two-wire interface master 0. (TWI)
rgrover1 496:08bd8a46630b 481 */
rgrover1 496:08bd8a46630b 482
rgrover1 496:08bd8a46630b 483 typedef struct { /*!< TWI Structure */
rgrover1 496:08bd8a46630b 484 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
rgrover1 496:08bd8a46630b 485 __I uint32_t RESERVED0;
rgrover1 496:08bd8a46630b 486 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
rgrover1 496:08bd8a46630b 487 __I uint32_t RESERVED1[2];
rgrover1 496:08bd8a46630b 488 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
rgrover1 496:08bd8a46630b 489 __I uint32_t RESERVED2;
rgrover1 496:08bd8a46630b 490 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
rgrover1 496:08bd8a46630b 491 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
rgrover1 496:08bd8a46630b 492 __I uint32_t RESERVED3[56];
rgrover1 496:08bd8a46630b 493 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
rgrover1 496:08bd8a46630b 494 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
rgrover1 496:08bd8a46630b 495 __I uint32_t RESERVED4[4];
rgrover1 496:08bd8a46630b 496 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
rgrover1 496:08bd8a46630b 497 __I uint32_t RESERVED5;
rgrover1 496:08bd8a46630b 498 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
rgrover1 496:08bd8a46630b 499 __I uint32_t RESERVED6[4];
rgrover1 496:08bd8a46630b 500 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
rgrover1 496:08bd8a46630b 501 __I uint32_t RESERVED7[3];
rgrover1 496:08bd8a46630b 502 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
rgrover1 496:08bd8a46630b 503 __I uint32_t RESERVED8[45];
rgrover1 496:08bd8a46630b 504 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
rgrover1 496:08bd8a46630b 505 __I uint32_t RESERVED9[64];
rgrover1 496:08bd8a46630b 506 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 507 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 508 __I uint32_t RESERVED10[110];
rgrover1 496:08bd8a46630b 509 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
rgrover1 496:08bd8a46630b 510 __I uint32_t RESERVED11[14];
rgrover1 496:08bd8a46630b 511 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
rgrover1 496:08bd8a46630b 512 __I uint32_t RESERVED12;
rgrover1 496:08bd8a46630b 513 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
rgrover1 496:08bd8a46630b 514 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
rgrover1 496:08bd8a46630b 515 __I uint32_t RESERVED13[2];
rgrover1 496:08bd8a46630b 516 __I uint32_t RXD; /*!< RX data register. */
rgrover1 496:08bd8a46630b 517 __IO uint32_t TXD; /*!< TX data register. */
rgrover1 496:08bd8a46630b 518 __I uint32_t RESERVED14;
rgrover1 496:08bd8a46630b 519 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
rgrover1 496:08bd8a46630b 520 __I uint32_t RESERVED15[24];
rgrover1 496:08bd8a46630b 521 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
rgrover1 496:08bd8a46630b 522 __I uint32_t RESERVED16[668];
rgrover1 496:08bd8a46630b 523 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 524 } NRF_TWI_Type;
rgrover1 496:08bd8a46630b 525
rgrover1 496:08bd8a46630b 526
rgrover1 496:08bd8a46630b 527 /* ================================================================================ */
rgrover1 496:08bd8a46630b 528 /* ================ SPIS ================ */
rgrover1 496:08bd8a46630b 529 /* ================================================================================ */
rgrover1 496:08bd8a46630b 530
rgrover1 496:08bd8a46630b 531
rgrover1 496:08bd8a46630b 532 /**
rgrover1 496:08bd8a46630b 533 * @brief SPI slave 1. (SPIS)
rgrover1 496:08bd8a46630b 534 */
rgrover1 496:08bd8a46630b 535
rgrover1 496:08bd8a46630b 536 typedef struct { /*!< SPIS Structure */
rgrover1 496:08bd8a46630b 537 __I uint32_t RESERVED0[9];
rgrover1 496:08bd8a46630b 538 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
rgrover1 496:08bd8a46630b 539 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
rgrover1 496:08bd8a46630b 540 __I uint32_t RESERVED1[54];
rgrover1 496:08bd8a46630b 541 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
rgrover1 496:08bd8a46630b 542 __I uint32_t RESERVED2[8];
rgrover1 496:08bd8a46630b 543 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
rgrover1 496:08bd8a46630b 544 __I uint32_t RESERVED3[53];
rgrover1 496:08bd8a46630b 545 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
rgrover1 496:08bd8a46630b 546 __I uint32_t RESERVED4[64];
rgrover1 496:08bd8a46630b 547 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 548 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 549 __I uint32_t RESERVED5[61];
rgrover1 496:08bd8a46630b 550 __I uint32_t SEMSTAT; /*!< Semaphore status. */
rgrover1 496:08bd8a46630b 551 __I uint32_t RESERVED6[15];
rgrover1 496:08bd8a46630b 552 __IO uint32_t STATUS; /*!< Status from last transaction. */
rgrover1 496:08bd8a46630b 553 __I uint32_t RESERVED7[47];
rgrover1 496:08bd8a46630b 554 __IO uint32_t ENABLE; /*!< Enable SPIS. */
rgrover1 496:08bd8a46630b 555 __I uint32_t RESERVED8;
rgrover1 496:08bd8a46630b 556 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
rgrover1 496:08bd8a46630b 557 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
rgrover1 496:08bd8a46630b 558 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
rgrover1 496:08bd8a46630b 559 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
rgrover1 496:08bd8a46630b 560 __I uint32_t RESERVED9[7];
rgrover1 496:08bd8a46630b 561 __IO uint32_t RXDPTR; /*!< RX data pointer. */
rgrover1 496:08bd8a46630b 562 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
rgrover1 496:08bd8a46630b 563 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
rgrover1 496:08bd8a46630b 564 __I uint32_t RESERVED10;
rgrover1 496:08bd8a46630b 565 __IO uint32_t TXDPTR; /*!< TX data pointer. */
rgrover1 496:08bd8a46630b 566 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
rgrover1 496:08bd8a46630b 567 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
rgrover1 496:08bd8a46630b 568 __I uint32_t RESERVED11;
rgrover1 496:08bd8a46630b 569 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 496:08bd8a46630b 570 __I uint32_t RESERVED12;
rgrover1 496:08bd8a46630b 571 __IO uint32_t DEF; /*!< Default character. */
rgrover1 496:08bd8a46630b 572 __I uint32_t RESERVED13[24];
rgrover1 496:08bd8a46630b 573 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 496:08bd8a46630b 574 __I uint32_t RESERVED14[654];
rgrover1 496:08bd8a46630b 575 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 576 } NRF_SPIS_Type;
rgrover1 496:08bd8a46630b 577
rgrover1 496:08bd8a46630b 578
rgrover1 496:08bd8a46630b 579 /* ================================================================================ */
rgrover1 496:08bd8a46630b 580 /* ================ SPIM ================ */
rgrover1 496:08bd8a46630b 581 /* ================================================================================ */
rgrover1 496:08bd8a46630b 582
rgrover1 496:08bd8a46630b 583
rgrover1 496:08bd8a46630b 584 /**
rgrover1 496:08bd8a46630b 585 * @brief SPI master with easyDMA 1. (SPIM)
rgrover1 496:08bd8a46630b 586 */
rgrover1 496:08bd8a46630b 587
rgrover1 496:08bd8a46630b 588 typedef struct { /*!< SPIM Structure */
rgrover1 496:08bd8a46630b 589 __I uint32_t RESERVED0[4];
rgrover1 496:08bd8a46630b 590 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
rgrover1 496:08bd8a46630b 591 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
rgrover1 496:08bd8a46630b 592 __I uint32_t RESERVED1;
rgrover1 496:08bd8a46630b 593 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
rgrover1 496:08bd8a46630b 594 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
rgrover1 496:08bd8a46630b 595 __I uint32_t RESERVED2[56];
rgrover1 496:08bd8a46630b 596 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
rgrover1 496:08bd8a46630b 597 __I uint32_t RESERVED3[2];
rgrover1 496:08bd8a46630b 598 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
rgrover1 496:08bd8a46630b 599 __I uint32_t RESERVED4;
rgrover1 496:08bd8a46630b 600 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
rgrover1 496:08bd8a46630b 601 __I uint32_t RESERVED5;
rgrover1 496:08bd8a46630b 602 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
rgrover1 496:08bd8a46630b 603 __I uint32_t RESERVED6[10];
rgrover1 496:08bd8a46630b 604 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
rgrover1 496:08bd8a46630b 605 __I uint32_t RESERVED7[44];
rgrover1 496:08bd8a46630b 606 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
rgrover1 496:08bd8a46630b 607 __I uint32_t RESERVED8[64];
rgrover1 496:08bd8a46630b 608 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 609 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 610 __I uint32_t RESERVED9[125];
rgrover1 496:08bd8a46630b 611 __IO uint32_t ENABLE; /*!< Enable SPIM. */
rgrover1 496:08bd8a46630b 612 __I uint32_t RESERVED10;
rgrover1 496:08bd8a46630b 613 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
rgrover1 498:d72c7e78ee13 614 __I uint32_t RESERVED11[4];
rgrover1 496:08bd8a46630b 615 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
rgrover1 498:d72c7e78ee13 616 __I uint32_t RESERVED12[3];
rgrover1 496:08bd8a46630b 617 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
rgrover1 498:d72c7e78ee13 618 __I uint32_t RESERVED13;
rgrover1 496:08bd8a46630b 619 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
rgrover1 498:d72c7e78ee13 620 __I uint32_t RESERVED14;
rgrover1 496:08bd8a46630b 621 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 498:d72c7e78ee13 622 __I uint32_t RESERVED15[26];
rgrover1 496:08bd8a46630b 623 __IO uint32_t ORC; /*!< Over-read character. */
rgrover1 498:d72c7e78ee13 624 __I uint32_t RESERVED16[654];
rgrover1 496:08bd8a46630b 625 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 626 } NRF_SPIM_Type;
rgrover1 496:08bd8a46630b 627
rgrover1 496:08bd8a46630b 628
rgrover1 496:08bd8a46630b 629 /* ================================================================================ */
rgrover1 496:08bd8a46630b 630 /* ================ GPIOTE ================ */
rgrover1 496:08bd8a46630b 631 /* ================================================================================ */
rgrover1 496:08bd8a46630b 632
rgrover1 496:08bd8a46630b 633
rgrover1 496:08bd8a46630b 634 /**
rgrover1 496:08bd8a46630b 635 * @brief GPIO tasks and events. (GPIOTE)
rgrover1 496:08bd8a46630b 636 */
rgrover1 496:08bd8a46630b 637
rgrover1 496:08bd8a46630b 638 typedef struct { /*!< GPIOTE Structure */
rgrover1 496:08bd8a46630b 639 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 496:08bd8a46630b 640 __I uint32_t RESERVED0[60];
rgrover1 496:08bd8a46630b 641 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
rgrover1 496:08bd8a46630b 642 __I uint32_t RESERVED1[27];
rgrover1 496:08bd8a46630b 643 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
rgrover1 496:08bd8a46630b 644 __I uint32_t RESERVED2[97];
rgrover1 496:08bd8a46630b 645 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 646 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 647 __I uint32_t RESERVED3[129];
rgrover1 496:08bd8a46630b 648 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
rgrover1 496:08bd8a46630b 649 __I uint32_t RESERVED4[695];
rgrover1 496:08bd8a46630b 650 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 651 } NRF_GPIOTE_Type;
rgrover1 496:08bd8a46630b 652
rgrover1 496:08bd8a46630b 653
rgrover1 496:08bd8a46630b 654 /* ================================================================================ */
rgrover1 496:08bd8a46630b 655 /* ================ ADC ================ */
rgrover1 496:08bd8a46630b 656 /* ================================================================================ */
rgrover1 496:08bd8a46630b 657
rgrover1 496:08bd8a46630b 658
rgrover1 496:08bd8a46630b 659 /**
rgrover1 496:08bd8a46630b 660 * @brief Analog to digital converter. (ADC)
rgrover1 496:08bd8a46630b 661 */
rgrover1 496:08bd8a46630b 662
rgrover1 496:08bd8a46630b 663 typedef struct { /*!< ADC Structure */
rgrover1 496:08bd8a46630b 664 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
rgrover1 496:08bd8a46630b 665 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
rgrover1 496:08bd8a46630b 666 __I uint32_t RESERVED0[62];
rgrover1 496:08bd8a46630b 667 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
rgrover1 496:08bd8a46630b 668 __I uint32_t RESERVED1[128];
rgrover1 496:08bd8a46630b 669 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 670 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 671 __I uint32_t RESERVED2[61];
rgrover1 496:08bd8a46630b 672 __I uint32_t BUSY; /*!< ADC busy register. */
rgrover1 496:08bd8a46630b 673 __I uint32_t RESERVED3[63];
rgrover1 496:08bd8a46630b 674 __IO uint32_t ENABLE; /*!< ADC enable. */
rgrover1 496:08bd8a46630b 675 __IO uint32_t CONFIG; /*!< ADC configuration register. */
rgrover1 496:08bd8a46630b 676 __I uint32_t RESULT; /*!< Result of ADC conversion. */
rgrover1 496:08bd8a46630b 677 __I uint32_t RESERVED4[700];
rgrover1 496:08bd8a46630b 678 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 679 } NRF_ADC_Type;
rgrover1 496:08bd8a46630b 680
rgrover1 496:08bd8a46630b 681
rgrover1 496:08bd8a46630b 682 /* ================================================================================ */
rgrover1 496:08bd8a46630b 683 /* ================ TIMER ================ */
rgrover1 496:08bd8a46630b 684 /* ================================================================================ */
rgrover1 496:08bd8a46630b 685
rgrover1 496:08bd8a46630b 686
rgrover1 496:08bd8a46630b 687 /**
rgrover1 496:08bd8a46630b 688 * @brief Timer 0. (TIMER)
rgrover1 496:08bd8a46630b 689 */
rgrover1 496:08bd8a46630b 690
rgrover1 496:08bd8a46630b 691 typedef struct { /*!< TIMER Structure */
rgrover1 496:08bd8a46630b 692 __O uint32_t TASKS_START; /*!< Start Timer. */
rgrover1 496:08bd8a46630b 693 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
rgrover1 496:08bd8a46630b 694 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
rgrover1 496:08bd8a46630b 695 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
rgrover1 496:08bd8a46630b 696 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
rgrover1 496:08bd8a46630b 697 __I uint32_t RESERVED0[11];
rgrover1 496:08bd8a46630b 698 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
rgrover1 496:08bd8a46630b 699 __I uint32_t RESERVED1[60];
rgrover1 496:08bd8a46630b 700 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 496:08bd8a46630b 701 __I uint32_t RESERVED2[44];
rgrover1 496:08bd8a46630b 702 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
rgrover1 496:08bd8a46630b 703 __I uint32_t RESERVED3[64];
rgrover1 496:08bd8a46630b 704 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 705 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 706 __I uint32_t RESERVED4[126];
rgrover1 496:08bd8a46630b 707 __IO uint32_t MODE; /*!< Timer Mode selection. */
rgrover1 496:08bd8a46630b 708 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
rgrover1 496:08bd8a46630b 709 __I uint32_t RESERVED5;
rgrover1 496:08bd8a46630b 710 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
rgrover1 496:08bd8a46630b 711 clock frequency is divided by 2^SCALE. */
rgrover1 496:08bd8a46630b 712 __I uint32_t RESERVED6[11];
rgrover1 496:08bd8a46630b 713 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 496:08bd8a46630b 714 __I uint32_t RESERVED7[683];
rgrover1 496:08bd8a46630b 715 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 716 } NRF_TIMER_Type;
rgrover1 496:08bd8a46630b 717
rgrover1 496:08bd8a46630b 718
rgrover1 496:08bd8a46630b 719 /* ================================================================================ */
rgrover1 496:08bd8a46630b 720 /* ================ RTC ================ */
rgrover1 496:08bd8a46630b 721 /* ================================================================================ */
rgrover1 496:08bd8a46630b 722
rgrover1 496:08bd8a46630b 723
rgrover1 496:08bd8a46630b 724 /**
rgrover1 496:08bd8a46630b 725 * @brief Real time counter 0. (RTC)
rgrover1 496:08bd8a46630b 726 */
rgrover1 496:08bd8a46630b 727
rgrover1 496:08bd8a46630b 728 typedef struct { /*!< RTC Structure */
rgrover1 496:08bd8a46630b 729 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
rgrover1 496:08bd8a46630b 730 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
rgrover1 496:08bd8a46630b 731 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
rgrover1 496:08bd8a46630b 732 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
rgrover1 496:08bd8a46630b 733 __I uint32_t RESERVED0[60];
rgrover1 496:08bd8a46630b 734 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
rgrover1 496:08bd8a46630b 735 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
rgrover1 496:08bd8a46630b 736 __I uint32_t RESERVED1[14];
rgrover1 496:08bd8a46630b 737 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
rgrover1 496:08bd8a46630b 738 __I uint32_t RESERVED2[109];
rgrover1 496:08bd8a46630b 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 741 __I uint32_t RESERVED3[13];
rgrover1 496:08bd8a46630b 742 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
rgrover1 496:08bd8a46630b 743 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
rgrover1 496:08bd8a46630b 744 the value of EVTEN. */
rgrover1 496:08bd8a46630b 745 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
rgrover1 496:08bd8a46630b 746 gives the value of EVTEN. */
rgrover1 496:08bd8a46630b 747 __I uint32_t RESERVED4[110];
rgrover1 496:08bd8a46630b 748 __I uint32_t COUNTER; /*!< Current COUNTER value. */
rgrover1 496:08bd8a46630b 749 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
rgrover1 496:08bd8a46630b 750 Must be written when RTC is STOPed. */
rgrover1 496:08bd8a46630b 751 __I uint32_t RESERVED5[13];
rgrover1 496:08bd8a46630b 752 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
rgrover1 496:08bd8a46630b 753 __I uint32_t RESERVED6[683];
rgrover1 496:08bd8a46630b 754 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 755 } NRF_RTC_Type;
rgrover1 496:08bd8a46630b 756
rgrover1 496:08bd8a46630b 757
rgrover1 496:08bd8a46630b 758 /* ================================================================================ */
rgrover1 496:08bd8a46630b 759 /* ================ TEMP ================ */
rgrover1 496:08bd8a46630b 760 /* ================================================================================ */
rgrover1 496:08bd8a46630b 761
rgrover1 496:08bd8a46630b 762
rgrover1 496:08bd8a46630b 763 /**
rgrover1 496:08bd8a46630b 764 * @brief Temperature Sensor. (TEMP)
rgrover1 496:08bd8a46630b 765 */
rgrover1 496:08bd8a46630b 766
rgrover1 496:08bd8a46630b 767 typedef struct { /*!< TEMP Structure */
rgrover1 496:08bd8a46630b 768 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
rgrover1 496:08bd8a46630b 769 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
rgrover1 496:08bd8a46630b 770 __I uint32_t RESERVED0[62];
rgrover1 496:08bd8a46630b 771 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
rgrover1 496:08bd8a46630b 772 __I uint32_t RESERVED1[128];
rgrover1 496:08bd8a46630b 773 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 774 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 775 __I uint32_t RESERVED2[127];
rgrover1 496:08bd8a46630b 776 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
rgrover1 496:08bd8a46630b 777 __I uint32_t RESERVED3[700];
rgrover1 496:08bd8a46630b 778 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 779 } NRF_TEMP_Type;
rgrover1 496:08bd8a46630b 780
rgrover1 496:08bd8a46630b 781
rgrover1 496:08bd8a46630b 782 /* ================================================================================ */
rgrover1 496:08bd8a46630b 783 /* ================ RNG ================ */
rgrover1 496:08bd8a46630b 784 /* ================================================================================ */
rgrover1 496:08bd8a46630b 785
rgrover1 496:08bd8a46630b 786
rgrover1 496:08bd8a46630b 787 /**
rgrover1 496:08bd8a46630b 788 * @brief Random Number Generator. (RNG)
rgrover1 496:08bd8a46630b 789 */
rgrover1 496:08bd8a46630b 790
rgrover1 496:08bd8a46630b 791 typedef struct { /*!< RNG Structure */
rgrover1 496:08bd8a46630b 792 __O uint32_t TASKS_START; /*!< Start the random number generator. */
rgrover1 496:08bd8a46630b 793 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
rgrover1 496:08bd8a46630b 794 __I uint32_t RESERVED0[62];
rgrover1 496:08bd8a46630b 795 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
rgrover1 496:08bd8a46630b 796 __I uint32_t RESERVED1[63];
rgrover1 496:08bd8a46630b 797 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
rgrover1 496:08bd8a46630b 798 __I uint32_t RESERVED2[64];
rgrover1 496:08bd8a46630b 799 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
rgrover1 496:08bd8a46630b 800 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
rgrover1 496:08bd8a46630b 801 __I uint32_t RESERVED3[126];
rgrover1 496:08bd8a46630b 802 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 496:08bd8a46630b 803 __I uint32_t VALUE; /*!< RNG random number. */
rgrover1 496:08bd8a46630b 804 __I uint32_t RESERVED4[700];
rgrover1 496:08bd8a46630b 805 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 806 } NRF_RNG_Type;
rgrover1 496:08bd8a46630b 807
rgrover1 496:08bd8a46630b 808
rgrover1 496:08bd8a46630b 809 /* ================================================================================ */
rgrover1 496:08bd8a46630b 810 /* ================ ECB ================ */
rgrover1 496:08bd8a46630b 811 /* ================================================================================ */
rgrover1 496:08bd8a46630b 812
rgrover1 496:08bd8a46630b 813
rgrover1 496:08bd8a46630b 814 /**
rgrover1 496:08bd8a46630b 815 * @brief AES ECB Mode Encryption. (ECB)
rgrover1 496:08bd8a46630b 816 */
rgrover1 496:08bd8a46630b 817
rgrover1 496:08bd8a46630b 818 typedef struct { /*!< ECB Structure */
rgrover1 496:08bd8a46630b 819 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
rgrover1 496:08bd8a46630b 820 will not initiate a new encryption and the ERRORECB event will
rgrover1 496:08bd8a46630b 821 be triggered. */
rgrover1 496:08bd8a46630b 822 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
rgrover1 496:08bd8a46630b 823 this will will trigger the ERRORECB event. */
rgrover1 496:08bd8a46630b 824 __I uint32_t RESERVED0[62];
rgrover1 496:08bd8a46630b 825 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
rgrover1 496:08bd8a46630b 826 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
rgrover1 496:08bd8a46630b 827 error. */
rgrover1 496:08bd8a46630b 828 __I uint32_t RESERVED1[127];
rgrover1 496:08bd8a46630b 829 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 830 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 831 __I uint32_t RESERVED2[126];
rgrover1 496:08bd8a46630b 832 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
rgrover1 496:08bd8a46630b 833 __I uint32_t RESERVED3[701];
rgrover1 496:08bd8a46630b 834 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 835 } NRF_ECB_Type;
rgrover1 496:08bd8a46630b 836
rgrover1 496:08bd8a46630b 837
rgrover1 496:08bd8a46630b 838 /* ================================================================================ */
rgrover1 496:08bd8a46630b 839 /* ================ AAR ================ */
rgrover1 496:08bd8a46630b 840 /* ================================================================================ */
rgrover1 496:08bd8a46630b 841
rgrover1 496:08bd8a46630b 842
rgrover1 496:08bd8a46630b 843 /**
rgrover1 496:08bd8a46630b 844 * @brief Accelerated Address Resolver. (AAR)
rgrover1 496:08bd8a46630b 845 */
rgrover1 496:08bd8a46630b 846
rgrover1 496:08bd8a46630b 847 typedef struct { /*!< AAR Structure */
rgrover1 496:08bd8a46630b 848 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
rgrover1 496:08bd8a46630b 849 data structure. */
rgrover1 496:08bd8a46630b 850 __I uint32_t RESERVED0;
rgrover1 496:08bd8a46630b 851 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
rgrover1 496:08bd8a46630b 852 __I uint32_t RESERVED1[61];
rgrover1 496:08bd8a46630b 853 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
rgrover1 496:08bd8a46630b 854 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
rgrover1 496:08bd8a46630b 855 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
rgrover1 496:08bd8a46630b 856 __I uint32_t RESERVED2[126];
rgrover1 496:08bd8a46630b 857 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 858 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 859 __I uint32_t RESERVED3[61];
rgrover1 496:08bd8a46630b 860 __I uint32_t STATUS; /*!< Resolution status. */
rgrover1 496:08bd8a46630b 861 __I uint32_t RESERVED4[63];
rgrover1 496:08bd8a46630b 862 __IO uint32_t ENABLE; /*!< Enable AAR. */
rgrover1 496:08bd8a46630b 863 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
rgrover1 496:08bd8a46630b 864 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
rgrover1 496:08bd8a46630b 865 __I uint32_t RESERVED5;
rgrover1 496:08bd8a46630b 866 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
rgrover1 496:08bd8a46630b 867 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 496:08bd8a46630b 868 during resolution. A minimum of 3 bytes must be reserved. */
rgrover1 496:08bd8a46630b 869 __I uint32_t RESERVED6[697];
rgrover1 496:08bd8a46630b 870 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 871 } NRF_AAR_Type;
rgrover1 496:08bd8a46630b 872
rgrover1 496:08bd8a46630b 873
rgrover1 496:08bd8a46630b 874 /* ================================================================================ */
rgrover1 496:08bd8a46630b 875 /* ================ CCM ================ */
rgrover1 496:08bd8a46630b 876 /* ================================================================================ */
rgrover1 496:08bd8a46630b 877
rgrover1 496:08bd8a46630b 878
rgrover1 496:08bd8a46630b 879 /**
rgrover1 496:08bd8a46630b 880 * @brief AES CCM Mode Encryption. (CCM)
rgrover1 496:08bd8a46630b 881 */
rgrover1 496:08bd8a46630b 882
rgrover1 496:08bd8a46630b 883 typedef struct { /*!< CCM Structure */
rgrover1 496:08bd8a46630b 884 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
rgrover1 496:08bd8a46630b 885 itself when completed. */
rgrover1 496:08bd8a46630b 886 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
rgrover1 496:08bd8a46630b 887 completed. */
rgrover1 496:08bd8a46630b 888 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
rgrover1 496:08bd8a46630b 889 __I uint32_t RESERVED0[61];
rgrover1 496:08bd8a46630b 890 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
rgrover1 496:08bd8a46630b 891 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
rgrover1 496:08bd8a46630b 892 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
rgrover1 496:08bd8a46630b 893 __I uint32_t RESERVED1[61];
rgrover1 496:08bd8a46630b 894 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
rgrover1 496:08bd8a46630b 895 __I uint32_t RESERVED2[64];
rgrover1 496:08bd8a46630b 896 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 897 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 898 __I uint32_t RESERVED3[61];
rgrover1 496:08bd8a46630b 899 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
rgrover1 496:08bd8a46630b 900 __I uint32_t RESERVED4[63];
rgrover1 496:08bd8a46630b 901 __IO uint32_t ENABLE; /*!< CCM enable. */
rgrover1 496:08bd8a46630b 902 __IO uint32_t MODE; /*!< Operation mode. */
rgrover1 496:08bd8a46630b 903 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
rgrover1 496:08bd8a46630b 904 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
rgrover1 496:08bd8a46630b 905 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
rgrover1 496:08bd8a46630b 906 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
rgrover1 496:08bd8a46630b 907 during resolution. A minimum of 43 bytes must be reserved. */
rgrover1 496:08bd8a46630b 908 __I uint32_t RESERVED5[697];
rgrover1 496:08bd8a46630b 909 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 910 } NRF_CCM_Type;
rgrover1 496:08bd8a46630b 911
rgrover1 496:08bd8a46630b 912
rgrover1 496:08bd8a46630b 913 /* ================================================================================ */
rgrover1 496:08bd8a46630b 914 /* ================ WDT ================ */
rgrover1 496:08bd8a46630b 915 /* ================================================================================ */
rgrover1 496:08bd8a46630b 916
rgrover1 496:08bd8a46630b 917
rgrover1 496:08bd8a46630b 918 /**
rgrover1 496:08bd8a46630b 919 * @brief Watchdog Timer. (WDT)
rgrover1 496:08bd8a46630b 920 */
rgrover1 496:08bd8a46630b 921
rgrover1 496:08bd8a46630b 922 typedef struct { /*!< WDT Structure */
rgrover1 496:08bd8a46630b 923 __O uint32_t TASKS_START; /*!< Start the watchdog. */
rgrover1 496:08bd8a46630b 924 __I uint32_t RESERVED0[63];
rgrover1 496:08bd8a46630b 925 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
rgrover1 496:08bd8a46630b 926 __I uint32_t RESERVED1[128];
rgrover1 496:08bd8a46630b 927 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 928 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 929 __I uint32_t RESERVED2[61];
rgrover1 496:08bd8a46630b 930 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
rgrover1 496:08bd8a46630b 931 __I uint32_t REQSTATUS; /*!< Request status. */
rgrover1 496:08bd8a46630b 932 __I uint32_t RESERVED3[63];
rgrover1 496:08bd8a46630b 933 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
rgrover1 496:08bd8a46630b 934 __IO uint32_t RREN; /*!< Reload request enable. */
rgrover1 496:08bd8a46630b 935 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 496:08bd8a46630b 936 __I uint32_t RESERVED4[60];
rgrover1 496:08bd8a46630b 937 __O uint32_t RR[8]; /*!< Reload requests registers. */
rgrover1 496:08bd8a46630b 938 __I uint32_t RESERVED5[631];
rgrover1 496:08bd8a46630b 939 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 940 } NRF_WDT_Type;
rgrover1 496:08bd8a46630b 941
rgrover1 496:08bd8a46630b 942
rgrover1 496:08bd8a46630b 943 /* ================================================================================ */
rgrover1 496:08bd8a46630b 944 /* ================ QDEC ================ */
rgrover1 496:08bd8a46630b 945 /* ================================================================================ */
rgrover1 496:08bd8a46630b 946
rgrover1 496:08bd8a46630b 947
rgrover1 496:08bd8a46630b 948 /**
rgrover1 496:08bd8a46630b 949 * @brief Rotary decoder. (QDEC)
rgrover1 496:08bd8a46630b 950 */
rgrover1 496:08bd8a46630b 951
rgrover1 496:08bd8a46630b 952 typedef struct { /*!< QDEC Structure */
rgrover1 496:08bd8a46630b 953 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
rgrover1 496:08bd8a46630b 954 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
rgrover1 496:08bd8a46630b 955 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
rgrover1 496:08bd8a46630b 956 and clears the ACC registers. */
rgrover1 496:08bd8a46630b 957 __I uint32_t RESERVED0[61];
rgrover1 496:08bd8a46630b 958 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
rgrover1 496:08bd8a46630b 959 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
rgrover1 496:08bd8a46630b 960 ACC register different than zero. */
rgrover1 496:08bd8a46630b 961 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
rgrover1 496:08bd8a46630b 962 __I uint32_t RESERVED1[61];
rgrover1 496:08bd8a46630b 963 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
rgrover1 496:08bd8a46630b 964 __I uint32_t RESERVED2[64];
rgrover1 496:08bd8a46630b 965 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 966 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 967 __I uint32_t RESERVED3[125];
rgrover1 496:08bd8a46630b 968 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
rgrover1 496:08bd8a46630b 969 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
rgrover1 496:08bd8a46630b 970 __IO uint32_t SAMPLEPER; /*!< Sample period. */
rgrover1 496:08bd8a46630b 971 __I int32_t SAMPLE; /*!< Motion sample value. */
rgrover1 496:08bd8a46630b 972 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
rgrover1 496:08bd8a46630b 973 __I int32_t ACC; /*!< Accumulated valid transitions register. */
rgrover1 496:08bd8a46630b 974 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
rgrover1 496:08bd8a46630b 975 task. */
rgrover1 496:08bd8a46630b 976 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
rgrover1 496:08bd8a46630b 977 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
rgrover1 496:08bd8a46630b 978 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
rgrover1 496:08bd8a46630b 979 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
rgrover1 496:08bd8a46630b 980 __I uint32_t RESERVED4[5];
rgrover1 496:08bd8a46630b 981 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
rgrover1 496:08bd8a46630b 982 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
rgrover1 496:08bd8a46630b 983 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
rgrover1 496:08bd8a46630b 984 task. */
rgrover1 496:08bd8a46630b 985 __I uint32_t RESERVED5[684];
rgrover1 496:08bd8a46630b 986 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 987 } NRF_QDEC_Type;
rgrover1 496:08bd8a46630b 988
rgrover1 496:08bd8a46630b 989
rgrover1 496:08bd8a46630b 990 /* ================================================================================ */
rgrover1 496:08bd8a46630b 991 /* ================ LPCOMP ================ */
rgrover1 496:08bd8a46630b 992 /* ================================================================================ */
rgrover1 496:08bd8a46630b 993
rgrover1 496:08bd8a46630b 994
rgrover1 496:08bd8a46630b 995 /**
rgrover1 496:08bd8a46630b 996 * @brief Low power comparator. (LPCOMP)
rgrover1 496:08bd8a46630b 997 */
rgrover1 496:08bd8a46630b 998
rgrover1 496:08bd8a46630b 999 typedef struct { /*!< LPCOMP Structure */
rgrover1 496:08bd8a46630b 1000 __O uint32_t TASKS_START; /*!< Start the comparator. */
rgrover1 496:08bd8a46630b 1001 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
rgrover1 496:08bd8a46630b 1002 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
rgrover1 496:08bd8a46630b 1003 __I uint32_t RESERVED0[61];
rgrover1 496:08bd8a46630b 1004 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
rgrover1 496:08bd8a46630b 1005 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
rgrover1 496:08bd8a46630b 1006 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
rgrover1 496:08bd8a46630b 1007 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
rgrover1 496:08bd8a46630b 1008 __I uint32_t RESERVED1[60];
rgrover1 496:08bd8a46630b 1009 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
rgrover1 496:08bd8a46630b 1010 __I uint32_t RESERVED2[64];
rgrover1 496:08bd8a46630b 1011 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
rgrover1 496:08bd8a46630b 1012 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
rgrover1 496:08bd8a46630b 1013 __I uint32_t RESERVED3[61];
rgrover1 496:08bd8a46630b 1014 __I uint32_t RESULT; /*!< Result of last compare. */
rgrover1 496:08bd8a46630b 1015 __I uint32_t RESERVED4[63];
rgrover1 496:08bd8a46630b 1016 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
rgrover1 496:08bd8a46630b 1017 __IO uint32_t PSEL; /*!< Input pin select. */
rgrover1 496:08bd8a46630b 1018 __IO uint32_t REFSEL; /*!< Reference select. */
rgrover1 496:08bd8a46630b 1019 __IO uint32_t EXTREFSEL; /*!< External reference select. */
rgrover1 496:08bd8a46630b 1020 __I uint32_t RESERVED5[4];
rgrover1 496:08bd8a46630b 1021 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
rgrover1 496:08bd8a46630b 1022 __I uint32_t RESERVED6[694];
rgrover1 496:08bd8a46630b 1023 __IO uint32_t POWER; /*!< Peripheral power control. */
rgrover1 496:08bd8a46630b 1024 } NRF_LPCOMP_Type;
rgrover1 496:08bd8a46630b 1025
rgrover1 496:08bd8a46630b 1026
rgrover1 496:08bd8a46630b 1027 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1028 /* ================ SWI ================ */
rgrover1 496:08bd8a46630b 1029 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1030
rgrover1 496:08bd8a46630b 1031
rgrover1 496:08bd8a46630b 1032 /**
rgrover1 496:08bd8a46630b 1033 * @brief SW Interrupts. (SWI)
rgrover1 496:08bd8a46630b 1034 */
rgrover1 496:08bd8a46630b 1035
rgrover1 496:08bd8a46630b 1036 typedef struct { /*!< SWI Structure */
rgrover1 496:08bd8a46630b 1037 __I uint32_t UNUSED; /*!< Unused. */
rgrover1 496:08bd8a46630b 1038 } NRF_SWI_Type;
rgrover1 496:08bd8a46630b 1039
rgrover1 496:08bd8a46630b 1040
rgrover1 496:08bd8a46630b 1041 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1042 /* ================ NVMC ================ */
rgrover1 496:08bd8a46630b 1043 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1044
rgrover1 496:08bd8a46630b 1045
rgrover1 496:08bd8a46630b 1046 /**
rgrover1 496:08bd8a46630b 1047 * @brief Non Volatile Memory Controller. (NVMC)
rgrover1 496:08bd8a46630b 1048 */
rgrover1 496:08bd8a46630b 1049
rgrover1 496:08bd8a46630b 1050 typedef struct { /*!< NVMC Structure */
rgrover1 496:08bd8a46630b 1051 __I uint32_t RESERVED0[256];
rgrover1 496:08bd8a46630b 1052 __I uint32_t READY; /*!< Ready flag. */
rgrover1 496:08bd8a46630b 1053 __I uint32_t RESERVED1[64];
rgrover1 496:08bd8a46630b 1054 __IO uint32_t CONFIG; /*!< Configuration register. */
rgrover1 498:d72c7e78ee13 1055
rgrover1 498:d72c7e78ee13 1056 union {
rgrover1 498:d72c7e78ee13 1057 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
rgrover1 498:d72c7e78ee13 1058 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
rgrover1 498:d72c7e78ee13 1059 };
rgrover1 496:08bd8a46630b 1060 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
rgrover1 498:d72c7e78ee13 1061 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
rgrover1 496:08bd8a46630b 1062 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
rgrover1 496:08bd8a46630b 1063 } NRF_NVMC_Type;
rgrover1 496:08bd8a46630b 1064
rgrover1 496:08bd8a46630b 1065
rgrover1 496:08bd8a46630b 1066 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1067 /* ================ PPI ================ */
rgrover1 496:08bd8a46630b 1068 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1069
rgrover1 496:08bd8a46630b 1070
rgrover1 496:08bd8a46630b 1071 /**
rgrover1 496:08bd8a46630b 1072 * @brief PPI controller. (PPI)
rgrover1 496:08bd8a46630b 1073 */
rgrover1 496:08bd8a46630b 1074
rgrover1 496:08bd8a46630b 1075 typedef struct { /*!< PPI Structure */
rgrover1 496:08bd8a46630b 1076 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
rgrover1 496:08bd8a46630b 1077 __I uint32_t RESERVED0[312];
rgrover1 496:08bd8a46630b 1078 __IO uint32_t CHEN; /*!< Channel enable. */
rgrover1 496:08bd8a46630b 1079 __IO uint32_t CHENSET; /*!< Channel enable set. */
rgrover1 496:08bd8a46630b 1080 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
rgrover1 496:08bd8a46630b 1081 __I uint32_t RESERVED1;
rgrover1 496:08bd8a46630b 1082 PPI_CH_Type CH[16]; /*!< PPI Channel. */
rgrover1 496:08bd8a46630b 1083 __I uint32_t RESERVED2[156];
rgrover1 496:08bd8a46630b 1084 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
rgrover1 496:08bd8a46630b 1085 } NRF_PPI_Type;
rgrover1 496:08bd8a46630b 1086
rgrover1 496:08bd8a46630b 1087
rgrover1 496:08bd8a46630b 1088 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1089 /* ================ FICR ================ */
rgrover1 496:08bd8a46630b 1090 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1091
rgrover1 496:08bd8a46630b 1092
rgrover1 496:08bd8a46630b 1093 /**
rgrover1 496:08bd8a46630b 1094 * @brief Factory Information Configuration. (FICR)
rgrover1 496:08bd8a46630b 1095 */
rgrover1 496:08bd8a46630b 1096
rgrover1 496:08bd8a46630b 1097 typedef struct { /*!< FICR Structure */
rgrover1 496:08bd8a46630b 1098 __I uint32_t RESERVED0[4];
rgrover1 496:08bd8a46630b 1099 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
rgrover1 496:08bd8a46630b 1100 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
rgrover1 496:08bd8a46630b 1101 __I uint32_t RESERVED1[4];
rgrover1 496:08bd8a46630b 1102 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
rgrover1 496:08bd8a46630b 1103 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
rgrover1 496:08bd8a46630b 1104 __I uint32_t RESERVED2;
rgrover1 496:08bd8a46630b 1105 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
rgrover1 496:08bd8a46630b 1106
rgrover1 496:08bd8a46630b 1107 union {
rgrover1 496:08bd8a46630b 1108 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
rgrover1 496:08bd8a46630b 1109 kept for backward compatinility purposes. Use SIZERAMBLOCKS
rgrover1 496:08bd8a46630b 1110 instead. */
rgrover1 496:08bd8a46630b 1111 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
rgrover1 496:08bd8a46630b 1112 };
rgrover1 496:08bd8a46630b 1113 __I uint32_t RESERVED3[5];
rgrover1 496:08bd8a46630b 1114 __I uint32_t CONFIGID; /*!< Configuration identifier. */
rgrover1 496:08bd8a46630b 1115 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
rgrover1 496:08bd8a46630b 1116 __I uint32_t RESERVED4[6];
rgrover1 496:08bd8a46630b 1117 __I uint32_t ER[4]; /*!< Encryption root. */
rgrover1 496:08bd8a46630b 1118 __I uint32_t IR[4]; /*!< Identity root. */
rgrover1 496:08bd8a46630b 1119 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
rgrover1 496:08bd8a46630b 1120 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
rgrover1 496:08bd8a46630b 1121 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
rgrover1 496:08bd8a46630b 1122 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
rgrover1 496:08bd8a46630b 1123 mode. */
rgrover1 496:08bd8a46630b 1124 __I uint32_t RESERVED5[10];
rgrover1 496:08bd8a46630b 1125 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
rgrover1 496:08bd8a46630b 1126 mode. */
rgrover1 496:08bd8a46630b 1127 } NRF_FICR_Type;
rgrover1 496:08bd8a46630b 1128
rgrover1 496:08bd8a46630b 1129
rgrover1 496:08bd8a46630b 1130 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1131 /* ================ UICR ================ */
rgrover1 496:08bd8a46630b 1132 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1133
rgrover1 496:08bd8a46630b 1134
rgrover1 496:08bd8a46630b 1135 /**
rgrover1 496:08bd8a46630b 1136 * @brief User Information Configuration. (UICR)
rgrover1 496:08bd8a46630b 1137 */
rgrover1 496:08bd8a46630b 1138
rgrover1 496:08bd8a46630b 1139 typedef struct { /*!< UICR Structure */
rgrover1 496:08bd8a46630b 1140 __IO uint32_t CLENR0; /*!< Length of code region 0. */
rgrover1 496:08bd8a46630b 1141 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
rgrover1 496:08bd8a46630b 1142 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
rgrover1 496:08bd8a46630b 1143 __I uint32_t RESERVED0;
rgrover1 496:08bd8a46630b 1144 __I uint32_t FWID; /*!< Firmware ID. */
rgrover1 498:d72c7e78ee13 1145
rgrover1 498:d72c7e78ee13 1146 union {
rgrover1 498:d72c7e78ee13 1147 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
rgrover1 498:d72c7e78ee13 1148 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
rgrover1 498:d72c7e78ee13 1149 };
rgrover1 498:d72c7e78ee13 1150 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
rgrover1 498:d72c7e78ee13 1151 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
rgrover1 496:08bd8a46630b 1152 } NRF_UICR_Type;
rgrover1 496:08bd8a46630b 1153
rgrover1 496:08bd8a46630b 1154
rgrover1 496:08bd8a46630b 1155 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1156 /* ================ GPIO ================ */
rgrover1 496:08bd8a46630b 1157 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1158
rgrover1 496:08bd8a46630b 1159
rgrover1 496:08bd8a46630b 1160 /**
rgrover1 496:08bd8a46630b 1161 * @brief General purpose input and output. (GPIO)
rgrover1 496:08bd8a46630b 1162 */
rgrover1 496:08bd8a46630b 1163
rgrover1 496:08bd8a46630b 1164 typedef struct { /*!< GPIO Structure */
rgrover1 496:08bd8a46630b 1165 __I uint32_t RESERVED0[321];
rgrover1 496:08bd8a46630b 1166 __IO uint32_t OUT; /*!< Write GPIO port. */
rgrover1 496:08bd8a46630b 1167 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
rgrover1 496:08bd8a46630b 1168 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
rgrover1 496:08bd8a46630b 1169 __I uint32_t IN; /*!< Read GPIO port. */
rgrover1 496:08bd8a46630b 1170 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
rgrover1 496:08bd8a46630b 1171 __IO uint32_t DIRSET; /*!< DIR set register. */
rgrover1 496:08bd8a46630b 1172 __IO uint32_t DIRCLR; /*!< DIR clear register. */
rgrover1 496:08bd8a46630b 1173 __I uint32_t RESERVED1[120];
rgrover1 496:08bd8a46630b 1174 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
rgrover1 496:08bd8a46630b 1175 } NRF_GPIO_Type;
rgrover1 496:08bd8a46630b 1176
rgrover1 496:08bd8a46630b 1177
rgrover1 496:08bd8a46630b 1178 /* -------------------- End of section using anonymous unions ------------------- */
rgrover1 496:08bd8a46630b 1179 #if defined(__CC_ARM)
rgrover1 496:08bd8a46630b 1180 #pragma pop
rgrover1 496:08bd8a46630b 1181 #elif defined(__ICCARM__)
rgrover1 496:08bd8a46630b 1182 /* leave anonymous unions enabled */
rgrover1 496:08bd8a46630b 1183 #elif defined(__GNUC__)
rgrover1 496:08bd8a46630b 1184 /* anonymous unions are enabled by default */
rgrover1 496:08bd8a46630b 1185 #elif defined(__TMS470__)
rgrover1 496:08bd8a46630b 1186 /* anonymous unions are enabled by default */
rgrover1 496:08bd8a46630b 1187 #elif defined(__TASKING__)
rgrover1 496:08bd8a46630b 1188 #pragma warning restore
rgrover1 496:08bd8a46630b 1189 #else
rgrover1 496:08bd8a46630b 1190 #warning Not supported compiler type
rgrover1 496:08bd8a46630b 1191 #endif
rgrover1 496:08bd8a46630b 1192
rgrover1 496:08bd8a46630b 1193
rgrover1 496:08bd8a46630b 1194
rgrover1 496:08bd8a46630b 1195
rgrover1 496:08bd8a46630b 1196 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1197 /* ================ Peripheral memory map ================ */
rgrover1 496:08bd8a46630b 1198 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1199
rgrover1 496:08bd8a46630b 1200 #define NRF_POWER_BASE 0x40000000UL
rgrover1 496:08bd8a46630b 1201 #define NRF_CLOCK_BASE 0x40000000UL
rgrover1 496:08bd8a46630b 1202 #define NRF_MPU_BASE 0x40000000UL
rgrover1 496:08bd8a46630b 1203 #define NRF_PU_BASE 0x40000000UL
rgrover1 496:08bd8a46630b 1204 #define NRF_AMLI_BASE 0x40000000UL
rgrover1 496:08bd8a46630b 1205 #define NRF_RADIO_BASE 0x40001000UL
rgrover1 496:08bd8a46630b 1206 #define NRF_UART0_BASE 0x40002000UL
rgrover1 496:08bd8a46630b 1207 #define NRF_SPI0_BASE 0x40003000UL
rgrover1 496:08bd8a46630b 1208 #define NRF_TWI0_BASE 0x40003000UL
rgrover1 496:08bd8a46630b 1209 #define NRF_SPI1_BASE 0x40004000UL
rgrover1 496:08bd8a46630b 1210 #define NRF_TWI1_BASE 0x40004000UL
rgrover1 496:08bd8a46630b 1211 #define NRF_SPIS1_BASE 0x40004000UL
rgrover1 496:08bd8a46630b 1212 #define NRF_SPIM1_BASE 0x40004000UL
rgrover1 496:08bd8a46630b 1213 #define NRF_GPIOTE_BASE 0x40006000UL
rgrover1 496:08bd8a46630b 1214 #define NRF_ADC_BASE 0x40007000UL
rgrover1 496:08bd8a46630b 1215 #define NRF_TIMER0_BASE 0x40008000UL
rgrover1 496:08bd8a46630b 1216 #define NRF_TIMER1_BASE 0x40009000UL
rgrover1 496:08bd8a46630b 1217 #define NRF_TIMER2_BASE 0x4000A000UL
rgrover1 496:08bd8a46630b 1218 #define NRF_RTC0_BASE 0x4000B000UL
rgrover1 496:08bd8a46630b 1219 #define NRF_TEMP_BASE 0x4000C000UL
rgrover1 496:08bd8a46630b 1220 #define NRF_RNG_BASE 0x4000D000UL
rgrover1 496:08bd8a46630b 1221 #define NRF_ECB_BASE 0x4000E000UL
rgrover1 496:08bd8a46630b 1222 #define NRF_AAR_BASE 0x4000F000UL
rgrover1 496:08bd8a46630b 1223 #define NRF_CCM_BASE 0x4000F000UL
rgrover1 496:08bd8a46630b 1224 #define NRF_WDT_BASE 0x40010000UL
rgrover1 496:08bd8a46630b 1225 #define NRF_RTC1_BASE 0x40011000UL
rgrover1 496:08bd8a46630b 1226 #define NRF_QDEC_BASE 0x40012000UL
rgrover1 496:08bd8a46630b 1227 #define NRF_LPCOMP_BASE 0x40013000UL
rgrover1 496:08bd8a46630b 1228 #define NRF_SWI_BASE 0x40014000UL
rgrover1 496:08bd8a46630b 1229 #define NRF_NVMC_BASE 0x4001E000UL
rgrover1 496:08bd8a46630b 1230 #define NRF_PPI_BASE 0x4001F000UL
rgrover1 496:08bd8a46630b 1231 #define NRF_FICR_BASE 0x10000000UL
rgrover1 496:08bd8a46630b 1232 #define NRF_UICR_BASE 0x10001000UL
rgrover1 496:08bd8a46630b 1233 #define NRF_GPIO_BASE 0x50000000UL
rgrover1 496:08bd8a46630b 1234
rgrover1 496:08bd8a46630b 1235
rgrover1 496:08bd8a46630b 1236 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1237 /* ================ Peripheral declaration ================ */
rgrover1 496:08bd8a46630b 1238 /* ================================================================================ */
rgrover1 496:08bd8a46630b 1239
rgrover1 496:08bd8a46630b 1240 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
rgrover1 496:08bd8a46630b 1241 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
rgrover1 496:08bd8a46630b 1242 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
rgrover1 496:08bd8a46630b 1243 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
rgrover1 496:08bd8a46630b 1244 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
rgrover1 496:08bd8a46630b 1245 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
rgrover1 496:08bd8a46630b 1246 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
rgrover1 496:08bd8a46630b 1247 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
rgrover1 496:08bd8a46630b 1248 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
rgrover1 496:08bd8a46630b 1249 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
rgrover1 496:08bd8a46630b 1250 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
rgrover1 496:08bd8a46630b 1251 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
rgrover1 496:08bd8a46630b 1252 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
rgrover1 496:08bd8a46630b 1253 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
rgrover1 496:08bd8a46630b 1254 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
rgrover1 496:08bd8a46630b 1255 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
rgrover1 496:08bd8a46630b 1256 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
rgrover1 496:08bd8a46630b 1257 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
rgrover1 496:08bd8a46630b 1258 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
rgrover1 496:08bd8a46630b 1259 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
rgrover1 496:08bd8a46630b 1260 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
rgrover1 496:08bd8a46630b 1261 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
rgrover1 496:08bd8a46630b 1262 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
rgrover1 496:08bd8a46630b 1263 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
rgrover1 496:08bd8a46630b 1264 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
rgrover1 496:08bd8a46630b 1265 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
rgrover1 496:08bd8a46630b 1266 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
rgrover1 496:08bd8a46630b 1267 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
rgrover1 496:08bd8a46630b 1268 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
rgrover1 496:08bd8a46630b 1269 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
rgrover1 496:08bd8a46630b 1270 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
rgrover1 496:08bd8a46630b 1271 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
rgrover1 496:08bd8a46630b 1272 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
rgrover1 496:08bd8a46630b 1273 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
rgrover1 496:08bd8a46630b 1274
rgrover1 496:08bd8a46630b 1275
rgrover1 496:08bd8a46630b 1276 /** @} */ /* End of group Device_Peripheral_Registers */
rgrover1 498:d72c7e78ee13 1277 /** @} */ /* End of group nrf51 */
rgrover1 496:08bd8a46630b 1278 /** @} */ /* End of group Nordic Semiconductor */
rgrover1 496:08bd8a46630b 1279
rgrover1 496:08bd8a46630b 1280 #ifdef __cplusplus
rgrover1 496:08bd8a46630b 1281 }
rgrover1 496:08bd8a46630b 1282 #endif
rgrover1 496:08bd8a46630b 1283
rgrover1 496:08bd8a46630b 1284
rgrover1 498:d72c7e78ee13 1285 #endif /* nrf51_H */