karthick B / GR-PEACH_video

vedio_gr_peach

Fork of GR-PEACH_video by Renesas

drivers/vdc5/src/r_vdc5_register.c@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
0:853f5b7408a7 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file r_vdc5_register.c
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief VDC5 driver register setup processing
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 /******************************************************************************
dkato 0:853f5b7408a7 32 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 33 ******************************************************************************/
dkato 0:853f5b7408a7 34 #include "r_vdc5.h"
dkato 0:853f5b7408a7 35 #include "r_vdc5_user.h"
dkato 0:853f5b7408a7 36 #include "r_vdc5_register.h"
dkato 0:853f5b7408a7 37 #include "r_vdc5_shared_param.h"
dkato 0:853f5b7408a7 38
dkato 0:853f5b7408a7 39
dkato 0:853f5b7408a7 40 /******************************************************************************
dkato 0:853f5b7408a7 41 Macro definitions
dkato 0:853f5b7408a7 42 ******************************************************************************/
dkato 0:853f5b7408a7 43 #define INITIAL_SCALING_PHASE ((uint32_t)2048u)
dkato 0:853f5b7408a7 44 #define SCALING_RATIO_SAME_SIZE (4096u)
dkato 0:853f5b7408a7 45 /* Vsync signal delay control for OIR */
dkato 0:853f5b7408a7 46 #define OIR_VSYNC_DELAY ((uint32_t)1u)
dkato 0:853f5b7408a7 47
dkato 0:853f5b7408a7 48 #define LVDS_LPHYACC_VALUE ((uint32_t)0x0001u)
dkato 0:853f5b7408a7 49
dkato 0:853f5b7408a7 50 /* Panel clock frequency division ratio */
dkato 0:853f5b7408a7 51 #define VDC5_REG_CLKDIV_1_1 (1u)
dkato 0:853f5b7408a7 52 #define VDC5_REG_CLKDIV_1_2 (2u)
dkato 0:853f5b7408a7 53 #define VDC5_REG_CLKDIV_1_3 (3u)
dkato 0:853f5b7408a7 54 #define VDC5_REG_CLKDIV_1_4 (4u)
dkato 0:853f5b7408a7 55 #define VDC5_REG_CLKDIV_1_5 (5u)
dkato 0:853f5b7408a7 56 #define VDC5_REG_CLKDIV_1_6 (6u)
dkato 0:853f5b7408a7 57 #define VDC5_REG_CLKDIV_1_7 (7u)
dkato 0:853f5b7408a7 58 #define VDC5_REG_CLKDIV_1_8 (8u)
dkato 0:853f5b7408a7 59 #define VDC5_REG_CLKDIV_1_9 (9u)
dkato 0:853f5b7408a7 60 #define VDC5_REG_CLKDIV_1_12 (12u)
dkato 0:853f5b7408a7 61 #define VDC5_REG_CLKDIV_1_16 (16u)
dkato 0:853f5b7408a7 62 #define VDC5_REG_CLKDIV_1_24 (24u)
dkato 0:853f5b7408a7 63 #define VDC5_REG_CLKDIV_1_32 (32u)
dkato 0:853f5b7408a7 64 /* Panel clock select */
dkato 0:853f5b7408a7 65 #define VDC5_REG_ICKSEL_IMG (0x0000u)
dkato 0:853f5b7408a7 66 #define VDC5_REG_ICKSEL_IMG_DV (0x0000u)
dkato 0:853f5b7408a7 67 #define VDC5_REG_ICKSEL_EXT_0 (0x1000u)
dkato 0:853f5b7408a7 68 #define VDC5_REG_ICKSEL_EXT_1 (0x2000u)
dkato 0:853f5b7408a7 69 #define VDC5_REG_ICKSEL_PERI (0x3000u)
dkato 0:853f5b7408a7 70 #define VDC5_REG_ICKSEL_LVDS (0x0400u)
dkato 0:853f5b7408a7 71 #define VDC5_REG_ICKSEL_LVDS_DIV7 (0x0800u)
dkato 0:853f5b7408a7 72 /* Output pin edge select */
dkato 0:853f5b7408a7 73 #define VDC5_REG_TCON0_EDGE (0x0040u)
dkato 0:853f5b7408a7 74 #define VDC5_REG_TCON1_EDGE (0x0020u)
dkato 0:853f5b7408a7 75 #define VDC5_REG_TCON2_EDGE (0x0010u)
dkato 0:853f5b7408a7 76 #define VDC5_REG_TCON3_EDGE (0x0008u)
dkato 0:853f5b7408a7 77 #define VDC5_REG_TCON4_EDGE (0x0004u)
dkato 0:853f5b7408a7 78 #define VDC5_REG_TCON5_EDGE (0x0002u)
dkato 0:853f5b7408a7 79 #define VDC5_REG_TCON6_EDGE (0x0001u)
dkato 0:853f5b7408a7 80 /* Panel dither output format select */
dkato 0:853f5b7408a7 81 #define VDC5_REG_PATH_FORMAT_RGB888 (0x00000000u)
dkato 0:853f5b7408a7 82 #define VDC5_REG_PATH_FORMAT_RGB666 (0x00010000u)
dkato 0:853f5b7408a7 83 #define VDC5_REG_PATH_FORMAT_RGB565 (0x00020000u)
dkato 0:853f5b7408a7 84 #define VDC5_REG_PATH_FORMAT_NON (0x00000000u)
dkato 0:853f5b7408a7 85 /* Calculate scaling ratio use value */
dkato 0:853f5b7408a7 86 #define VDC5_REG_FLOAT_1_0 (1.0f)
dkato 0:853f5b7408a7 87 #define VDC5_REG_FLOAT_0_5 (0.5f)
dkato 0:853f5b7408a7 88 /* bits per pixel */
dkato 0:853f5b7408a7 89 #define VDC5_REG_BIT_PER_PIXEL_RGB565 (16u)
dkato 0:853f5b7408a7 90 #define VDC5_REG_BIT_PER_PIXEL_RGB888 (32u)
dkato 0:853f5b7408a7 91 #define VDC5_REG_BIT_PER_PIXEL_ARGB1555 (16u)
dkato 0:853f5b7408a7 92 #define VDC5_REG_BIT_PER_PIXEL_ARGB4444 (16u)
dkato 0:853f5b7408a7 93 #define VDC5_REG_BIT_PER_PIXEL_ARGB8888 (32u)
dkato 0:853f5b7408a7 94 #define VDC5_REG_BIT_PER_PIXEL_CLUT8 (8u)
dkato 0:853f5b7408a7 95 #define VDC5_REG_BIT_PER_PIXEL_CLUT4 (4u)
dkato 0:853f5b7408a7 96 #define VDC5_REG_BIT_PER_PIXEL_CLUT1 (1u)
dkato 0:853f5b7408a7 97 #define VDC5_REG_BIT_PER_PIXEL_YCBCR422 (32u)
dkato 0:853f5b7408a7 98 #define VDC5_REG_BIT_PER_PIXEL_YCBCR444 (32u)
dkato 0:853f5b7408a7 99 #define VDC5_REG_BIT_PER_PIXEL_RGBA5551 (16u)
dkato 0:853f5b7408a7 100 #define VDC5_REG_BIT_PER_PIXEL_RGBA8888 (32u)
dkato 0:853f5b7408a7 101 #define VDC5_REG_BIT_PER_PIXEL_VALUE_8 (8u)
dkato 0:853f5b7408a7 102 /* Convert the color data from 4 bits value into 8 bits value */
dkato 0:853f5b7408a7 103 #define VDC5_REG_EXTENSION_VALUE_17 (17u)
dkato 0:853f5b7408a7 104 /* Convert the color data from 5 bits value into 8 bits value */
dkato 0:853f5b7408a7 105 #define VDC5_REG_EXTENSION_VALUE_263 (263u)
dkato 0:853f5b7408a7 106 #define VDC5_REG_EXTENSION_VALUE_32 (32u)
dkato 0:853f5b7408a7 107 /* Convert the color data from 6 bits value into 8 bits value */
dkato 0:853f5b7408a7 108 #define VDC5_REG_EXTENSION_VALUE_259 (259u)
dkato 0:853f5b7408a7 109 #define VDC5_REG_EXTENSION_VALUE_64 (64u)
dkato 0:853f5b7408a7 110 /* Round off */
dkato 0:853f5b7408a7 111 #define VDC5_REG_ROUND_OFF_VALUE_1 (1u)
dkato 0:853f5b7408a7 112 #define VDC5_REG_ROUND_OFF_VALUE_2 (2u)
dkato 0:853f5b7408a7 113 /* Color mask data */
dkato 0:853f5b7408a7 114 #define VDC5_REG_ALPHA_8BIT (0xFF000000u)
dkato 0:853f5b7408a7 115 #define VDC5_REG_RGB_24BIT_MASK (0x00FFFFFFu)
dkato 0:853f5b7408a7 116 #define VDC5_REG_COLOR_8BIT_MASK (0x000000FFu)
dkato 0:853f5b7408a7 117 #define VDC5_REG_COLOR_6BIT_MASK (0x0000003Fu)
dkato 0:853f5b7408a7 118 #define VDC5_REG_COLOR_5BIT_MASK (0x0000001Fu)
dkato 0:853f5b7408a7 119 #define VDC5_REG_COLOR_4BIT_MASK (0x0000000Fu)
dkato 0:853f5b7408a7 120 #define VDC5_REG_ARGB8888_GB_MASK (0x00FFFF00u)
dkato 0:853f5b7408a7 121
dkato 0:853f5b7408a7 122 /* RGB565 bits mask data */
dkato 0:853f5b7408a7 123 #define VDC5_REG_RGB565_R_MASK (0x0000F800u)
dkato 0:853f5b7408a7 124 #define VDC5_REG_RGB565_G_MASK (0x000007E0u)
dkato 0:853f5b7408a7 125 #define VDC5_REG_RGB565_B_MASK (0x0000001Fu)
dkato 0:853f5b7408a7 126 /* ARGB4444 bits mask data */
dkato 0:853f5b7408a7 127 #define VDC5_REG_ARGB4444_R_MASK (0x00000F00u)
dkato 0:853f5b7408a7 128 #define VDC5_REG_ARGB4444_G_MASK (0x000000F0u)
dkato 0:853f5b7408a7 129 #define VDC5_REG_ARGB4444_B_MASK (0x0000000Fu)
dkato 0:853f5b7408a7 130 /* ARGB1555 bits mask data */
dkato 0:853f5b7408a7 131 #define VDC5_REG_ARGB1555_R_MASK (0x00007C00u)
dkato 0:853f5b7408a7 132 #define VDC5_REG_ARGB1555_G_MASK (0x000003E0u)
dkato 0:853f5b7408a7 133 #define VDC5_REG_ARGB1555_B_MASK (0x0000001Fu)
dkato 0:853f5b7408a7 134 /* RGBA5551 bits mask data */
dkato 0:853f5b7408a7 135 #define VDC5_REG_RGBA5551_R_MASK (0x0000F800u)
dkato 0:853f5b7408a7 136 #define VDC5_REG_RGBA5551_G_MASK (0x000007C0u)
dkato 0:853f5b7408a7 137 #define VDC5_REG_RGBA5551_B_MASK (0x0000003Eu)
dkato 0:853f5b7408a7 138
dkato 0:853f5b7408a7 139 /* bit pattern */
dkato 0:853f5b7408a7 140 #define VDC5_REG_BIT31 (0x80000000u)
dkato 0:853f5b7408a7 141 #define VDC5_REG_BIT29 (0x20000000u)
dkato 0:853f5b7408a7 142 #define VDC5_REG_BIT28 (0x10000000u)
dkato 0:853f5b7408a7 143 #define VDC5_REG_BIT24 (0x01000000u)
dkato 0:853f5b7408a7 144 #define VDC5_REG_BIT20 (0x00100000u)
dkato 0:853f5b7408a7 145 #define VDC5_REG_BIT16 (0x00010000u)
dkato 0:853f5b7408a7 146 #define VDC5_REG_BIT15 (0x00008000u)
dkato 0:853f5b7408a7 147 #define VDC5_REG_BIT14 (0x00004000u)
dkato 0:853f5b7408a7 148 #define VDC5_REG_BIT13 (0x00002000u)
dkato 0:853f5b7408a7 149 #define VDC5_REG_BIT12 (0x00001000u)
dkato 0:853f5b7408a7 150 #define VDC5_REG_BIT8 (0x00000100u)
dkato 0:853f5b7408a7 151 #define VDC5_REG_BIT4 (0x00000010u)
dkato 0:853f5b7408a7 152 #define VDC5_REG_BIT2 (0x00000004u)
dkato 0:853f5b7408a7 153 #define VDC5_REG_BIT1 (0x00000002u)
dkato 0:853f5b7408a7 154 #define VDC5_REG_BIT0 (0x00000001u)
dkato 0:853f5b7408a7 155
dkato 0:853f5b7408a7 156 /* shift value */
dkato 0:853f5b7408a7 157 #define VDC5_REG_SHIFT_28 (28u)
dkato 0:853f5b7408a7 158 #define VDC5_REG_SHIFT_24 (24u)
dkato 0:853f5b7408a7 159 #define VDC5_REG_SHIFT_20 (20u)
dkato 0:853f5b7408a7 160 #define VDC5_REG_SHIFT_16 (16u)
dkato 0:853f5b7408a7 161 #define VDC5_REG_SHIFT_13 (13u)
dkato 0:853f5b7408a7 162 #define VDC5_REG_SHIFT_12 (12u)
dkato 0:853f5b7408a7 163 #define VDC5_REG_SHIFT_11 (11u)
dkato 0:853f5b7408a7 164 #define VDC5_REG_SHIFT_10 (10u)
dkato 0:853f5b7408a7 165 #define VDC5_REG_SHIFT_8 (8u)
dkato 0:853f5b7408a7 166 #define VDC5_REG_SHIFT_6 (6u)
dkato 0:853f5b7408a7 167 #define VDC5_REG_SHIFT_5 (5u)
dkato 0:853f5b7408a7 168 #define VDC5_REG_SHIFT_4 (4u)
dkato 0:853f5b7408a7 169 #define VDC5_REG_SHIFT_2 (2u)
dkato 0:853f5b7408a7 170 #define VDC5_REG_SHIFT_1 (1u)
dkato 0:853f5b7408a7 171
dkato 0:853f5b7408a7 172 /* register set value */
dkato 0:853f5b7408a7 173 #define VDC5_REG_BIT_0XFFFF0000 (0xFFFF0000u) /* scaler_0->scl0_frc2 */
dkato 0:853f5b7408a7 174 /* scaler_1->scl0_frc2 */
dkato 0:853f5b7408a7 175 /* register mask value */
dkato 0:853f5b7408a7 176 #define VDC5_REG_MASK_0XF7FF1C3F (0xF7FF1C3Fu) /* mask img_synthesizer->gr_flm6 */
dkato 0:853f5b7408a7 177 #define VDC5_REG_MASK_0X0000D000 (0x0000D000u) /* mask img_synthesizer->gr_ab1 */
dkato 0:853f5b7408a7 178 #define VDC5_REG_MASK_0X01FF00FF (0x01FF00FFu) /* mask img_synthesizer->gr_ab6 */
dkato 0:853f5b7408a7 179 #define VDC5_REG_MASK_0X0000007F (0x0000007Fu) /* mask output_ctrl->out_clk_phase */
dkato 0:853f5b7408a7 180 #define VDC5_REG_MASK_0X11003313 (0x11003313u) /* mask output_ctrl->out_set */
dkato 0:853f5b7408a7 181 #define VDC5_REG_MASK_0X00030000 (0x00030000u) /* mask output_ctrl->out_pdtha */
dkato 0:853f5b7408a7 182 #define VDC5_REG_MASK_0X0007000D (0x0007000Du) /* mask scaler->scl1_wr1 */
dkato 0:853f5b7408a7 183 #define VDC5_REG_MASK_0X00000300 (0x00000300u) /* mask scaler->scl1_wr5 */
dkato 0:853f5b7408a7 184 #define VDC5_REG_MASK_0X0703FF02 (0x0703FF02u) /* mask regaddr_lvds->lclkselr */
dkato 0:853f5b7408a7 185 #define VDC5_REG_MASK_0X07FF1F30 (0x07FF1F30u) /* mask regaddr_lvds->lpllsetr */
dkato 0:853f5b7408a7 186 #define VDC5_REG_MASK_0X00010301 (0x00010301u) /* mask img_synthesizer->gr_flm1 */
dkato 0:853f5b7408a7 187 #define VDC5_REG_MASK_0X7FFF03FF (0x7FFF03FFu) /* mask img_synthesizer->gr_flm3 */
dkato 0:853f5b7408a7 188 #define VDC5_REG_MASK_0X0000E000 (0x0000E000u) /* mask img_synthesizer->gr_flm6 */
dkato 0:853f5b7408a7 189 #define VDC5_REG_MASK_0X00007F33 (0x00007F33u) /* mask input_ctrl->imgcnt_nr_cnt0 */
dkato 0:853f5b7408a7 190 #define VDC5_REG_MASK_0X00FF0000 (0x00FF0000u) /* mask img_synthesizer->gr_ab7 */
dkato 0:853f5b7408a7 191 #define VDC5_REG_MASK_0X00300000 (0x00300000u) /* mask output_ctrl->out_pdtha */
dkato 0:853f5b7408a7 192 #define VDC5_REG_MASK_0X00003333 (0x00003333u) /* mask output_ctrl->out_pdtha */
dkato 0:853f5b7408a7 193 #define VDC5_REG_MASK_0X00007111 (0x00007111u) /* mask input_ctrl->inp_sel_cnt */
dkato 0:853f5b7408a7 194 #define VDC5_REG_MASK_0X11110113 (0x11110113u) /* mask input_ctrl->inp_ext_sync_cnt */
dkato 0:853f5b7408a7 195 #define VDC5_REG_MASK_0X000007FF (0x000007FFu) /* mask img_synthesizer->gr_flm5 */
dkato 0:853f5b7408a7 196 #define VDC5_REG_MASK_0X0000FFFF (0x0000FFFFu) /* mask scaler->scl0_ds4 */
dkato 0:853f5b7408a7 197 /* caler->scl0_us5 */
dkato 0:853f5b7408a7 198 #define VDC5_REG_MASK_0X00000011 (0x00000011u) /* mask scaler->scl0_ds1 */
dkato 0:853f5b7408a7 199 /* scaler->scl0_us1 */
dkato 0:853f5b7408a7 200 #define VDC5_REG_MASK_0X00000070 (0x00000070u) /* mask scaler->scl1_wr1 */
dkato 0:853f5b7408a7 201 #define VDC5_REG_MASK_0X00000080 (0x00000080u) /* mask scaler->scl1_wr1 */
dkato 0:853f5b7408a7 202 #define VDC5_REG_MASK_0X00003110 (0x00003110u) /* mask output_ctrl->tcon_tim_pola2 */
dkato 0:853f5b7408a7 203 /* output_ctrl->tcon_tim_polb2 */
dkato 0:853f5b7408a7 204 #define VDC5_REG_MASK_0X000000FF (0x000000FFu) /* mask scaler_0->scl0_frc5 */
dkato 0:853f5b7408a7 205 /* scaler_1->scl0_frc5 */
dkato 0:853f5b7408a7 206 #define VDC5_REG_MASK_0X0000003F (0x0000003Fu) /* mask img_synthesizer->gr_flm6 */
dkato 0:853f5b7408a7 207 /* img_qlty_imp->adj_enh_shp1 */
dkato 0:853f5b7408a7 208 #define VDC5_REG_MASK_0XFF000000 (0xFF000000u) /* mask img_synthesizer->gr_ab10 */
dkato 0:853f5b7408a7 209 /* img_synthesizer->gr_ab11 */
dkato 0:853f5b7408a7 210 #define VDC5_REG_MASK_0X00000110 (0x00000110u) /* mask output_ctrl->tcon_tim_sth2 */
dkato 0:853f5b7408a7 211 /* output_ctrl->tcon_tim_stb2 */
dkato 0:853f5b7408a7 212 /* output_ctrl->tcon_tim_cpv2 */
dkato 0:853f5b7408a7 213 #define VDC5_REG_MASK_0X00000007 (0x00000007u) /* mask *(output_pin_regaddr[tcon_pin]) */
dkato 0:853f5b7408a7 214 /* img_synthesizer->gr_flm2 */
dkato 0:853f5b7408a7 215 /* img_synthesizer->gr_flm2 */
dkato 0:853f5b7408a7 216 #define VDC5_REG_MASK_0X07FF0000 (0x07FF0000u) /* mask scaler_0->scl0_frc4 */
dkato 0:853f5b7408a7 217 /* scaler_1->scl0_frc4 */
dkato 0:853f5b7408a7 218 /* img_synthesizer->gr_flm5 */
dkato 0:853f5b7408a7 219 /* img_synthesizer->gr_flm6 */
dkato 0:853f5b7408a7 220 #define VDC5_REG_MASK_0X0FFF0FFF (0x0FFF0FFFu) /* mask */
dkato 0:853f5b7408a7 221 /* scaler->scl0_ds5, scaler->scl0_us6 */
dkato 0:853f5b7408a7 222 /* scaler->scl0_ds5, scaler->scl0_us6 */
dkato 0:853f5b7408a7 223 /* scaler->scl0_ds5, scaler->scl0_us6 */
dkato 0:853f5b7408a7 224 /* scaler->scl0_ds5, scaler->scl0_us6 */
dkato 0:853f5b7408a7 225 /* scaler->scl0_ds5, scaler->scl0_us6 */
dkato 0:853f5b7408a7 226 #define VDC5_REG_MASK_0X00000003 (0x00000003u) /* mask img_synthesizer->gr_ab1 */
dkato 0:853f5b7408a7 227 /* regaddr_lvds->lphyacc */
dkato 0:853f5b7408a7 228
dkato 0:853f5b7408a7 229
dkato 0:853f5b7408a7 230 /******************************************************************************
dkato 0:853f5b7408a7 231 Typedef definitions
dkato 0:853f5b7408a7 232 ******************************************************************************/
dkato 0:853f5b7408a7 233
dkato 0:853f5b7408a7 234 /******************************************************************************
dkato 0:853f5b7408a7 235 Private global variables and functions
dkato 0:853f5b7408a7 236 ******************************************************************************/
dkato 0:853f5b7408a7 237 static void SetVideoExternalInput(
dkato 0:853f5b7408a7 238 const vdc5_ext_in_sig_t * const ext_sig_tmp,
dkato 0:853f5b7408a7 239 const vdc5_regaddr_input_ctrl_t * const input_ctrl);
dkato 0:853f5b7408a7 240 static void SetInitialConnection(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 241 static void SetGrapicsBackgroundColor(const vdc5_channel_t ch);
dkato 0:853f5b7408a7 242 static void SetScalerBackgroundColor(
dkato 0:853f5b7408a7 243 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 244 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 245 const vdc5_color_space_t color_space);
dkato 0:853f5b7408a7 246 static void SetLcdTcon_STVA_VS(
dkato 0:853f5b7408a7 247 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 248 const vdc5_regaddr_output_ctrl_t * const output_ctrl);
dkato 0:853f5b7408a7 249 static void SetLcdTcon_STVB_VE(
dkato 0:853f5b7408a7 250 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 251 const vdc5_regaddr_output_ctrl_t * const output_ctrl);
dkato 0:853f5b7408a7 252 static void SetLcdTcon_STH_HS(
dkato 0:853f5b7408a7 253 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 254 const vdc5_regaddr_output_ctrl_t * const output_ctrl);
dkato 0:853f5b7408a7 255 static void SetLcdTcon_STB_HE(
dkato 0:853f5b7408a7 256 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 257 const vdc5_regaddr_output_ctrl_t * const output_ctrl);
dkato 0:853f5b7408a7 258 static void SetLcdTcon_CPV_GCK(
dkato 0:853f5b7408a7 259 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 260 const vdc5_regaddr_output_ctrl_t * const output_ctrl);
dkato 0:853f5b7408a7 261 static void SetLcdTcon_POLA(
dkato 0:853f5b7408a7 262 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 263 const vdc5_regaddr_output_ctrl_t * const output_ctrl);
dkato 0:853f5b7408a7 264 static void SetLcdTcon_POLB(
dkato 0:853f5b7408a7 265 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 266 const vdc5_regaddr_output_ctrl_t * const output_ctrl);
dkato 0:853f5b7408a7 267 static void SetLcdTcon_DE(
dkato 0:853f5b7408a7 268 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 269 const vdc5_regaddr_output_ctrl_t * const output_ctrl);
dkato 0:853f5b7408a7 270 static void SetScalingDown(
dkato 0:853f5b7408a7 271 const vdc5_scalingdown_rot_t * const scldw_rot,
dkato 0:853f5b7408a7 272 const vdc5_res_inter_t res_inter,
dkato 0:853f5b7408a7 273 const vdc5_regaddr_scaler_t * const scaler);
dkato 0:853f5b7408a7 274 static void SetScalingUp(
dkato 0:853f5b7408a7 275 const vdc5_width_read_fb_t * const w_read_fb,
dkato 0:853f5b7408a7 276 const vdc5_period_rect_t * const gr_grc,
dkato 0:853f5b7408a7 277 const vdc5_onoff_t adj_sel,
dkato 0:853f5b7408a7 278 const vdc5_onoff_t ip_conversion,
dkato 0:853f5b7408a7 279 const vdc5_wr_md_t res_ds_wr_md,
dkato 0:853f5b7408a7 280 const vdc5_gr_ln_off_dir_t ln_off_dir,
dkato 0:853f5b7408a7 281 const vdc5_regaddr_scaler_t * const scaler);
dkato 0:853f5b7408a7 282 static uint32_t CalcScalingRatio(
dkato 0:853f5b7408a7 283 const uint32_t before_scl,
dkato 0:853f5b7408a7 284 const uint32_t after_scl,
dkato 0:853f5b7408a7 285 const vdc5_onoff_t adj_sel,
dkato 0:853f5b7408a7 286 const vdc5_onoff_t round_up);
dkato 0:853f5b7408a7 287 static void SetInputCntrlColorMtx(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
dkato 0:853f5b7408a7 288 static vdc5_onoff_t ConfirmGraphicsEnlargement(
dkato 0:853f5b7408a7 289 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 290 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 291 const vdc5_width_read_fb_t * const w_read_fb,
dkato 0:853f5b7408a7 292 const vdc5_period_rect_t * const gr_grc);
dkato 0:853f5b7408a7 293 static void SetScalerGraphics(
dkato 0:853f5b7408a7 294 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 295 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 296 const vdc5_width_read_fb_t * const w_read_fb,
dkato 0:853f5b7408a7 297 const vdc5_period_rect_t * const gr_grc,
dkato 0:853f5b7408a7 298 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 299 const vdc5_onoff_t gr_enlarge);
dkato 0:853f5b7408a7 300 static uint32_t DisplayStartPixelSetting(const uint32_t gr_base, const vdc5_gr_format_t gr_format);
dkato 0:853f5b7408a7 301 static vdc5_onoff_t SetCascade(
dkato 0:853f5b7408a7 302 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 303 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 304 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 305 const vdc5_onoff_t gr_enlarge);
dkato 0:853f5b7408a7 306 static void SetupGraphicsVIN(
dkato 0:853f5b7408a7 307 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 308 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 309 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 310 const vdc5_onoff_t gr_enlarge);
dkato 0:853f5b7408a7 311 static void ChangeGraphicsVIN(
dkato 0:853f5b7408a7 312 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 313 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 314 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 315 const vdc5_onoff_t gr_enlarge);
dkato 0:853f5b7408a7 316 static void SetImgQaImproverColorMtx(
dkato 0:853f5b7408a7 317 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 318 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 319 const vdc5_color_space_t color_space);
dkato 0:853f5b7408a7 320
dkato 0:853f5b7408a7 321 static void SetRwProcAbility_Write_0(const vdc5_channel_t ch, const vdc5_onoff_t ability);
dkato 0:853f5b7408a7 322 static void SetRwProcAbility_Write_1(const vdc5_channel_t ch, const vdc5_onoff_t ability);
dkato 0:853f5b7408a7 323 static void SetRwProcAbility_Write_OIR(const vdc5_channel_t ch, const vdc5_onoff_t ability);
dkato 0:853f5b7408a7 324 static void SetRwProcAbility_Read_0(const vdc5_channel_t ch, const vdc5_onoff_t ability);
dkato 0:853f5b7408a7 325 static void SetRwProcAbility_Read_1(const vdc5_channel_t ch, const vdc5_onoff_t ability);
dkato 0:853f5b7408a7 326 static void SetRwProcAbility_Read_2(const vdc5_channel_t ch, const vdc5_onoff_t ability);
dkato 0:853f5b7408a7 327 static void SetRwProcAbility_Read_3(const vdc5_channel_t ch, const vdc5_onoff_t ability);
dkato 0:853f5b7408a7 328 static void SetRwProcAbility_Read_OIR(const vdc5_channel_t ch, const vdc5_onoff_t ability);
dkato 0:853f5b7408a7 329 static void SetRegUpdateRwEnable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 330
dkato 0:853f5b7408a7 331 static void SetGraphicsDisplayMode(
dkato 0:853f5b7408a7 332 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 333 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 334 const vdc5_gr_disp_sel_t * const gr_disp_sel);
dkato 0:853f5b7408a7 335 static void SetColorMatrix(
dkato 0:853f5b7408a7 336 const vdc5_colormtx_mode_t mtx_mode,
dkato 0:853f5b7408a7 337 const uint16_t * const offset,
dkato 0:853f5b7408a7 338 const uint16_t * const gain,
dkato 0:853f5b7408a7 339 const vdc5_regaddr_color_matrix_t * const color_matrix);
dkato 0:853f5b7408a7 340 static void SetImageEnhancementSharpness(
dkato 0:853f5b7408a7 341 const vdc5_onoff_t shp_h_on,
dkato 0:853f5b7408a7 342 const vdc5_enhance_sharp_t * const sharp_param,
dkato 0:853f5b7408a7 343 const vdc5_regaddr_img_qlty_imp_t * const img_qlty_imp);
dkato 0:853f5b7408a7 344 static void SetImageEnhancementLti(
dkato 0:853f5b7408a7 345 const vdc5_onoff_t lti_h_on,
dkato 0:853f5b7408a7 346 const vdc5_enhance_lti_t * const lti_param,
dkato 0:853f5b7408a7 347 const vdc5_regaddr_img_qlty_imp_t * const img_qlty_imp);
dkato 0:853f5b7408a7 348 static void SetAlphaRectArea(
dkato 0:853f5b7408a7 349 const vdc5_pd_disp_rect_t * const pd_disp_rect,
dkato 0:853f5b7408a7 350 const vdc5_regaddr_img_synthesizer_t * const img_synthesizer);
dkato 0:853f5b7408a7 351 static void SetUndSel(const vdc5_channel_t ch, const vdc5_onoff_t und_sel);
dkato 0:853f5b7408a7 352 static uint32_t ColorConversion(const vdc5_gr_format_t gr_format, const uint32_t input_color);
dkato 0:853f5b7408a7 353 static uint32_t ColorConversionFrom4to8(const uint32_t color_value);
dkato 0:853f5b7408a7 354 static uint32_t ColorConversionFrom5to8(const uint32_t color_value);
dkato 0:853f5b7408a7 355 static uint32_t ColorConversionFrom6to8(const uint32_t color_value);
dkato 0:853f5b7408a7 356 static uint32_t ColorConversionIntoAgbr(const uint32_t color_value);
dkato 0:853f5b7408a7 357 static void Set_Clut(const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut);
dkato 0:853f5b7408a7 358 static void Set_StartThreshold_Gamma(const uint8_t * gam_th, volatile uint32_t * const * const gam_area);
dkato 0:853f5b7408a7 359 static void Set_GainAdjustment_Gamma(const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut);
dkato 0:853f5b7408a7 360 static void Wait_200_usec(void);
dkato 0:853f5b7408a7 361
dkato 0:853f5b7408a7 362 /*! Color matrix offset (DC) adjustment (YG, B, and R) */
dkato 0:853f5b7408a7 363 static const uint16_t colormtx_offset_adj[VDC5_COLORMTX_OFFST_NUM] = {
dkato 0:853f5b7408a7 364 (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET
dkato 0:853f5b7408a7 365 };
dkato 0:853f5b7408a7 366 /*! Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
dkato 0:853f5b7408a7 367 static const uint16_t colormtx_gain_adj[VDC5_COLORMTX_MODE_NUM][VDC5_COLORMTX_GAIN_NUM] = {
dkato 0:853f5b7408a7 368 { /* GBR to GBR */
dkato 0:853f5b7408a7 369 (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
dkato 0:853f5b7408a7 370 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
dkato 0:853f5b7408a7 371 0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
dkato 0:853f5b7408a7 372 },
dkato 0:853f5b7408a7 373 { /* GBR to YCbCr */
dkato 0:853f5b7408a7 374 (uint16_t)VDC5_COLORCONV_Y_G, (uint16_t)VDC5_COLORCONV_Y_B, (uint16_t)VDC5_COLORCONV_Y_R,
dkato 0:853f5b7408a7 375 (uint16_t)VDC5_COLORCONV_CB_G, (uint16_t)VDC5_COLORCONV_CB_B, (uint16_t)VDC5_COLORCONV_CB_R,
dkato 0:853f5b7408a7 376 (uint16_t)VDC5_COLORCONV_CR_G, (uint16_t)VDC5_COLORCONV_CR_B, (uint16_t)VDC5_COLORCONV_CR_R
dkato 0:853f5b7408a7 377 },
dkato 0:853f5b7408a7 378 { /* YCbCr to GBR */
dkato 0:853f5b7408a7 379 (uint16_t)VDC5_COLORCONV_G_Y, (uint16_t)VDC5_COLORCONV_G_CB, (uint16_t)VDC5_COLORCONV_G_CR,
dkato 0:853f5b7408a7 380 (uint16_t)VDC5_COLORCONV_B_Y, (uint16_t)VDC5_COLORCONV_B_CB, (uint16_t)VDC5_COLORCONV_B_CR,
dkato 0:853f5b7408a7 381 (uint16_t)VDC5_COLORCONV_R_Y, (uint16_t)VDC5_COLORCONV_R_CB, (uint16_t)VDC5_COLORCONV_R_CR
dkato 0:853f5b7408a7 382 },
dkato 0:853f5b7408a7 383 { /* YCbCr to YCbCr */
dkato 0:853f5b7408a7 384 (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
dkato 0:853f5b7408a7 385 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
dkato 0:853f5b7408a7 386 0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
dkato 0:853f5b7408a7 387 }
dkato 0:853f5b7408a7 388 };
dkato 0:853f5b7408a7 389
dkato 0:853f5b7408a7 390 static void (* const rw_proc_function_tbl[VDC5_LAYER_ID_NUM])(const vdc5_channel_t ch, const vdc5_onoff_t ability) = {
dkato 0:853f5b7408a7 391 &SetRwProcAbility_Write_0, /* Write scaler 0 */
dkato 0:853f5b7408a7 392 &SetRwProcAbility_Write_1, /* Write scaler 1 */
dkato 0:853f5b7408a7 393 &SetRwProcAbility_Write_OIR, /* Write OIR */
dkato 0:853f5b7408a7 394 &SetRwProcAbility_Read_0, /* Read graphics 0 */
dkato 0:853f5b7408a7 395 &SetRwProcAbility_Read_1, /* Read graphics 1 */
dkato 0:853f5b7408a7 396 &SetRwProcAbility_Read_2, /* Read graphics 2 */
dkato 0:853f5b7408a7 397 &SetRwProcAbility_Read_3, /* Read graphics 3 */
dkato 0:853f5b7408a7 398 0, /* Read VIN */
dkato 0:853f5b7408a7 399 &SetRwProcAbility_Read_OIR /* Read OIR */
dkato 0:853f5b7408a7 400 };
dkato 0:853f5b7408a7 401
dkato 0:853f5b7408a7 402
dkato 0:853f5b7408a7 403 /**************************************************************************//**
dkato 0:853f5b7408a7 404 * @brief Sets registers for initialization
dkato 0:853f5b7408a7 405 * @param[in] ch : Channel
dkato 0:853f5b7408a7 406 * @param[in] param : Initialization parameter
dkato 0:853f5b7408a7 407 * @retval None
dkato 0:853f5b7408a7 408 *****************************************************************************/
dkato 0:853f5b7408a7 409 void VDC5_Initialize (const vdc5_channel_t ch, const vdc5_init_t * const param)
dkato 0:853f5b7408a7 410 {
dkato 0:853f5b7408a7 411 const vdc5_lvds_t * lvds_tmp;
dkato 0:853f5b7408a7 412 const vdc5_regaddr_lvds_t * regaddr_lvds;
dkato 0:853f5b7408a7 413 volatile uint32_t counter;
dkato 0:853f5b7408a7 414 uint16_t syscnt_panel_clk_tmp;
dkato 0:853f5b7408a7 415 volatile uint16_t * syscnt_panel_clk_reg;
dkato 0:853f5b7408a7 416 volatile uint32_t * inp_sel_cnt_reg;
dkato 0:853f5b7408a7 417 static const uint16_t panel_dcdr_tbl[VDC5_PANEL_CLKDIV_NUM] = {
dkato 0:853f5b7408a7 418 /* Panel clock frequency division ratio */
dkato 0:853f5b7408a7 419 (uint16_t)VDC5_REG_CLKDIV_1_1, (uint16_t)VDC5_REG_CLKDIV_1_2, (uint16_t)VDC5_REG_CLKDIV_1_3, (uint16_t)VDC5_REG_CLKDIV_1_4,
dkato 0:853f5b7408a7 420 (uint16_t)VDC5_REG_CLKDIV_1_5, (uint16_t)VDC5_REG_CLKDIV_1_6, (uint16_t)VDC5_REG_CLKDIV_1_7, (uint16_t)VDC5_REG_CLKDIV_1_8,
dkato 0:853f5b7408a7 421 (uint16_t)VDC5_REG_CLKDIV_1_9, (uint16_t)VDC5_REG_CLKDIV_1_12, (uint16_t)VDC5_REG_CLKDIV_1_16, (uint16_t)VDC5_REG_CLKDIV_1_24,
dkato 0:853f5b7408a7 422 (uint16_t)VDC5_REG_CLKDIV_1_32
dkato 0:853f5b7408a7 423 };
dkato 0:853f5b7408a7 424 static const uint16_t panel_icksel_tbl[VDC5_PANEL_ICKSEL_NUM] = {
dkato 0:853f5b7408a7 425 /* Panel clock select */
dkato 0:853f5b7408a7 426 (uint16_t)VDC5_REG_ICKSEL_IMG, (uint16_t)VDC5_REG_ICKSEL_IMG_DV, (uint16_t)VDC5_REG_ICKSEL_EXT_0, (uint16_t)VDC5_REG_ICKSEL_EXT_1,
dkato 0:853f5b7408a7 427 (uint16_t)VDC5_REG_ICKSEL_PERI, (uint16_t)VDC5_REG_ICKSEL_LVDS, (uint16_t)VDC5_REG_ICKSEL_LVDS_DIV7
dkato 0:853f5b7408a7 428 };
dkato 0:853f5b7408a7 429
dkato 0:853f5b7408a7 430 syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl[ch].syscnt_panel_clk;
dkato 0:853f5b7408a7 431 /* Disable */
dkato 0:853f5b7408a7 432 syscnt_panel_clk_tmp = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
dkato 0:853f5b7408a7 433 *syscnt_panel_clk_reg = syscnt_panel_clk_tmp;
dkato 0:853f5b7408a7 434
dkato 0:853f5b7408a7 435 /* LVDS */
dkato 0:853f5b7408a7 436 lvds_tmp = param->lvds;
dkato 0:853f5b7408a7 437 if (lvds_tmp != NULL) {
dkato 0:853f5b7408a7 438 regaddr_lvds = &vdc5_regaddr_lvds;
dkato 0:853f5b7408a7 439
dkato 0:853f5b7408a7 440 /* Output from the LVDS PLL is disabled. */
dkato 0:853f5b7408a7 441 *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 442 /* Controls power-down for the LVDS PLL: Power-down state */
dkato 0:853f5b7408a7 443 *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 444 for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
dkato 0:853f5b7408a7 445 /* This is a delay (1 usec) while waiting for PLL PD to settle. */
dkato 0:853f5b7408a7 446 }
dkato 0:853f5b7408a7 447
dkato 0:853f5b7408a7 448 /* LPHYACC */
dkato 0:853f5b7408a7 449 *(regaddr_lvds->lphyacc) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 450 *(regaddr_lvds->lphyacc) |= LVDS_LPHYACC_VALUE;
dkato 0:853f5b7408a7 451 /* LCLKSELR: LVDS clock select register */
dkato 0:853f5b7408a7 452 *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_MASK_0X0703FF02;
dkato 0:853f5b7408a7 453 /* The clock input to frequency divider 1 */
dkato 0:853f5b7408a7 454 *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_in_clk_sel << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 455 /* The frequency dividing value (NIDIV) for frequency divider 1 */
dkato 0:853f5b7408a7 456 *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_idiv_set << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 457 /* Internal parameter setting for LVDS PLL */
dkato 0:853f5b7408a7 458 *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvdspll_tst << VDC5_REG_SHIFT_10;
dkato 0:853f5b7408a7 459 /* The frequency dividing value (NODIV) for frequency divider 2 */
dkato 0:853f5b7408a7 460 *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_odiv_set << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 461 if (lvds_tmp->lvds_vdc_sel != VDC5_CHANNEL_0) {
dkato 0:853f5b7408a7 462 /* A channel in VDC5 whose data is to be output through the LVDS */
dkato 0:853f5b7408a7 463 *(regaddr_lvds->lclkselr) |= (uint32_t)VDC5_REG_BIT1;
dkato 0:853f5b7408a7 464 }
dkato 0:853f5b7408a7 465
dkato 0:853f5b7408a7 466 /* LPLLSETR: LVDS PLL setting register */
dkato 0:853f5b7408a7 467 *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC5_REG_MASK_0X07FF1F30;
dkato 0:853f5b7408a7 468 /* The frequency dividing value (NFD) for the feedback frequency */
dkato 0:853f5b7408a7 469 *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_fd << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 470 /* The frequency dividing value (NRD) for the input frequency */
dkato 0:853f5b7408a7 471 *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_rd << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 472 /* The frequency dividing value (NOD) for the output frequency */
dkato 0:853f5b7408a7 473 *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_od << VDC5_REG_SHIFT_4;
dkato 0:853f5b7408a7 474
dkato 0:853f5b7408a7 475 for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
dkato 0:853f5b7408a7 476 /* This is a delay (1 usec) while waiting for PLL PD to settle. */
dkato 0:853f5b7408a7 477 }
dkato 0:853f5b7408a7 478 /* Controls power-down for the LVDS PLL: Normal operation */
dkato 0:853f5b7408a7 479 *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 480
dkato 0:853f5b7408a7 481 /* Wait for 200 usec. */
dkato 0:853f5b7408a7 482 Wait_200_usec();
dkato 0:853f5b7408a7 483
dkato 0:853f5b7408a7 484 /* Output from the LVDS PLL is enabled. */
dkato 0:853f5b7408a7 485 *(regaddr_lvds->lclkselr) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 486 }
dkato 0:853f5b7408a7 487
dkato 0:853f5b7408a7 488 inp_sel_cnt_reg = vdc5_regaddr_input_ctrl[ch].inp_sel_cnt;
dkato 0:853f5b7408a7 489 /* Input select */
dkato 0:853f5b7408a7 490 if (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG_DV) {
dkato 0:853f5b7408a7 491 *inp_sel_cnt_reg |= (uint32_t)VDC5_REG_BIT20;
dkato 0:853f5b7408a7 492 } else {
dkato 0:853f5b7408a7 493 *inp_sel_cnt_reg &= (uint32_t)~VDC5_REG_BIT20;
dkato 0:853f5b7408a7 494 }
dkato 0:853f5b7408a7 495 syscnt_panel_clk_tmp = panel_dcdr_tbl[param->panel_dcdr];
dkato 0:853f5b7408a7 496 syscnt_panel_clk_tmp = (uint16_t)((uint32_t)syscnt_panel_clk_tmp |
dkato 0:853f5b7408a7 497 (uint32_t)panel_icksel_tbl[param->panel_icksel]);
dkato 0:853f5b7408a7 498 *syscnt_panel_clk_reg = syscnt_panel_clk_tmp;
dkato 0:853f5b7408a7 499 /* Enable */
dkato 0:853f5b7408a7 500 syscnt_panel_clk_tmp = (uint16_t)((uint32_t)syscnt_panel_clk_tmp | VDC5_REG_BIT8);
dkato 0:853f5b7408a7 501 *syscnt_panel_clk_reg = syscnt_panel_clk_tmp;
dkato 0:853f5b7408a7 502
dkato 0:853f5b7408a7 503 } /* End of function VDC5_Initialize() */
dkato 0:853f5b7408a7 504
dkato 0:853f5b7408a7 505 /**************************************************************************//**
dkato 0:853f5b7408a7 506 * @brief Sets registers for termination
dkato 0:853f5b7408a7 507 * @param[in] ch : Channel
dkato 0:853f5b7408a7 508 * @retval None
dkato 0:853f5b7408a7 509 ******************************************************************************/
dkato 0:853f5b7408a7 510 void VDC5_Terminate (const vdc5_channel_t ch)
dkato 0:853f5b7408a7 511 {
dkato 0:853f5b7408a7 512 volatile uint16_t * syscnt_panel_clk_reg;
dkato 0:853f5b7408a7 513 uint16_t syscnt_panel_clk_tmp;
dkato 0:853f5b7408a7 514 vdc5_resource_state_t rsrc_state;
dkato 0:853f5b7408a7 515 vdc5_onoff_t lvds_ref;
dkato 0:853f5b7408a7 516 const vdc5_regaddr_lvds_t * regaddr_lvds;
dkato 0:853f5b7408a7 517 volatile uint32_t counter;
dkato 0:853f5b7408a7 518
dkato 0:853f5b7408a7 519 syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl[ch].syscnt_panel_clk;
dkato 0:853f5b7408a7 520 /* Disable */
dkato 0:853f5b7408a7 521 syscnt_panel_clk_tmp = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
dkato 0:853f5b7408a7 522 *syscnt_panel_clk_reg = syscnt_panel_clk_tmp;
dkato 0:853f5b7408a7 523
dkato 0:853f5b7408a7 524 rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
dkato 0:853f5b7408a7 525 if (rsrc_state != VDC5_RESOURCE_ST_INVALID) { /* LVDS PLL clock is set. */
dkato 0:853f5b7408a7 526 lvds_ref = VDC5_ShrdPrmGetLvdsClkRef();
dkato 0:853f5b7408a7 527 if (lvds_ref == VDC5_OFF) { /* LVDS PLL clock is not referred. */
dkato 0:853f5b7408a7 528 regaddr_lvds = &vdc5_regaddr_lvds;
dkato 0:853f5b7408a7 529
dkato 0:853f5b7408a7 530 /* Output from the LVDS PLL is disabled. */
dkato 0:853f5b7408a7 531 *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 532 /* Controls power-down for the LVDS PLL: Power-down state */
dkato 0:853f5b7408a7 533 *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 534 for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
dkato 0:853f5b7408a7 535 /* This is a delay (1 usec) while waiting for PLL PD to settle. */
dkato 0:853f5b7408a7 536 }
dkato 0:853f5b7408a7 537 }
dkato 0:853f5b7408a7 538 }
dkato 0:853f5b7408a7 539 } /* End of function VDC5_Terminate() */
dkato 0:853f5b7408a7 540
dkato 0:853f5b7408a7 541 /**************************************************************************//**
dkato 0:853f5b7408a7 542 * @brief Sets registers for video input
dkato 0:853f5b7408a7 543 * @param[in] ch : Channel
dkato 0:853f5b7408a7 544 * @param[in] param : Video input setup parameter
dkato 0:853f5b7408a7 545 * @retval None
dkato 0:853f5b7408a7 546 ******************************************************************************/
dkato 0:853f5b7408a7 547 void VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t * const param)
dkato 0:853f5b7408a7 548 {
dkato 0:853f5b7408a7 549 const vdc5_regaddr_input_ctrl_t * input_ctrl;
dkato 0:853f5b7408a7 550 const vdc5_sync_delay_t * dly_tmp;
dkato 0:853f5b7408a7 551 const vdc5_ext_in_sig_t * ext_sig_tmp;
dkato 0:853f5b7408a7 552
dkato 0:853f5b7408a7 553 input_ctrl = &vdc5_regaddr_input_ctrl[ch];
dkato 0:853f5b7408a7 554
dkato 0:853f5b7408a7 555 /* Input select */
dkato 0:853f5b7408a7 556 if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
dkato 0:853f5b7408a7 557 *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_BIT20;
dkato 0:853f5b7408a7 558 } else {
dkato 0:853f5b7408a7 559 *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT20;
dkato 0:853f5b7408a7 560 }
dkato 0:853f5b7408a7 561 /* Vsync signal 1/2fH and 1/4fH phase timing */
dkato 0:853f5b7408a7 562 *(input_ctrl->inp_vsync_ph_adj) = (uint32_t)param->inp_fh50 << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 563 *(input_ctrl->inp_vsync_ph_adj) |= (uint32_t)param->inp_fh25;
dkato 0:853f5b7408a7 564
dkato 0:853f5b7408a7 565 /* Sync signal delay adjustment */
dkato 0:853f5b7408a7 566 dly_tmp = param->dly;
dkato 0:853f5b7408a7 567 if (dly_tmp != NULL) {
dkato 0:853f5b7408a7 568 /* Number of lines for delaying Vsync signal and field differentiation signal */
dkato 0:853f5b7408a7 569 *(input_ctrl->inp_dly_adj) = (uint32_t)dly_tmp->inp_vs_dly_l << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 570 /* Field differentiation signal delay amount */
dkato 0:853f5b7408a7 571 *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_fld_dly << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 572 /* Vsync signal delay amount */
dkato 0:853f5b7408a7 573 *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_vs_dly << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 574 /* Hsync signal delay amount */
dkato 0:853f5b7408a7 575 *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_hs_dly;
dkato 0:853f5b7408a7 576 }
dkato 0:853f5b7408a7 577
dkato 0:853f5b7408a7 578 /* Horizontal noise reduction operating mode, Y/Cb/Cr mode */
dkato 0:853f5b7408a7 579 *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT20;
dkato 0:853f5b7408a7 580
dkato 0:853f5b7408a7 581 /* External input signal */
dkato 0:853f5b7408a7 582 ext_sig_tmp = param->ext_sig;
dkato 0:853f5b7408a7 583 if (ext_sig_tmp != NULL) {
dkato 0:853f5b7408a7 584 /* Setting external input video signal */
dkato 0:853f5b7408a7 585 SetVideoExternalInput(ext_sig_tmp, input_ctrl);
dkato 0:853f5b7408a7 586
dkato 0:853f5b7408a7 587 /* Horizontal noise reduction operating mode, G/B/R mode */
dkato 0:853f5b7408a7 588 if ((ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
dkato 0:853f5b7408a7 589 (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
dkato 0:853f5b7408a7 590 (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB565)) {
dkato 0:853f5b7408a7 591 *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT20;
dkato 0:853f5b7408a7 592 }
dkato 0:853f5b7408a7 593 }
dkato 0:853f5b7408a7 594
dkato 0:853f5b7408a7 595 /* Register update control register (INP_UPDATE)
dkato 0:853f5b7408a7 596 b4 INP_EXT_UPDATE
dkato 0:853f5b7408a7 597 b0 INP_IMG_UPDATE */
dkato 0:853f5b7408a7 598 *(input_ctrl->inp_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 599 /* Register update control register (IMGCNT_UPDATE)
dkato 0:853f5b7408a7 600 b0 IMGCNT_VEN */
dkato 0:853f5b7408a7 601 *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 602 } /* End of function VDC5_VideoInput() */
dkato 0:853f5b7408a7 603
dkato 0:853f5b7408a7 604 /**************************************************************************//**
dkato 0:853f5b7408a7 605 * @brief Sets registers for sync control
dkato 0:853f5b7408a7 606 * @param[in] ch : Channel
dkato 0:853f5b7408a7 607 * @param[in] param : Sync signal control parameter
dkato 0:853f5b7408a7 608 * @retval None
dkato 0:853f5b7408a7 609 ******************************************************************************/
dkato 0:853f5b7408a7 610 void VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
dkato 0:853f5b7408a7 611 {
dkato 0:853f5b7408a7 612 const vdc5_regaddr_scaler_t * scaler_0;
dkato 0:853f5b7408a7 613 const vdc5_regaddr_scaler_t * scaler_1;
dkato 0:853f5b7408a7 614 const vdc5_regaddr_scaler_t * scaler_oir;
dkato 0:853f5b7408a7 615 uint32_t full_scr;
dkato 0:853f5b7408a7 616
dkato 0:853f5b7408a7 617 scaler_0 = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
dkato 0:853f5b7408a7 618 scaler_1 = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
dkato 0:853f5b7408a7 619 scaler_oir = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
dkato 0:853f5b7408a7 620
dkato 0:853f5b7408a7 621 if (param->vsync_cpmpe != NULL) {
dkato 0:853f5b7408a7 622 /* Frequent Vsync signal masking period */
dkato 0:853f5b7408a7 623 *(scaler_0->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 624 *(scaler_1->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 625 /* Missing-Sync compensating pulse output wait time */
dkato 0:853f5b7408a7 626 *(scaler_0->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 627 *(scaler_1->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 628 /* Frequent Vsync signal masking and missing Vsync signal compensation */
dkato 0:853f5b7408a7 629 *(scaler_0->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 630 *(scaler_1->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 631 *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 632 *(scaler_1->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 633 } else {
dkato 0:853f5b7408a7 634 /* Frequent Vsync signal masking and missing Vsync signal compensation are disabled, if unnecessary. */
dkato 0:853f5b7408a7 635 *(scaler_0->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 636 *(scaler_1->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 637 *(scaler_0->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 638 *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
dkato 0:853f5b7408a7 639 *(scaler_1->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 640 *(scaler_1->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
dkato 0:853f5b7408a7 641 }
dkato 0:853f5b7408a7 642 /* In OIR, frequent Vsync signal masking and missing Vsync signal compensation are set to off. */
dkato 0:853f5b7408a7 643 *(scaler_oir->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 644 *(scaler_oir->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 645
dkato 0:853f5b7408a7 646 /* Hsync period setting and free-running Vsync period initialization */
dkato 0:853f5b7408a7 647 *(scaler_0->scl0_frc4) = (uint32_t)param->res_fh;
dkato 0:853f5b7408a7 648 *(scaler_1->scl0_frc4) = (uint32_t)param->res_fh;
dkato 0:853f5b7408a7 649 *(scaler_oir->scl0_frc4) = (uint32_t)param->res_fh;
dkato 0:853f5b7408a7 650 /* Vsync signal output select (free-running Vsync on/off control) */
dkato 0:853f5b7408a7 651 if (param->res_vs_sel == VDC5_OFF) {
dkato 0:853f5b7408a7 652 *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 653 *(scaler_1->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 654 } else {
dkato 0:853f5b7408a7 655 *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 656 *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 657 *(scaler_0->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
dkato 0:853f5b7408a7 658 *(scaler_0->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 659 *(scaler_1->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
dkato 0:853f5b7408a7 660 *(scaler_1->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 661 }
dkato 0:853f5b7408a7 662 /* In OIR, external input Vsync signal is selected automatically. */
dkato 0:853f5b7408a7 663 *(scaler_oir->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 664
dkato 0:853f5b7408a7 665 /* Sync signal output and full-screen enable signal select: Scaler 0 */
dkato 0:853f5b7408a7 666 *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
dkato 0:853f5b7408a7 667 *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 668
dkato 0:853f5b7408a7 669 /* Vsync signal delay control */
dkato 0:853f5b7408a7 670 *(scaler_0->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
dkato 0:853f5b7408a7 671 *(scaler_0->scl0_frc5) |= (uint32_t)param->res_vsdly;
dkato 0:853f5b7408a7 672 *(scaler_1->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
dkato 0:853f5b7408a7 673 *(scaler_1->scl0_frc5) |= (uint32_t)param->res_vsdly;
dkato 0:853f5b7408a7 674 *(scaler_oir->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
dkato 0:853f5b7408a7 675 *(scaler_oir->scl0_frc5) |= OIR_VSYNC_DELAY;
dkato 0:853f5b7408a7 676
dkato 0:853f5b7408a7 677 /* Full-screen enable signal */
dkato 0:853f5b7408a7 678 full_scr = (uint32_t)param->res_f.vs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 679 full_scr |= (uint32_t)param->res_f.vw;
dkato 0:853f5b7408a7 680
dkato 0:853f5b7408a7 681 *(scaler_0->scl0_frc6) = full_scr;
dkato 0:853f5b7408a7 682 *(scaler_1->scl0_frc6) = full_scr;
dkato 0:853f5b7408a7 683 *(scaler_oir->scl0_frc6) = full_scr;
dkato 0:853f5b7408a7 684
dkato 0:853f5b7408a7 685 full_scr = (uint32_t)param->res_f.hs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 686 full_scr |= (uint32_t)param->res_f.hw;
dkato 0:853f5b7408a7 687
dkato 0:853f5b7408a7 688 *(scaler_0->scl0_frc7) = full_scr;
dkato 0:853f5b7408a7 689 *(scaler_1->scl0_frc7) = full_scr;
dkato 0:853f5b7408a7 690 *(scaler_oir->scl0_frc7) = full_scr;
dkato 0:853f5b7408a7 691
dkato 0:853f5b7408a7 692 /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
dkato 0:853f5b7408a7 693 b8 SCL0_UPDATE
dkato 0:853f5b7408a7 694 b4 SCL0_VEN_B */
dkato 0:853f5b7408a7 695 *(scaler_0->scl0_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
dkato 0:853f5b7408a7 696 *(scaler_1->scl0_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
dkato 0:853f5b7408a7 697 *(scaler_oir->scl0_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
dkato 0:853f5b7408a7 698
dkato 0:853f5b7408a7 699 SetInitialConnection(ch);
dkato 0:853f5b7408a7 700
dkato 0:853f5b7408a7 701 VDC5_ShrdPrmSetUndSel(ch, VDC5_OFF);
dkato 0:853f5b7408a7 702 } /* End of function VDC5_SyncControl() */
dkato 0:853f5b7408a7 703
dkato 0:853f5b7408a7 704 /**************************************************************************//**
dkato 0:853f5b7408a7 705 * @brief Sets registers for display output
dkato 0:853f5b7408a7 706 * @param[in] ch : Channel
dkato 0:853f5b7408a7 707 * @param[in] param : Display output configuration parameter
dkato 0:853f5b7408a7 708 * @retval None
dkato 0:853f5b7408a7 709 ******************************************************************************/
dkato 0:853f5b7408a7 710 void VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t * const param)
dkato 0:853f5b7408a7 711 {
dkato 0:853f5b7408a7 712 const vdc5_regaddr_output_ctrl_t * output_ctrl;
dkato 0:853f5b7408a7 713 volatile uint32_t * output_pin_regaddr[VDC5_LCD_TCON_PIN_NUM];
dkato 0:853f5b7408a7 714 uint32_t tcon_sig_index;
dkato 0:853f5b7408a7 715 const vdc5_lcd_tcon_timing_t * const * lcd_tcon_timing;
dkato 0:853f5b7408a7 716 static void (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
dkato 0:853f5b7408a7 717 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 718 const vdc5_regaddr_output_ctrl_t * const output_ctrl) = {
dkato 0:853f5b7408a7 719 &SetLcdTcon_STVA_VS, /* STVA/VS */
dkato 0:853f5b7408a7 720 &SetLcdTcon_STVB_VE, /* STVB/VE */
dkato 0:853f5b7408a7 721 &SetLcdTcon_STH_HS, /* STH_HS */
dkato 0:853f5b7408a7 722 &SetLcdTcon_STB_HE, /* STB_HE */
dkato 0:853f5b7408a7 723 &SetLcdTcon_CPV_GCK, /* CPV_GCK */
dkato 0:853f5b7408a7 724 &SetLcdTcon_POLA, /* POLA */
dkato 0:853f5b7408a7 725 &SetLcdTcon_POLB, /* POLB */
dkato 0:853f5b7408a7 726 &SetLcdTcon_DE /* DE */
dkato 0:853f5b7408a7 727 };
dkato 0:853f5b7408a7 728 const uint32_t output_pin_edge[VDC5_LCD_TCON_PIN_NUM] = {
dkato 0:853f5b7408a7 729 VDC5_REG_TCON0_EDGE, VDC5_REG_TCON1_EDGE, VDC5_REG_TCON2_EDGE, VDC5_REG_TCON3_EDGE,
dkato 0:853f5b7408a7 730 VDC5_REG_TCON4_EDGE, VDC5_REG_TCON5_EDGE, VDC5_REG_TCON6_EDGE
dkato 0:853f5b7408a7 731 };
dkato 0:853f5b7408a7 732 vdc5_lcd_tcon_pin_t tcon_pin_tmp;
dkato 0:853f5b7408a7 733 const vdc5_gr_disp_sel_t gr_disp_sel_tbl[VDC5_GR_TYPE_NUM] = {
dkato 0:853f5b7408a7 734 /* Graphics display mode for initialization */
dkato 0:853f5b7408a7 735 VDC5_DISPSEL_BACK, /* Graphics 0 */
dkato 0:853f5b7408a7 736 VDC5_DISPSEL_LOWER, /* Graphics 1 */
dkato 0:853f5b7408a7 737 VDC5_DISPSEL_LOWER, /* Graphics 2 */
dkato 0:853f5b7408a7 738 VDC5_DISPSEL_LOWER, /* Graphics 3 */
dkato 0:853f5b7408a7 739 VDC5_DISPSEL_IGNORED, /* VIN */
dkato 0:853f5b7408a7 740 VDC5_DISPSEL_BACK /* OIR */
dkato 0:853f5b7408a7 741 };
dkato 0:853f5b7408a7 742 const uint32_t dither_format[VDC5_LCD_OUTFORMAT_NUM] = {
dkato 0:853f5b7408a7 743 /* Panel dither output format select */
dkato 0:853f5b7408a7 744 VDC5_REG_PATH_FORMAT_RGB888, VDC5_REG_PATH_FORMAT_RGB666,
dkato 0:853f5b7408a7 745 VDC5_REG_PATH_FORMAT_RGB565, VDC5_REG_PATH_FORMAT_NON
dkato 0:853f5b7408a7 746 };
dkato 0:853f5b7408a7 747
dkato 0:853f5b7408a7 748 output_ctrl = &vdc5_regaddr_output_ctrl[ch];
dkato 0:853f5b7408a7 749
dkato 0:853f5b7408a7 750 /* 1/2fH timing */
dkato 0:853f5b7408a7 751 *(output_ctrl->tcon_tim) = (uint32_t)param->tcon_half << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 752 /* Offset Hsync signal timing */
dkato 0:853f5b7408a7 753 *(output_ctrl->tcon_tim) |= (uint32_t)param->tcon_offset;
dkato 0:853f5b7408a7 754
dkato 0:853f5b7408a7 755 /* Create output pin register address table */
dkato 0:853f5b7408a7 756 output_pin_regaddr[VDC5_LCD_TCON_PIN_0] = output_ctrl->tcon_tim_stva2;
dkato 0:853f5b7408a7 757 output_pin_regaddr[VDC5_LCD_TCON_PIN_1] = output_ctrl->tcon_tim_stvb2;
dkato 0:853f5b7408a7 758 output_pin_regaddr[VDC5_LCD_TCON_PIN_2] = output_ctrl->tcon_tim_sth2;
dkato 0:853f5b7408a7 759 output_pin_regaddr[VDC5_LCD_TCON_PIN_3] = output_ctrl->tcon_tim_stb2;
dkato 0:853f5b7408a7 760 output_pin_regaddr[VDC5_LCD_TCON_PIN_4] = output_ctrl->tcon_tim_cpv2;
dkato 0:853f5b7408a7 761 output_pin_regaddr[VDC5_LCD_TCON_PIN_5] = output_ctrl->tcon_tim_pola2;
dkato 0:853f5b7408a7 762 output_pin_regaddr[VDC5_LCD_TCON_PIN_6] = output_ctrl->tcon_tim_polb2;
dkato 0:853f5b7408a7 763
dkato 0:853f5b7408a7 764 /* Clear output phase control of LCT_TCON0~6 pin */
dkato 0:853f5b7408a7 765 *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_MASK_0X0000007F;
dkato 0:853f5b7408a7 766 /* LCD TCON */
dkato 0:853f5b7408a7 767 lcd_tcon_timing = param->outctrl;
dkato 0:853f5b7408a7 768 for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++) {
dkato 0:853f5b7408a7 769 if (*lcd_tcon_timing != NULL) {
dkato 0:853f5b7408a7 770 /* Setting LCD TCON */
dkato 0:853f5b7408a7 771 tcon_function_tbl[tcon_sig_index](*lcd_tcon_timing, output_ctrl);
dkato 0:853f5b7408a7 772
dkato 0:853f5b7408a7 773 tcon_pin_tmp = (*lcd_tcon_timing)->tcon_pin;
dkato 0:853f5b7408a7 774 if (tcon_pin_tmp != VDC5_LCD_TCON_PIN_NON) {
dkato 0:853f5b7408a7 775 /* LCD TCON output pin select */
dkato 0:853f5b7408a7 776 *(output_pin_regaddr[tcon_pin_tmp]) &= (uint32_t)~VDC5_REG_MASK_0X00000007;
dkato 0:853f5b7408a7 777 *(output_pin_regaddr[tcon_pin_tmp]) |= tcon_sig_index;
dkato 0:853f5b7408a7 778 /* Output phase control of LCT_TCON pin */
dkato 0:853f5b7408a7 779 if ((*lcd_tcon_timing)->outcnt_edge != VDC5_EDGE_RISING) {
dkato 0:853f5b7408a7 780 *(output_ctrl->out_clk_phase) |= output_pin_edge[tcon_pin_tmp];
dkato 0:853f5b7408a7 781 }
dkato 0:853f5b7408a7 782 }
dkato 0:853f5b7408a7 783 }
dkato 0:853f5b7408a7 784 lcd_tcon_timing++;
dkato 0:853f5b7408a7 785 }
dkato 0:853f5b7408a7 786
dkato 0:853f5b7408a7 787 *(output_ctrl->out_set) &= (uint32_t)~VDC5_REG_MASK_0X11003313;
dkato 0:853f5b7408a7 788 /* Bit endian change ON/OFF control */
dkato 0:853f5b7408a7 789 if (param->out_endian_on != VDC5_OFF) {
dkato 0:853f5b7408a7 790 *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT28;
dkato 0:853f5b7408a7 791 }
dkato 0:853f5b7408a7 792 /* B/R signal swap ON/OFF control */
dkato 0:853f5b7408a7 793 if (param->out_swap_on != VDC5_OFF) {
dkato 0:853f5b7408a7 794 *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT24;
dkato 0:853f5b7408a7 795 }
dkato 0:853f5b7408a7 796 /* Output format select */
dkato 0:853f5b7408a7 797 *(output_ctrl->out_set) |= (uint32_t)param->out_format << VDC5_REG_SHIFT_12;
dkato 0:853f5b7408a7 798
dkato 0:853f5b7408a7 799 /* Panel dither output format select */
dkato 0:853f5b7408a7 800 *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00030000;
dkato 0:853f5b7408a7 801 *(output_ctrl->out_pdtha) |= dither_format[param->out_format];
dkato 0:853f5b7408a7 802
dkato 0:853f5b7408a7 803 if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB) {
dkato 0:853f5b7408a7 804 /* Clock frequency control */
dkato 0:853f5b7408a7 805 *(output_ctrl->out_set) |= (uint32_t)param->out_frq_sel << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 806 /* Scan direction select */
dkato 0:853f5b7408a7 807 if (param->out_dir_sel != VDC5_LCD_SERIAL_SCAN_FORWARD) {
dkato 0:853f5b7408a7 808 *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 809 }
dkato 0:853f5b7408a7 810 /* Clock phase adjustment */
dkato 0:853f5b7408a7 811 *(output_ctrl->out_set) |= (uint32_t)param->out_phase;
dkato 0:853f5b7408a7 812 } else {
dkato 0:853f5b7408a7 813 /* Clock frequency control */
dkato 0:853f5b7408a7 814 *(output_ctrl->out_set) |= (uint32_t)VDC5_LCD_PARALLEL_CLKFRQ_1 << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 815 }
dkato 0:853f5b7408a7 816
dkato 0:853f5b7408a7 817 /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
dkato 0:853f5b7408a7 818 if (param->outcnt_lcd_edge == VDC5_EDGE_RISING) {
dkato 0:853f5b7408a7 819 *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT8;
dkato 0:853f5b7408a7 820 } else {
dkato 0:853f5b7408a7 821 *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 822 }
dkato 0:853f5b7408a7 823
dkato 0:853f5b7408a7 824 /* Set background color */
dkato 0:853f5b7408a7 825 SetGrapicsBackgroundColor(ch);
dkato 0:853f5b7408a7 826 /* Initialize graphics display mode */
dkato 0:853f5b7408a7 827 SetGraphicsDisplayMode(ch, VDC5_LAYER_ID_ALL, gr_disp_sel_tbl);
dkato 0:853f5b7408a7 828
dkato 0:853f5b7408a7 829 /* TCON register update control register (TCON_UPDATE)
dkato 0:853f5b7408a7 830 b0 TCON_VEN */
dkato 0:853f5b7408a7 831 *(output_ctrl->tcon_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 832 /* Register update control register (OUT_UPDATE)
dkato 0:853f5b7408a7 833 b0 OUTCNT_VEN */
dkato 0:853f5b7408a7 834 *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 835
dkato 0:853f5b7408a7 836 } /* End of function VDC5_DisplayOutput() */
dkato 0:853f5b7408a7 837
dkato 0:853f5b7408a7 838 /**************************************************************************//**
dkato 0:853f5b7408a7 839 * @brief Sets registers for data write control processing
dkato 0:853f5b7408a7 840 * @param[in] ch : Channel
dkato 0:853f5b7408a7 841 * @param[in] scaling_id : Scaling type ID
dkato 0:853f5b7408a7 842 * @param[in] param : Data write control parameter
dkato 0:853f5b7408a7 843 * @retval None
dkato 0:853f5b7408a7 844 ******************************************************************************/
dkato 0:853f5b7408a7 845 void VDC5_WriteDataControl (
dkato 0:853f5b7408a7 846 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 847 const vdc5_scaling_type_t scaling_id,
dkato 0:853f5b7408a7 848 const vdc5_write_t * const param)
dkato 0:853f5b7408a7 849 {
dkato 0:853f5b7408a7 850 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 851 const vdc5_scalingdown_rot_t * scldw_rot;
dkato 0:853f5b7408a7 852
dkato 0:853f5b7408a7 853 scaler = &vdc5_regaddr_scaler[ch][scaling_id];
dkato 0:853f5b7408a7 854 scldw_rot = &param->scalingdown_rot;
dkato 0:853f5b7408a7 855
dkato 0:853f5b7408a7 856 /* Image area to be captured */
dkato 0:853f5b7408a7 857 *(scaler->scl0_ds2) = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 858 *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
dkato 0:853f5b7408a7 859 *(scaler->scl0_ds3) = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 860 *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
dkato 0:853f5b7408a7 861
dkato 0:853f5b7408a7 862 *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X0007000D;
dkato 0:853f5b7408a7 863 /* Swap setting in frame buffer writing */
dkato 0:853f5b7408a7 864 *(scaler->scl1_wr1) |= (uint32_t)param->res_wrswa << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 865 /* Frame buffer video-signal writing format */
dkato 0:853f5b7408a7 866 *(scaler->scl1_wr1) |= (uint32_t)param->res_md << VDC5_REG_SHIFT_2;
dkato 0:853f5b7408a7 867 /* Transfer burst length for frame buffer writing */
dkato 0:853f5b7408a7 868 if (param->res_bst_md != VDC5_BST_MD_32BYTE) {
dkato 0:853f5b7408a7 869 *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 870 }
dkato 0:853f5b7408a7 871
dkato 0:853f5b7408a7 872 /* Frame buffer base address */
dkato 0:853f5b7408a7 873 *(scaler->scl1_wr2) = (uint32_t)param->base;
dkato 0:853f5b7408a7 874 /* Frame buffer line offset address[byte] */
dkato 0:853f5b7408a7 875 *(scaler->scl1_wr3) = param->ln_off << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 876 /* Number of frames of buffer to be written to (res_flm_num + 1) */
dkato 0:853f5b7408a7 877 *(scaler->scl1_wr3) |= param->flm_num;
dkato 0:853f5b7408a7 878 /* Frame buffer frame offset address [byte] */
dkato 0:853f5b7408a7 879 if (param->flm_num != 0u) {
dkato 0:853f5b7408a7 880 *(scaler->scl1_wr4) = param->flm_off;
dkato 0:853f5b7408a7 881 }
dkato 0:853f5b7408a7 882
dkato 0:853f5b7408a7 883 /* Writing rate */
dkato 0:853f5b7408a7 884 *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_MASK_0X00000300;
dkato 0:853f5b7408a7 885 *(scaler->scl1_wr5) |= (uint32_t)param->res_fs_rate << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 886
dkato 0:853f5b7408a7 887 /* Dither correction on/off */
dkato 0:853f5b7408a7 888 if (param->res_dth_on == VDC5_OFF) {
dkato 0:853f5b7408a7 889 *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 890 } else {
dkato 0:853f5b7408a7 891 *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 892 }
dkato 0:853f5b7408a7 893 /* Bit Reduction */
dkato 0:853f5b7408a7 894 if (param->res_md == VDC5_RES_MD_RGB565) {
dkato 0:853f5b7408a7 895 /* On */
dkato 0:853f5b7408a7 896 *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 897 } else {
dkato 0:853f5b7408a7 898 /* Off */
dkato 0:853f5b7408a7 899 *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 900 }
dkato 0:853f5b7408a7 901
dkato 0:853f5b7408a7 902 if (scaling_id == VDC5_SC_TYPE_OIR) {
dkato 0:853f5b7408a7 903 /* OIR */
dkato 0:853f5b7408a7 904 /* Vertical and horizontal width after scaling-down control block */
dkato 0:853f5b7408a7 905 *(scaler->scl0_ds7) = (uint32_t)scldw_rot->res.vw << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 906 *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res.hw;
dkato 0:853f5b7408a7 907
dkato 0:853f5b7408a7 908 /* Vertical scaling-down and horizontal scaling-down : OFF */
dkato 0:853f5b7408a7 909 *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_MASK_0X00000011;
dkato 0:853f5b7408a7 910
dkato 0:853f5b7408a7 911 /* Field operating mode select is fixed to progressive */
dkato 0:853f5b7408a7 912 *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
dkato 0:853f5b7408a7 913 } else {
dkato 0:853f5b7408a7 914 /* Scaler 0 or 1 */
dkato 0:853f5b7408a7 915 /* Field determination signal delay control */
dkato 0:853f5b7408a7 916 if (param->flm_num == 0u) {
dkato 0:853f5b7408a7 917 /* Frame buffer: One plane */
dkato 0:853f5b7408a7 918 *(scaler->scl0_frc5) &= (uint32_t)~VDC5_REG_BIT8;
dkato 0:853f5b7408a7 919 } else {
dkato 0:853f5b7408a7 920 /* Frame buffer: Two planes or more */
dkato 0:853f5b7408a7 921 *(scaler->scl0_frc5) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 922 }
dkato 0:853f5b7408a7 923
dkato 0:853f5b7408a7 924 /* Horizontal prefilter */
dkato 0:853f5b7408a7 925 if (scldw_rot->res_pfil_sel == VDC5_OFF) {
dkato 0:853f5b7408a7 926 *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
dkato 0:853f5b7408a7 927 } else {
dkato 0:853f5b7408a7 928 *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
dkato 0:853f5b7408a7 929 }
dkato 0:853f5b7408a7 930 /* Number of valid lines in vertical direction output by scaling-down control block */
dkato 0:853f5b7408a7 931 *(scaler->scl0_ds7) = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 932 /* Number of valid horizontal pixels output by scaling-down control block */
dkato 0:853f5b7408a7 933 *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
dkato 0:853f5b7408a7 934
dkato 0:853f5b7408a7 935 /* Scaling-down */
dkato 0:853f5b7408a7 936 SetScalingDown(scldw_rot, param->res_inter, scaler);
dkato 0:853f5b7408a7 937
dkato 0:853f5b7408a7 938 /* Frame buffer writing mode for image processing */
dkato 0:853f5b7408a7 939 *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
dkato 0:853f5b7408a7 940 *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
dkato 0:853f5b7408a7 941
dkato 0:853f5b7408a7 942 /* Field operating mode select */
dkato 0:853f5b7408a7 943 if (param->res_inter == VDC5_RES_INTER_PROGRESSIVE) {
dkato 0:853f5b7408a7 944 /* Progressive */
dkato 0:853f5b7408a7 945 *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
dkato 0:853f5b7408a7 946 } else {
dkato 0:853f5b7408a7 947 /* Interlace */
dkato 0:853f5b7408a7 948 *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT12;
dkato 0:853f5b7408a7 949 }
dkato 0:853f5b7408a7 950 /* Write field select */
dkato 0:853f5b7408a7 951 if (param->res_fld_sel == VDC5_RES_FLD_SEL_TOP) {
dkato 0:853f5b7408a7 952 /* Top field */
dkato 0:853f5b7408a7 953 *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 954 } else {
dkato 0:853f5b7408a7 955 /* Bottom field */
dkato 0:853f5b7408a7 956 *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 957 }
dkato 0:853f5b7408a7 958
dkato 0:853f5b7408a7 959 /* Frame buffer for bottom */
dkato 0:853f5b7408a7 960 if (param->btm_base != NULL) {
dkato 0:853f5b7408a7 961 /* SC_RES_TB_ADD_MOD */
dkato 0:853f5b7408a7 962 *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_MASK_0X00000080;
dkato 0:853f5b7408a7 963
dkato 0:853f5b7408a7 964 /* Frame buffer base address */
dkato 0:853f5b7408a7 965 *(scaler->scl1_wr8) = (uint32_t)param->btm_base;
dkato 0:853f5b7408a7 966 /* Frame buffer line offset address[byte] */
dkato 0:853f5b7408a7 967 *(scaler->scl1_wr9) = param->ln_off << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 968 /* Number of frames of buffer to be written to (defined by res_flm_num + 1) */
dkato 0:853f5b7408a7 969 *(scaler->scl1_wr9) |= param->flm_num;
dkato 0:853f5b7408a7 970 /* Frame buffer frame offset address */
dkato 0:853f5b7408a7 971 if (param->flm_num != 0u) {
dkato 0:853f5b7408a7 972 *(scaler->scl1_wr10) = param->flm_off;
dkato 0:853f5b7408a7 973 }
dkato 0:853f5b7408a7 974 } else {
dkato 0:853f5b7408a7 975 /* SC_RES_TB_ADD_MOD */
dkato 0:853f5b7408a7 976 *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000080;
dkato 0:853f5b7408a7 977 }
dkato 0:853f5b7408a7 978 }
dkato 0:853f5b7408a7 979
dkato 0:853f5b7408a7 980 /* Register update control register (SC0/SC1/OIR_SCL0_UPDATE)
dkato 0:853f5b7408a7 981 b12 SCL0_VEN_C
dkato 0:853f5b7408a7 982 b4 SCL0_VEN_B
dkato 0:853f5b7408a7 983 b0 SCL0_VEN_A */
dkato 0:853f5b7408a7 984 *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 985 /* Register update control register (SC0/SC1/OIR_SCL1_UPDATE)
dkato 0:853f5b7408a7 986 b16 SCL1_UPDATE_A
dkato 0:853f5b7408a7 987 b4 SCL1_VEN_B
dkato 0:853f5b7408a7 988 b0 SCL1_VEN_A */
dkato 0:853f5b7408a7 989 *(scaler->scl1_update) |= (uint32_t)(VDC5_REG_BIT16 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 990
dkato 0:853f5b7408a7 991 if (scaling_id != VDC5_SC_TYPE_OIR) {
dkato 0:853f5b7408a7 992 SetInputCntrlColorMtx(ch, scaling_id);
dkato 0:853f5b7408a7 993 }
dkato 0:853f5b7408a7 994 } /* End of function VDC5_WriteDataControl() */
dkato 0:853f5b7408a7 995
dkato 0:853f5b7408a7 996 /**************************************************************************//**
dkato 0:853f5b7408a7 997 * @brief Sets registers for data write change processing
dkato 0:853f5b7408a7 998 * @param[in] ch : Channel
dkato 0:853f5b7408a7 999 * @param[in] scaling_id : Scaling type ID
dkato 0:853f5b7408a7 1000 * @param[in] param : Data write change parameter
dkato 0:853f5b7408a7 1001 * @retval None
dkato 0:853f5b7408a7 1002 ******************************************************************************/
dkato 0:853f5b7408a7 1003 void VDC5_ChangeWriteProcess (
dkato 0:853f5b7408a7 1004 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1005 const vdc5_scaling_type_t scaling_id,
dkato 0:853f5b7408a7 1006 const vdc5_write_chg_t * const param)
dkato 0:853f5b7408a7 1007 {
dkato 0:853f5b7408a7 1008 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 1009 const vdc5_scalingdown_rot_t * scldw_rot;
dkato 0:853f5b7408a7 1010 vdc5_res_inter_t res_inter_tmp;
dkato 0:853f5b7408a7 1011
dkato 0:853f5b7408a7 1012 scaler = &vdc5_regaddr_scaler[ch][scaling_id];
dkato 0:853f5b7408a7 1013 scldw_rot = &param->scalingdown_rot;
dkato 0:853f5b7408a7 1014
dkato 0:853f5b7408a7 1015 /* Image area to be captured */
dkato 0:853f5b7408a7 1016 *(scaler->scl0_ds2) = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1017 *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
dkato 0:853f5b7408a7 1018 *(scaler->scl0_ds3) = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1019 *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
dkato 0:853f5b7408a7 1020
dkato 0:853f5b7408a7 1021 if (scaling_id == VDC5_SC_TYPE_OIR) {
dkato 0:853f5b7408a7 1022 /* OIR */
dkato 0:853f5b7408a7 1023 /* Vertical and horizontal width after scaling-down control block */
dkato 0:853f5b7408a7 1024 *(scaler->scl0_ds7) = (uint32_t)scldw_rot->res.vw << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1025 *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res.hw;
dkato 0:853f5b7408a7 1026 } else {
dkato 0:853f5b7408a7 1027 /* Scaler 0 or 1 */
dkato 0:853f5b7408a7 1028 /* Horizontal prefilter */
dkato 0:853f5b7408a7 1029 if (scldw_rot->res_pfil_sel == VDC5_OFF) {
dkato 0:853f5b7408a7 1030 *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
dkato 0:853f5b7408a7 1031 } else {
dkato 0:853f5b7408a7 1032 *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
dkato 0:853f5b7408a7 1033 }
dkato 0:853f5b7408a7 1034 /* Number of valid lines in vertical direction output by scaling-down control block */
dkato 0:853f5b7408a7 1035 *(scaler->scl0_ds7) = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1036 /* Number of valid horizontal pixels output by scaling-down control block */
dkato 0:853f5b7408a7 1037 *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
dkato 0:853f5b7408a7 1038
dkato 0:853f5b7408a7 1039 /* Progressive or interlace */
dkato 0:853f5b7408a7 1040 res_inter_tmp = VDC5_ShrdPrmGetInterlace(ch, scaling_id);
dkato 0:853f5b7408a7 1041 /* Scaling-down */
dkato 0:853f5b7408a7 1042 SetScalingDown(scldw_rot, res_inter_tmp, scaler);
dkato 0:853f5b7408a7 1043
dkato 0:853f5b7408a7 1044 /* Frame buffer writing mode for image processing */
dkato 0:853f5b7408a7 1045 *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
dkato 0:853f5b7408a7 1046 *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
dkato 0:853f5b7408a7 1047
dkato 0:853f5b7408a7 1048 /* Register update control register (SC0/SC1)
dkato 0:853f5b7408a7 1049 b4 SCL1_VEN_B
dkato 0:853f5b7408a7 1050 b0 SCL1_VEN_A */
dkato 0:853f5b7408a7 1051 *(scaler->scl1_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 1052 }
dkato 0:853f5b7408a7 1053
dkato 0:853f5b7408a7 1054 /* Register update control register (SC0/SC1/OIR_SCL0_UPDATE)
dkato 0:853f5b7408a7 1055 b12 SCL0_VEN_C
dkato 0:853f5b7408a7 1056 b4 SCL0_VEN_B
dkato 0:853f5b7408a7 1057 b0 SCL0_VEN_A */
dkato 0:853f5b7408a7 1058 *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 1059
dkato 0:853f5b7408a7 1060 } /* End of function VDC5_ChangeWriteProcess() */
dkato 0:853f5b7408a7 1061
dkato 0:853f5b7408a7 1062 /**************************************************************************//**
dkato 0:853f5b7408a7 1063 * @brief Sets registers for data read control processing
dkato 0:853f5b7408a7 1064 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1065 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 1066 * @param[in] param : Data read control parameter
dkato 0:853f5b7408a7 1067 * @retval None
dkato 0:853f5b7408a7 1068 ******************************************************************************/
dkato 0:853f5b7408a7 1069 void VDC5_ReadDataControl (
dkato 0:853f5b7408a7 1070 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1071 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 1072 const vdc5_read_t * const param)
dkato 0:853f5b7408a7 1073 {
dkato 0:853f5b7408a7 1074 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 1075 const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
dkato 0:853f5b7408a7 1076 vdc5_width_read_fb_t * w_read_fb;
dkato 0:853f5b7408a7 1077 vdc5_onoff_t graphics_enlargement;
dkato 0:853f5b7408a7 1078 vdc5_color_space_t color_space;
dkato 0:853f5b7408a7 1079 vdc5_resource_state_t rsrc_state;
dkato 0:853f5b7408a7 1080 uint32_t reg_data;
dkato 0:853f5b7408a7 1081
dkato 0:853f5b7408a7 1082 w_read_fb = VDC5_ShrdPrmGetFrBuffWidth_Rd(ch, graphics_id);
dkato 0:853f5b7408a7 1083
dkato 0:853f5b7408a7 1084 graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, param->gr_flm_sel, w_read_fb, &param->gr_grc);
dkato 0:853f5b7408a7 1085
dkato 0:853f5b7408a7 1086 if ((graphics_id == VDC5_GR_TYPE_GR0) ||
dkato 0:853f5b7408a7 1087 (graphics_id == VDC5_GR_TYPE_GR1) ||
dkato 0:853f5b7408a7 1088 (graphics_id == VDC5_GR_TYPE_OIR)) {
dkato 0:853f5b7408a7 1089 SetScalerGraphics(ch, graphics_id, w_read_fb, &param->gr_grc, param->gr_flm_sel, graphics_enlargement);
dkato 0:853f5b7408a7 1090 }
dkato 0:853f5b7408a7 1091
dkato 0:853f5b7408a7 1092 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 1093
dkato 0:853f5b7408a7 1094 *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_MASK_0X00010301;
dkato 0:853f5b7408a7 1095 /* Line offset address direction of the frame buffer */
dkato 0:853f5b7408a7 1096 if (param->gr_ln_off_dir != VDC5_GR_LN_OFF_DIR_INC) {
dkato 0:853f5b7408a7 1097 *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 1098 }
dkato 0:853f5b7408a7 1099 /* Frame buffer address setting signal */
dkato 0:853f5b7408a7 1100 *(img_synthesizer->gr_flm1) |= (uint32_t)param->gr_flm_sel << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 1101 /* Frame buffer burst transfer mode */
dkato 0:853f5b7408a7 1102 if (param->gr_bst_md != VDC5_BST_MD_32BYTE) {
dkato 0:853f5b7408a7 1103 *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1104 }
dkato 0:853f5b7408a7 1105 /* Sets the frame buffer number for distortion correction */
dkato 0:853f5b7408a7 1106 if (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION) {
dkato 0:853f5b7408a7 1107 if (param->gr_imr_flm_inv == VDC5_OFF) {
dkato 0:853f5b7408a7 1108 *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1109 } else {
dkato 0:853f5b7408a7 1110 *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1111 }
dkato 0:853f5b7408a7 1112 }
dkato 0:853f5b7408a7 1113
dkato 0:853f5b7408a7 1114 /* Frame buffer base address */
dkato 0:853f5b7408a7 1115 *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
dkato 0:853f5b7408a7 1116
dkato 0:853f5b7408a7 1117 /* Frame buffer line offset address[byte] */
dkato 0:853f5b7408a7 1118 *(img_synthesizer->gr_flm3) &= (uint32_t)~VDC5_REG_MASK_0X7FFF03FF;
dkato 0:853f5b7408a7 1119 *(img_synthesizer->gr_flm3) |= param->gr_ln_off << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1120
dkato 0:853f5b7408a7 1121 /* The number of lines when reading the addresses repeatedly */
dkato 0:853f5b7408a7 1122 *(img_synthesizer->gr_flm5) = (uint32_t)VDC5_REG_MASK_0X000007FF;
dkato 0:853f5b7408a7 1123 /* Number of lines in a frame */
dkato 0:853f5b7408a7 1124 *(img_synthesizer->gr_flm5) |= ((uint32_t)w_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1125
dkato 0:853f5b7408a7 1126 *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0XF7FF1C3F;
dkato 0:853f5b7408a7 1127 /* Format of the frame buffer read signal */
dkato 0:853f5b7408a7 1128 *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_format << VDC5_REG_SHIFT_28;
dkato 0:853f5b7408a7 1129 /* Width of the horizontal valid period */
dkato 0:853f5b7408a7 1130 *(img_synthesizer->gr_flm6) |= ((uint32_t)w_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1131 /* Swap setting in frame buffer reading */
dkato 0:853f5b7408a7 1132 *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_rdswa << VDC5_REG_SHIFT_10;
dkato 0:853f5b7408a7 1133
dkato 0:853f5b7408a7 1134 if ((param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM)) {
dkato 0:853f5b7408a7 1135 /* Sets the amount of data to be skipped through */
dkato 0:853f5b7408a7 1136 *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, param->gr_format);
dkato 0:853f5b7408a7 1137 }
dkato 0:853f5b7408a7 1138
dkato 0:853f5b7408a7 1139 /* Graphics display mode */
dkato 0:853f5b7408a7 1140 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 1141 if ((graphics_id == VDC5_GR_TYPE_GR0) ||
dkato 0:853f5b7408a7 1142 (graphics_id == VDC5_GR_TYPE_OIR)) {
dkato 0:853f5b7408a7 1143 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
dkato 0:853f5b7408a7 1144 } else {
dkato 0:853f5b7408a7 1145 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
dkato 0:853f5b7408a7 1146 }
dkato 0:853f5b7408a7 1147
dkato 0:853f5b7408a7 1148 /* Graphics display area */
dkato 0:853f5b7408a7 1149 *(img_synthesizer->gr_ab2) = (uint32_t)param->gr_grc.vs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1150 *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc.vw;
dkato 0:853f5b7408a7 1151 *(img_synthesizer->gr_ab3) = (uint32_t)param->gr_grc.hs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1152 *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc.hw;
dkato 0:853f5b7408a7 1153
dkato 0:853f5b7408a7 1154 /* Initialize alpha blending in a rectangular area */
dkato 0:853f5b7408a7 1155 if ((graphics_id == VDC5_GR_TYPE_GR1) ||
dkato 0:853f5b7408a7 1156 (graphics_id == VDC5_GR_TYPE_GR2) ||
dkato 0:853f5b7408a7 1157 (graphics_id == VDC5_GR_TYPE_GR3)) {
dkato 0:853f5b7408a7 1158 /* Turns off alpha blending in a rectangular area */
dkato 0:853f5b7408a7 1159 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X0000D000;
dkato 0:853f5b7408a7 1160 /* The valid image area for alpha blending in a rectangular area */
dkato 0:853f5b7408a7 1161 reg_data = *(img_synthesizer->gr_ab2);
dkato 0:853f5b7408a7 1162 *(img_synthesizer->gr_ab4) = reg_data;
dkato 0:853f5b7408a7 1163 reg_data = *(img_synthesizer->gr_ab3);
dkato 0:853f5b7408a7 1164 *(img_synthesizer->gr_ab5) = reg_data;
dkato 0:853f5b7408a7 1165 /* Disable fade-in and fade-out */
dkato 0:853f5b7408a7 1166 *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
dkato 0:853f5b7408a7 1167 /* Set the initial alpha value to '255' */
dkato 0:853f5b7408a7 1168 *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
dkato 0:853f5b7408a7 1169 }
dkato 0:853f5b7408a7 1170 /* Turns off chroma-key processing */
dkato 0:853f5b7408a7 1171 *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1172
dkato 0:853f5b7408a7 1173 if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
dkato 0:853f5b7408a7 1174 /* Alpha value is set to 255. */
dkato 0:853f5b7408a7 1175 *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
dkato 0:853f5b7408a7 1176 *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
dkato 0:853f5b7408a7 1177 }
dkato 0:853f5b7408a7 1178 if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
dkato 0:853f5b7408a7 1179 /* Swapping of data read from buffer in the YCbCr422 format */
dkato 0:853f5b7408a7 1180 *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000E000;
dkato 0:853f5b7408a7 1181 if (param->gr_format == VDC5_GR_FORMAT_YCBCR422) {
dkato 0:853f5b7408a7 1182 *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_ycc_swap << VDC5_REG_SHIFT_13;
dkato 0:853f5b7408a7 1183 /* The interpolation mode for YCC422 to YCbCr444 conversion is fixed to average interpolation */
dkato 0:853f5b7408a7 1184 *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1185 } else {
dkato 0:853f5b7408a7 1186 /* If the format of the frame buffer read signal is not YCbCr422,
dkato 0:853f5b7408a7 1187 initialize the swapping of data read from buffer in the YCbCr422 format. */
dkato 0:853f5b7408a7 1188 *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_GR_YCCSWAP_CBY0CRY1 << VDC5_REG_SHIFT_13;
dkato 0:853f5b7408a7 1189 }
dkato 0:853f5b7408a7 1190
dkato 0:853f5b7408a7 1191 SetupGraphicsVIN(ch, graphics_id, param->gr_flm_sel, graphics_enlargement);
dkato 0:853f5b7408a7 1192
dkato 0:853f5b7408a7 1193 color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
dkato 0:853f5b7408a7 1194
dkato 0:853f5b7408a7 1195 SetScalerBackgroundColor(ch, graphics_id, color_space);
dkato 0:853f5b7408a7 1196 SetImgQaImproverColorMtx(ch, graphics_id, color_space);
dkato 0:853f5b7408a7 1197
dkato 0:853f5b7408a7 1198 if (graphics_id == VDC5_GR_TYPE_GR0) {
dkato 0:853f5b7408a7 1199 img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][VDC5_IMG_IMPRV_0];
dkato 0:853f5b7408a7 1200 } else {
dkato 0:853f5b7408a7 1201 img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][VDC5_IMG_IMPRV_1];
dkato 0:853f5b7408a7 1202 }
dkato 0:853f5b7408a7 1203 /* Operating mode */
dkato 0:853f5b7408a7 1204 if (color_space == VDC5_COLOR_SPACE_GBR) {
dkato 0:853f5b7408a7 1205 *(img_qlty_imp->adj_enh_tim1) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1206 } else {
dkato 0:853f5b7408a7 1207 *(img_qlty_imp->adj_enh_tim1) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1208 }
dkato 0:853f5b7408a7 1209 /* Register update control register (ADJx_UPDATE)
dkato 0:853f5b7408a7 1210 b0 ADJx_VEN */
dkato 0:853f5b7408a7 1211 *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1212 }
dkato 0:853f5b7408a7 1213
dkato 0:853f5b7408a7 1214 rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_RD);
dkato 0:853f5b7408a7 1215 if ((graphics_id == VDC5_GR_TYPE_GR0) && (rsrc_state == VDC5_RESOURCE_ST_INVALID)) {
dkato 0:853f5b7408a7 1216 /* Graphics 0 is specified when graphics 1 is not used. */
dkato 0:853f5b7408a7 1217 SetImgQaImproverColorMtx(ch, VDC5_GR_TYPE_GR1, VDC5_COLOR_SPACE_GBR);
dkato 0:853f5b7408a7 1218 }
dkato 0:853f5b7408a7 1219 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 1220 b8 GRx_UPDATE
dkato 0:853f5b7408a7 1221 b4 GRx_P_VEN
dkato 0:853f5b7408a7 1222 b0 GRx_IBUS_VEN */
dkato 0:853f5b7408a7 1223 *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 1224
dkato 0:853f5b7408a7 1225 } /* End of function VDC5_ReadDataControl() */
dkato 0:853f5b7408a7 1226
dkato 0:853f5b7408a7 1227 /**************************************************************************//**
dkato 0:853f5b7408a7 1228 * @brief Sets registers for data read change processing
dkato 0:853f5b7408a7 1229 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1230 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 1231 * @param[in] param : Data read change parameter
dkato 0:853f5b7408a7 1232 * @retval None
dkato 0:853f5b7408a7 1233 ******************************************************************************/
dkato 0:853f5b7408a7 1234 void VDC5_ChangeReadProcess (
dkato 0:853f5b7408a7 1235 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1236 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 1237 const vdc5_read_chg_t * const param)
dkato 0:853f5b7408a7 1238 {
dkato 0:853f5b7408a7 1239 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 1240 vdc5_gr_flm_sel_t gr_flm_sel_tmp;
dkato 0:853f5b7408a7 1241 vdc5_period_rect_t * gr_grc_tmp;
dkato 0:853f5b7408a7 1242 vdc5_width_read_fb_t * w_read_fb;
dkato 0:853f5b7408a7 1243 vdc5_onoff_t graphics_enlargement;
dkato 0:853f5b7408a7 1244 vdc5_gr_format_t gr_format_tmp;
dkato 0:853f5b7408a7 1245
dkato 0:853f5b7408a7 1246 gr_flm_sel_tmp = VDC5_ShrdPrmGetSelFbAddrSig(ch, graphics_id);
dkato 0:853f5b7408a7 1247 gr_grc_tmp = VDC5_ShrdPrmGetDisplayArea(ch, graphics_id);
dkato 0:853f5b7408a7 1248 w_read_fb = VDC5_ShrdPrmGetFrBuffWidth_Rd(ch, graphics_id);
dkato 0:853f5b7408a7 1249
dkato 0:853f5b7408a7 1250 graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, gr_flm_sel_tmp, w_read_fb, gr_grc_tmp);
dkato 0:853f5b7408a7 1251
dkato 0:853f5b7408a7 1252 if ((graphics_id == VDC5_GR_TYPE_GR0) ||
dkato 0:853f5b7408a7 1253 (graphics_id == VDC5_GR_TYPE_GR1) ||
dkato 0:853f5b7408a7 1254 (graphics_id == VDC5_GR_TYPE_OIR)) {
dkato 0:853f5b7408a7 1255 SetScalerGraphics(ch, graphics_id, w_read_fb, gr_grc_tmp, gr_flm_sel_tmp, graphics_enlargement);
dkato 0:853f5b7408a7 1256 }
dkato 0:853f5b7408a7 1257
dkato 0:853f5b7408a7 1258 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 1259
dkato 0:853f5b7408a7 1260 /* Frame buffer base address */
dkato 0:853f5b7408a7 1261 if (param->gr_base != NULL) {
dkato 0:853f5b7408a7 1262 *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
dkato 0:853f5b7408a7 1263
dkato 0:853f5b7408a7 1264 if ((gr_flm_sel_tmp == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel_tmp == VDC5_GR_FLM_SEL_FLM_NUM)) {
dkato 0:853f5b7408a7 1265 gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
dkato 0:853f5b7408a7 1266 /* Sets the amount of data to be skipped through */
dkato 0:853f5b7408a7 1267 *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
dkato 0:853f5b7408a7 1268 *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, gr_format_tmp);
dkato 0:853f5b7408a7 1269 }
dkato 0:853f5b7408a7 1270 }
dkato 0:853f5b7408a7 1271
dkato 0:853f5b7408a7 1272 /* Size of the frame buffer to be read */
dkato 0:853f5b7408a7 1273 if (param->width_read_fb != NULL) {
dkato 0:853f5b7408a7 1274 /* Number of lines in a frame */
dkato 0:853f5b7408a7 1275 *(img_synthesizer->gr_flm5) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
dkato 0:853f5b7408a7 1276 *(img_synthesizer->gr_flm5) |= ((uint32_t)param->width_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1277 /* Width of the horizontal valid period */
dkato 0:853f5b7408a7 1278 *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
dkato 0:853f5b7408a7 1279 *(img_synthesizer->gr_flm6) |= ((uint32_t)param->width_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1280 }
dkato 0:853f5b7408a7 1281
dkato 0:853f5b7408a7 1282 /* Graphics display mode */
dkato 0:853f5b7408a7 1283 if (param->gr_disp_sel != NULL) {
dkato 0:853f5b7408a7 1284 if (*(param->gr_disp_sel) != VDC5_DISPSEL_IGNORED) {
dkato 0:853f5b7408a7 1285 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 1286 *(img_synthesizer->gr_ab1) |= (uint32_t)*(param->gr_disp_sel);
dkato 0:853f5b7408a7 1287 }
dkato 0:853f5b7408a7 1288 }
dkato 0:853f5b7408a7 1289
dkato 0:853f5b7408a7 1290 /* Graphics display area */
dkato 0:853f5b7408a7 1291 if (param->gr_grc != NULL) {
dkato 0:853f5b7408a7 1292 *(img_synthesizer->gr_ab2) = (uint32_t)param->gr_grc->vs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1293 *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc->vw;
dkato 0:853f5b7408a7 1294 *(img_synthesizer->gr_ab3) = (uint32_t)param->gr_grc->hs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1295 *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc->hw;
dkato 0:853f5b7408a7 1296 }
dkato 0:853f5b7408a7 1297
dkato 0:853f5b7408a7 1298 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 1299 b4 GRx_P_VEN
dkato 0:853f5b7408a7 1300 b0 GRx_IBUS_VEN */
dkato 0:853f5b7408a7 1301 *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 1302
dkato 0:853f5b7408a7 1303 if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
dkato 0:853f5b7408a7 1304 ChangeGraphicsVIN(ch, graphics_id, gr_flm_sel_tmp, graphics_enlargement);
dkato 0:853f5b7408a7 1305 }
dkato 0:853f5b7408a7 1306 } /* End of function VDC5_ChangeReadProcess() */
dkato 0:853f5b7408a7 1307
dkato 0:853f5b7408a7 1308 /**************************************************************************//**
dkato 0:853f5b7408a7 1309 * @brief Sets registers for data write/read start processing
dkato 0:853f5b7408a7 1310 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1311 * @param[in] layer_id : Layer ID
dkato 0:853f5b7408a7 1312 * @param[in] param : Data write/read start parameter
dkato 0:853f5b7408a7 1313 * @retval None
dkato 0:853f5b7408a7 1314 ******************************************************************************/
dkato 0:853f5b7408a7 1315 void VDC5_StartProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t * const param)
dkato 0:853f5b7408a7 1316 {
dkato 0:853f5b7408a7 1317 uint32_t layer_id_num;
dkato 0:853f5b7408a7 1318 vdc5_resource_state_t resource_state;
dkato 0:853f5b7408a7 1319 vdc5_resource_state_t oir_resrc_st_before;
dkato 0:853f5b7408a7 1320 vdc5_resource_state_t oir_resrc_st_after;
dkato 0:853f5b7408a7 1321 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 1322
dkato 0:853f5b7408a7 1323 if (param->gr_disp_sel != NULL) {
dkato 0:853f5b7408a7 1324 /* Set graphics display mode */
dkato 0:853f5b7408a7 1325 SetGraphicsDisplayMode(ch, layer_id, param->gr_disp_sel);
dkato 0:853f5b7408a7 1326 }
dkato 0:853f5b7408a7 1327
dkato 0:853f5b7408a7 1328 oir_resrc_st_before = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
dkato 0:853f5b7408a7 1329
dkato 0:853f5b7408a7 1330 if (layer_id != VDC5_LAYER_ID_ALL) {
dkato 0:853f5b7408a7 1331 rw_proc_function_tbl[layer_id](ch, VDC5_ON);
dkato 0:853f5b7408a7 1332 } else {
dkato 0:853f5b7408a7 1333 for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
dkato 0:853f5b7408a7 1334 resource_state = VDC5_ShrdPrmGetRwProcReady(ch, (vdc5_layer_id_t)layer_id_num);
dkato 0:853f5b7408a7 1335 if (resource_state != VDC5_RESOURCE_ST_INVALID) {
dkato 0:853f5b7408a7 1336 rw_proc_function_tbl[layer_id_num](ch, VDC5_ON);
dkato 0:853f5b7408a7 1337 }
dkato 0:853f5b7408a7 1338 }
dkato 0:853f5b7408a7 1339 }
dkato 0:853f5b7408a7 1340 SetRegUpdateRwEnable(ch, layer_id);
dkato 0:853f5b7408a7 1341
dkato 0:853f5b7408a7 1342 oir_resrc_st_after = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
dkato 0:853f5b7408a7 1343
dkato 0:853f5b7408a7 1344 /* OIR */
dkato 0:853f5b7408a7 1345 if ((oir_resrc_st_before == VDC5_RESOURCE_ST_INVALID) &&
dkato 0:853f5b7408a7 1346 (oir_resrc_st_after != VDC5_RESOURCE_ST_INVALID)) {
dkato 0:853f5b7408a7 1347 scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
dkato 0:853f5b7408a7 1348 *(scaler->scl0_frc3) |= (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 1349 /* Register update control register (OIR_SCL0_UPDATE)
dkato 0:853f5b7408a7 1350 b8 SCL0_UPDATE */
dkato 0:853f5b7408a7 1351 *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1352 }
dkato 0:853f5b7408a7 1353 } /* End of function VDC5_StartProcess() */
dkato 0:853f5b7408a7 1354
dkato 0:853f5b7408a7 1355 /**************************************************************************//**
dkato 0:853f5b7408a7 1356 * @brief Sets registers for data write/read stop processing
dkato 0:853f5b7408a7 1357 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1358 * @param[in] layer_id : Layer ID
dkato 0:853f5b7408a7 1359 * @retval None
dkato 0:853f5b7408a7 1360 ******************************************************************************/
dkato 0:853f5b7408a7 1361 void VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
dkato 0:853f5b7408a7 1362 {
dkato 0:853f5b7408a7 1363 uint32_t layer_id_num;
dkato 0:853f5b7408a7 1364 vdc5_resource_state_t resource_state;
dkato 0:853f5b7408a7 1365 vdc5_resource_state_t oir_resrc_st_before;
dkato 0:853f5b7408a7 1366 vdc5_resource_state_t oir_resrc_st_after;
dkato 0:853f5b7408a7 1367 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 1368
dkato 0:853f5b7408a7 1369 oir_resrc_st_before = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
dkato 0:853f5b7408a7 1370
dkato 0:853f5b7408a7 1371 if (layer_id != VDC5_LAYER_ID_ALL) {
dkato 0:853f5b7408a7 1372 rw_proc_function_tbl[layer_id](ch, VDC5_OFF);
dkato 0:853f5b7408a7 1373 } else {
dkato 0:853f5b7408a7 1374 for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
dkato 0:853f5b7408a7 1375 resource_state = VDC5_ShrdPrmGetRwProcEnabled(ch, (vdc5_layer_id_t)layer_id_num);
dkato 0:853f5b7408a7 1376 if (resource_state != VDC5_RESOURCE_ST_INVALID) {
dkato 0:853f5b7408a7 1377 rw_proc_function_tbl[layer_id_num](ch, VDC5_OFF);
dkato 0:853f5b7408a7 1378 }
dkato 0:853f5b7408a7 1379 }
dkato 0:853f5b7408a7 1380 }
dkato 0:853f5b7408a7 1381 SetRegUpdateRwEnable(ch, layer_id);
dkato 0:853f5b7408a7 1382
dkato 0:853f5b7408a7 1383 oir_resrc_st_after = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
dkato 0:853f5b7408a7 1384
dkato 0:853f5b7408a7 1385 /* OIR */
dkato 0:853f5b7408a7 1386 if ((oir_resrc_st_before != VDC5_RESOURCE_ST_INVALID) &&
dkato 0:853f5b7408a7 1387 (oir_resrc_st_after == VDC5_RESOURCE_ST_INVALID)) {
dkato 0:853f5b7408a7 1388 scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
dkato 0:853f5b7408a7 1389 *(scaler->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT16;
dkato 0:853f5b7408a7 1390 /* Register update control register (OIR_SCL0_UPDATE)
dkato 0:853f5b7408a7 1391 b8 SCL0_UPDATE */
dkato 0:853f5b7408a7 1392 *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1393 }
dkato 0:853f5b7408a7 1394 } /* End of function VDC5_StopProcess() */
dkato 0:853f5b7408a7 1395
dkato 0:853f5b7408a7 1396 /**************************************************************************//**
dkato 0:853f5b7408a7 1397 * @brief Sets registers for data write/read control release processing
dkato 0:853f5b7408a7 1398 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1399 * @param[in] layer_id : Layer ID
dkato 0:853f5b7408a7 1400 * @retval None
dkato 0:853f5b7408a7 1401 ******************************************************************************/
dkato 0:853f5b7408a7 1402 void VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
dkato 0:853f5b7408a7 1403 {
dkato 0:853f5b7408a7 1404 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 1405 vdc5_resource_state_t resource_state;
dkato 0:853f5b7408a7 1406 const vdc5_regaddr_img_synthesizer_t * img_synthesizer_vin;
dkato 0:853f5b7408a7 1407
dkato 0:853f5b7408a7 1408 resource_state = VDC5_ShrdPrmGetRwProcReady(ch, VDC5_LAYER_ID_1_RD);
dkato 0:853f5b7408a7 1409 if ((layer_id == VDC5_LAYER_ID_1_RD) ||
dkato 0:853f5b7408a7 1410 ((layer_id == VDC5_LAYER_ID_ALL) && (resource_state!= VDC5_RESOURCE_ST_INVALID))) {
dkato 0:853f5b7408a7 1411 SetInitialConnection(ch);
dkato 0:853f5b7408a7 1412
dkato 0:853f5b7408a7 1413 /* Use Vsync and enable signal output from scaler 0 */
dkato 0:853f5b7408a7 1414 scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
dkato 0:853f5b7408a7 1415 *(scaler->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1416 /* Register update control register (SC0_SCL0_UPDATE)
dkato 0:853f5b7408a7 1417 b8 SCL0_UPDATE */
dkato 0:853f5b7408a7 1418 *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1419
dkato 0:853f5b7408a7 1420 scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
dkato 0:853f5b7408a7 1421 *(scaler->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1422 /* Register update control register (SC1_SCL0_UPDATE)
dkato 0:853f5b7408a7 1423 b8 SCL0_UPDATE */
dkato 0:853f5b7408a7 1424 *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1425
dkato 0:853f5b7408a7 1426 /* Initialize the color matrix in the image quality improver (scaler 1 output) */
dkato 0:853f5b7408a7 1427 SetImgQaImproverColorMtx(ch, VDC5_GR_TYPE_GR1, VDC5_COLOR_SPACE_GBR);
dkato 0:853f5b7408a7 1428 }
dkato 0:853f5b7408a7 1429
dkato 0:853f5b7408a7 1430 resource_state = VDC5_ShrdPrmGetRwProcReady(ch, VDC5_LAYER_ID_0_RD);
dkato 0:853f5b7408a7 1431 if ((layer_id == VDC5_LAYER_ID_0_RD) ||
dkato 0:853f5b7408a7 1432 ((layer_id == VDC5_LAYER_ID_ALL) && (resource_state!= VDC5_RESOURCE_ST_INVALID))) {
dkato 0:853f5b7408a7 1433 img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
dkato 0:853f5b7408a7 1434
dkato 0:853f5b7408a7 1435 /* Turns off alpha blending in a rectangular area */
dkato 0:853f5b7408a7 1436 *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
dkato 0:853f5b7408a7 1437 /* Selection of lower-layer plane in scaler, graphics 1 is used as lower-layer graphics. */
dkato 0:853f5b7408a7 1438 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
dkato 0:853f5b7408a7 1439 /* Graphics display mode in VIN */
dkato 0:853f5b7408a7 1440 *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 1441 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
dkato 0:853f5b7408a7 1442 /* Disable fade-in and fade-out */
dkato 0:853f5b7408a7 1443 *(img_synthesizer_vin->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
dkato 0:853f5b7408a7 1444 /* Set the initial alpha value to '255' */
dkato 0:853f5b7408a7 1445 *(img_synthesizer_vin->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
dkato 0:853f5b7408a7 1446
dkato 0:853f5b7408a7 1447 /* Graphics register update control register (GR_VIN_UPDATE)
dkato 0:853f5b7408a7 1448 b8 GR_VIN_UPDATE
dkato 0:853f5b7408a7 1449 b4 GR_VIN_P_VEN */
dkato 0:853f5b7408a7 1450 *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
dkato 0:853f5b7408a7 1451 }
dkato 0:853f5b7408a7 1452 } /* End of function VDC5_ReleaseDataControl() */
dkato 0:853f5b7408a7 1453
dkato 0:853f5b7408a7 1454 /**************************************************************************//**
dkato 0:853f5b7408a7 1455 * @brief Sets registers for noise reduction
dkato 0:853f5b7408a7 1456 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1457 * @param[in] nr1d_on : Noise reduction ON/OFF setting
dkato 0:853f5b7408a7 1458 * @param[in] param : Noise reduction setup parameter
dkato 0:853f5b7408a7 1459 * @retval None
dkato 0:853f5b7408a7 1460 ******************************************************************************/
dkato 0:853f5b7408a7 1461 void VDC5_VideoNoiseReduction (
dkato 0:853f5b7408a7 1462 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1463 const vdc5_onoff_t nr1d_on,
dkato 0:853f5b7408a7 1464 const vdc5_noise_reduction_t * const param)
dkato 0:853f5b7408a7 1465 {
dkato 0:853f5b7408a7 1466 const vdc5_regaddr_input_ctrl_t * input_ctrl;
dkato 0:853f5b7408a7 1467 const vdc5_nr_param_t * nr_param;
dkato 0:853f5b7408a7 1468
dkato 0:853f5b7408a7 1469 input_ctrl = &vdc5_regaddr_input_ctrl[ch];
dkato 0:853f5b7408a7 1470
dkato 0:853f5b7408a7 1471 if (param != NULL) {
dkato 0:853f5b7408a7 1472 /* Y/G signal noise reduction parameter */
dkato 0:853f5b7408a7 1473 nr_param = &param->y;
dkato 0:853f5b7408a7 1474 *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_MASK_0X00007F33;
dkato 0:853f5b7408a7 1475 /* Maximum value of coring (absolute value) */
dkato 0:853f5b7408a7 1476 *(input_ctrl->imgcnt_nr_cnt0) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 1477 /* TAP select */
dkato 0:853f5b7408a7 1478 *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
dkato 0:853f5b7408a7 1479 /* Noise reduction gain adjustment */
dkato 0:853f5b7408a7 1480 *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_gain;
dkato 0:853f5b7408a7 1481
dkato 0:853f5b7408a7 1482 /* Cb/B signal noise reduction parameter */
dkato 0:853f5b7408a7 1483 nr_param = &param->cb;
dkato 0:853f5b7408a7 1484 /* Maximum value of coring (absolute value) */
dkato 0:853f5b7408a7 1485 *(input_ctrl->imgcnt_nr_cnt1) = nr_param->nr1d_th << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 1486 /* TAP select */
dkato 0:853f5b7408a7 1487 *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_20;
dkato 0:853f5b7408a7 1488 /* Noise reduction gain adjustment */
dkato 0:853f5b7408a7 1489 *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1490
dkato 0:853f5b7408a7 1491 /* Cr/R signal noise reduction parameter */
dkato 0:853f5b7408a7 1492 nr_param = &param->cr;
dkato 0:853f5b7408a7 1493 /* Maximum value of coring (absolute value) */
dkato 0:853f5b7408a7 1494 *(input_ctrl->imgcnt_nr_cnt1) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 1495 /* TAP select */
dkato 0:853f5b7408a7 1496 *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
dkato 0:853f5b7408a7 1497 /* Noise reduction gain adjustment */
dkato 0:853f5b7408a7 1498 *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain;
dkato 0:853f5b7408a7 1499 }
dkato 0:853f5b7408a7 1500
dkato 0:853f5b7408a7 1501 if (nr1d_on == VDC5_OFF) {
dkato 0:853f5b7408a7 1502 *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT16;
dkato 0:853f5b7408a7 1503 } else {
dkato 0:853f5b7408a7 1504 *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 1505 }
dkato 0:853f5b7408a7 1506
dkato 0:853f5b7408a7 1507 /* Register update control register (IMGCNT_UPDATE)
dkato 0:853f5b7408a7 1508 b0 IMGCNT_VEN */
dkato 0:853f5b7408a7 1509 *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1510
dkato 0:853f5b7408a7 1511 } /* End of function VDC5_VideoNoiseReduction() */
dkato 0:853f5b7408a7 1512
dkato 0:853f5b7408a7 1513 /**************************************************************************//**
dkato 0:853f5b7408a7 1514 * @brief Sets registers for color matrix
dkato 0:853f5b7408a7 1515 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1516 * @param[in] param : Color matrix setup parameter
dkato 0:853f5b7408a7 1517 * @retval None
dkato 0:853f5b7408a7 1518 ******************************************************************************/
dkato 0:853f5b7408a7 1519 void VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
dkato 0:853f5b7408a7 1520 {
dkato 0:853f5b7408a7 1521 SetColorMatrix(param->mtx_mode, param->offset, param->gain, &vdc5_regaddr_color_matrix[ch][param->module]);
dkato 0:853f5b7408a7 1522 } /* End of function VDC5_ImageColorMatrix() */
dkato 0:853f5b7408a7 1523
dkato 0:853f5b7408a7 1524 /**************************************************************************//**
dkato 0:853f5b7408a7 1525 * @brief Sets registers for image enhancement processing
dkato 0:853f5b7408a7 1526 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1527 * @param[in] imgimprv_id : Image quality improver ID
dkato 0:853f5b7408a7 1528 * @param[in] shp_h_on : Sharpness ON/OFF setting
dkato 0:853f5b7408a7 1529 * @param[in] sharp_param : Sharpness setup parameter
dkato 0:853f5b7408a7 1530 * @param[in] lti_h_on : LTI ON/OFF setting
dkato 0:853f5b7408a7 1531 * @param[in] lti_param : LTI setup parameter
dkato 0:853f5b7408a7 1532 * @param[in] enh_area : Enhancer-enabled area setup parameter
dkato 0:853f5b7408a7 1533 * @retval None
dkato 0:853f5b7408a7 1534 ******************************************************************************/
dkato 0:853f5b7408a7 1535 void VDC5_ImageEnhancement (
dkato 0:853f5b7408a7 1536 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1537 const vdc5_imgimprv_id_t imgimprv_id,
dkato 0:853f5b7408a7 1538 const vdc5_onoff_t shp_h_on,
dkato 0:853f5b7408a7 1539 const vdc5_enhance_sharp_t * const sharp_param,
dkato 0:853f5b7408a7 1540 const vdc5_onoff_t lti_h_on,
dkato 0:853f5b7408a7 1541 const vdc5_enhance_lti_t * const lti_param,
dkato 0:853f5b7408a7 1542 const vdc5_period_rect_t * const enh_area)
dkato 0:853f5b7408a7 1543 {
dkato 0:853f5b7408a7 1544 const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
dkato 0:853f5b7408a7 1545
dkato 0:853f5b7408a7 1546 img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][imgimprv_id];
dkato 0:853f5b7408a7 1547
dkato 0:853f5b7408a7 1548 /* Sharpness */
dkato 0:853f5b7408a7 1549 SetImageEnhancementSharpness(shp_h_on, sharp_param, img_qlty_imp);
dkato 0:853f5b7408a7 1550
dkato 0:853f5b7408a7 1551 /* LTI */
dkato 0:853f5b7408a7 1552 SetImageEnhancementLti(lti_h_on, lti_param, img_qlty_imp);
dkato 0:853f5b7408a7 1553
dkato 0:853f5b7408a7 1554 /* Enhancer area */
dkato 0:853f5b7408a7 1555 if (enh_area != NULL) {
dkato 0:853f5b7408a7 1556 *(img_qlty_imp->adj_enh_tim2) = (uint32_t)enh_area->vs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1557 *(img_qlty_imp->adj_enh_tim2) |= (uint32_t)enh_area->vw;
dkato 0:853f5b7408a7 1558 *(img_qlty_imp->adj_enh_tim3) = (uint32_t)enh_area->hs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1559 *(img_qlty_imp->adj_enh_tim3) |= (uint32_t)enh_area->hw;
dkato 0:853f5b7408a7 1560 }
dkato 0:853f5b7408a7 1561
dkato 0:853f5b7408a7 1562 /* Register update control register (ADJx_UPDATE)
dkato 0:853f5b7408a7 1563 b0 ADJx_VEN */
dkato 0:853f5b7408a7 1564 *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1565
dkato 0:853f5b7408a7 1566 } /* End of function VDC5_ImageEnhancement() */
dkato 0:853f5b7408a7 1567
dkato 0:853f5b7408a7 1568 /**************************************************************************//**
dkato 0:853f5b7408a7 1569 * @brief Sets registers for black stretch
dkato 0:853f5b7408a7 1570 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1571 * @param[in] imgimprv_id : Image quality improver ID
dkato 0:853f5b7408a7 1572 * @param[in] bkstr_on : Black stretch ON/OFF setting
dkato 0:853f5b7408a7 1573 * @param[in] param : Black stretch setup parameter
dkato 0:853f5b7408a7 1574 * @retval None
dkato 0:853f5b7408a7 1575 ******************************************************************************/
dkato 0:853f5b7408a7 1576 void VDC5_ImageBlackStretch (
dkato 0:853f5b7408a7 1577 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1578 const vdc5_imgimprv_id_t imgimprv_id,
dkato 0:853f5b7408a7 1579 const vdc5_onoff_t bkstr_on,
dkato 0:853f5b7408a7 1580 const vdc5_black_t * const param)
dkato 0:853f5b7408a7 1581 {
dkato 0:853f5b7408a7 1582 const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
dkato 0:853f5b7408a7 1583
dkato 0:853f5b7408a7 1584 img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][imgimprv_id];
dkato 0:853f5b7408a7 1585
dkato 0:853f5b7408a7 1586 if (param != NULL) {
dkato 0:853f5b7408a7 1587 /* Black stretch start point */
dkato 0:853f5b7408a7 1588 *(img_qlty_imp->adj_bkstr_set) = (uint32_t)((uint32_t)param->bkstr_st << VDC5_REG_SHIFT_20);
dkato 0:853f5b7408a7 1589 /* Black stretch depth */
dkato 0:853f5b7408a7 1590 *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_d << VDC5_REG_SHIFT_16);
dkato 0:853f5b7408a7 1591 /* Black stretch time constant (T1) */
dkato 0:853f5b7408a7 1592 *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_t1 << VDC5_REG_SHIFT_8);
dkato 0:853f5b7408a7 1593 /* Black stretch time constant (T2) */
dkato 0:853f5b7408a7 1594 *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)param->bkstr_t2;
dkato 0:853f5b7408a7 1595 }
dkato 0:853f5b7408a7 1596
dkato 0:853f5b7408a7 1597 if (bkstr_on == VDC5_OFF) {
dkato 0:853f5b7408a7 1598 *(img_qlty_imp->adj_bkstr_set) &= (uint32_t)~VDC5_REG_BIT24;
dkato 0:853f5b7408a7 1599 } else {
dkato 0:853f5b7408a7 1600 *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)VDC5_REG_BIT24;
dkato 0:853f5b7408a7 1601 }
dkato 0:853f5b7408a7 1602
dkato 0:853f5b7408a7 1603 /* Register update control register (ADJx_UPDATE)
dkato 0:853f5b7408a7 1604 b0 ADJx_VEN */
dkato 0:853f5b7408a7 1605 *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1606
dkato 0:853f5b7408a7 1607 } /* End of function VDC5_ImageBlackStretch() */
dkato 0:853f5b7408a7 1608
dkato 0:853f5b7408a7 1609 /**************************************************************************//**
dkato 0:853f5b7408a7 1610 * @brief Sets registers for alpha blending
dkato 0:853f5b7408a7 1611 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1612 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 1613 * @param[in] param : Alpha blending setup parameter
dkato 0:853f5b7408a7 1614 * @retval None
dkato 0:853f5b7408a7 1615 ******************************************************************************/
dkato 0:853f5b7408a7 1616 void VDC5_AlphaBlending (
dkato 0:853f5b7408a7 1617 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1618 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 1619 const vdc5_alpha_blending_t * const param)
dkato 0:853f5b7408a7 1620 {
dkato 0:853f5b7408a7 1621 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 1622
dkato 0:853f5b7408a7 1623 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 1624
dkato 0:853f5b7408a7 1625 /* Alpha signal of the ARGB1555/ARGB5551 format */
dkato 0:853f5b7408a7 1626 if (param->alpha_1bit != NULL) {
dkato 0:853f5b7408a7 1627 *(img_synthesizer->gr_ab10) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
dkato 0:853f5b7408a7 1628 *(img_synthesizer->gr_ab10) |= (uint32_t)param->alpha_1bit->gr_a0 << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 1629 *(img_synthesizer->gr_ab11) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
dkato 0:853f5b7408a7 1630 *(img_synthesizer->gr_ab11) |= (uint32_t)param->alpha_1bit->gr_a1 << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 1631 }
dkato 0:853f5b7408a7 1632
dkato 0:853f5b7408a7 1633 /* Premultiplication processing at alpha blending in one-pixel */
dkato 0:853f5b7408a7 1634 if (param->alpha_pixel != NULL) {
dkato 0:853f5b7408a7 1635 if (param->alpha_pixel->gr_acalc_md == VDC5_OFF) {
dkato 0:853f5b7408a7 1636 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT14;
dkato 0:853f5b7408a7 1637 } else {
dkato 0:853f5b7408a7 1638 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT14;
dkato 0:853f5b7408a7 1639 }
dkato 0:853f5b7408a7 1640 }
dkato 0:853f5b7408a7 1641
dkato 0:853f5b7408a7 1642 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 1643 b4 GRx_P_VEN */
dkato 0:853f5b7408a7 1644 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1645
dkato 0:853f5b7408a7 1646 } /* End of function VDC5_AlphaBlending() */
dkato 0:853f5b7408a7 1647
dkato 0:853f5b7408a7 1648 /**************************************************************************//**
dkato 0:853f5b7408a7 1649 * @brief Sets registers for rectangle alpha blending
dkato 0:853f5b7408a7 1650 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1651 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 1652 * @param[in] gr_arc_on : ON/OFF setting for alpha blending in a rectangular area
dkato 0:853f5b7408a7 1653 * @param[in] param : Setup parameter for alpha blending in a rectangular area
dkato 0:853f5b7408a7 1654 * @retval None
dkato 0:853f5b7408a7 1655 ******************************************************************************/
dkato 0:853f5b7408a7 1656 void VDC5_AlphaBlendingRect (
dkato 0:853f5b7408a7 1657 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1658 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 1659 const vdc5_onoff_t gr_arc_on,
dkato 0:853f5b7408a7 1660 const vdc5_alpha_blending_rect_t * const param)
dkato 0:853f5b7408a7 1661 {
dkato 0:853f5b7408a7 1662 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 1663 const vdc5_alpha_rect_t * alpha_rect_tmp;
dkato 0:853f5b7408a7 1664 uint32_t arc_coef;
dkato 0:853f5b7408a7 1665
dkato 0:853f5b7408a7 1666 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 1667
dkato 0:853f5b7408a7 1668 /* Alpha blending on/off control in a rectangular area */
dkato 0:853f5b7408a7 1669 if (gr_arc_on == VDC5_OFF) {
dkato 0:853f5b7408a7 1670 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
dkato 0:853f5b7408a7 1671 } else {
dkato 0:853f5b7408a7 1672 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT12;
dkato 0:853f5b7408a7 1673 }
dkato 0:853f5b7408a7 1674
dkato 0:853f5b7408a7 1675 if (param != NULL) {
dkato 0:853f5b7408a7 1676 /* Selection of lower-layer plane in scaler */
dkato 0:853f5b7408a7 1677 if (param->scl_und_sel != NULL) {
dkato 0:853f5b7408a7 1678 SetUndSel(ch, param->scl_und_sel->gr_vin_scl_und_sel);
dkato 0:853f5b7408a7 1679 }
dkato 0:853f5b7408a7 1680 /* Rectangular area subjected to alpha blending */
dkato 0:853f5b7408a7 1681 SetAlphaRectArea(param->gr_arc, img_synthesizer);
dkato 0:853f5b7408a7 1682
dkato 0:853f5b7408a7 1683 /* Alpha blending in a rectangular area */
dkato 0:853f5b7408a7 1684 alpha_rect_tmp = param->alpha_rect;
dkato 0:853f5b7408a7 1685 if (alpha_rect_tmp != NULL) {
dkato 0:853f5b7408a7 1686 if (graphics_id != VDC5_GR_TYPE_VIN) {
dkato 0:853f5b7408a7 1687 /* Multiplication processing with current alpha at alpha blending in a rectangular area (on/off) */
dkato 0:853f5b7408a7 1688 if (alpha_rect_tmp->gr_arc_mul == VDC5_OFF) {
dkato 0:853f5b7408a7 1689 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT15;
dkato 0:853f5b7408a7 1690 } else {
dkato 0:853f5b7408a7 1691 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT15;
dkato 0:853f5b7408a7 1692 }
dkato 0:853f5b7408a7 1693 }
dkato 0:853f5b7408a7 1694 /* Alpha coefficient for alpha blending in a rectangular area (-255 to 255) */
dkato 0:853f5b7408a7 1695 if (alpha_rect_tmp->gr_arc_coef < 0) {
dkato 0:853f5b7408a7 1696 arc_coef = (uint32_t)(alpha_rect_tmp->gr_arc_coef * (-1)); /* Conversion into absolute value */
dkato 0:853f5b7408a7 1697 /* Subtraction of the alpha coefficient */
dkato 0:853f5b7408a7 1698 *(img_synthesizer->gr_ab6) = (uint32_t)VDC5_REG_BIT24;
dkato 0:853f5b7408a7 1699 } else {
dkato 0:853f5b7408a7 1700 arc_coef = (uint32_t)alpha_rect_tmp->gr_arc_coef;
dkato 0:853f5b7408a7 1701 /* Addition of the alpha coefficient */
dkato 0:853f5b7408a7 1702 *(img_synthesizer->gr_ab6) = (uint32_t)0x00000000u;
dkato 0:853f5b7408a7 1703 }
dkato 0:853f5b7408a7 1704 *(img_synthesizer->gr_ab6) |= arc_coef << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1705 /* Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
dkato 0:853f5b7408a7 1706 *(img_synthesizer->gr_ab6) |= (uint32_t)alpha_rect_tmp->gr_arc_rate;
dkato 0:853f5b7408a7 1707 /* Initial alpha value for alpha blending in a rectangular area */
dkato 0:853f5b7408a7 1708 *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_MASK_0X00FF0000;
dkato 0:853f5b7408a7 1709 *(img_synthesizer->gr_ab7) |= (uint32_t)alpha_rect_tmp->gr_arc_def << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1710 }
dkato 0:853f5b7408a7 1711 }
dkato 0:853f5b7408a7 1712 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 1713 b4 GRx_P_VEN */
dkato 0:853f5b7408a7 1714 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1715
dkato 0:853f5b7408a7 1716 } /* End of function VDC5_AlphaBlending() */
dkato 0:853f5b7408a7 1717
dkato 0:853f5b7408a7 1718 /**************************************************************************//**
dkato 0:853f5b7408a7 1719 * @brief Sets registers for chroma-key
dkato 0:853f5b7408a7 1720 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1721 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 1722 * @param[in] gr_ck_on : Chroma-key ON/OFF setting
dkato 0:853f5b7408a7 1723 * @param[in] param : Chroma-key setup parameter
dkato 0:853f5b7408a7 1724 * @retval None
dkato 0:853f5b7408a7 1725 ******************************************************************************/
dkato 0:853f5b7408a7 1726 void VDC5_Chromakey (
dkato 0:853f5b7408a7 1727 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1728 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 1729 const vdc5_onoff_t gr_ck_on,
dkato 0:853f5b7408a7 1730 const vdc5_chromakey_t * const param)
dkato 0:853f5b7408a7 1731 {
dkato 0:853f5b7408a7 1732 vdc5_gr_format_t gr_format_tmp;
dkato 0:853f5b7408a7 1733 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 1734
dkato 0:853f5b7408a7 1735 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 1736
dkato 0:853f5b7408a7 1737 if (param != NULL) {
dkato 0:853f5b7408a7 1738 gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
dkato 0:853f5b7408a7 1739 if ((gr_format_tmp == VDC5_GR_FORMAT_CLUT1) ||
dkato 0:853f5b7408a7 1740 (gr_format_tmp == VDC5_GR_FORMAT_CLUT4) ||
dkato 0:853f5b7408a7 1741 (gr_format_tmp == VDC5_GR_FORMAT_CLUT8)) {
dkato 0:853f5b7408a7 1742 *(img_synthesizer->gr_ab8) = (uint32_t)(param->ck_color << VDC5_REG_SHIFT_24);
dkato 0:853f5b7408a7 1743 *(img_synthesizer->gr_ab9) = ColorConversionIntoAgbr(param->rep_color & VDC5_REG_RGB_24BIT_MASK);
dkato 0:853f5b7408a7 1744 } else {
dkato 0:853f5b7408a7 1745 /* Color conversion from gr_format_tmp into RGB888 format */
dkato 0:853f5b7408a7 1746 *(img_synthesizer->gr_ab8) = ColorConversion(gr_format_tmp, param->ck_color);
dkato 0:853f5b7408a7 1747 *(img_synthesizer->gr_ab9) = ColorConversion(gr_format_tmp, param->rep_color);
dkato 0:853f5b7408a7 1748 }
dkato 0:853f5b7408a7 1749 if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
dkato 0:853f5b7408a7 1750 /* Alpha value is set to 255. */
dkato 0:853f5b7408a7 1751 *(img_synthesizer->gr_ab9) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
dkato 0:853f5b7408a7 1752 } else {
dkato 0:853f5b7408a7 1753 *(img_synthesizer->gr_ab9) |= (uint32_t)param->rep_alpha << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 1754 }
dkato 0:853f5b7408a7 1755 }
dkato 0:853f5b7408a7 1756
dkato 0:853f5b7408a7 1757 if (gr_ck_on == VDC5_OFF) {
dkato 0:853f5b7408a7 1758 *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1759 } else {
dkato 0:853f5b7408a7 1760 *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1761 }
dkato 0:853f5b7408a7 1762
dkato 0:853f5b7408a7 1763 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 1764 b4 GRx_P_VEN */
dkato 0:853f5b7408a7 1765 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1766
dkato 0:853f5b7408a7 1767 } /* End of function VDC5_Chromakey() */
dkato 0:853f5b7408a7 1768
dkato 0:853f5b7408a7 1769 /**************************************************************************//**
dkato 0:853f5b7408a7 1770 * @brief Sets registers for CLUT
dkato 0:853f5b7408a7 1771 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1772 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 1773 * @param[in] param : CLUT setup parameter
dkato 0:853f5b7408a7 1774 * @retval None
dkato 0:853f5b7408a7 1775 ******************************************************************************/
dkato 0:853f5b7408a7 1776 void VDC5_CLUT (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param)
dkato 0:853f5b7408a7 1777 {
dkato 0:853f5b7408a7 1778 vdc5_gr_format_t gr_format_tmp;
dkato 0:853f5b7408a7 1779 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 1780
dkato 0:853f5b7408a7 1781 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 1782
dkato 0:853f5b7408a7 1783 gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
dkato 0:853f5b7408a7 1784 if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1) {
dkato 0:853f5b7408a7 1785 if (param->color_num == ((uint32_t)1u)) {
dkato 0:853f5b7408a7 1786 *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
dkato 0:853f5b7408a7 1787 if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
dkato 0:853f5b7408a7 1788 /* Alpha value is set to 255. */
dkato 0:853f5b7408a7 1789 *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
dkato 0:853f5b7408a7 1790 }
dkato 0:853f5b7408a7 1791 } else {
dkato 0:853f5b7408a7 1792 *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
dkato 0:853f5b7408a7 1793 *(img_synthesizer->gr_ab11) = ColorConversionIntoAgbr(param->clut[1]);
dkato 0:853f5b7408a7 1794 if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
dkato 0:853f5b7408a7 1795 /* Alpha value is set to 255. */
dkato 0:853f5b7408a7 1796 *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
dkato 0:853f5b7408a7 1797 *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
dkato 0:853f5b7408a7 1798 }
dkato 0:853f5b7408a7 1799 }
dkato 0:853f5b7408a7 1800 } else { /* CLUT4 or CLUT8 */
dkato 0:853f5b7408a7 1801 Set_Clut(param, vdc5_regaddr_clut[ch][graphics_id]);
dkato 0:853f5b7408a7 1802
dkato 0:853f5b7408a7 1803 /* CLUT table control register (GRx_CLUT)
dkato 0:853f5b7408a7 1804 b16 GRx_CLT_SEL - CLUT table select signal - XOR, flip signal */
dkato 0:853f5b7408a7 1805 *(img_synthesizer->gr_clut) ^= (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 1806 }
dkato 0:853f5b7408a7 1807 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 1808 b4 GRx_P_VEN */
dkato 0:853f5b7408a7 1809 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1810
dkato 0:853f5b7408a7 1811 } /* End of function VDC5_CLUT() */
dkato 0:853f5b7408a7 1812
dkato 0:853f5b7408a7 1813 /**************************************************************************//**
dkato 0:853f5b7408a7 1814 * @brief Sets registers for display calibration
dkato 0:853f5b7408a7 1815 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1816 * @param[in] param : Display calibration parameter
dkato 0:853f5b7408a7 1817 * @retval None
dkato 0:853f5b7408a7 1818 ******************************************************************************/
dkato 0:853f5b7408a7 1819 void VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
dkato 0:853f5b7408a7 1820 {
dkato 0:853f5b7408a7 1821 const vdc5_calibr_bright_t * bright_tmp;
dkato 0:853f5b7408a7 1822 const vdc5_calibr_contrast_t * contrast_tmp;
dkato 0:853f5b7408a7 1823 const vdc5_calibr_dither_t * panel_dither_tmp;
dkato 0:853f5b7408a7 1824 const vdc5_regaddr_output_ctrl_t * output_ctrl;
dkato 0:853f5b7408a7 1825
dkato 0:853f5b7408a7 1826 output_ctrl = &vdc5_regaddr_output_ctrl[ch];
dkato 0:853f5b7408a7 1827
dkato 0:853f5b7408a7 1828 /* Correction circuit sequence control */
dkato 0:853f5b7408a7 1829 if (param->route == VDC5_CALIBR_ROUTE_BCG) {
dkato 0:853f5b7408a7 1830 *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT12;
dkato 0:853f5b7408a7 1831 } else {
dkato 0:853f5b7408a7 1832 *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT12;
dkato 0:853f5b7408a7 1833 }
dkato 0:853f5b7408a7 1834
dkato 0:853f5b7408a7 1835 /* Brightness (DC) adjustment */
dkato 0:853f5b7408a7 1836 bright_tmp = param->bright;
dkato 0:853f5b7408a7 1837 if (bright_tmp != NULL) {
dkato 0:853f5b7408a7 1838 *(output_ctrl->out_bright1) = (uint32_t)bright_tmp->pbrt_g;
dkato 0:853f5b7408a7 1839 *(output_ctrl->out_bright2) = (uint32_t)bright_tmp->pbrt_b << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1840 *(output_ctrl->out_bright2) |= (uint32_t)bright_tmp->pbrt_r;
dkato 0:853f5b7408a7 1841 }
dkato 0:853f5b7408a7 1842
dkato 0:853f5b7408a7 1843 /* Contrast (gain) adjustment */
dkato 0:853f5b7408a7 1844 contrast_tmp = param->contrast;
dkato 0:853f5b7408a7 1845 if (contrast_tmp != NULL) {
dkato 0:853f5b7408a7 1846 *(output_ctrl->out_contrast) = (uint32_t)contrast_tmp->cont_g << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 1847 *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_b << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 1848 *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_r;
dkato 0:853f5b7408a7 1849 }
dkato 0:853f5b7408a7 1850
dkato 0:853f5b7408a7 1851 /* Panel dithering */
dkato 0:853f5b7408a7 1852 panel_dither_tmp = param->panel_dither;
dkato 0:853f5b7408a7 1853 if (panel_dither_tmp != NULL) {
dkato 0:853f5b7408a7 1854 *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00300000;
dkato 0:853f5b7408a7 1855 *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_sel << VDC5_REG_SHIFT_20;
dkato 0:853f5b7408a7 1856 if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2) {
dkato 0:853f5b7408a7 1857 *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00003333;
dkato 0:853f5b7408a7 1858 *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pa << VDC5_REG_SHIFT_12;
dkato 0:853f5b7408a7 1859 *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pb << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 1860 *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pc << VDC5_REG_SHIFT_4;
dkato 0:853f5b7408a7 1861 *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pd;
dkato 0:853f5b7408a7 1862 }
dkato 0:853f5b7408a7 1863 }
dkato 0:853f5b7408a7 1864
dkato 0:853f5b7408a7 1865 /* Register update control register (OUT_UPDATE)
dkato 0:853f5b7408a7 1866 b0 OUTCNT_VEN */
dkato 0:853f5b7408a7 1867 *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1868
dkato 0:853f5b7408a7 1869 } /* End of function VDC5_DisplayCalibration() */
dkato 0:853f5b7408a7 1870
dkato 0:853f5b7408a7 1871 /**************************************************************************//**
dkato 0:853f5b7408a7 1872 * @brief Sets registers for gamma correction
dkato 0:853f5b7408a7 1873 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1874 * @param[in] gam_on : Gamma correction ON/OFF setting
dkato 0:853f5b7408a7 1875 * @param[in] param : Gamma correction setup parameter
dkato 0:853f5b7408a7 1876 * @retval None
dkato 0:853f5b7408a7 1877 ******************************************************************************/
dkato 0:853f5b7408a7 1878 void VDC5_GammaCorrection (
dkato 0:853f5b7408a7 1879 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 1880 const vdc5_onoff_t gam_on,
dkato 0:853f5b7408a7 1881 const vdc5_gamma_correction_t * const param)
dkato 0:853f5b7408a7 1882 {
dkato 0:853f5b7408a7 1883 const vdc5_regaddr_gamma_t * gamma;
dkato 0:853f5b7408a7 1884
dkato 0:853f5b7408a7 1885 gamma = &vdc5_regaddr_gamma[ch];
dkato 0:853f5b7408a7 1886
dkato 0:853f5b7408a7 1887 /* Gamma correction on/off control */
dkato 0:853f5b7408a7 1888 *(gamma->gam_sw) = (gam_on == VDC5_OFF) ? 0x0000u : 0x0001u;
dkato 0:853f5b7408a7 1889
dkato 0:853f5b7408a7 1890 if (param != NULL) {
dkato 0:853f5b7408a7 1891 /* Start threshold of area 1 to 31 of G signal */
dkato 0:853f5b7408a7 1892 Set_StartThreshold_Gamma(param->gam_g_th, gamma->gam_g_area);
dkato 0:853f5b7408a7 1893 /* Gain adjustment of area 0 to 31 of G signal */
dkato 0:853f5b7408a7 1894 Set_GainAdjustment_Gamma(param->gam_g_gain, gamma->gam_g_lut);
dkato 0:853f5b7408a7 1895 /* Register update control register G (GAM_G_UPDATE)
dkato 0:853f5b7408a7 1896 b0 GAM_G_VEN */
dkato 0:853f5b7408a7 1897 *(gamma->gam_g_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1898
dkato 0:853f5b7408a7 1899 /* Start threshold of area 1 to 31 of B signal */
dkato 0:853f5b7408a7 1900 Set_StartThreshold_Gamma(param->gam_b_th, gamma->gam_b_area);
dkato 0:853f5b7408a7 1901 /* Gain adjustment of area 0 to 31 of B signal */
dkato 0:853f5b7408a7 1902 Set_GainAdjustment_Gamma(param->gam_b_gain, gamma->gam_b_lut);
dkato 0:853f5b7408a7 1903 /* Register update control register B (GAM_B_UPDATE)
dkato 0:853f5b7408a7 1904 b0 GAM_B_VEN */
dkato 0:853f5b7408a7 1905 *(gamma->gam_b_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1906
dkato 0:853f5b7408a7 1907 /* Start threshold of area 1 to 31 of R signal */
dkato 0:853f5b7408a7 1908 Set_StartThreshold_Gamma(param->gam_r_th, gamma->gam_r_area);
dkato 0:853f5b7408a7 1909 /* Gain adjustment of area 0 to 31 of R signal */
dkato 0:853f5b7408a7 1910 Set_GainAdjustment_Gamma(param->gam_r_gain, gamma->gam_r_lut);
dkato 0:853f5b7408a7 1911 /* Register update control register R (GAM_R_UPDATE)
dkato 0:853f5b7408a7 1912 b0 GAM_R_VEN */
dkato 0:853f5b7408a7 1913 *(gamma->gam_r_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1914 }
dkato 0:853f5b7408a7 1915 } /* End of function VDC5_GammaCorrection() */
dkato 0:853f5b7408a7 1916
dkato 0:853f5b7408a7 1917 /******************************************************************************
dkato 0:853f5b7408a7 1918 Local Functions
dkato 0:853f5b7408a7 1919 ******************************************************************************/
dkato 0:853f5b7408a7 1920 /**************************************************************************//**
dkato 0:853f5b7408a7 1921 * @brief Sets external input video signal
dkato 0:853f5b7408a7 1922 * @param[in] ext_sig_tmp : External input signal parameter
dkato 0:853f5b7408a7 1923 * @param[in] input_ctrl : Input controller registers
dkato 0:853f5b7408a7 1924 * @retval None
dkato 0:853f5b7408a7 1925 ******************************************************************************/
dkato 0:853f5b7408a7 1926 static void SetVideoExternalInput (
dkato 0:853f5b7408a7 1927 const vdc5_ext_in_sig_t * const ext_sig_tmp,
dkato 0:853f5b7408a7 1928 const vdc5_regaddr_input_ctrl_t * const input_ctrl)
dkato 0:853f5b7408a7 1929 {
dkato 0:853f5b7408a7 1930 *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_MASK_0X00007111;
dkato 0:853f5b7408a7 1931 /* External input format select */
dkato 0:853f5b7408a7 1932 if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR444) {
dkato 0:853f5b7408a7 1933 *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_EXTIN_FORMAT_RGB888 << VDC5_REG_SHIFT_12;
dkato 0:853f5b7408a7 1934 } else {
dkato 0:853f5b7408a7 1935 *(input_ctrl->inp_sel_cnt) |= (uint32_t)ext_sig_tmp->inp_format << VDC5_REG_SHIFT_12;
dkato 0:853f5b7408a7 1936 }
dkato 0:853f5b7408a7 1937 /* Clock edge select for capturing external input video image signals */
dkato 0:853f5b7408a7 1938 if (ext_sig_tmp->inp_pxd_edge != VDC5_EDGE_RISING) {
dkato 0:853f5b7408a7 1939 *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1940 }
dkato 0:853f5b7408a7 1941 /* Clock edge select for capturing external input Vsync signals */
dkato 0:853f5b7408a7 1942 if (ext_sig_tmp->inp_vs_edge != VDC5_EDGE_RISING) {
dkato 0:853f5b7408a7 1943 *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1944 }
dkato 0:853f5b7408a7 1945 /* Clock edge select for capturing external input Hsync signals */
dkato 0:853f5b7408a7 1946 if (ext_sig_tmp->inp_hs_edge != VDC5_EDGE_RISING) {
dkato 0:853f5b7408a7 1947 *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 1948 }
dkato 0:853f5b7408a7 1949
dkato 0:853f5b7408a7 1950 *(input_ctrl->inp_ext_sync_cnt) &= (uint32_t)~VDC5_REG_MASK_0X11110113;
dkato 0:853f5b7408a7 1951 /* External input bit endian change on/off control */
dkato 0:853f5b7408a7 1952 if (ext_sig_tmp->inp_endian_on != VDC5_OFF) {
dkato 0:853f5b7408a7 1953 *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT28;
dkato 0:853f5b7408a7 1954 }
dkato 0:853f5b7408a7 1955 /* External input B/R signal swap on/off control */
dkato 0:853f5b7408a7 1956 if (ext_sig_tmp->inp_swap_on != VDC5_OFF) {
dkato 0:853f5b7408a7 1957 *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT24;
dkato 0:853f5b7408a7 1958 }
dkato 0:853f5b7408a7 1959 /* External input Vsync signal DV_VSYNC inversion control */
dkato 0:853f5b7408a7 1960 if (ext_sig_tmp->inp_vs_inv != VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 1961 *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT20;
dkato 0:853f5b7408a7 1962 }
dkato 0:853f5b7408a7 1963 /* External input Hsync signal DV_HSYNC inversion control */
dkato 0:853f5b7408a7 1964 if (ext_sig_tmp->inp_hs_inv != VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 1965 *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 1966 }
dkato 0:853f5b7408a7 1967 /* Reference select for external input BT.656 Hsync signal */
dkato 0:853f5b7408a7 1968 if (ext_sig_tmp->inp_h_edge_sel != VDC5_EXTIN_REF_H_EAV) {
dkato 0:853f5b7408a7 1969 *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1970 }
dkato 0:853f5b7408a7 1971 /* Number of lines for BT.656 external input */
dkato 0:853f5b7408a7 1972 if (ext_sig_tmp->inp_f525_625 != VDC5_EXTIN_LINE_525) {
dkato 0:853f5b7408a7 1973 *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 1974 }
dkato 0:853f5b7408a7 1975 /* Y/Cb/Y/Cr data string start timing to Hsync reference */
dkato 0:853f5b7408a7 1976 *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)ext_sig_tmp->inp_h_pos;
dkato 0:853f5b7408a7 1977 } /* End of function SetVideoExternalInput() */
dkato 0:853f5b7408a7 1978
dkato 0:853f5b7408a7 1979 /**************************************************************************//**
dkato 0:853f5b7408a7 1980 * @brief Initializes cascaded connection
dkato 0:853f5b7408a7 1981 * @param[in] ch : Channel
dkato 0:853f5b7408a7 1982 * @retval None
dkato 0:853f5b7408a7 1983 ******************************************************************************/
dkato 0:853f5b7408a7 1984 static void SetInitialConnection (const vdc5_channel_t ch)
dkato 0:853f5b7408a7 1985 {
dkato 0:853f5b7408a7 1986 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 1987
dkato 0:853f5b7408a7 1988 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
dkato 0:853f5b7408a7 1989
dkato 0:853f5b7408a7 1990 /* Cascade ON */
dkato 0:853f5b7408a7 1991 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT28;
dkato 0:853f5b7408a7 1992 /* Graphics register update control register (GR1_UPDATE)
dkato 0:853f5b7408a7 1993 b8 GR1_UPDATE */
dkato 0:853f5b7408a7 1994 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 1995
dkato 0:853f5b7408a7 1996 VDC5_ShrdPrmSetCascade(ch, VDC5_ON);
dkato 0:853f5b7408a7 1997
dkato 0:853f5b7408a7 1998 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
dkato 0:853f5b7408a7 1999
dkato 0:853f5b7408a7 2000 /* Turns off alpha blending in a rectangular area */
dkato 0:853f5b7408a7 2001 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
dkato 0:853f5b7408a7 2002 /* Selection of lower-layer plane in scaler, graphics 1 is used as lower-layer graphics. */
dkato 0:853f5b7408a7 2003 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
dkato 0:853f5b7408a7 2004 /* Graphics display mode in VIN */
dkato 0:853f5b7408a7 2005 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 2006 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
dkato 0:853f5b7408a7 2007 /* Disable fade-in and fade-out */
dkato 0:853f5b7408a7 2008 *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
dkato 0:853f5b7408a7 2009 /* Set the initial alpha value to '255' */
dkato 0:853f5b7408a7 2010 *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
dkato 0:853f5b7408a7 2011 /* Graphics register update control register (GR_VIN_UPDATE)
dkato 0:853f5b7408a7 2012 b8 GR_VIN_UPDATE
dkato 0:853f5b7408a7 2013 b4 GR_VIN_P_VEN */
dkato 0:853f5b7408a7 2014 *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
dkato 0:853f5b7408a7 2015
dkato 0:853f5b7408a7 2016 } /* End of function SetInitialConnection() */
dkato 0:853f5b7408a7 2017
dkato 0:853f5b7408a7 2018 /**************************************************************************//**
dkato 0:853f5b7408a7 2019 * @brief Sets background color for graphics
dkato 0:853f5b7408a7 2020 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2021 * @retval None
dkato 0:853f5b7408a7 2022 ******************************************************************************/
dkato 0:853f5b7408a7 2023 static void SetGrapicsBackgroundColor (const vdc5_channel_t ch)
dkato 0:853f5b7408a7 2024 {
dkato 0:853f5b7408a7 2025 uint32_t bg_color_tmp;
dkato 0:853f5b7408a7 2026 uint32_t bg_color_conv;
dkato 0:853f5b7408a7 2027 volatile uint32_t * bg_color_reg;
dkato 0:853f5b7408a7 2028 volatile uint32_t * update_reg;
dkato 0:853f5b7408a7 2029 vdc5_graphics_type_t gr_type_index;
dkato 0:853f5b7408a7 2030
dkato 0:853f5b7408a7 2031 /* Background color in 24-bit RGB color format or CrYCb format */
dkato 0:853f5b7408a7 2032 bg_color_tmp = VDC5_ShrdPrmGetBgColor(ch, VDC5_COLOR_SPACE_GBR);
dkato 0:853f5b7408a7 2033 /* Conversion from RGB into GBR / from CrYCb into YCbCr */
dkato 0:853f5b7408a7 2034 bg_color_conv = ColorConversionIntoAgbr(bg_color_tmp);
dkato 0:853f5b7408a7 2035 bg_color_conv &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
dkato 0:853f5b7408a7 2036
dkato 0:853f5b7408a7 2037 /* GR2, GR3, VIN, OIR */
dkato 0:853f5b7408a7 2038 for (gr_type_index = VDC5_GR_TYPE_GR2; gr_type_index < VDC5_GR_TYPE_NUM; gr_type_index++) {
dkato 0:853f5b7408a7 2039 /* Background color in GBR format (GRx_BASE) */
dkato 0:853f5b7408a7 2040 bg_color_reg = vdc5_regaddr_img_synthesizer[ch][gr_type_index].gr_base;
dkato 0:853f5b7408a7 2041 *bg_color_reg = bg_color_conv;
dkato 0:853f5b7408a7 2042 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 2043 b4 GRx_P_VEN */
dkato 0:853f5b7408a7 2044 update_reg = vdc5_regaddr_img_synthesizer[ch][gr_type_index].gr_update;
dkato 0:853f5b7408a7 2045 *update_reg |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2046 }
dkato 0:853f5b7408a7 2047 /* For OIR */
dkato 0:853f5b7408a7 2048 /* Background color in RGB format (OIR_SCL0_OVR1) */
dkato 0:853f5b7408a7 2049 bg_color_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl0_ovr1;
dkato 0:853f5b7408a7 2050 *bg_color_reg = bg_color_tmp;
dkato 0:853f5b7408a7 2051 /* Register update control register (OIR_SCL0_UPDATE)
dkato 0:853f5b7408a7 2052 b4 SCL0_VEN_B */
dkato 0:853f5b7408a7 2053 update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl0_update;
dkato 0:853f5b7408a7 2054 *update_reg |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2055 } /* End of function SetGrapicsBackgroundColor() */
dkato 0:853f5b7408a7 2056
dkato 0:853f5b7408a7 2057 /**************************************************************************//**
dkato 0:853f5b7408a7 2058 * @brief Sets background color for scaler 0, scaler 1, graphics 0, and graphics 1
dkato 0:853f5b7408a7 2059 *
dkato 0:853f5b7408a7 2060 * Description:<br>
dkato 0:853f5b7408a7 2061 * This function should be called only when graphics 0 or graphics 1 is selected.
dkato 0:853f5b7408a7 2062 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2063 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 2064 * @param[in] color_space : Color space (GBR or YCbCr)
dkato 0:853f5b7408a7 2065 * @retval None
dkato 0:853f5b7408a7 2066 ******************************************************************************/
dkato 0:853f5b7408a7 2067 static void SetScalerBackgroundColor (
dkato 0:853f5b7408a7 2068 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 2069 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 2070 const vdc5_color_space_t color_space)
dkato 0:853f5b7408a7 2071 {
dkato 0:853f5b7408a7 2072 volatile uint32_t * scl0_update_reg;
dkato 0:853f5b7408a7 2073 volatile uint32_t * scl0_ovr1_reg;
dkato 0:853f5b7408a7 2074 volatile uint32_t * gr_base_reg;
dkato 0:853f5b7408a7 2075 volatile uint32_t * gr_update_reg;
dkato 0:853f5b7408a7 2076 uint32_t bg_color_tmp;
dkato 0:853f5b7408a7 2077 uint32_t bg_color_conv;
dkato 0:853f5b7408a7 2078
dkato 0:853f5b7408a7 2079 if (graphics_id == VDC5_GR_TYPE_GR0) {
dkato 0:853f5b7408a7 2080 scl0_ovr1_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_ovr1;
dkato 0:853f5b7408a7 2081 scl0_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_update;
dkato 0:853f5b7408a7 2082 gr_base_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_base;
dkato 0:853f5b7408a7 2083 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
dkato 0:853f5b7408a7 2084 } else {
dkato 0:853f5b7408a7 2085 /* graphics_id == VDC5_GR_TYPE_GR1 */
dkato 0:853f5b7408a7 2086 scl0_ovr1_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_ovr1;
dkato 0:853f5b7408a7 2087 scl0_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_update;
dkato 0:853f5b7408a7 2088 gr_base_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_base;
dkato 0:853f5b7408a7 2089 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
dkato 0:853f5b7408a7 2090 }
dkato 0:853f5b7408a7 2091 /* Background color in 24-bit RGB color format or CrYCb format */
dkato 0:853f5b7408a7 2092 bg_color_tmp = VDC5_ShrdPrmGetBgColor(ch, color_space);
dkato 0:853f5b7408a7 2093 /* Conversion from RGB into GBR / from CrYCb into YCbCr */
dkato 0:853f5b7408a7 2094 bg_color_conv = ColorConversionIntoAgbr(bg_color_tmp);
dkato 0:853f5b7408a7 2095 bg_color_conv &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
dkato 0:853f5b7408a7 2096
dkato 0:853f5b7408a7 2097 /* Background color in RGB format or CrYCb format */
dkato 0:853f5b7408a7 2098 *scl0_ovr1_reg = bg_color_tmp;
dkato 0:853f5b7408a7 2099 /* Register update control register
dkato 0:853f5b7408a7 2100 b4 SCL0_VEN_B */
dkato 0:853f5b7408a7 2101 *scl0_update_reg |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2102
dkato 0:853f5b7408a7 2103 /* Background color in GBR format or YCbCr format */
dkato 0:853f5b7408a7 2104 *gr_base_reg = bg_color_conv;
dkato 0:853f5b7408a7 2105 /* Graphics register update control register
dkato 0:853f5b7408a7 2106 b4 GRx_P_VEN */
dkato 0:853f5b7408a7 2107 *gr_update_reg |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2108 } /* End of function SetScalerBackgroundColor() */
dkato 0:853f5b7408a7 2109
dkato 0:853f5b7408a7 2110 /**************************************************************************//**
dkato 0:853f5b7408a7 2111 * @brief Sets LCD TCON - STVA/VS
dkato 0:853f5b7408a7 2112 * @param[in] lcd_tcon : LCD TCON timing signal parameter
dkato 0:853f5b7408a7 2113 * @param[in] output_ctrl : Output controller registers
dkato 0:853f5b7408a7 2114 * @retval None
dkato 0:853f5b7408a7 2115 ******************************************************************************/
dkato 0:853f5b7408a7 2116 static void SetLcdTcon_STVA_VS (
dkato 0:853f5b7408a7 2117 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 2118 const vdc5_regaddr_output_ctrl_t * const output_ctrl)
dkato 0:853f5b7408a7 2119 {
dkato 0:853f5b7408a7 2120 /* Signal pulse start position */
dkato 0:853f5b7408a7 2121 *(output_ctrl->tcon_tim_stva1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2122 /* Pulse width */
dkato 0:853f5b7408a7 2123 *(output_ctrl->tcon_tim_stva1) |= (uint32_t)lcd_tcon->tcon_hwvw;
dkato 0:853f5b7408a7 2124
dkato 0:853f5b7408a7 2125 /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 2126 if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 2127 *(output_ctrl->tcon_tim_stva2) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2128 } else {
dkato 0:853f5b7408a7 2129 *(output_ctrl->tcon_tim_stva2) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2130 }
dkato 0:853f5b7408a7 2131 } /* End of function SetLcdTcon_STVA_VS() */
dkato 0:853f5b7408a7 2132
dkato 0:853f5b7408a7 2133 /**************************************************************************//**
dkato 0:853f5b7408a7 2134 * @brief Sets LCD TCON - STVB/VE
dkato 0:853f5b7408a7 2135 * @param[in] lcd_tcon : LCD TCON timing signal parameter
dkato 0:853f5b7408a7 2136 * @param[in] output_ctrl : Output controller registers
dkato 0:853f5b7408a7 2137 * @retval None
dkato 0:853f5b7408a7 2138 ******************************************************************************/
dkato 0:853f5b7408a7 2139 static void SetLcdTcon_STVB_VE (
dkato 0:853f5b7408a7 2140 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 2141 const vdc5_regaddr_output_ctrl_t * const output_ctrl)
dkato 0:853f5b7408a7 2142 {
dkato 0:853f5b7408a7 2143 /* Signal pulse start position */
dkato 0:853f5b7408a7 2144 *(output_ctrl->tcon_tim_stvb1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2145 /* Pulse width */
dkato 0:853f5b7408a7 2146 *(output_ctrl->tcon_tim_stvb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
dkato 0:853f5b7408a7 2147
dkato 0:853f5b7408a7 2148 /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 2149 if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 2150 *(output_ctrl->tcon_tim_stvb2) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2151 } else {
dkato 0:853f5b7408a7 2152 *(output_ctrl->tcon_tim_stvb2) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2153 }
dkato 0:853f5b7408a7 2154 } /* End of function SetLcdTcon_STVB_VE() */
dkato 0:853f5b7408a7 2155
dkato 0:853f5b7408a7 2156 /**************************************************************************//**
dkato 0:853f5b7408a7 2157 * @brief Sets LCD TCON - STH/HS
dkato 0:853f5b7408a7 2158 * @param[in] lcd_tcon : LCD TCON timing signal parameter
dkato 0:853f5b7408a7 2159 * @param[in] output_ctrl : Output controller registers
dkato 0:853f5b7408a7 2160 * @retval None
dkato 0:853f5b7408a7 2161 ******************************************************************************/
dkato 0:853f5b7408a7 2162 static void SetLcdTcon_STH_HS (
dkato 0:853f5b7408a7 2163 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 2164 const vdc5_regaddr_output_ctrl_t * const output_ctrl)
dkato 0:853f5b7408a7 2165 {
dkato 0:853f5b7408a7 2166 /* Signal pulse start position */
dkato 0:853f5b7408a7 2167 *(output_ctrl->tcon_tim_sth1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2168 /* Pulse width */
dkato 0:853f5b7408a7 2169 *(output_ctrl->tcon_tim_sth1) |= (uint32_t)lcd_tcon->tcon_hwvw;
dkato 0:853f5b7408a7 2170
dkato 0:853f5b7408a7 2171 *(output_ctrl->tcon_tim_sth2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
dkato 0:853f5b7408a7 2172 /* Signal operating reference select */
dkato 0:853f5b7408a7 2173 if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
dkato 0:853f5b7408a7 2174 *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2175 }
dkato 0:853f5b7408a7 2176 /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 2177 if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 2178 *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2179 }
dkato 0:853f5b7408a7 2180 } /* End of function SetLcdTcon_STH_HS() */
dkato 0:853f5b7408a7 2181
dkato 0:853f5b7408a7 2182 /**************************************************************************//**
dkato 0:853f5b7408a7 2183 * @brief Sets LCD TCON - STB/HE
dkato 0:853f5b7408a7 2184 * @param[in] lcd_tcon : LCD TCON timing signal parameter
dkato 0:853f5b7408a7 2185 * @param[in] output_ctrl : Output controller registers
dkato 0:853f5b7408a7 2186 * @retval None
dkato 0:853f5b7408a7 2187 ******************************************************************************/
dkato 0:853f5b7408a7 2188 static void SetLcdTcon_STB_HE (
dkato 0:853f5b7408a7 2189 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 2190 const vdc5_regaddr_output_ctrl_t * const output_ctrl)
dkato 0:853f5b7408a7 2191 {
dkato 0:853f5b7408a7 2192 /* Signal pulse start position */
dkato 0:853f5b7408a7 2193 *(output_ctrl->tcon_tim_stb1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2194 /* Pulse width */
dkato 0:853f5b7408a7 2195 *(output_ctrl->tcon_tim_stb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
dkato 0:853f5b7408a7 2196
dkato 0:853f5b7408a7 2197 *(output_ctrl->tcon_tim_stb2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
dkato 0:853f5b7408a7 2198 /* Signal operating reference select */
dkato 0:853f5b7408a7 2199 if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
dkato 0:853f5b7408a7 2200 *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2201 }
dkato 0:853f5b7408a7 2202 /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 2203 if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 2204 *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2205 }
dkato 0:853f5b7408a7 2206 } /* End of function SetLcdTcon_STB_HE() */
dkato 0:853f5b7408a7 2207
dkato 0:853f5b7408a7 2208 /**************************************************************************//**
dkato 0:853f5b7408a7 2209 * @brief Sets LCD TCON - CPV/GCK
dkato 0:853f5b7408a7 2210 * @param[in] lcd_tcon : LCD TCON timing signal parameter
dkato 0:853f5b7408a7 2211 * @param[in] output_ctrl : Output controller registers
dkato 0:853f5b7408a7 2212 * @retval None
dkato 0:853f5b7408a7 2213 ******************************************************************************/
dkato 0:853f5b7408a7 2214 static void SetLcdTcon_CPV_GCK (
dkato 0:853f5b7408a7 2215 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 2216 const vdc5_regaddr_output_ctrl_t * const output_ctrl)
dkato 0:853f5b7408a7 2217 {
dkato 0:853f5b7408a7 2218 /* Signal pulse start position */
dkato 0:853f5b7408a7 2219 *(output_ctrl->tcon_tim_cpv1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2220 /* Pulse width */
dkato 0:853f5b7408a7 2221 *(output_ctrl->tcon_tim_cpv1) |= (uint32_t)lcd_tcon->tcon_hwvw;
dkato 0:853f5b7408a7 2222
dkato 0:853f5b7408a7 2223 *(output_ctrl->tcon_tim_cpv2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
dkato 0:853f5b7408a7 2224 /* Signal operating reference select */
dkato 0:853f5b7408a7 2225 if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
dkato 0:853f5b7408a7 2226 *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2227 }
dkato 0:853f5b7408a7 2228 /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 2229 if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 2230 *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2231 }
dkato 0:853f5b7408a7 2232 } /* End of function SetLcdTcon_CPV_GCK() */
dkato 0:853f5b7408a7 2233
dkato 0:853f5b7408a7 2234 /**************************************************************************//**
dkato 0:853f5b7408a7 2235 * @brief Sets LCD TCON - POLA
dkato 0:853f5b7408a7 2236 * @param[in] lcd_tcon : LCD TCON timing signal parameter
dkato 0:853f5b7408a7 2237 * @param[in] output_ctrl : Output controller registers
dkato 0:853f5b7408a7 2238 * @retval None
dkato 0:853f5b7408a7 2239 ******************************************************************************/
dkato 0:853f5b7408a7 2240 static void SetLcdTcon_POLA (
dkato 0:853f5b7408a7 2241 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 2242 const vdc5_regaddr_output_ctrl_t * const output_ctrl)
dkato 0:853f5b7408a7 2243 {
dkato 0:853f5b7408a7 2244 /* Signal pulse start position */
dkato 0:853f5b7408a7 2245 *(output_ctrl->tcon_tim_pola1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2246 /* Pulse width */
dkato 0:853f5b7408a7 2247 *(output_ctrl->tcon_tim_pola1) |= (uint32_t)lcd_tcon->tcon_hwvw;
dkato 0:853f5b7408a7 2248
dkato 0:853f5b7408a7 2249 *(output_ctrl->tcon_tim_pola2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
dkato 0:853f5b7408a7 2250 /* POLA/POLB signal generation mode select */
dkato 0:853f5b7408a7 2251 *(output_ctrl->tcon_tim_pola2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
dkato 0:853f5b7408a7 2252 /* Signal operating reference select */
dkato 0:853f5b7408a7 2253 if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
dkato 0:853f5b7408a7 2254 *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2255 }
dkato 0:853f5b7408a7 2256 /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 2257 if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 2258 *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2259 }
dkato 0:853f5b7408a7 2260 } /* End of function SetLcdTcon_POLA() */
dkato 0:853f5b7408a7 2261
dkato 0:853f5b7408a7 2262 /**************************************************************************//**
dkato 0:853f5b7408a7 2263 * @brief Sets LCD TCON - POLB
dkato 0:853f5b7408a7 2264 * @param[in] lcd_tcon : LCD TCON timing signal parameter
dkato 0:853f5b7408a7 2265 * @param[in] output_ctrl : Output controller registers
dkato 0:853f5b7408a7 2266 * @retval None
dkato 0:853f5b7408a7 2267 ******************************************************************************/
dkato 0:853f5b7408a7 2268 static void SetLcdTcon_POLB (
dkato 0:853f5b7408a7 2269 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 2270 const vdc5_regaddr_output_ctrl_t * const output_ctrl)
dkato 0:853f5b7408a7 2271 {
dkato 0:853f5b7408a7 2272 /* Signal pulse start position */
dkato 0:853f5b7408a7 2273 *(output_ctrl->tcon_tim_polb1) = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2274 /* Pulse width */
dkato 0:853f5b7408a7 2275 *(output_ctrl->tcon_tim_polb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
dkato 0:853f5b7408a7 2276
dkato 0:853f5b7408a7 2277 *(output_ctrl->tcon_tim_polb2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
dkato 0:853f5b7408a7 2278 /* POLA/POLB signal generation mode select */
dkato 0:853f5b7408a7 2279 *(output_ctrl->tcon_tim_polb2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
dkato 0:853f5b7408a7 2280 /* Signal operating reference select */
dkato 0:853f5b7408a7 2281 if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
dkato 0:853f5b7408a7 2282 *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2283 }
dkato 0:853f5b7408a7 2284 /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 2285 if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
dkato 0:853f5b7408a7 2286 *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2287 }
dkato 0:853f5b7408a7 2288 } /* End of function SetLcdTcon_POLB() */
dkato 0:853f5b7408a7 2289
dkato 0:853f5b7408a7 2290 /**************************************************************************//**
dkato 0:853f5b7408a7 2291 * @brief Sets LCD TCON - DE
dkato 0:853f5b7408a7 2292 * @param[in] lcd_tcon : LCD TCON timing signal parameter
dkato 0:853f5b7408a7 2293 * @param[in] output_ctrl : Output controller registers
dkato 0:853f5b7408a7 2294 * @retval None
dkato 0:853f5b7408a7 2295 ******************************************************************************/
dkato 0:853f5b7408a7 2296 static void SetLcdTcon_DE (
dkato 0:853f5b7408a7 2297 const vdc5_lcd_tcon_timing_t * const lcd_tcon,
dkato 0:853f5b7408a7 2298 const vdc5_regaddr_output_ctrl_t * const output_ctrl)
dkato 0:853f5b7408a7 2299 {
dkato 0:853f5b7408a7 2300 /* Polarity inversion control of signal */
dkato 0:853f5b7408a7 2301 *(output_ctrl->tcon_tim_de) = (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) ? (uint32_t)0u : (uint32_t)1u;
dkato 0:853f5b7408a7 2302
dkato 0:853f5b7408a7 2303 } /* End of function SetLcdTcon_DE() */
dkato 0:853f5b7408a7 2304
dkato 0:853f5b7408a7 2305 /**************************************************************************//**
dkato 0:853f5b7408a7 2306 * @brief Sets scaling-down
dkato 0:853f5b7408a7 2307 * @param[in] scldw_rot : Scaling-down and rotation parameter
dkato 0:853f5b7408a7 2308 * @param[in] res_inter : Field operating mode select
dkato 0:853f5b7408a7 2309 * @param[in] scaler : Scaler registers
dkato 0:853f5b7408a7 2310 * @retval None
dkato 0:853f5b7408a7 2311 ******************************************************************************/
dkato 0:853f5b7408a7 2312 static void SetScalingDown (
dkato 0:853f5b7408a7 2313 const vdc5_scalingdown_rot_t * const scldw_rot,
dkato 0:853f5b7408a7 2314 const vdc5_res_inter_t res_inter,
dkato 0:853f5b7408a7 2315 const vdc5_regaddr_scaler_t * const scaler)
dkato 0:853f5b7408a7 2316 {
dkato 0:853f5b7408a7 2317 uint32_t vw_before_scld; /* Vertical width before scaling-down */
dkato 0:853f5b7408a7 2318 uint32_t hw_before_scld; /* Horizontal width before scaling-down */
dkato 0:853f5b7408a7 2319 uint32_t vw_after_scld; /* Vertical width after scaling-down */
dkato 0:853f5b7408a7 2320 uint32_t hw_after_scld; /* Horizontal width after scaling-down */
dkato 0:853f5b7408a7 2321 uint32_t scaling_ratio;
dkato 0:853f5b7408a7 2322
dkato 0:853f5b7408a7 2323 vw_before_scld = (uint32_t)scldw_rot->res.vw;
dkato 0:853f5b7408a7 2324 hw_before_scld = (uint32_t)scldw_rot->res.hw;
dkato 0:853f5b7408a7 2325
dkato 0:853f5b7408a7 2326 vw_after_scld = (uint32_t)scldw_rot->res_out_vw;
dkato 0:853f5b7408a7 2327 hw_after_scld = (uint32_t)scldw_rot->res_out_hw;
dkato 0:853f5b7408a7 2328
dkato 0:853f5b7408a7 2329 /* Vertical scaling-down: ON, vertical scaling-up: OFF */
dkato 0:853f5b7408a7 2330 *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2331 *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2332 if (vw_before_scld > vw_after_scld) {
dkato 0:853f5b7408a7 2333 scaling_ratio = CalcScalingRatio(vw_before_scld, vw_after_scld, scldw_rot->adj_sel, VDC5_OFF);
dkato 0:853f5b7408a7 2334
dkato 0:853f5b7408a7 2335 *(scaler->scl0_ds6) = scaling_ratio;
dkato 0:853f5b7408a7 2336 } else {
dkato 0:853f5b7408a7 2337 *(scaler->scl0_ds6) = (uint32_t)SCALING_RATIO_SAME_SIZE;
dkato 0:853f5b7408a7 2338 }
dkato 0:853f5b7408a7 2339
dkato 0:853f5b7408a7 2340 /* Horizontal scaling-down */
dkato 0:853f5b7408a7 2341 if (hw_before_scld > hw_after_scld) {
dkato 0:853f5b7408a7 2342 /* ON */
dkato 0:853f5b7408a7 2343 *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 2344
dkato 0:853f5b7408a7 2345 scaling_ratio = CalcScalingRatio(hw_before_scld, hw_after_scld, VDC5_ON, VDC5_ON);
dkato 0:853f5b7408a7 2346
dkato 0:853f5b7408a7 2347 *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
dkato 0:853f5b7408a7 2348 *(scaler->scl0_ds4) |= scaling_ratio;
dkato 0:853f5b7408a7 2349 } else {
dkato 0:853f5b7408a7 2350 /* OFF */
dkato 0:853f5b7408a7 2351 *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 2352 }
dkato 0:853f5b7408a7 2353
dkato 0:853f5b7408a7 2354 /* Initial scaling phase */
dkato 0:853f5b7408a7 2355 *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2356 *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2357 if (res_inter != VDC5_RES_INTER_PROGRESSIVE) {
dkato 0:853f5b7408a7 2358 /* Top */
dkato 0:853f5b7408a7 2359 *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2360 }
dkato 0:853f5b7408a7 2361
dkato 0:853f5b7408a7 2362 } /* End of function SetScalingDown() */
dkato 0:853f5b7408a7 2363
dkato 0:853f5b7408a7 2364 /**************************************************************************//**
dkato 0:853f5b7408a7 2365 * @brief Sets scaling-up
dkato 0:853f5b7408a7 2366 * @param[in] w_read_fb : Size of the frame buffer to be read
dkato 0:853f5b7408a7 2367 * @param[in] gr_grc : Graphics display area
dkato 0:853f5b7408a7 2368 * @param[in] adj_sel : Folding handling (on/off)
dkato 0:853f5b7408a7 2369 * @param[in] ip_conversion : IP conversion on/off
dkato 0:853f5b7408a7 2370 * @param[in] res_ds_wr_md : Frame buffer writing mode for image processing
dkato 0:853f5b7408a7 2371 * @param[in] ln_off_dir : Line offset address direction of the frame buffer
dkato 0:853f5b7408a7 2372 * @param[in] scaler : Scaler registers
dkato 0:853f5b7408a7 2373 * @retval None
dkato 0:853f5b7408a7 2374 ******************************************************************************/
dkato 0:853f5b7408a7 2375 static void SetScalingUp (
dkato 0:853f5b7408a7 2376 const vdc5_width_read_fb_t * const w_read_fb,
dkato 0:853f5b7408a7 2377 const vdc5_period_rect_t * const gr_grc,
dkato 0:853f5b7408a7 2378 const vdc5_onoff_t adj_sel,
dkato 0:853f5b7408a7 2379 const vdc5_onoff_t ip_conversion,
dkato 0:853f5b7408a7 2380 const vdc5_wr_md_t res_ds_wr_md,
dkato 0:853f5b7408a7 2381 const vdc5_gr_ln_off_dir_t ln_off_dir,
dkato 0:853f5b7408a7 2382 const vdc5_regaddr_scaler_t * const scaler)
dkato 0:853f5b7408a7 2383 {
dkato 0:853f5b7408a7 2384 uint32_t w_before_scl; /* Width before scaling-up */
dkato 0:853f5b7408a7 2385 uint32_t w_after_scl; /* Width after scaling-up */
dkato 0:853f5b7408a7 2386 uint32_t scaling_ratio;
dkato 0:853f5b7408a7 2387 vdc5_onoff_t vscl_up; /* Vertical scaling-up */
dkato 0:853f5b7408a7 2388
dkato 0:853f5b7408a7 2389 vscl_up = VDC5_OFF;
dkato 0:853f5b7408a7 2390
dkato 0:853f5b7408a7 2391 /* Vertical scaling-up */
dkato 0:853f5b7408a7 2392 w_before_scl = (uint32_t)w_read_fb->in_vw;
dkato 0:853f5b7408a7 2393 w_after_scl = (uint32_t)gr_grc->vw;
dkato 0:853f5b7408a7 2394 if (w_before_scl < w_after_scl) {
dkato 0:853f5b7408a7 2395 /* Vertical scaling-down: OFF, vertical scaling-up: ON */
dkato 0:853f5b7408a7 2396 *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2397 *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2398
dkato 0:853f5b7408a7 2399 scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
dkato 0:853f5b7408a7 2400 *(scaler->scl0_ds6) = scaling_ratio;
dkato 0:853f5b7408a7 2401
dkato 0:853f5b7408a7 2402 vscl_up = VDC5_ON;
dkato 0:853f5b7408a7 2403 } else {
dkato 0:853f5b7408a7 2404 /* Vertical scaling-up: OFF */
dkato 0:853f5b7408a7 2405 *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2406 }
dkato 0:853f5b7408a7 2407
dkato 0:853f5b7408a7 2408 /* Horizontal scaling-up */
dkato 0:853f5b7408a7 2409 w_before_scl = (uint32_t)w_read_fb->in_hw;
dkato 0:853f5b7408a7 2410 w_after_scl = (uint32_t)gr_grc->hw;
dkato 0:853f5b7408a7 2411 if (w_before_scl < w_after_scl) {
dkato 0:853f5b7408a7 2412 /* Horizontal scaling-up: ON */
dkato 0:853f5b7408a7 2413 *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 2414
dkato 0:853f5b7408a7 2415 scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
dkato 0:853f5b7408a7 2416
dkato 0:853f5b7408a7 2417 *(scaler->scl0_us5) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
dkato 0:853f5b7408a7 2418 *(scaler->scl0_us5) |= scaling_ratio;
dkato 0:853f5b7408a7 2419 } else {
dkato 0:853f5b7408a7 2420 /* Horizontal scaling-up: OFF */
dkato 0:853f5b7408a7 2421 *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 2422 }
dkato 0:853f5b7408a7 2423
dkato 0:853f5b7408a7 2424 /* Initial scaling phase */
dkato 0:853f5b7408a7 2425 if (ip_conversion == VDC5_OFF) {
dkato 0:853f5b7408a7 2426 *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2427 *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2428 } else {
dkato 0:853f5b7408a7 2429 if (vscl_up != VDC5_OFF) {
dkato 0:853f5b7408a7 2430 switch (res_ds_wr_md) {
dkato 0:853f5b7408a7 2431 case VDC5_WR_MD_ROT_90DEG:
dkato 0:853f5b7408a7 2432 *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2433 *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2434 /* US_HB */
dkato 0:853f5b7408a7 2435 *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE;
dkato 0:853f5b7408a7 2436 break;
dkato 0:853f5b7408a7 2437 case VDC5_WR_MD_ROT_180DEG:
dkato 0:853f5b7408a7 2438 if (ln_off_dir == VDC5_GR_LN_OFF_DIR_INC) {
dkato 0:853f5b7408a7 2439 *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2440 *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2441 /* BTM */
dkato 0:853f5b7408a7 2442 *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
dkato 0:853f5b7408a7 2443 }
dkato 0:853f5b7408a7 2444 break;
dkato 0:853f5b7408a7 2445 case VDC5_WR_MD_ROT_270DEG:
dkato 0:853f5b7408a7 2446 *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2447 *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2448 /* US_HT */
dkato 0:853f5b7408a7 2449 *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2450 break;
dkato 0:853f5b7408a7 2451 default: /* Normal or horizontal mirroring */
dkato 0:853f5b7408a7 2452 if (ln_off_dir == VDC5_GR_LN_OFF_DIR_DEC) {
dkato 0:853f5b7408a7 2453 *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2454 *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
dkato 0:853f5b7408a7 2455 /* BTM */
dkato 0:853f5b7408a7 2456 *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
dkato 0:853f5b7408a7 2457 }
dkato 0:853f5b7408a7 2458 break;
dkato 0:853f5b7408a7 2459 }
dkato 0:853f5b7408a7 2460 }
dkato 0:853f5b7408a7 2461 }
dkato 0:853f5b7408a7 2462 } /* End of function SetScalingUp() */
dkato 0:853f5b7408a7 2463
dkato 0:853f5b7408a7 2464 /**************************************************************************//**
dkato 0:853f5b7408a7 2465 * @brief Calculates scaling ratio
dkato 0:853f5b7408a7 2466 *
dkato 0:853f5b7408a7 2467 * Description:<br>
dkato 0:853f5b7408a7 2468 * In this function, the overflow in calculation is not considered.
dkato 0:853f5b7408a7 2469 * before_scl and after_scl are 11bit width, so the overflow does not occur.
dkato 0:853f5b7408a7 2470 * @param[in] before_scl : Size before scaling
dkato 0:853f5b7408a7 2471 * @param[in] after_scl : Size after scaling
dkato 0:853f5b7408a7 2472 * @param[in] adj_sel : Handling for lack of last-input pixel/line, or folding handling
dkato 0:853f5b7408a7 2473 * @param[in] round_up : Round-up on/off
dkato 0:853f5b7408a7 2474 * @retval Scaling ratio
dkato 0:853f5b7408a7 2475 ******************************************************************************/
dkato 0:853f5b7408a7 2476 static uint32_t CalcScalingRatio (
dkato 0:853f5b7408a7 2477 const uint32_t before_scl,
dkato 0:853f5b7408a7 2478 const uint32_t after_scl,
dkato 0:853f5b7408a7 2479 const vdc5_onoff_t adj_sel,
dkato 0:853f5b7408a7 2480 const vdc5_onoff_t round_up)
dkato 0:853f5b7408a7 2481 {
dkato 0:853f5b7408a7 2482 float32_t ratio;
dkato 0:853f5b7408a7 2483 float32_t sigma;
dkato 0:853f5b7408a7 2484 int32_t ratio_int;
dkato 0:853f5b7408a7 2485 uint32_t scaling_ratio;
dkato 0:853f5b7408a7 2486
dkato 0:853f5b7408a7 2487 /* When parameter checking is not performed,
dkato 0:853f5b7408a7 2488 following checks are necessary to avoid a division by zero exception and a negative number. */
dkato 0:853f5b7408a7 2489 if ((after_scl == 0u) || (after_scl == 1u)) {
dkato 0:853f5b7408a7 2490 scaling_ratio = (uint32_t)SCALING_RATIO_SAME_SIZE;
dkato 0:853f5b7408a7 2491 } else {
dkato 0:853f5b7408a7 2492 /* ratio = before_scl * 4096.0 / after_scl */
dkato 0:853f5b7408a7 2493 ratio = (float32_t)before_scl * (float32_t)SCALING_RATIO_SAME_SIZE;
dkato 0:853f5b7408a7 2494 ratio /= (float32_t)after_scl;
dkato 0:853f5b7408a7 2495
dkato 0:853f5b7408a7 2496 if (adj_sel != VDC5_OFF) {
dkato 0:853f5b7408a7 2497 sigma = ratio * ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
dkato 0:853f5b7408a7 2498 sigma -= ((float32_t)before_scl - (float32_t)VDC5_REG_FLOAT_1_0) * (float32_t)SCALING_RATIO_SAME_SIZE;
dkato 0:853f5b7408a7 2499 sigma /= ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
dkato 0:853f5b7408a7 2500 ratio -= sigma;
dkato 0:853f5b7408a7 2501 }
dkato 0:853f5b7408a7 2502
dkato 0:853f5b7408a7 2503 if (round_up == VDC5_OFF) {
dkato 0:853f5b7408a7 2504 /* Round off */
dkato 0:853f5b7408a7 2505 ratio += (float32_t)VDC5_REG_FLOAT_0_5;
dkato 0:853f5b7408a7 2506 ratio_int = (int32_t)ratio;
dkato 0:853f5b7408a7 2507 } else {
dkato 0:853f5b7408a7 2508 /* Round up */
dkato 0:853f5b7408a7 2509 ratio_int = (int32_t)ratio;
dkato 0:853f5b7408a7 2510 if ((float32_t)ratio_int < ratio) {
dkato 0:853f5b7408a7 2511 ratio_int++;
dkato 0:853f5b7408a7 2512 }
dkato 0:853f5b7408a7 2513 }
dkato 0:853f5b7408a7 2514 scaling_ratio = (uint32_t)ratio_int;
dkato 0:853f5b7408a7 2515 }
dkato 0:853f5b7408a7 2516 return scaling_ratio;
dkato 0:853f5b7408a7 2517 } /* End of function CalcScalingRatio() */
dkato 0:853f5b7408a7 2518
dkato 0:853f5b7408a7 2519 /**************************************************************************//**
dkato 0:853f5b7408a7 2520 * @brief Sets color matrix in the input controller
dkato 0:853f5b7408a7 2521 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2522 * @param[in] scaling_id : Scaling type ID
dkato 0:853f5b7408a7 2523 * @retval None
dkato 0:853f5b7408a7 2524 ******************************************************************************/
dkato 0:853f5b7408a7 2525 static void SetInputCntrlColorMtx (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
dkato 0:853f5b7408a7 2526 {
dkato 0:853f5b7408a7 2527 vdc5_channel_t channel;
dkato 0:853f5b7408a7 2528 vdc5_color_space_t color_space_input;
dkato 0:853f5b7408a7 2529 vdc5_color_space_t color_space_fb;
dkato 0:853f5b7408a7 2530 vdc5_colormtx_mode_t mtx_mode_tmp;
dkato 0:853f5b7408a7 2531 const uint16_t * offset_tmp;
dkato 0:853f5b7408a7 2532 const uint16_t * gain_tmp;
dkato 0:853f5b7408a7 2533
dkato 0:853f5b7408a7 2534 if (scaling_id == VDC5_SC_TYPE_SC0) {
dkato 0:853f5b7408a7 2535 channel = ch;
dkato 0:853f5b7408a7 2536 } else {
dkato 0:853f5b7408a7 2537 channel = (ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0;
dkato 0:853f5b7408a7 2538 }
dkato 0:853f5b7408a7 2539 color_space_input = VDC5_ShrdPrmGetColorSpace(channel);
dkato 0:853f5b7408a7 2540 color_space_fb = VDC5_ShrdPrmGetColorSpaceFbWr(ch, scaling_id);
dkato 0:853f5b7408a7 2541 /* Color matrix operating mode */
dkato 0:853f5b7408a7 2542 if (color_space_input == VDC5_COLOR_SPACE_GBR) {
dkato 0:853f5b7408a7 2543 if (color_space_fb == VDC5_COLOR_SPACE_GBR) {
dkato 0:853f5b7408a7 2544 /* GBR to GBR */
dkato 0:853f5b7408a7 2545 mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
dkato 0:853f5b7408a7 2546 } else {
dkato 0:853f5b7408a7 2547 /* GBR to YCbCr */
dkato 0:853f5b7408a7 2548 mtx_mode_tmp = VDC5_COLORMTX_GBR_YCBCR;
dkato 0:853f5b7408a7 2549 }
dkato 0:853f5b7408a7 2550 } else {
dkato 0:853f5b7408a7 2551 if (color_space_fb == VDC5_COLOR_SPACE_GBR) {
dkato 0:853f5b7408a7 2552 /* YCbCr to GBR */
dkato 0:853f5b7408a7 2553 mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
dkato 0:853f5b7408a7 2554 } else {
dkato 0:853f5b7408a7 2555 /* YCbCr to YCbCr */
dkato 0:853f5b7408a7 2556 mtx_mode_tmp = VDC5_COLORMTX_YCBCR_YCBCR;
dkato 0:853f5b7408a7 2557 }
dkato 0:853f5b7408a7 2558 }
dkato 0:853f5b7408a7 2559 /* Color matrix offset (DC) adjustment (YG, B, and R) */
dkato 0:853f5b7408a7 2560 offset_tmp = colormtx_offset_adj;
dkato 0:853f5b7408a7 2561 /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
dkato 0:853f5b7408a7 2562 gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
dkato 0:853f5b7408a7 2563
dkato 0:853f5b7408a7 2564 SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[channel][VDC5_COLORMTX_IMGCNT]);
dkato 0:853f5b7408a7 2565
dkato 0:853f5b7408a7 2566 } /* End of function SetInputCntrlColorMtx() */
dkato 0:853f5b7408a7 2567
dkato 0:853f5b7408a7 2568 /**************************************************************************//**
dkato 0:853f5b7408a7 2569 * @brief Confirms whether the graphics enlargement will occur or not
dkato 0:853f5b7408a7 2570 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 2571 * @param[in] gr_flm_sel : Frame buffer address setting signal
dkato 0:853f5b7408a7 2572 * @param[in] w_read_fb : Size of the frame buffer to be read
dkato 0:853f5b7408a7 2573 * @param[in] gr_grc : Graphics display area
dkato 0:853f5b7408a7 2574 * @retval Graphics enlargement on/off
dkato 0:853f5b7408a7 2575 ******************************************************************************/
dkato 0:853f5b7408a7 2576 static vdc5_onoff_t ConfirmGraphicsEnlargement (
dkato 0:853f5b7408a7 2577 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 2578 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 2579 const vdc5_width_read_fb_t * const w_read_fb,
dkato 0:853f5b7408a7 2580 const vdc5_period_rect_t * const gr_grc)
dkato 0:853f5b7408a7 2581 {
dkato 0:853f5b7408a7 2582 vdc5_onoff_t graphics_enlargement;
dkato 0:853f5b7408a7 2583
dkato 0:853f5b7408a7 2584 graphics_enlargement = VDC5_OFF;
dkato 0:853f5b7408a7 2585 if (gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) {
dkato 0:853f5b7408a7 2586 if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
dkato 0:853f5b7408a7 2587 if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) ||
dkato 0:853f5b7408a7 2588 ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw)) {
dkato 0:853f5b7408a7 2589 graphics_enlargement = VDC5_ON;
dkato 0:853f5b7408a7 2590 }
dkato 0:853f5b7408a7 2591 }
dkato 0:853f5b7408a7 2592 } else {
dkato 0:853f5b7408a7 2593 if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) || ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw)) {
dkato 0:853f5b7408a7 2594 graphics_enlargement = VDC5_ON;
dkato 0:853f5b7408a7 2595 }
dkato 0:853f5b7408a7 2596 }
dkato 0:853f5b7408a7 2597 return graphics_enlargement;
dkato 0:853f5b7408a7 2598 } /* End of function ConfirmGraphicsEnlargement() */
dkato 0:853f5b7408a7 2599
dkato 0:853f5b7408a7 2600 /**************************************************************************//**
dkato 0:853f5b7408a7 2601 * @brief Sets scaler for graphics
dkato 0:853f5b7408a7 2602 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2603 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 2604 * @param[in] w_read_fb : Size of the frame buffer to be read
dkato 0:853f5b7408a7 2605 * @param[in] gr_grc : Graphics display area
dkato 0:853f5b7408a7 2606 * @param[in] gr_flm_sel : Frame buffer address setting signal
dkato 0:853f5b7408a7 2607 * @param[in] gr_enlarge : Graphics enlargement on/off
dkato 0:853f5b7408a7 2608 * @retval None
dkato 0:853f5b7408a7 2609 ******************************************************************************/
dkato 0:853f5b7408a7 2610 static void SetScalerGraphics (
dkato 0:853f5b7408a7 2611 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 2612 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 2613 const vdc5_width_read_fb_t * const w_read_fb,
dkato 0:853f5b7408a7 2614 const vdc5_period_rect_t * const gr_grc,
dkato 0:853f5b7408a7 2615 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 2616 const vdc5_onoff_t gr_enlarge)
dkato 0:853f5b7408a7 2617 {
dkato 0:853f5b7408a7 2618 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 2619 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 2620 vdc5_scaling_type_t scaling_id;
dkato 0:853f5b7408a7 2621 vdc5_res_inter_t res_inter_tmp;
dkato 0:853f5b7408a7 2622 vdc5_wr_md_t res_ds_wr_md_tmp;
dkato 0:853f5b7408a7 2623 vdc5_onoff_t adj_sel_tmp;
dkato 0:853f5b7408a7 2624 vdc5_onoff_t ip_conversion;
dkato 0:853f5b7408a7 2625 uint32_t reg_data;
dkato 0:853f5b7408a7 2626 vdc5_gr_ln_off_dir_t ln_off_dir;
dkato 0:853f5b7408a7 2627
dkato 0:853f5b7408a7 2628 if (graphics_id == VDC5_GR_TYPE_GR0) {
dkato 0:853f5b7408a7 2629 /* Scaler 0 */
dkato 0:853f5b7408a7 2630 scaling_id = VDC5_SC_TYPE_SC0;
dkato 0:853f5b7408a7 2631 } else if (graphics_id == VDC5_GR_TYPE_GR1) {
dkato 0:853f5b7408a7 2632 /* Scaler 1 */
dkato 0:853f5b7408a7 2633 scaling_id = VDC5_SC_TYPE_SC1;
dkato 0:853f5b7408a7 2634 } else {
dkato 0:853f5b7408a7 2635 /* OIR */
dkato 0:853f5b7408a7 2636 scaling_id = VDC5_SC_TYPE_OIR;
dkato 0:853f5b7408a7 2637 }
dkato 0:853f5b7408a7 2638
dkato 0:853f5b7408a7 2639 scaler = &vdc5_regaddr_scaler[ch][scaling_id];
dkato 0:853f5b7408a7 2640
dkato 0:853f5b7408a7 2641 if ((gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) && (gr_enlarge == VDC5_OFF)) {
dkato 0:853f5b7408a7 2642 /* Normal graphics display */
dkato 0:853f5b7408a7 2643 /* Sync signals from the graphics processing block */
dkato 0:853f5b7408a7 2644 *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2645
dkato 0:853f5b7408a7 2646 /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
dkato 0:853f5b7408a7 2647 b13 SCL0_VEN_D
dkato 0:853f5b7408a7 2648 b4 SCL0_VEN_B */
dkato 0:853f5b7408a7 2649 *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT4);
dkato 0:853f5b7408a7 2650 } else {
dkato 0:853f5b7408a7 2651 /* Video image or graphics enlargement */
dkato 0:853f5b7408a7 2652 if (graphics_id == VDC5_GR_TYPE_OIR) {
dkato 0:853f5b7408a7 2653 /* Turn the vertical scaling-up and the horizontal scaling-up off */
dkato 0:853f5b7408a7 2654 *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_MASK_0X00000011;
dkato 0:853f5b7408a7 2655 /* Sync signals from the graphics processing block */
dkato 0:853f5b7408a7 2656 *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2657 } else {
dkato 0:853f5b7408a7 2658 /* Sync signals from the scaling-up control block */
dkato 0:853f5b7408a7 2659 *(scaler->scl0_us8) &= (uint32_t)~VDC5_REG_BIT4;
dkato 0:853f5b7408a7 2660
dkato 0:853f5b7408a7 2661 /* Graphics display area */
dkato 0:853f5b7408a7 2662 *(scaler->scl0_us2) = (uint32_t)gr_grc->vs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2663 *(scaler->scl0_us2) |= (uint32_t)gr_grc->vw;
dkato 0:853f5b7408a7 2664 *(scaler->scl0_us3) = (uint32_t)gr_grc->hs << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2665 *(scaler->scl0_us3) |= (uint32_t)gr_grc->hw;
dkato 0:853f5b7408a7 2666
dkato 0:853f5b7408a7 2667 *(scaler->scl0_us4) = (uint32_t)w_read_fb->in_vw << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 2668 *(scaler->scl0_us4) |= (uint32_t)w_read_fb->in_hw;
dkato 0:853f5b7408a7 2669
dkato 0:853f5b7408a7 2670 res_ds_wr_md_tmp = VDC5_ShrdPrmGetWritingMode(ch, scaling_id);
dkato 0:853f5b7408a7 2671 adj_sel_tmp = VDC5_ShrdPrmGetMeasureFolding(ch, graphics_id);
dkato 0:853f5b7408a7 2672 ip_conversion = VDC5_OFF;
dkato 0:853f5b7408a7 2673 if ((gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel == VDC5_GR_FLM_SEL_POINTER_BUFF)) {
dkato 0:853f5b7408a7 2674 res_inter_tmp = VDC5_ShrdPrmGetInterlace(ch, scaling_id);
dkato 0:853f5b7408a7 2675 if (res_inter_tmp != VDC5_RES_INTER_PROGRESSIVE) {
dkato 0:853f5b7408a7 2676 ip_conversion = VDC5_ON;
dkato 0:853f5b7408a7 2677 }
dkato 0:853f5b7408a7 2678 }
dkato 0:853f5b7408a7 2679
dkato 0:853f5b7408a7 2680 ln_off_dir = VDC5_ShrdPrmGetLineOfsAddrDir(ch, graphics_id);
dkato 0:853f5b7408a7 2681 /* Scaling-up */
dkato 0:853f5b7408a7 2682 SetScalingUp(w_read_fb, gr_grc, adj_sel_tmp, ip_conversion, res_ds_wr_md_tmp, ln_off_dir, scaler);
dkato 0:853f5b7408a7 2683 }
dkato 0:853f5b7408a7 2684 /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
dkato 0:853f5b7408a7 2685 b13 SCL0_VEN_D
dkato 0:853f5b7408a7 2686 b8 SCL0_UPDATE
dkato 0:853f5b7408a7 2687 b4 SCL0_VEN_B
dkato 0:853f5b7408a7 2688 b0 SCL0_VEN_A */
dkato 0:853f5b7408a7 2689 *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 2690 }
dkato 0:853f5b7408a7 2691
dkato 0:853f5b7408a7 2692 if (gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) {
dkato 0:853f5b7408a7 2693 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 2694 /* Frame buffer frame offset address */
dkato 0:853f5b7408a7 2695 reg_data = *(scaler->scl1_wr4);
dkato 0:853f5b7408a7 2696 *(img_synthesizer->gr_flm4) = reg_data;
dkato 0:853f5b7408a7 2697
dkato 0:853f5b7408a7 2698 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 2699 b0 GRx_IBUS_VEN */
dkato 0:853f5b7408a7 2700 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 2701 }
dkato 0:853f5b7408a7 2702 } /* End of function SetScalerGraphics() */
dkato 0:853f5b7408a7 2703
dkato 0:853f5b7408a7 2704 /**************************************************************************//**
dkato 0:853f5b7408a7 2705 * @brief Gets the amount of data to be skipped through
dkato 0:853f5b7408a7 2706 * @param[in] gr_base : Frame buffer base address
dkato 0:853f5b7408a7 2707 * @param[in] gr_format : Graphics format
dkato 0:853f5b7408a7 2708 * @retval The amount of data to be skipped through
dkato 0:853f5b7408a7 2709 ******************************************************************************/
dkato 0:853f5b7408a7 2710 static uint32_t DisplayStartPixelSetting (const uint32_t gr_base, const vdc5_gr_format_t gr_format)
dkato 0:853f5b7408a7 2711 {
dkato 0:853f5b7408a7 2712 uint32_t gr_sta_pos;
dkato 0:853f5b7408a7 2713 static const uint32_t bits_per_pixel[VDC5_GR_FORMAT_NUM] = {
dkato 0:853f5b7408a7 2714 VDC5_REG_BIT_PER_PIXEL_RGB565, /* RGB565 */
dkato 0:853f5b7408a7 2715 VDC5_REG_BIT_PER_PIXEL_RGB888, /* RGB888 */
dkato 0:853f5b7408a7 2716 VDC5_REG_BIT_PER_PIXEL_ARGB1555, /* ARGB1555 */
dkato 0:853f5b7408a7 2717 VDC5_REG_BIT_PER_PIXEL_ARGB4444, /* ARGB4444 */
dkato 0:853f5b7408a7 2718 VDC5_REG_BIT_PER_PIXEL_ARGB8888, /* ARGB8888 */
dkato 0:853f5b7408a7 2719 VDC5_REG_BIT_PER_PIXEL_CLUT8, /* CLUT8 */
dkato 0:853f5b7408a7 2720 VDC5_REG_BIT_PER_PIXEL_CLUT4, /* CLUT4 */
dkato 0:853f5b7408a7 2721 VDC5_REG_BIT_PER_PIXEL_CLUT1, /* CLUT1 */
dkato 0:853f5b7408a7 2722 VDC5_REG_BIT_PER_PIXEL_YCBCR422, /* YCbCr422: In the YCbCr422 format, 32 bits are used for two pixels. */
dkato 0:853f5b7408a7 2723 VDC5_REG_BIT_PER_PIXEL_YCBCR444, /* YCbCr444 */
dkato 0:853f5b7408a7 2724 VDC5_REG_BIT_PER_PIXEL_RGBA5551, /* RGBA5551 */
dkato 0:853f5b7408a7 2725 VDC5_REG_BIT_PER_PIXEL_RGBA8888 /* RGBA8888 */
dkato 0:853f5b7408a7 2726 };
dkato 0:853f5b7408a7 2727
dkato 0:853f5b7408a7 2728 gr_sta_pos = gr_base & (uint32_t)VDC5_REG_MASK_0X00000007;
dkato 0:853f5b7408a7 2729 gr_sta_pos *= (uint32_t)VDC5_REG_BIT_PER_PIXEL_VALUE_8;
dkato 0:853f5b7408a7 2730 gr_sta_pos /= bits_per_pixel[gr_format];
dkato 0:853f5b7408a7 2731 gr_sta_pos &= (uint32_t)VDC5_REG_MASK_0X0000003F;
dkato 0:853f5b7408a7 2732
dkato 0:853f5b7408a7 2733 return gr_sta_pos;
dkato 0:853f5b7408a7 2734 } /* End of function DisplayStartPixelSetting() */
dkato 0:853f5b7408a7 2735
dkato 0:853f5b7408a7 2736 /**************************************************************************//**
dkato 0:853f5b7408a7 2737 * @brief Sets cascaded connection
dkato 0:853f5b7408a7 2738 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2739 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 2740 * @param[in] gr_flm_sel : Frame buffer address setting signal
dkato 0:853f5b7408a7 2741 * @param[in] gr_enlarge : Graphics enlargement on/off
dkato 0:853f5b7408a7 2742 * @retval Cascade ON/OFF
dkato 0:853f5b7408a7 2743 ******************************************************************************/
dkato 0:853f5b7408a7 2744 static vdc5_onoff_t SetCascade (
dkato 0:853f5b7408a7 2745 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 2746 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 2747 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 2748 const vdc5_onoff_t gr_enlarge)
dkato 0:853f5b7408a7 2749 {
dkato 0:853f5b7408a7 2750 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 2751 const vdc5_regaddr_scaler_t * scaler_0;
dkato 0:853f5b7408a7 2752 const vdc5_regaddr_scaler_t * scaler_1;
dkato 0:853f5b7408a7 2753 vdc5_res_vs_in_sel_t res_vs_in_sel_tmp;
dkato 0:853f5b7408a7 2754 vdc5_onoff_t cascade;
dkato 0:853f5b7408a7 2755
dkato 0:853f5b7408a7 2756 cascade = VDC5_ShrdPrmGetCascade(ch);
dkato 0:853f5b7408a7 2757 /* Cascade */
dkato 0:853f5b7408a7 2758 if (graphics_id == VDC5_GR_TYPE_GR1) {
dkato 0:853f5b7408a7 2759 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
dkato 0:853f5b7408a7 2760 scaler_0 = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
dkato 0:853f5b7408a7 2761 scaler_1 = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
dkato 0:853f5b7408a7 2762
dkato 0:853f5b7408a7 2763 if ((gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) || (gr_enlarge != VDC5_OFF)) {
dkato 0:853f5b7408a7 2764 /* Video image or graphics enlargement */
dkato 0:853f5b7408a7 2765 /* Cascade OFF */
dkato 0:853f5b7408a7 2766 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT28;
dkato 0:853f5b7408a7 2767
dkato 0:853f5b7408a7 2768 cascade = VDC5_OFF;
dkato 0:853f5b7408a7 2769 /* Get sync signal output and full-screen enable signal select */
dkato 0:853f5b7408a7 2770 res_vs_in_sel_tmp = VDC5_ShrdPrmGetVsInSel(ch);
dkato 0:853f5b7408a7 2771 if (res_vs_in_sel_tmp == VDC5_RES_VS_IN_SEL_SC0) {
dkato 0:853f5b7408a7 2772 /* Use Vsync and enable signal output from scaler 0 */
dkato 0:853f5b7408a7 2773 *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2774 *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2775 } else {
dkato 0:853f5b7408a7 2776 /* Use Vsync and enable signal output from scaler 1 */
dkato 0:853f5b7408a7 2777 *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2778 *(scaler_1->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2779 }
dkato 0:853f5b7408a7 2780 } else {
dkato 0:853f5b7408a7 2781 /* Cascade ON */
dkato 0:853f5b7408a7 2782 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT28;
dkato 0:853f5b7408a7 2783
dkato 0:853f5b7408a7 2784 cascade = VDC5_ON;
dkato 0:853f5b7408a7 2785 /* Use Vsync and enable signal output from scaler 0 */
dkato 0:853f5b7408a7 2786 *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2787 }
dkato 0:853f5b7408a7 2788 VDC5_ShrdPrmSetCascade(ch, cascade);
dkato 0:853f5b7408a7 2789
dkato 0:853f5b7408a7 2790 /* Register update control register (SC0_SCL0_UPDATE)
dkato 0:853f5b7408a7 2791 b8 SCL0_UPDATE */
dkato 0:853f5b7408a7 2792 *(scaler_0->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2793 /* Register update control register (SC1_SCL0_UPDATE)
dkato 0:853f5b7408a7 2794 b8 SCL0_UPDATE */
dkato 0:853f5b7408a7 2795 *(scaler_1->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2796 /* Graphics register update control register (GR1_UPDATE)
dkato 0:853f5b7408a7 2797 b8 GR1_UPDATE */
dkato 0:853f5b7408a7 2798 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT8;
dkato 0:853f5b7408a7 2799 }
dkato 0:853f5b7408a7 2800 return cascade;
dkato 0:853f5b7408a7 2801 } /* End of function SetCascade() */
dkato 0:853f5b7408a7 2802
dkato 0:853f5b7408a7 2803 /**************************************************************************//**
dkato 0:853f5b7408a7 2804 * @brief Sets VIN synthesizer
dkato 0:853f5b7408a7 2805 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2806 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 2807 * @param[in] gr_flm_sel : Frame buffer address setting signal
dkato 0:853f5b7408a7 2808 * @param[in] gr_enlarge : Graphics enlargement on/off
dkato 0:853f5b7408a7 2809 * @retval None
dkato 0:853f5b7408a7 2810 ******************************************************************************/
dkato 0:853f5b7408a7 2811 static void SetupGraphicsVIN (
dkato 0:853f5b7408a7 2812 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 2813 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 2814 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 2815 const vdc5_onoff_t gr_enlarge)
dkato 0:853f5b7408a7 2816 {
dkato 0:853f5b7408a7 2817 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 2818 const vdc5_regaddr_img_synthesizer_t * img_synthesizer_vin;
dkato 0:853f5b7408a7 2819 vdc5_onoff_t cascade;
dkato 0:853f5b7408a7 2820 vdc5_resource_state_t rsrc_state;
dkato 0:853f5b7408a7 2821 vdc5_onoff_t und_sel;
dkato 0:853f5b7408a7 2822 uint32_t reg_data;
dkato 0:853f5b7408a7 2823
dkato 0:853f5b7408a7 2824 /* Cascade */
dkato 0:853f5b7408a7 2825 cascade = SetCascade(ch, graphics_id, gr_flm_sel, gr_enlarge);
dkato 0:853f5b7408a7 2826
dkato 0:853f5b7408a7 2827 /* Display area for VIN */
dkato 0:853f5b7408a7 2828 rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
dkato 0:853f5b7408a7 2829 if ((cascade == VDC5_OFF) &&
dkato 0:853f5b7408a7 2830 ((rsrc_state != VDC5_RESOURCE_ST_INVALID) || (graphics_id == VDC5_GR_TYPE_GR0))) {
dkato 0:853f5b7408a7 2831 /* Cascade connection OFF and graphics 0 is used */
dkato 0:853f5b7408a7 2832 img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
dkato 0:853f5b7408a7 2833
dkato 0:853f5b7408a7 2834 und_sel = VDC5_ShrdPrmGetUndSel(ch);
dkato 0:853f5b7408a7 2835 if (und_sel == VDC5_OFF) {
dkato 0:853f5b7408a7 2836 /* Graphics 1 is allocated to the upper-layer. */
dkato 0:853f5b7408a7 2837 *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
dkato 0:853f5b7408a7 2838
dkato 0:853f5b7408a7 2839 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
dkato 0:853f5b7408a7 2840 } else {
dkato 0:853f5b7408a7 2841 /* Graphics 0 is allocated to the upper-layer. */
dkato 0:853f5b7408a7 2842 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
dkato 0:853f5b7408a7 2843
dkato 0:853f5b7408a7 2844 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
dkato 0:853f5b7408a7 2845 }
dkato 0:853f5b7408a7 2846 /* Graphics display mode in VIN */
dkato 0:853f5b7408a7 2847 *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 2848 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BLEND;
dkato 0:853f5b7408a7 2849 /* Copy the graphics display area in the upper-layer to the VIN display area. */
dkato 0:853f5b7408a7 2850 reg_data = *(img_synthesizer->gr_ab2);
dkato 0:853f5b7408a7 2851 *(img_synthesizer_vin->gr_ab2) = reg_data;
dkato 0:853f5b7408a7 2852 reg_data = *(img_synthesizer->gr_ab3);
dkato 0:853f5b7408a7 2853 *(img_synthesizer_vin->gr_ab3) = reg_data;
dkato 0:853f5b7408a7 2854 /* The valid image area for alpha blending in a rectangular area */
dkato 0:853f5b7408a7 2855 reg_data = *(img_synthesizer_vin->gr_ab2);
dkato 0:853f5b7408a7 2856 *(img_synthesizer_vin->gr_ab4) = reg_data;
dkato 0:853f5b7408a7 2857 reg_data = *(img_synthesizer_vin->gr_ab3);
dkato 0:853f5b7408a7 2858 *(img_synthesizer_vin->gr_ab5) = reg_data;
dkato 0:853f5b7408a7 2859
dkato 0:853f5b7408a7 2860 /* Graphics register update control register (GR_VIN_UPDATE)
dkato 0:853f5b7408a7 2861 b8 GR_VIN_UPDATE
dkato 0:853f5b7408a7 2862 b4 GR_VIN_P_VEN */
dkato 0:853f5b7408a7 2863 *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
dkato 0:853f5b7408a7 2864 }
dkato 0:853f5b7408a7 2865 } /* End of function SetupGraphicsVIN() */
dkato 0:853f5b7408a7 2866
dkato 0:853f5b7408a7 2867 /**************************************************************************//**
dkato 0:853f5b7408a7 2868 * @brief Changes VIN synthesizer settings
dkato 0:853f5b7408a7 2869 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2870 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 2871 * @param[in] gr_flm_sel : Frame buffer address setting signal
dkato 0:853f5b7408a7 2872 * @param[in] gr_enlarge : Graphics enlargement on/off
dkato 0:853f5b7408a7 2873 * @retval None
dkato 0:853f5b7408a7 2874 ******************************************************************************/
dkato 0:853f5b7408a7 2875 static void ChangeGraphicsVIN (
dkato 0:853f5b7408a7 2876 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 2877 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 2878 const vdc5_gr_flm_sel_t gr_flm_sel,
dkato 0:853f5b7408a7 2879 const vdc5_onoff_t gr_enlarge)
dkato 0:853f5b7408a7 2880 {
dkato 0:853f5b7408a7 2881 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 2882 const vdc5_regaddr_img_synthesizer_t * img_synthesizer_vin;
dkato 0:853f5b7408a7 2883 vdc5_onoff_t cascade;
dkato 0:853f5b7408a7 2884 vdc5_onoff_t cascade_prev;
dkato 0:853f5b7408a7 2885 vdc5_resource_state_t rsrc_state;
dkato 0:853f5b7408a7 2886 vdc5_onoff_t und_sel;
dkato 0:853f5b7408a7 2887 uint32_t reg_data;
dkato 0:853f5b7408a7 2888
dkato 0:853f5b7408a7 2889 /* Cascade */
dkato 0:853f5b7408a7 2890 cascade_prev = VDC5_ShrdPrmGetCascade(ch);
dkato 0:853f5b7408a7 2891 cascade = SetCascade(ch, graphics_id, gr_flm_sel, gr_enlarge);
dkato 0:853f5b7408a7 2892
dkato 0:853f5b7408a7 2893 /* Display area for VIN */
dkato 0:853f5b7408a7 2894 rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
dkato 0:853f5b7408a7 2895 if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
dkato 0:853f5b7408a7 2896 /* Graphics 0 is used */
dkato 0:853f5b7408a7 2897 img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
dkato 0:853f5b7408a7 2898 if (cascade == VDC5_OFF) {
dkato 0:853f5b7408a7 2899 /* Cascade connection is OFF */
dkato 0:853f5b7408a7 2900 und_sel = VDC5_ShrdPrmGetUndSel(ch);
dkato 0:853f5b7408a7 2901 if (und_sel == VDC5_OFF) {
dkato 0:853f5b7408a7 2902 /* Graphics 1 is allocated to the upper-layer. */
dkato 0:853f5b7408a7 2903 *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
dkato 0:853f5b7408a7 2904
dkato 0:853f5b7408a7 2905 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
dkato 0:853f5b7408a7 2906 } else {
dkato 0:853f5b7408a7 2907 /* Graphics 0 is allocated to the upper-layer. */
dkato 0:853f5b7408a7 2908 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
dkato 0:853f5b7408a7 2909
dkato 0:853f5b7408a7 2910 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
dkato 0:853f5b7408a7 2911 }
dkato 0:853f5b7408a7 2912 /* Graphics display mode in VIN */
dkato 0:853f5b7408a7 2913 *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 2914 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BLEND;
dkato 0:853f5b7408a7 2915 /* Copy the graphics display area in the upper-layer to the VIN display area. */
dkato 0:853f5b7408a7 2916 reg_data = *(img_synthesizer->gr_ab2);
dkato 0:853f5b7408a7 2917 *(img_synthesizer_vin->gr_ab2) = reg_data;
dkato 0:853f5b7408a7 2918 reg_data = *(img_synthesizer->gr_ab3);
dkato 0:853f5b7408a7 2919 *(img_synthesizer_vin->gr_ab3) = reg_data;
dkato 0:853f5b7408a7 2920 } else {
dkato 0:853f5b7408a7 2921 /* Cascade connection is ON */
dkato 0:853f5b7408a7 2922 if (cascade_prev == VDC5_OFF) {
dkato 0:853f5b7408a7 2923 /* Cascade connection was turned on in this function. */
dkato 0:853f5b7408a7 2924 /* Selection of lower-layer plane in scaler is set to 1. */
dkato 0:853f5b7408a7 2925 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
dkato 0:853f5b7408a7 2926 /* Graphics display mode in VIN */
dkato 0:853f5b7408a7 2927 *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 2928 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
dkato 0:853f5b7408a7 2929 }
dkato 0:853f5b7408a7 2930 }
dkato 0:853f5b7408a7 2931 /* Graphics register update control register (GR_VIN_UPDATE)
dkato 0:853f5b7408a7 2932 b8 GR_VIN_UPDATE
dkato 0:853f5b7408a7 2933 b4 GR_VIN_P_VEN */
dkato 0:853f5b7408a7 2934 *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
dkato 0:853f5b7408a7 2935 }
dkato 0:853f5b7408a7 2936 } /* End of function ChangeGraphicsVIN() */
dkato 0:853f5b7408a7 2937
dkato 0:853f5b7408a7 2938 /**************************************************************************//**
dkato 0:853f5b7408a7 2939 * @brief Sets color matrix in the image quality improver
dkato 0:853f5b7408a7 2940 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2941 * @param[in] graphics_id : Graphics type ID
dkato 0:853f5b7408a7 2942 * @param[in] color_space : Color space (GBR or YCbCr)
dkato 0:853f5b7408a7 2943 * @retval None
dkato 0:853f5b7408a7 2944 ******************************************************************************/
dkato 0:853f5b7408a7 2945 static void SetImgQaImproverColorMtx (
dkato 0:853f5b7408a7 2946 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 2947 const vdc5_graphics_type_t graphics_id,
dkato 0:853f5b7408a7 2948 const vdc5_color_space_t color_space)
dkato 0:853f5b7408a7 2949 {
dkato 0:853f5b7408a7 2950 vdc5_colormtx_module_t module_tmp;
dkato 0:853f5b7408a7 2951 vdc5_colormtx_mode_t mtx_mode_tmp;
dkato 0:853f5b7408a7 2952 const uint16_t * offset_tmp;
dkato 0:853f5b7408a7 2953 const uint16_t * gain_tmp;
dkato 0:853f5b7408a7 2954
dkato 0:853f5b7408a7 2955 /* Color matrix operating mode */
dkato 0:853f5b7408a7 2956 if (color_space == VDC5_COLOR_SPACE_GBR) {
dkato 0:853f5b7408a7 2957 mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
dkato 0:853f5b7408a7 2958 } else {
dkato 0:853f5b7408a7 2959 mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
dkato 0:853f5b7408a7 2960 }
dkato 0:853f5b7408a7 2961 /* Color matrix module */
dkato 0:853f5b7408a7 2962 module_tmp = (graphics_id == VDC5_GR_TYPE_GR0) ? VDC5_COLORMTX_ADJ_0 : VDC5_COLORMTX_ADJ_1;
dkato 0:853f5b7408a7 2963 /* Color matrix offset (DC) adjustment (YG, B, and R) */
dkato 0:853f5b7408a7 2964 offset_tmp = colormtx_offset_adj;
dkato 0:853f5b7408a7 2965 /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
dkato 0:853f5b7408a7 2966 gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
dkato 0:853f5b7408a7 2967
dkato 0:853f5b7408a7 2968 SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[ch][module_tmp]);
dkato 0:853f5b7408a7 2969
dkato 0:853f5b7408a7 2970 } /* End of function SetImgQaImproverColorMtx() */
dkato 0:853f5b7408a7 2971
dkato 0:853f5b7408a7 2972 /**************************************************************************//**
dkato 0:853f5b7408a7 2973 * @brief Activates/deactivates frame buffer writing for scaler 0
dkato 0:853f5b7408a7 2974 * @param[in] ch : Channel
dkato 0:853f5b7408a7 2975 * @param[in] ability : Ability to enable read/write access to the memory
dkato 0:853f5b7408a7 2976 * @retval None
dkato 0:853f5b7408a7 2977 ******************************************************************************/
dkato 0:853f5b7408a7 2978 static void SetRwProcAbility_Write_0 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
dkato 0:853f5b7408a7 2979 {
dkato 0:853f5b7408a7 2980 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 2981 volatile uint32_t dummy_read;
dkato 0:853f5b7408a7 2982 uint32_t reg_data;
dkato 0:853f5b7408a7 2983
dkato 0:853f5b7408a7 2984 /* SC0/GR0 writing */
dkato 0:853f5b7408a7 2985 scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
dkato 0:853f5b7408a7 2986
dkato 0:853f5b7408a7 2987 if (ability == VDC5_OFF) {
dkato 0:853f5b7408a7 2988 /* SC0 frame buffer writing is disabled */
dkato 0:853f5b7408a7 2989 *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 2990
dkato 0:853f5b7408a7 2991 VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_0_WR);
dkato 0:853f5b7408a7 2992 } else {
dkato 0:853f5b7408a7 2993 /* SC0 frame buffer writing is enabled */
dkato 0:853f5b7408a7 2994 *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 2995 /* Reset and reset cancellation of the pointer buffer with dummy read */
dkato 0:853f5b7408a7 2996 *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 2997 reg_data = *(scaler->scl1_pbuf_cnt);
dkato 0:853f5b7408a7 2998 dummy_read = reg_data;
dkato 0:853f5b7408a7 2999 *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
dkato 0:853f5b7408a7 3000 reg_data = *(scaler->scl1_pbuf_cnt);
dkato 0:853f5b7408a7 3001 dummy_read = reg_data;
dkato 0:853f5b7408a7 3002
dkato 0:853f5b7408a7 3003 VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_0_WR);
dkato 0:853f5b7408a7 3004 }
dkato 0:853f5b7408a7 3005 } /* End of function SetRwProcAbility_Write_0() */
dkato 0:853f5b7408a7 3006
dkato 0:853f5b7408a7 3007 /**************************************************************************//**
dkato 0:853f5b7408a7 3008 * @brief Activates/deactivates frame buffer writing for scaler 1
dkato 0:853f5b7408a7 3009 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3010 * @param[in] ability : Ability to enable read/write access to the memory
dkato 0:853f5b7408a7 3011 * @retval None
dkato 0:853f5b7408a7 3012 ******************************************************************************/
dkato 0:853f5b7408a7 3013 static void SetRwProcAbility_Write_1 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
dkato 0:853f5b7408a7 3014 {
dkato 0:853f5b7408a7 3015 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 3016 volatile uint32_t dummy_read;
dkato 0:853f5b7408a7 3017 uint32_t reg_data;
dkato 0:853f5b7408a7 3018
dkato 0:853f5b7408a7 3019 /* SC1/GR1 writing */
dkato 0:853f5b7408a7 3020 scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
dkato 0:853f5b7408a7 3021
dkato 0:853f5b7408a7 3022 if (ability == VDC5_OFF) {
dkato 0:853f5b7408a7 3023 /* SC1 frame buffer writing is disabled */
dkato 0:853f5b7408a7 3024 *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3025
dkato 0:853f5b7408a7 3026 VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_1_WR);
dkato 0:853f5b7408a7 3027 } else {
dkato 0:853f5b7408a7 3028 /* SC1 frame buffer writing is enabled */
dkato 0:853f5b7408a7 3029 *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3030 /* Reset and reset cancellation of the pointer buffer with dummy read */
dkato 0:853f5b7408a7 3031 *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 3032 reg_data = *(scaler->scl1_pbuf_cnt);
dkato 0:853f5b7408a7 3033 dummy_read = reg_data;
dkato 0:853f5b7408a7 3034 *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
dkato 0:853f5b7408a7 3035 reg_data = *(scaler->scl1_pbuf_cnt);
dkato 0:853f5b7408a7 3036 dummy_read = reg_data;
dkato 0:853f5b7408a7 3037
dkato 0:853f5b7408a7 3038 VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_1_WR);
dkato 0:853f5b7408a7 3039 }
dkato 0:853f5b7408a7 3040 } /* End of function SetRwProcAbility_Write_1() */
dkato 0:853f5b7408a7 3041
dkato 0:853f5b7408a7 3042 /**************************************************************************//**
dkato 0:853f5b7408a7 3043 * @brief Activates/deactivates frame buffer writing for OIR
dkato 0:853f5b7408a7 3044 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3045 * @param[in] ability : Ability to enable read/write access to the memory
dkato 0:853f5b7408a7 3046 * @retval None
dkato 0:853f5b7408a7 3047 ******************************************************************************/
dkato 0:853f5b7408a7 3048 static void SetRwProcAbility_Write_OIR (const vdc5_channel_t ch, const vdc5_onoff_t ability)
dkato 0:853f5b7408a7 3049 {
dkato 0:853f5b7408a7 3050 const vdc5_regaddr_scaler_t * scaler;
dkato 0:853f5b7408a7 3051
dkato 0:853f5b7408a7 3052 /* OIR writing */
dkato 0:853f5b7408a7 3053 scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
dkato 0:853f5b7408a7 3054
dkato 0:853f5b7408a7 3055 if (ability == VDC5_OFF) {
dkato 0:853f5b7408a7 3056 /* OIR frame buffer writing is disabled */
dkato 0:853f5b7408a7 3057 *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3058
dkato 0:853f5b7408a7 3059 VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_OIR_WR);
dkato 0:853f5b7408a7 3060 } else {
dkato 0:853f5b7408a7 3061 /* OIR frame buffer writing is enabled */
dkato 0:853f5b7408a7 3062 *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3063
dkato 0:853f5b7408a7 3064 VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_OIR_WR);
dkato 0:853f5b7408a7 3065 }
dkato 0:853f5b7408a7 3066 } /* End of function SetRwProcAbility_Write_OIR() */
dkato 0:853f5b7408a7 3067
dkato 0:853f5b7408a7 3068 /**************************************************************************//**
dkato 0:853f5b7408a7 3069 * @brief Activates/deactivates frame buffer reading for graphics 0
dkato 0:853f5b7408a7 3070 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3071 * @param[in] ability : Ability to enable read/write access to the memory
dkato 0:853f5b7408a7 3072 * @retval None
dkato 0:853f5b7408a7 3073 ******************************************************************************/
dkato 0:853f5b7408a7 3074 static void SetRwProcAbility_Read_0 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
dkato 0:853f5b7408a7 3075 {
dkato 0:853f5b7408a7 3076 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 3077
dkato 0:853f5b7408a7 3078 /* SC0/GR0 reading */
dkato 0:853f5b7408a7 3079 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
dkato 0:853f5b7408a7 3080
dkato 0:853f5b7408a7 3081 if (ability == VDC5_OFF) {
dkato 0:853f5b7408a7 3082 /* GR0 frame buffer reading is disabled */
dkato 0:853f5b7408a7 3083 *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3084 /* Graphics display mode */
dkato 0:853f5b7408a7 3085 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 3086 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
dkato 0:853f5b7408a7 3087
dkato 0:853f5b7408a7 3088 VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_0_RD);
dkato 0:853f5b7408a7 3089 } else {
dkato 0:853f5b7408a7 3090 /* GR0 frame buffer reading is enabled */
dkato 0:853f5b7408a7 3091 *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3092
dkato 0:853f5b7408a7 3093 VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_0_RD);
dkato 0:853f5b7408a7 3094 }
dkato 0:853f5b7408a7 3095 } /* End of function SetRwProcAbility_Read_0() */
dkato 0:853f5b7408a7 3096
dkato 0:853f5b7408a7 3097 /**************************************************************************//**
dkato 0:853f5b7408a7 3098 * @brief Activates/deactivates frame buffer reading for graphics 1
dkato 0:853f5b7408a7 3099 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3100 * @param[in] ability : Ability to enable read/write access to the memory
dkato 0:853f5b7408a7 3101 * @retval None
dkato 0:853f5b7408a7 3102 ******************************************************************************/
dkato 0:853f5b7408a7 3103 static void SetRwProcAbility_Read_1 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
dkato 0:853f5b7408a7 3104 {
dkato 0:853f5b7408a7 3105 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 3106
dkato 0:853f5b7408a7 3107 /* SC1/GR1 reading */
dkato 0:853f5b7408a7 3108 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
dkato 0:853f5b7408a7 3109
dkato 0:853f5b7408a7 3110 if (ability == VDC5_OFF) {
dkato 0:853f5b7408a7 3111 /* GR1 frame buffer reading is disabled */
dkato 0:853f5b7408a7 3112 *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3113 /* Graphics display mode */
dkato 0:853f5b7408a7 3114 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 3115 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
dkato 0:853f5b7408a7 3116
dkato 0:853f5b7408a7 3117 VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_1_RD);
dkato 0:853f5b7408a7 3118 } else {
dkato 0:853f5b7408a7 3119 /* GR1 frame buffer reading is enabled */
dkato 0:853f5b7408a7 3120 *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3121
dkato 0:853f5b7408a7 3122 VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_1_RD);
dkato 0:853f5b7408a7 3123 }
dkato 0:853f5b7408a7 3124 } /* End of function SetRwProcAbility_Read_1() */
dkato 0:853f5b7408a7 3125
dkato 0:853f5b7408a7 3126 /**************************************************************************//**
dkato 0:853f5b7408a7 3127 * @brief Activates/deactivates frame buffer reading for graphics 2
dkato 0:853f5b7408a7 3128 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3129 * @param[in] ability : Ability to enable read/write access to the memory
dkato 0:853f5b7408a7 3130 * @retval None
dkato 0:853f5b7408a7 3131 ******************************************************************************/
dkato 0:853f5b7408a7 3132 static void SetRwProcAbility_Read_2 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
dkato 0:853f5b7408a7 3133 {
dkato 0:853f5b7408a7 3134 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 3135
dkato 0:853f5b7408a7 3136 /* GR2 reading */
dkato 0:853f5b7408a7 3137 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2];
dkato 0:853f5b7408a7 3138
dkato 0:853f5b7408a7 3139 if (ability == VDC5_OFF) {
dkato 0:853f5b7408a7 3140 /* GR2 frame buffer reading is disabled */
dkato 0:853f5b7408a7 3141 *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3142 /* Graphics display mode */
dkato 0:853f5b7408a7 3143 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 3144 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
dkato 0:853f5b7408a7 3145
dkato 0:853f5b7408a7 3146 VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_2_RD);
dkato 0:853f5b7408a7 3147 } else {
dkato 0:853f5b7408a7 3148 /* GR2 frame buffer reading is enabled */
dkato 0:853f5b7408a7 3149 *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3150
dkato 0:853f5b7408a7 3151 VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_2_RD);
dkato 0:853f5b7408a7 3152 }
dkato 0:853f5b7408a7 3153 } /* End of function SetRwProcAbility_Read_2() */
dkato 0:853f5b7408a7 3154
dkato 0:853f5b7408a7 3155 /**************************************************************************//**
dkato 0:853f5b7408a7 3156 * @brief Activates/deactivates frame buffer reading for graphics 3
dkato 0:853f5b7408a7 3157 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3158 * @param[in] ability : Ability to enable read/write access to the memory
dkato 0:853f5b7408a7 3159 * @retval None
dkato 0:853f5b7408a7 3160 ******************************************************************************/
dkato 0:853f5b7408a7 3161 static void SetRwProcAbility_Read_3 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
dkato 0:853f5b7408a7 3162 {
dkato 0:853f5b7408a7 3163 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 3164
dkato 0:853f5b7408a7 3165 /* GR3 reading */
dkato 0:853f5b7408a7 3166 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3];
dkato 0:853f5b7408a7 3167
dkato 0:853f5b7408a7 3168 if (ability == VDC5_OFF) {
dkato 0:853f5b7408a7 3169 /* GR3 frame buffer reading is disabled */
dkato 0:853f5b7408a7 3170 *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3171 /* Graphics display mode */
dkato 0:853f5b7408a7 3172 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 3173 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
dkato 0:853f5b7408a7 3174
dkato 0:853f5b7408a7 3175 VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_3_RD);
dkato 0:853f5b7408a7 3176 } else {
dkato 0:853f5b7408a7 3177 /* GR3 frame buffer reading is enabled */
dkato 0:853f5b7408a7 3178 *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3179
dkato 0:853f5b7408a7 3180 VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_3_RD);
dkato 0:853f5b7408a7 3181 }
dkato 0:853f5b7408a7 3182 } /* End of function SetRwProcAbility_Read_3() */
dkato 0:853f5b7408a7 3183
dkato 0:853f5b7408a7 3184 /**************************************************************************//**
dkato 0:853f5b7408a7 3185 * @brief Activates/deactivates frame buffer reading for OIR
dkato 0:853f5b7408a7 3186 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3187 * @param[in] ability : Ability to enable read/write access to the memory
dkato 0:853f5b7408a7 3188 * @retval None
dkato 0:853f5b7408a7 3189 ******************************************************************************/
dkato 0:853f5b7408a7 3190 static void SetRwProcAbility_Read_OIR (const vdc5_channel_t ch, const vdc5_onoff_t ability)
dkato 0:853f5b7408a7 3191 {
dkato 0:853f5b7408a7 3192 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 3193
dkato 0:853f5b7408a7 3194 /* OIR reading */
dkato 0:853f5b7408a7 3195 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR];
dkato 0:853f5b7408a7 3196
dkato 0:853f5b7408a7 3197 if (ability == VDC5_OFF) {
dkato 0:853f5b7408a7 3198 /* OIR frame buffer reading is disabled */
dkato 0:853f5b7408a7 3199 *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3200 /* Graphics display mode */
dkato 0:853f5b7408a7 3201 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 3202 *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
dkato 0:853f5b7408a7 3203
dkato 0:853f5b7408a7 3204 VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_OIR_RD);
dkato 0:853f5b7408a7 3205 } else {
dkato 0:853f5b7408a7 3206 /* OIR frame buffer reading is enabled */
dkato 0:853f5b7408a7 3207 *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3208
dkato 0:853f5b7408a7 3209 VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_OIR_RD);
dkato 0:853f5b7408a7 3210 }
dkato 0:853f5b7408a7 3211 } /* End of function SetRwProcAbility_Read_OIR() */
dkato 0:853f5b7408a7 3212
dkato 0:853f5b7408a7 3213 /**************************************************************************//**
dkato 0:853f5b7408a7 3214 * @brief Sets register update control register to update the frame buffer
dkato 0:853f5b7408a7 3215 * read and write enable settings.
dkato 0:853f5b7408a7 3216 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3217 * @param[in] layer_id : Layer ID
dkato 0:853f5b7408a7 3218 * @retval None
dkato 0:853f5b7408a7 3219 ******************************************************************************/
dkato 0:853f5b7408a7 3220 static void SetRegUpdateRwEnable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
dkato 0:853f5b7408a7 3221 {
dkato 0:853f5b7408a7 3222 volatile uint32_t * scl1_update_reg;
dkato 0:853f5b7408a7 3223 volatile uint32_t * gr_update_reg;
dkato 0:853f5b7408a7 3224
dkato 0:853f5b7408a7 3225 switch (layer_id) {
dkato 0:853f5b7408a7 3226 case VDC5_LAYER_ID_0_WR: /* Layer 0, write process */
dkato 0:853f5b7408a7 3227 scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl1_update;
dkato 0:853f5b7408a7 3228 *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3229 break;
dkato 0:853f5b7408a7 3230 case VDC5_LAYER_ID_1_WR: /* Layer 1, write process */
dkato 0:853f5b7408a7 3231 scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl1_update;
dkato 0:853f5b7408a7 3232 *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3233 break;
dkato 0:853f5b7408a7 3234 case VDC5_LAYER_ID_OIR_WR: /* Layer OIR, write process */
dkato 0:853f5b7408a7 3235 scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl1_update;
dkato 0:853f5b7408a7 3236 *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3237 break;
dkato 0:853f5b7408a7 3238 case VDC5_LAYER_ID_0_RD: /* Layer 0, read process */
dkato 0:853f5b7408a7 3239 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
dkato 0:853f5b7408a7 3240 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3241 break;
dkato 0:853f5b7408a7 3242 case VDC5_LAYER_ID_1_RD: /* Layer 1, read process */
dkato 0:853f5b7408a7 3243 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
dkato 0:853f5b7408a7 3244 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3245 break;
dkato 0:853f5b7408a7 3246 case VDC5_LAYER_ID_2_RD: /* Layer 2, read process */
dkato 0:853f5b7408a7 3247 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2].gr_update;
dkato 0:853f5b7408a7 3248 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3249 break;
dkato 0:853f5b7408a7 3250 case VDC5_LAYER_ID_3_RD: /* Layer 3, read process */
dkato 0:853f5b7408a7 3251 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
dkato 0:853f5b7408a7 3252 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3253 break;
dkato 0:853f5b7408a7 3254 case VDC5_LAYER_ID_OIR_RD: /* Layer OIR, read process */
dkato 0:853f5b7408a7 3255 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
dkato 0:853f5b7408a7 3256 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3257 break;
dkato 0:853f5b7408a7 3258
dkato 0:853f5b7408a7 3259 case VDC5_LAYER_ID_ALL: /* All */
dkato 0:853f5b7408a7 3260 /* Register update control register (SCx_SCL1_UPDATE)
dkato 0:853f5b7408a7 3261 b20 SCL1_UPDATE_B
dkato 0:853f5b7408a7 3262 b4 SCL1_VEN_B
dkato 0:853f5b7408a7 3263 b0 SCL1_VEN_A */
dkato 0:853f5b7408a7 3264 scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl1_update;
dkato 0:853f5b7408a7 3265 *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3266 scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl1_update;
dkato 0:853f5b7408a7 3267 *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3268 /* Register update control register (OIR_SCL1_UPDATE)
dkato 0:853f5b7408a7 3269 b4 SCL1_VEN_B
dkato 0:853f5b7408a7 3270 b0 SCL1_VEN_A */
dkato 0:853f5b7408a7 3271 scl1_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl1_update;
dkato 0:853f5b7408a7 3272 *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3273 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 3274 b4 GRx_P_VEN
dkato 0:853f5b7408a7 3275 b0 GRx_IBUS_VEN */
dkato 0:853f5b7408a7 3276 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
dkato 0:853f5b7408a7 3277 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3278 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
dkato 0:853f5b7408a7 3279 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3280 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2].gr_update;
dkato 0:853f5b7408a7 3281 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3282 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
dkato 0:853f5b7408a7 3283 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3284 gr_update_reg = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
dkato 0:853f5b7408a7 3285 *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
dkato 0:853f5b7408a7 3286 break;
dkato 0:853f5b7408a7 3287
dkato 0:853f5b7408a7 3288 default:
dkato 0:853f5b7408a7 3289 /* DO NOTHING */
dkato 0:853f5b7408a7 3290 break;
dkato 0:853f5b7408a7 3291 }
dkato 0:853f5b7408a7 3292 } /* End of function SetRegUpdateRwEnable() */
dkato 0:853f5b7408a7 3293
dkato 0:853f5b7408a7 3294 /**************************************************************************//**
dkato 0:853f5b7408a7 3295 * @brief Sets graphics display mode
dkato 0:853f5b7408a7 3296 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3297 * @param[in] layer_id : Layer ID
dkato 0:853f5b7408a7 3298 * @param[in] gr_disp_sel : Graphics display mode
dkato 0:853f5b7408a7 3299 * @retval None
dkato 0:853f5b7408a7 3300 ******************************************************************************/
dkato 0:853f5b7408a7 3301 static void SetGraphicsDisplayMode (
dkato 0:853f5b7408a7 3302 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 3303 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 3304 const vdc5_gr_disp_sel_t * const gr_disp_sel)
dkato 0:853f5b7408a7 3305 {
dkato 0:853f5b7408a7 3306 uint32_t graphics_id;
dkato 0:853f5b7408a7 3307 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 3308
dkato 0:853f5b7408a7 3309 if (layer_id == VDC5_LAYER_ID_ALL) {
dkato 0:853f5b7408a7 3310 for (graphics_id = 0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++) {
dkato 0:853f5b7408a7 3311 if ((graphics_id != VDC5_GR_TYPE_VIN) && (gr_disp_sel[graphics_id] != VDC5_DISPSEL_IGNORED)) {
dkato 0:853f5b7408a7 3312 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 3313
dkato 0:853f5b7408a7 3314 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 3315 *(img_synthesizer->gr_ab1) |= (uint32_t)gr_disp_sel[graphics_id];
dkato 0:853f5b7408a7 3316 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 3317 b4 GRx_P_VEN */
dkato 0:853f5b7408a7 3318 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 3319 }
dkato 0:853f5b7408a7 3320 }
dkato 0:853f5b7408a7 3321 } else if ((layer_id >= VDC5_LAYER_ID_0_RD) && (layer_id <= VDC5_LAYER_ID_OIR_RD)) {
dkato 0:853f5b7408a7 3322 if (*gr_disp_sel != VDC5_DISPSEL_IGNORED) {
dkato 0:853f5b7408a7 3323 graphics_id = (uint32_t)(layer_id - VDC5_SC_TYPE_NUM);
dkato 0:853f5b7408a7 3324
dkato 0:853f5b7408a7 3325 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
dkato 0:853f5b7408a7 3326
dkato 0:853f5b7408a7 3327 *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
dkato 0:853f5b7408a7 3328 *(img_synthesizer->gr_ab1) |= (uint32_t)*gr_disp_sel;
dkato 0:853f5b7408a7 3329 /* Graphics register update control register (GRx_UPDATE)
dkato 0:853f5b7408a7 3330 b4 GRx_P_VEN */
dkato 0:853f5b7408a7 3331 *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
dkato 0:853f5b7408a7 3332 }
dkato 0:853f5b7408a7 3333 } else {
dkato 0:853f5b7408a7 3334 /* Do nothing */
dkato 0:853f5b7408a7 3335 }
dkato 0:853f5b7408a7 3336 } /* End of function SetGraphicsDisplayMode() */
dkato 0:853f5b7408a7 3337
dkato 0:853f5b7408a7 3338 /**************************************************************************//**
dkato 0:853f5b7408a7 3339 * @brief Sets color matrix
dkato 0:853f5b7408a7 3340 * @param[in] mtx_mode : Operating mode
dkato 0:853f5b7408a7 3341 * @param[in] offset : Offset (DC) adjustment of Y/G, B, and R signal
dkato 0:853f5b7408a7 3342 * @param[in] gain : GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment
dkato 0:853f5b7408a7 3343 * @param[in] color_matrix : Color matrix registers
dkato 0:853f5b7408a7 3344 * @retval None
dkato 0:853f5b7408a7 3345 ******************************************************************************/
dkato 0:853f5b7408a7 3346 static void SetColorMatrix (
dkato 0:853f5b7408a7 3347 const vdc5_colormtx_mode_t mtx_mode,
dkato 0:853f5b7408a7 3348 const uint16_t * const offset,
dkato 0:853f5b7408a7 3349 const uint16_t * const gain,
dkato 0:853f5b7408a7 3350 const vdc5_regaddr_color_matrix_t * const color_matrix)
dkato 0:853f5b7408a7 3351 {
dkato 0:853f5b7408a7 3352 /* Operating mode */
dkato 0:853f5b7408a7 3353 *(color_matrix->mtx_mode) = (uint32_t)mtx_mode;
dkato 0:853f5b7408a7 3354
dkato 0:853f5b7408a7 3355 /* Offset (DC) adjustment of Y/G, B, and R signal and
dkato 0:853f5b7408a7 3356 GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
dkato 0:853f5b7408a7 3357 *(color_matrix->mtx_yg_adj0) = (uint32_t)offset[VDC5_COLORMTX_OFFST_YG] << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3358 *(color_matrix->mtx_yg_adj0) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GG];
dkato 0:853f5b7408a7 3359 *(color_matrix->mtx_yg_adj1) = (uint32_t)gain[VDC5_COLORMTX_GAIN_GB] << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3360 *(color_matrix->mtx_yg_adj1) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GR];
dkato 0:853f5b7408a7 3361 *(color_matrix->mtx_cbb_adj0) = (uint32_t)offset[VDC5_COLORMTX_OFFST_B] << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3362 *(color_matrix->mtx_cbb_adj0) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BG];
dkato 0:853f5b7408a7 3363 *(color_matrix->mtx_cbb_adj1) = (uint32_t)gain[VDC5_COLORMTX_GAIN_BB] << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3364 *(color_matrix->mtx_cbb_adj1) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BR];
dkato 0:853f5b7408a7 3365 *(color_matrix->mtx_crr_adj0) = (uint32_t)offset[VDC5_COLORMTX_OFFST_R] << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3366 *(color_matrix->mtx_crr_adj0) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RG];
dkato 0:853f5b7408a7 3367 *(color_matrix->mtx_crr_adj1) = (uint32_t)gain[VDC5_COLORMTX_GAIN_RB] << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3368 *(color_matrix->mtx_crr_adj1) |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RR];
dkato 0:853f5b7408a7 3369
dkato 0:853f5b7408a7 3370 /* Register update control register (IMGCNT_UPDATE/ADJx_UPDATE)
dkato 0:853f5b7408a7 3371 b0 IMGCNT_VEN/ADJx_VEN */
dkato 0:853f5b7408a7 3372 *(color_matrix->mtx_update) |= (uint32_t)VDC5_REG_BIT0;
dkato 0:853f5b7408a7 3373
dkato 0:853f5b7408a7 3374 } /* End of function SetColorMatrix() */
dkato 0:853f5b7408a7 3375
dkato 0:853f5b7408a7 3376 /**************************************************************************//**
dkato 0:853f5b7408a7 3377 * @brief Sets sharpness
dkato 0:853f5b7408a7 3378 * @param[in] shp_h_on : Sharpness ON/OFF setting
dkato 0:853f5b7408a7 3379 * @param[in] sharp_param : Sharpness ON/OFF setting
dkato 0:853f5b7408a7 3380 * @param[in] img_qlty_imp : Image quality improver registers
dkato 0:853f5b7408a7 3381 * @retval None
dkato 0:853f5b7408a7 3382 ******************************************************************************/
dkato 0:853f5b7408a7 3383 static void SetImageEnhancementSharpness (
dkato 0:853f5b7408a7 3384 const vdc5_onoff_t shp_h_on,
dkato 0:853f5b7408a7 3385 const vdc5_enhance_sharp_t * const sharp_param,
dkato 0:853f5b7408a7 3386 const vdc5_regaddr_img_qlty_imp_t * const img_qlty_imp)
dkato 0:853f5b7408a7 3387 {
dkato 0:853f5b7408a7 3388 const vdc5_sharpness_ctrl_t * sharpness_ctrl;
dkato 0:853f5b7408a7 3389
dkato 0:853f5b7408a7 3390 if (sharp_param != NULL) {
dkato 0:853f5b7408a7 3391 /* H1, adjacent pixel used as reference */
dkato 0:853f5b7408a7 3392 sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1];
dkato 0:853f5b7408a7 3393 /* Active sharpness range */
dkato 0:853f5b7408a7 3394 *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
dkato 0:853f5b7408a7 3395 *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)sharpness_ctrl->shp_core;
dkato 0:853f5b7408a7 3396 /* Sharpness correction value clipping and sharpness edge amplitude value gain */
dkato 0:853f5b7408a7 3397 *(img_qlty_imp->adj_enh_shp2) = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 3398 *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3399 *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 3400 *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_u;
dkato 0:853f5b7408a7 3401
dkato 0:853f5b7408a7 3402 /* H2, second adjacent pixel used as reference */
dkato 0:853f5b7408a7 3403 sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2];
dkato 0:853f5b7408a7 3404 /* LPF selection for folding prevention before H2 edge detection */
dkato 0:853f5b7408a7 3405 if (sharp_param->shp_h2_lpf_sel == VDC5_OFF) {
dkato 0:853f5b7408a7 3406 *(img_qlty_imp->adj_enh_shp3) = (uint32_t)0x00000000u;
dkato 0:853f5b7408a7 3407 } else {
dkato 0:853f5b7408a7 3408 *(img_qlty_imp->adj_enh_shp3) = (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 3409 }
dkato 0:853f5b7408a7 3410 /* Active sharpness range */
dkato 0:853f5b7408a7 3411 *(img_qlty_imp->adj_enh_shp3) |= (uint32_t)sharpness_ctrl->shp_core;
dkato 0:853f5b7408a7 3412 /* Sharpness correction value clipping and sharpness edge amplitude value gain */
dkato 0:853f5b7408a7 3413 *(img_qlty_imp->adj_enh_shp4) = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 3414 *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3415 *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 3416 *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_u;
dkato 0:853f5b7408a7 3417
dkato 0:853f5b7408a7 3418 /* H3, third adjacent pixel used as reference */
dkato 0:853f5b7408a7 3419 sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3];
dkato 0:853f5b7408a7 3420 /* Active sharpness range */
dkato 0:853f5b7408a7 3421 *(img_qlty_imp->adj_enh_shp5) = (uint32_t)sharpness_ctrl->shp_core;
dkato 0:853f5b7408a7 3422 /* Sharpness correction value clipping and sharpness edge amplitude value gain */
dkato 0:853f5b7408a7 3423 *(img_qlty_imp->adj_enh_shp6) = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 3424 *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3425 *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 3426 *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_u;
dkato 0:853f5b7408a7 3427 }
dkato 0:853f5b7408a7 3428
dkato 0:853f5b7408a7 3429 if (shp_h_on == VDC5_OFF) {
dkato 0:853f5b7408a7 3430 *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_BIT16;
dkato 0:853f5b7408a7 3431 } else {
dkato 0:853f5b7408a7 3432 *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)VDC5_REG_BIT16;
dkato 0:853f5b7408a7 3433 }
dkato 0:853f5b7408a7 3434 } /* End of function SetImageEnhancementSharpness() */
dkato 0:853f5b7408a7 3435
dkato 0:853f5b7408a7 3436 /**************************************************************************//**
dkato 0:853f5b7408a7 3437 * @brief Sets LTI
dkato 0:853f5b7408a7 3438 * @param[in] lti_h_on : LTI ON/OFF setting
dkato 0:853f5b7408a7 3439 * @param[in] lti_param : LTI setup parameter
dkato 0:853f5b7408a7 3440 * @param[in] img_qlty_imp : Image quality improver registers
dkato 0:853f5b7408a7 3441 * @retval None
dkato 0:853f5b7408a7 3442 ******************************************************************************/
dkato 0:853f5b7408a7 3443 static void SetImageEnhancementLti (
dkato 0:853f5b7408a7 3444 const vdc5_onoff_t lti_h_on,
dkato 0:853f5b7408a7 3445 const vdc5_enhance_lti_t * const lti_param,
dkato 0:853f5b7408a7 3446 const vdc5_regaddr_img_qlty_imp_t * const img_qlty_imp)
dkato 0:853f5b7408a7 3447 {
dkato 0:853f5b7408a7 3448 const vdc5_lti_ctrl_t * lti_ctrl;
dkato 0:853f5b7408a7 3449
dkato 0:853f5b7408a7 3450 if (lti_param != NULL) {
dkato 0:853f5b7408a7 3451 /* H2, second adjacent pixel used as reference */
dkato 0:853f5b7408a7 3452 lti_ctrl = &lti_param->lti[VDC5_IMGENH_LTI1];
dkato 0:853f5b7408a7 3453 /* LPF selection for folding prevention before H2 edge detection */
dkato 0:853f5b7408a7 3454 if (lti_param->lti_h2_lpf_sel == VDC5_OFF) {
dkato 0:853f5b7408a7 3455 *(img_qlty_imp->adj_enh_lti1) = (uint32_t)0x00000000u;
dkato 0:853f5b7408a7 3456 } else {
dkato 0:853f5b7408a7 3457 *(img_qlty_imp->adj_enh_lti1) = (uint32_t)VDC5_REG_BIT24;
dkato 0:853f5b7408a7 3458 }
dkato 0:853f5b7408a7 3459 /* Median filter LTI correction threshold */
dkato 0:853f5b7408a7 3460 *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
dkato 0:853f5b7408a7 3461 /* LTI edge amplitude value gain */
dkato 0:853f5b7408a7 3462 *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
dkato 0:853f5b7408a7 3463 /* LTI coring (maximum core value of 255) */
dkato 0:853f5b7408a7 3464 *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)lti_ctrl->lti_core;
dkato 0:853f5b7408a7 3465
dkato 0:853f5b7408a7 3466 /* H4, fourth adjacent pixel used as reference */
dkato 0:853f5b7408a7 3467 lti_ctrl = &lti_param->lti[VDC5_IMGENH_LTI2];
dkato 0:853f5b7408a7 3468 /* Median filter reference pixel select */
dkato 0:853f5b7408a7 3469 if (lti_param->lti_h4_median_tap_sel == VDC5_LTI_MDFIL_SEL_ADJ2) {
dkato 0:853f5b7408a7 3470 *(img_qlty_imp->adj_enh_lti2) = (uint32_t)0x00000000u;
dkato 0:853f5b7408a7 3471 } else {
dkato 0:853f5b7408a7 3472 *(img_qlty_imp->adj_enh_lti2) = (uint32_t)VDC5_REG_BIT24;
dkato 0:853f5b7408a7 3473 }
dkato 0:853f5b7408a7 3474 /* Median filter LTI correction threshold */
dkato 0:853f5b7408a7 3475 *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
dkato 0:853f5b7408a7 3476 /* LTI edge amplitude value gain */
dkato 0:853f5b7408a7 3477 *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
dkato 0:853f5b7408a7 3478 /* LTI coring (maximum core value of 255) */
dkato 0:853f5b7408a7 3479 *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)lti_ctrl->lti_core;
dkato 0:853f5b7408a7 3480 }
dkato 0:853f5b7408a7 3481
dkato 0:853f5b7408a7 3482 if (lti_h_on == VDC5_OFF) {
dkato 0:853f5b7408a7 3483 *(img_qlty_imp->adj_enh_lti1) &= (uint32_t)~VDC5_REG_BIT31;
dkato 0:853f5b7408a7 3484 } else {
dkato 0:853f5b7408a7 3485 *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)VDC5_REG_BIT31;
dkato 0:853f5b7408a7 3486 }
dkato 0:853f5b7408a7 3487 } /* End of function SetImageEnhancementLti() */
dkato 0:853f5b7408a7 3488
dkato 0:853f5b7408a7 3489 /**************************************************************************//**
dkato 0:853f5b7408a7 3490 * @brief Sets alpha blending area of a rectangle
dkato 0:853f5b7408a7 3491 * @param[in] pd_disp_rect : Rectangular area for alpha blending
dkato 0:853f5b7408a7 3492 * @param[in] img_synthesizer : Image synthesizer registers
dkato 0:853f5b7408a7 3493 * @retval None
dkato 0:853f5b7408a7 3494 ******************************************************************************/
dkato 0:853f5b7408a7 3495 static void SetAlphaRectArea (
dkato 0:853f5b7408a7 3496 const vdc5_pd_disp_rect_t * const pd_disp_rect,
dkato 0:853f5b7408a7 3497 const vdc5_regaddr_img_synthesizer_t * const img_synthesizer)
dkato 0:853f5b7408a7 3498 {
dkato 0:853f5b7408a7 3499 uint32_t v_start;
dkato 0:853f5b7408a7 3500 uint32_t h_start;
dkato 0:853f5b7408a7 3501
dkato 0:853f5b7408a7 3502 if (pd_disp_rect != NULL) {
dkato 0:853f5b7408a7 3503 v_start = *(img_synthesizer->gr_ab2) >> VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3504 h_start = *(img_synthesizer->gr_ab3) >> VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3505
dkato 0:853f5b7408a7 3506 v_start += (uint32_t)pd_disp_rect->vs_rel;
dkato 0:853f5b7408a7 3507 h_start += (uint32_t)pd_disp_rect->hs_rel;
dkato 0:853f5b7408a7 3508 /* If the start position exceeds the maximum bit width, the value should be saturated. */
dkato 0:853f5b7408a7 3509 if ((v_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u) {
dkato 0:853f5b7408a7 3510 v_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
dkato 0:853f5b7408a7 3511 }
dkato 0:853f5b7408a7 3512 if ((h_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u) {
dkato 0:853f5b7408a7 3513 h_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
dkato 0:853f5b7408a7 3514 }
dkato 0:853f5b7408a7 3515
dkato 0:853f5b7408a7 3516 *(img_synthesizer->gr_ab4) = (v_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->vw_rel;
dkato 0:853f5b7408a7 3517 *(img_synthesizer->gr_ab5) = (h_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->hw_rel;
dkato 0:853f5b7408a7 3518 }
dkato 0:853f5b7408a7 3519 } /* End of function SetAlphaRectArea() */
dkato 0:853f5b7408a7 3520
dkato 0:853f5b7408a7 3521 /**************************************************************************//**
dkato 0:853f5b7408a7 3522 * @brief Sets upper-layer and lower-layer plane in scaler
dkato 0:853f5b7408a7 3523 * @param[in] ch : Channel
dkato 0:853f5b7408a7 3524 * @param[in] und_sel : Selection of lower-layer plane in scaler
dkato 0:853f5b7408a7 3525 * @retval None
dkato 0:853f5b7408a7 3526 *****************************************************************************/
dkato 0:853f5b7408a7 3527 static void SetUndSel (const vdc5_channel_t ch, const vdc5_onoff_t und_sel)
dkato 0:853f5b7408a7 3528 {
dkato 0:853f5b7408a7 3529 const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
dkato 0:853f5b7408a7 3530 const vdc5_regaddr_img_synthesizer_t * img_synthesizer_vin;
dkato 0:853f5b7408a7 3531 vdc5_onoff_t current_und_sel;
dkato 0:853f5b7408a7 3532 vdc5_onoff_t cascade;
dkato 0:853f5b7408a7 3533 vdc5_resource_state_t rsrc_state;
dkato 0:853f5b7408a7 3534 uint32_t reg_data;
dkato 0:853f5b7408a7 3535
dkato 0:853f5b7408a7 3536 current_und_sel = VDC5_ShrdPrmGetUndSel(ch);
dkato 0:853f5b7408a7 3537 if (und_sel != current_und_sel) {
dkato 0:853f5b7408a7 3538 VDC5_ShrdPrmSetUndSel(ch, und_sel);
dkato 0:853f5b7408a7 3539
dkato 0:853f5b7408a7 3540 cascade = VDC5_ShrdPrmGetCascade(ch);
dkato 0:853f5b7408a7 3541 rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
dkato 0:853f5b7408a7 3542 if ((cascade == VDC5_OFF) && (rsrc_state != VDC5_RESOURCE_ST_INVALID)) {
dkato 0:853f5b7408a7 3543 /* Cascade connection OFF and graphics 0 is used */
dkato 0:853f5b7408a7 3544 img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
dkato 0:853f5b7408a7 3545 if (und_sel == VDC5_OFF) {
dkato 0:853f5b7408a7 3546 /* Graphics 1 is allocated to the upper-layer. */
dkato 0:853f5b7408a7 3547 *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
dkato 0:853f5b7408a7 3548
dkato 0:853f5b7408a7 3549 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
dkato 0:853f5b7408a7 3550 } else {
dkato 0:853f5b7408a7 3551 /* Graphics 0 is allocated to the upper-layer. */
dkato 0:853f5b7408a7 3552 *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
dkato 0:853f5b7408a7 3553
dkato 0:853f5b7408a7 3554 img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
dkato 0:853f5b7408a7 3555 }
dkato 0:853f5b7408a7 3556 /* Copy the graphics display area in the upper-layer to the VIN display area. */
dkato 0:853f5b7408a7 3557 reg_data = *(img_synthesizer->gr_ab2);
dkato 0:853f5b7408a7 3558 *(img_synthesizer_vin->gr_ab2) = reg_data;
dkato 0:853f5b7408a7 3559 reg_data = *(img_synthesizer->gr_ab3);
dkato 0:853f5b7408a7 3560 *(img_synthesizer_vin->gr_ab3) = reg_data;
dkato 0:853f5b7408a7 3561
dkato 0:853f5b7408a7 3562 /* Graphics register update control register (GR_VIN_UPDATE)
dkato 0:853f5b7408a7 3563 b8 GR_VIN_UPDATE
dkato 0:853f5b7408a7 3564 b4 GR_VIN_P_VEN */
dkato 0:853f5b7408a7 3565 *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
dkato 0:853f5b7408a7 3566 }
dkato 0:853f5b7408a7 3567 }
dkato 0:853f5b7408a7 3568 } /* End of function SetUndSel() */
dkato 0:853f5b7408a7 3569
dkato 0:853f5b7408a7 3570 /**************************************************************************//**
dkato 0:853f5b7408a7 3571 * @brief Converts the color format from gr_format format into 24-bit RGB888 format
dkato 0:853f5b7408a7 3572 * @param[in] gr_format : Color format
dkato 0:853f5b7408a7 3573 * @param[in] input_color : Color data
dkato 0:853f5b7408a7 3574 * @retval RGB888 color data
dkato 0:853f5b7408a7 3575 ******************************************************************************/
dkato 0:853f5b7408a7 3576 static uint32_t ColorConversion (const vdc5_gr_format_t gr_format, const uint32_t input_color)
dkato 0:853f5b7408a7 3577 {
dkato 0:853f5b7408a7 3578 uint32_t red;
dkato 0:853f5b7408a7 3579 uint32_t green;
dkato 0:853f5b7408a7 3580 uint32_t blue;
dkato 0:853f5b7408a7 3581 uint32_t conv_color;
dkato 0:853f5b7408a7 3582
dkato 0:853f5b7408a7 3583 conv_color = 0;
dkato 0:853f5b7408a7 3584 switch (gr_format) {
dkato 0:853f5b7408a7 3585 case VDC5_GR_FORMAT_RGB565:
dkato 0:853f5b7408a7 3586 red = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGB565_R_MASK) >> VDC5_REG_SHIFT_11));
dkato 0:853f5b7408a7 3587 green = ColorConversionFrom6to8((uint32_t)((input_color & VDC5_REG_RGB565_G_MASK) >> VDC5_REG_SHIFT_5));
dkato 0:853f5b7408a7 3588 blue = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_RGB565_B_MASK));
dkato 0:853f5b7408a7 3589 conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
dkato 0:853f5b7408a7 3590 break;
dkato 0:853f5b7408a7 3591 case VDC5_GR_FORMAT_RGB888:
dkato 0:853f5b7408a7 3592 conv_color = ColorConversionIntoAgbr(input_color);
dkato 0:853f5b7408a7 3593 break;
dkato 0:853f5b7408a7 3594 case VDC5_GR_FORMAT_ARGB1555:
dkato 0:853f5b7408a7 3595 red = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_R_MASK) >> VDC5_REG_SHIFT_10));
dkato 0:853f5b7408a7 3596 green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_G_MASK) >> VDC5_REG_SHIFT_5));
dkato 0:853f5b7408a7 3597 blue = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_ARGB1555_B_MASK));
dkato 0:853f5b7408a7 3598 conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
dkato 0:853f5b7408a7 3599 break;
dkato 0:853f5b7408a7 3600 case VDC5_GR_FORMAT_ARGB4444:
dkato 0:853f5b7408a7 3601 red = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_R_MASK) >> VDC5_REG_SHIFT_8));
dkato 0:853f5b7408a7 3602 green = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_G_MASK) >> VDC5_REG_SHIFT_4));
dkato 0:853f5b7408a7 3603 blue = ColorConversionFrom4to8((uint32_t)(input_color & VDC5_REG_ARGB4444_B_MASK));
dkato 0:853f5b7408a7 3604 conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
dkato 0:853f5b7408a7 3605 break;
dkato 0:853f5b7408a7 3606 case VDC5_GR_FORMAT_ARGB8888:
dkato 0:853f5b7408a7 3607 conv_color = ColorConversionIntoAgbr((uint32_t)(input_color & VDC5_REG_RGB_24BIT_MASK));
dkato 0:853f5b7408a7 3608 break;
dkato 0:853f5b7408a7 3609 case VDC5_GR_FORMAT_RGBA5551:
dkato 0:853f5b7408a7 3610 red = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_R_MASK) >> VDC5_REG_SHIFT_11));
dkato 0:853f5b7408a7 3611 green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_G_MASK) >> VDC5_REG_SHIFT_6));
dkato 0:853f5b7408a7 3612 blue = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_B_MASK) >> VDC5_REG_SHIFT_1));
dkato 0:853f5b7408a7 3613 conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
dkato 0:853f5b7408a7 3614 break;
dkato 0:853f5b7408a7 3615 case VDC5_GR_FORMAT_RGBA8888:
dkato 0:853f5b7408a7 3616 conv_color = ColorConversionIntoAgbr((uint32_t)((input_color >> VDC5_REG_SHIFT_8) & VDC5_REG_RGB_24BIT_MASK));
dkato 0:853f5b7408a7 3617 break;
dkato 0:853f5b7408a7 3618 default:
dkato 0:853f5b7408a7 3619 /* DO NOTHING */
dkato 0:853f5b7408a7 3620 break;
dkato 0:853f5b7408a7 3621 }
dkato 0:853f5b7408a7 3622 return conv_color;
dkato 0:853f5b7408a7 3623 } /* End of function ColorConversion() */
dkato 0:853f5b7408a7 3624
dkato 0:853f5b7408a7 3625 /**************************************************************************//**
dkato 0:853f5b7408a7 3626 * @brief Converts the color data from 4 bits value into 8 bits value
dkato 0:853f5b7408a7 3627 * @param[in] color_value : 4-bit color data
dkato 0:853f5b7408a7 3628 * @retval 8-bit color data
dkato 0:853f5b7408a7 3629 ******************************************************************************/
dkato 0:853f5b7408a7 3630 static uint32_t ColorConversionFrom4to8 (const uint32_t color_value)
dkato 0:853f5b7408a7 3631 {
dkato 0:853f5b7408a7 3632 uint32_t color;
dkato 0:853f5b7408a7 3633
dkato 0:853f5b7408a7 3634 color = color_value & (uint32_t)VDC5_REG_COLOR_4BIT_MASK;
dkato 0:853f5b7408a7 3635 color *= (uint32_t)VDC5_REG_EXTENSION_VALUE_17;
dkato 0:853f5b7408a7 3636
dkato 0:853f5b7408a7 3637 return color;
dkato 0:853f5b7408a7 3638 } /* End of function ColorConversionFrom4to8() */
dkato 0:853f5b7408a7 3639
dkato 0:853f5b7408a7 3640 /**************************************************************************//**
dkato 0:853f5b7408a7 3641 * @brief Converts the color data from 5 bits value into 8 bits value
dkato 0:853f5b7408a7 3642 * @param[in] color_value : 5-bit color data
dkato 0:853f5b7408a7 3643 * @retval 8-bit color data
dkato 0:853f5b7408a7 3644 ******************************************************************************/
dkato 0:853f5b7408a7 3645 static uint32_t ColorConversionFrom5to8 (const uint32_t color_value)
dkato 0:853f5b7408a7 3646 {
dkato 0:853f5b7408a7 3647 uint32_t color;
dkato 0:853f5b7408a7 3648
dkato 0:853f5b7408a7 3649 color = color_value & (uint32_t)VDC5_REG_COLOR_5BIT_MASK;
dkato 0:853f5b7408a7 3650 color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_263 * VDC5_REG_ROUND_OFF_VALUE_2);
dkato 0:853f5b7408a7 3651 color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_32;
dkato 0:853f5b7408a7 3652 /* Round off */
dkato 0:853f5b7408a7 3653 color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
dkato 0:853f5b7408a7 3654 color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
dkato 0:853f5b7408a7 3655
dkato 0:853f5b7408a7 3656 return color;
dkato 0:853f5b7408a7 3657 } /* End of function ColorConversionFrom5to8() */
dkato 0:853f5b7408a7 3658
dkato 0:853f5b7408a7 3659 /**************************************************************************//**
dkato 0:853f5b7408a7 3660 * @brief Converts the color data from 6 bits value into 8 bits value
dkato 0:853f5b7408a7 3661 * @param[in] color_value : 6-bit color data
dkato 0:853f5b7408a7 3662 * @retval 8-bit color data
dkato 0:853f5b7408a7 3663 ******************************************************************************/
dkato 0:853f5b7408a7 3664 static uint32_t ColorConversionFrom6to8 (const uint32_t color_value)
dkato 0:853f5b7408a7 3665 {
dkato 0:853f5b7408a7 3666 uint32_t color;
dkato 0:853f5b7408a7 3667
dkato 0:853f5b7408a7 3668 color = color_value & (uint32_t)VDC5_REG_COLOR_6BIT_MASK;
dkato 0:853f5b7408a7 3669 color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_259 * VDC5_REG_ROUND_OFF_VALUE_2);
dkato 0:853f5b7408a7 3670 color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_64;
dkato 0:853f5b7408a7 3671 /* Round off */
dkato 0:853f5b7408a7 3672 color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
dkato 0:853f5b7408a7 3673 color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
dkato 0:853f5b7408a7 3674
dkato 0:853f5b7408a7 3675 return color;
dkato 0:853f5b7408a7 3676 } /* End of function ColorConversionFrom6to8() */
dkato 0:853f5b7408a7 3677
dkato 0:853f5b7408a7 3678 /**************************************************************************//**
dkato 0:853f5b7408a7 3679 * @brief Converts the color data from ARGB8888 format into AGBR8888 format
dkato 0:853f5b7408a7 3680 * @param[in] color_value : ARGB8888 color data
dkato 0:853f5b7408a7 3681 * @retval AGBR8888 color data
dkato 0:853f5b7408a7 3682 ******************************************************************************/
dkato 0:853f5b7408a7 3683 static uint32_t ColorConversionIntoAgbr (const uint32_t color_value)
dkato 0:853f5b7408a7 3684 {
dkato 0:853f5b7408a7 3685 uint32_t color_bgr;
dkato 0:853f5b7408a7 3686 uint32_t color_dat;
dkato 0:853f5b7408a7 3687
dkato 0:853f5b7408a7 3688 /* Green and blue */
dkato 0:853f5b7408a7 3689 color_bgr = (uint32_t)(color_value << VDC5_REG_SHIFT_8);
dkato 0:853f5b7408a7 3690 color_bgr &= (uint32_t)VDC5_REG_ARGB8888_GB_MASK;
dkato 0:853f5b7408a7 3691 /* Alpha */
dkato 0:853f5b7408a7 3692 color_dat = (uint32_t)(color_value & VDC5_REG_ALPHA_8BIT);
dkato 0:853f5b7408a7 3693 color_bgr |= color_dat;
dkato 0:853f5b7408a7 3694 /* Red */
dkato 0:853f5b7408a7 3695 color_dat = (uint32_t)((color_value >> VDC5_REG_SHIFT_16) & VDC5_REG_COLOR_8BIT_MASK);
dkato 0:853f5b7408a7 3696 color_bgr |= color_dat;
dkato 0:853f5b7408a7 3697
dkato 0:853f5b7408a7 3698 return color_bgr;
dkato 0:853f5b7408a7 3699 } /* End of function ColorConversionIntoAgbr() */
dkato 0:853f5b7408a7 3700
dkato 0:853f5b7408a7 3701 /**************************************************************************//**
dkato 0:853f5b7408a7 3702 * @brief Sets color lookup table (CLUT)
dkato 0:853f5b7408a7 3703 * @param[in] param : CLUT parameter
dkato 0:853f5b7408a7 3704 * @param[out] regaddr_clut : CLUT register top address
dkato 0:853f5b7408a7 3705 * @retval None
dkato 0:853f5b7408a7 3706 ******************************************************************************/
dkato 0:853f5b7408a7 3707 static void Set_Clut (const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut)
dkato 0:853f5b7408a7 3708 {
dkato 0:853f5b7408a7 3709 uint32_t data_len;
dkato 0:853f5b7408a7 3710 const uint32_t * clut_tmp;
dkato 0:853f5b7408a7 3711
dkato 0:853f5b7408a7 3712 clut_tmp = param->clut;
dkato 0:853f5b7408a7 3713 for (data_len = 0; data_len < param->color_num; data_len++) {
dkato 0:853f5b7408a7 3714 *regaddr_clut = *clut_tmp;
dkato 0:853f5b7408a7 3715 regaddr_clut++;
dkato 0:853f5b7408a7 3716 clut_tmp++;
dkato 0:853f5b7408a7 3717 }
dkato 0:853f5b7408a7 3718 } /* End of function Set_Clut() */
dkato 0:853f5b7408a7 3719
dkato 0:853f5b7408a7 3720 /**************************************************************************//**
dkato 0:853f5b7408a7 3721 * @brief Sets start threshold for gamma correction
dkato 0:853f5b7408a7 3722 * @param[in] gam_th : Start threshold of area 1 to 31
dkato 0:853f5b7408a7 3723 * @param[out] gam_area : Gamma correction registers for start threshold
dkato 0:853f5b7408a7 3724 * @retval None
dkato 0:853f5b7408a7 3725 ******************************************************************************/
dkato 0:853f5b7408a7 3726 static void Set_StartThreshold_Gamma (const uint8_t * gam_th, volatile uint32_t * const * const gam_area)
dkato 0:853f5b7408a7 3727 {
dkato 0:853f5b7408a7 3728 uint32_t reg_index;
dkato 0:853f5b7408a7 3729
dkato 0:853f5b7408a7 3730 if (gam_th != NULL) {
dkato 0:853f5b7408a7 3731 *(gam_area[0]) = (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3732 gam_th++;
dkato 0:853f5b7408a7 3733 *(gam_area[0]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 3734 gam_th++;
dkato 0:853f5b7408a7 3735 *(gam_area[0]) |= (uint32_t)*gam_th;
dkato 0:853f5b7408a7 3736 gam_th++;
dkato 0:853f5b7408a7 3737
dkato 0:853f5b7408a7 3738 for (reg_index = 1; reg_index < VDC5_GAM_AREA_REG_NUM; reg_index++) {
dkato 0:853f5b7408a7 3739 *(gam_area[reg_index]) = (uint32_t)*gam_th << VDC5_REG_SHIFT_24;
dkato 0:853f5b7408a7 3740 gam_th++;
dkato 0:853f5b7408a7 3741 *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3742 gam_th++;
dkato 0:853f5b7408a7 3743 *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
dkato 0:853f5b7408a7 3744 gam_th++;
dkato 0:853f5b7408a7 3745 *(gam_area[reg_index]) |= (uint32_t)*gam_th;
dkato 0:853f5b7408a7 3746 gam_th++;
dkato 0:853f5b7408a7 3747 }
dkato 0:853f5b7408a7 3748 }
dkato 0:853f5b7408a7 3749 } /* End of function Set_StartThreshold_Gamma() */
dkato 0:853f5b7408a7 3750
dkato 0:853f5b7408a7 3751 /**************************************************************************//**
dkato 0:853f5b7408a7 3752 * @brief Sets gain adjustment for gamma correction
dkato 0:853f5b7408a7 3753 * @param[in] gam_gain : Gain adjustment of area 0 to 31
dkato 0:853f5b7408a7 3754 * @param[out] gam_lut : Gamma correction registers for gain adjustment
dkato 0:853f5b7408a7 3755 * @retval None
dkato 0:853f5b7408a7 3756 ******************************************************************************/
dkato 0:853f5b7408a7 3757 static void Set_GainAdjustment_Gamma (const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut)
dkato 0:853f5b7408a7 3758 {
dkato 0:853f5b7408a7 3759 uint32_t reg_index;
dkato 0:853f5b7408a7 3760
dkato 0:853f5b7408a7 3761 if (gam_gain != NULL) {
dkato 0:853f5b7408a7 3762 for (reg_index = 0; reg_index < VDC5_GAM_LUT_REG_NUM; reg_index++) {
dkato 0:853f5b7408a7 3763 *(gam_lut[reg_index]) = (uint32_t)*gam_gain << VDC5_REG_SHIFT_16;
dkato 0:853f5b7408a7 3764 gam_gain++;
dkato 0:853f5b7408a7 3765 *(gam_lut[reg_index]) |= (uint32_t)*gam_gain;
dkato 0:853f5b7408a7 3766 gam_gain++;
dkato 0:853f5b7408a7 3767 }
dkato 0:853f5b7408a7 3768 }
dkato 0:853f5b7408a7 3769 } /* End of function Set_GainAdjustment_Gamma() */
dkato 0:853f5b7408a7 3770
dkato 0:853f5b7408a7 3771 /**************************************************************************//**
dkato 0:853f5b7408a7 3772 * @brief Waits for 200 usec
dkato 0:853f5b7408a7 3773 * @param[in] void
dkato 0:853f5b7408a7 3774 * @retval None
dkato 0:853f5b7408a7 3775 ******************************************************************************/
dkato 0:853f5b7408a7 3776 static void Wait_200_usec (void)
dkato 0:853f5b7408a7 3777 {
dkato 0:853f5b7408a7 3778 volatile uint32_t counter;
dkato 0:853f5b7408a7 3779
dkato 0:853f5b7408a7 3780 for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_200USEC; counter++) {
dkato 0:853f5b7408a7 3781 /* Wait for 200 usec. */
dkato 0:853f5b7408a7 3782 }
dkato 0:853f5b7408a7 3783 } /* End of function Wait_200_usec() */
dkato 0:853f5b7408a7 3784