karthick B / GR-PEACH_video

vedio_gr_peach

Fork of GR-PEACH_video by Renesas

drivers/vdc5/include/r_vdc5.h@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
0:853f5b7408a7 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file r_vdc5.h
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief VDC5 driver API definitions
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 #ifndef R_VDC5_H
dkato 0:853f5b7408a7 32 #define R_VDC5_H
dkato 0:853f5b7408a7 33
dkato 0:853f5b7408a7 34 /******************************************************************************
dkato 0:853f5b7408a7 35 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 36 ******************************************************************************/
dkato 0:853f5b7408a7 37 #include "r_vdc5_user.h"
dkato 0:853f5b7408a7 38
dkato 0:853f5b7408a7 39
dkato 0:853f5b7408a7 40 #ifdef __cplusplus
dkato 0:853f5b7408a7 41 extern "C"
dkato 0:853f5b7408a7 42 {
dkato 0:853f5b7408a7 43 #endif /* __cplusplus */
dkato 0:853f5b7408a7 44
dkato 0:853f5b7408a7 45
dkato 0:853f5b7408a7 46 /******************************************************************************
dkato 0:853f5b7408a7 47 Macro definitions
dkato 0:853f5b7408a7 48 ******************************************************************************/
dkato 0:853f5b7408a7 49 #define VDC5_GAM_GAIN_ADJ_NUM (32u) /*!< The number of the gamma correction gain coefficient */
dkato 0:853f5b7408a7 50 #define VDC5_GAM_START_TH_NUM (31u) /*!< The number of the gamma correction start threshold */
dkato 0:853f5b7408a7 51
dkato 0:853f5b7408a7 52
dkato 0:853f5b7408a7 53 /******************************************************************************
dkato 0:853f5b7408a7 54 Typedef definitions
dkato 0:853f5b7408a7 55 ******************************************************************************/
dkato 0:853f5b7408a7 56 /*! Error codes of the VDC5 driver */
dkato 0:853f5b7408a7 57 typedef enum {
dkato 0:853f5b7408a7 58 VDC5_OK = 0, /*!< Normal termination */
dkato 0:853f5b7408a7 59 VDC5_ERR_PARAM_CHANNEL, /*!< Invalid channel error (parameter error): An illegal channel is specified. */
dkato 0:853f5b7408a7 60 VDC5_ERR_PARAM_LAYER_ID, /*!< Invalid layer ID error (parameter error): An illegal layer ID is specified. */
dkato 0:853f5b7408a7 61 VDC5_ERR_PARAM_NULL, /*!< NULL specification error (parameter error):
dkato 0:853f5b7408a7 62 NULL is specified for a required parameter. */
dkato 0:853f5b7408a7 63 VDC5_ERR_PARAM_BIT_WIDTH, /*!< Bit width error (parameter error):
dkato 0:853f5b7408a7 64 A value exceeding the possible bit width is specified. */
dkato 0:853f5b7408a7 65 VDC5_ERR_PARAM_UNDEFINED, /*!< Undefined parameter error (parameter error):
dkato 0:853f5b7408a7 66 A value that is not defined in the specification is specified. */
dkato 0:853f5b7408a7 67 VDC5_ERR_PARAM_EXCEED_RANGE,/*!< Out-of-value-range error (parameter error):
dkato 0:853f5b7408a7 68 The specified parameter value is beyond the value range defined
dkato 0:853f5b7408a7 69 in the specification. */
dkato 0:853f5b7408a7 70 VDC5_ERR_PARAM_CONDITION, /*!< Unauthorized condition error (parameter error):
dkato 0:853f5b7408a7 71 A parameter is specified under conditions that are not authorized
dkato 0:853f5b7408a7 72 by the specification. */
dkato 0:853f5b7408a7 73 VDC5_ERR_IF_CONDITION, /*!< Interface condition error (interface error):
dkato 0:853f5b7408a7 74 An API function is called under unauthorized conditions. */
dkato 0:853f5b7408a7 75 VDC5_ERR_RESOURCE_CLK, /*!< Clock resource error (resource error): No panel clock is set up. */
dkato 0:853f5b7408a7 76 VDC5_ERR_RESOURCE_VSYNC, /*!< Vsync signal resource error (resource error): No Vsync signal is set up. */
dkato 0:853f5b7408a7 77 VDC5_ERR_RESOURCE_INPUT, /*!< Input signal resource error (resource error): No video image input is set up. */
dkato 0:853f5b7408a7 78 VDC5_ERR_RESOURCE_OUTPUT, /*!< Output resource error (resource error): No display output is set up. */
dkato 0:853f5b7408a7 79 VDC5_ERR_RESOURCE_LVDS_CLK, /*!< LVDS clock resource error (resource error):
dkato 0:853f5b7408a7 80 An attempt is made to use the LVDS clock without setting it up,
dkato 0:853f5b7408a7 81 or the LVDS clock is specified when it is already set up. */
dkato 0:853f5b7408a7 82 VDC5_ERR_RESOURCE_LAYER, /*!< Layer resource error (resource error):
dkato 0:853f5b7408a7 83 The specified layer is under unavailable conditions. */
dkato 0:853f5b7408a7 84 VDC5_ERR_NUM /*!< The number of error codes */
dkato 0:853f5b7408a7 85 } vdc5_error_t;
dkato 0:853f5b7408a7 86
dkato 0:853f5b7408a7 87 /*! VDC5 channels */
dkato 0:853f5b7408a7 88 typedef enum {
dkato 0:853f5b7408a7 89 VDC5_CHANNEL_0 = 0, /*!< Channel 0 */
dkato 0:853f5b7408a7 90 VDC5_CHANNEL_1, /*!< Channel 1 */
dkato 0:853f5b7408a7 91 VDC5_CHANNEL_NUM /*!< The number of channels */
dkato 0:853f5b7408a7 92 } vdc5_channel_t;
dkato 0:853f5b7408a7 93
dkato 0:853f5b7408a7 94 /*! On/off */
dkato 0:853f5b7408a7 95 typedef enum {
dkato 0:853f5b7408a7 96 VDC5_OFF = 0, /*!< Off */
dkato 0:853f5b7408a7 97 VDC5_ON = 1 /*!< On */
dkato 0:853f5b7408a7 98 } vdc5_onoff_t;
dkato 0:853f5b7408a7 99 /*! Edge of a signal */
dkato 0:853f5b7408a7 100 typedef enum {
dkato 0:853f5b7408a7 101 VDC5_EDGE_RISING = 0, /*!< Rising edge */
dkato 0:853f5b7408a7 102 VDC5_EDGE_FALLING = 1 /*!< Falling edge */
dkato 0:853f5b7408a7 103 } vdc5_edge_t;
dkato 0:853f5b7408a7 104 /*! Polarity of a signal */
dkato 0:853f5b7408a7 105 typedef enum {
dkato 0:853f5b7408a7 106 VDC5_SIG_POL_NOT_INVERTED = 0, /*!< Not inverted */
dkato 0:853f5b7408a7 107 VDC5_SIG_POL_INVERTED = 1 /*!< Inverted */
dkato 0:853f5b7408a7 108 } vdc5_sig_pol_t;
dkato 0:853f5b7408a7 109
dkato 0:853f5b7408a7 110 /*! Scaling type ID */
dkato 0:853f5b7408a7 111 typedef enum {
dkato 0:853f5b7408a7 112 VDC5_SC_TYPE_SC0 = 0, /*!< Scaler 0 */
dkato 0:853f5b7408a7 113 VDC5_SC_TYPE_SC1, /*!< Scaler 1 */
dkato 0:853f5b7408a7 114 VDC5_SC_TYPE_OIR, /*!< Output image generator (OIR) */
dkato 0:853f5b7408a7 115 VDC5_SC_TYPE_NUM /*!< The number of scaler types */
dkato 0:853f5b7408a7 116 } vdc5_scaling_type_t;
dkato 0:853f5b7408a7 117 /*! Graphics type ID */
dkato 0:853f5b7408a7 118 typedef enum {
dkato 0:853f5b7408a7 119 VDC5_GR_TYPE_GR0 = 0, /*!< Graphics 0 */
dkato 0:853f5b7408a7 120 VDC5_GR_TYPE_GR1, /*!< Graphics 1 */
dkato 0:853f5b7408a7 121 VDC5_GR_TYPE_GR2, /*!< Graphics 2 */
dkato 0:853f5b7408a7 122 VDC5_GR_TYPE_GR3, /*!< Graphics 3 */
dkato 0:853f5b7408a7 123 VDC5_GR_TYPE_VIN, /*!< VIN synthesizer */
dkato 0:853f5b7408a7 124 VDC5_GR_TYPE_OIR, /*!< Output image generator (OIR) */
dkato 0:853f5b7408a7 125 VDC5_GR_TYPE_NUM /*!< The number of graphics types */
dkato 0:853f5b7408a7 126 } vdc5_graphics_type_t;
dkato 0:853f5b7408a7 127 /*! Layer ID */
dkato 0:853f5b7408a7 128 typedef enum {
dkato 0:853f5b7408a7 129 VDC5_LAYER_ID_ALL = -1, /*!< All layers */
dkato 0:853f5b7408a7 130 VDC5_LAYER_ID_0_WR = (VDC5_SC_TYPE_SC0 + 0), /*!< Write process for layer 0 */
dkato 0:853f5b7408a7 131 VDC5_LAYER_ID_1_WR = (VDC5_SC_TYPE_SC1 + 0), /*!< Write process for layer 1 */
dkato 0:853f5b7408a7 132 VDC5_LAYER_ID_OIR_WR = (VDC5_SC_TYPE_OIR + 0), /*!< Write process for layer OIR */
dkato 0:853f5b7408a7 133 VDC5_LAYER_ID_0_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR0), /*!< Read process for layer 0 */
dkato 0:853f5b7408a7 134 VDC5_LAYER_ID_1_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR1), /*!< Read process for layer 1 */
dkato 0:853f5b7408a7 135 VDC5_LAYER_ID_2_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR2), /*!< Read process for layer 2 */
dkato 0:853f5b7408a7 136 VDC5_LAYER_ID_3_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR3), /*!< Read process for layer 3 */
dkato 0:853f5b7408a7 137 VDC5_LAYER_ID_VIN_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_VIN), /*!< VIN synthesizer */
dkato 0:853f5b7408a7 138 VDC5_LAYER_ID_OIR_RD = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_OIR), /*!< Read process for layer OIR */
dkato 0:853f5b7408a7 139 VDC5_LAYER_ID_NUM = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_NUM) /*!< The number of layer IDs */
dkato 0:853f5b7408a7 140 } vdc5_layer_id_t;
dkato 0:853f5b7408a7 141 /*! The horizontal/vertical timing of the VDC5 signals */
dkato 0:853f5b7408a7 142 typedef struct {
dkato 0:853f5b7408a7 143 uint16_t vs; /*!< Vertical signal start position from the reference signal */
dkato 0:853f5b7408a7 144 uint16_t vw; /*!< Vertical signal width (height) */
dkato 0:853f5b7408a7 145 uint16_t hs; /*!< Horizontal signal start position from the reference signal */
dkato 0:853f5b7408a7 146 uint16_t hw; /*!< Horizontal signal width */
dkato 0:853f5b7408a7 147 } vdc5_period_rect_t;
dkato 0:853f5b7408a7 148 /*! The relative position within the graphics display area */
dkato 0:853f5b7408a7 149 typedef struct {
dkato 0:853f5b7408a7 150 uint16_t vs_rel; /*!< Vertical start position */
dkato 0:853f5b7408a7 151 uint16_t vw_rel; /*!< Vertical width (height) */
dkato 0:853f5b7408a7 152 uint16_t hs_rel; /*!< Horizontal start position */
dkato 0:853f5b7408a7 153 uint16_t hw_rel; /*!< Horizontal width */
dkato 0:853f5b7408a7 154 } vdc5_pd_disp_rect_t;
dkato 0:853f5b7408a7 155
dkato 0:853f5b7408a7 156 /*********************** For R_VDC5_Initialize ***********************/
dkato 0:853f5b7408a7 157 /*! Panel clock select */
dkato 0:853f5b7408a7 158 typedef enum {
dkato 0:853f5b7408a7 159 VDC5_PANEL_ICKSEL_IMG = 0, /*!< Divided video image clock (VIDEO_X1) */
dkato 0:853f5b7408a7 160 VDC5_PANEL_ICKSEL_IMG_DV, /*!< Divided video image clock (DV_CLK) */
dkato 0:853f5b7408a7 161 VDC5_PANEL_ICKSEL_EXT_0, /*!< Divided external clock (LCD0_EXTCLK) */
dkato 0:853f5b7408a7 162 VDC5_PANEL_ICKSEL_EXT_1, /*!< Divided external clock (LCD1_EXTCLK) */
dkato 0:853f5b7408a7 163 VDC5_PANEL_ICKSEL_PERI, /*!< Divided peripheral clock 1 */
dkato 0:853f5b7408a7 164 VDC5_PANEL_ICKSEL_LVDS, /*!< LVDS PLL clock */
dkato 0:853f5b7408a7 165 VDC5_PANEL_ICKSEL_LVDS_DIV7, /*!< LVDS PLL clock divided by 7 */
dkato 0:853f5b7408a7 166 VDC5_PANEL_ICKSEL_NUM /*!< The number of panel clock select settings */
dkato 0:853f5b7408a7 167 } vdc5_panel_clksel_t;
dkato 0:853f5b7408a7 168 /*! Clock frequency division ratio */
dkato 0:853f5b7408a7 169 typedef enum {
dkato 0:853f5b7408a7 170 VDC5_PANEL_CLKDIV_1_1 = 0, /*!< Division Ratio 1/1 */
dkato 0:853f5b7408a7 171 VDC5_PANEL_CLKDIV_1_2, /*!< Division Ratio 1/2 */
dkato 0:853f5b7408a7 172 VDC5_PANEL_CLKDIV_1_3, /*!< Division Ratio 1/3 */
dkato 0:853f5b7408a7 173 VDC5_PANEL_CLKDIV_1_4, /*!< Division Ratio 1/4 */
dkato 0:853f5b7408a7 174 VDC5_PANEL_CLKDIV_1_5, /*!< Division Ratio 1/5 */
dkato 0:853f5b7408a7 175 VDC5_PANEL_CLKDIV_1_6, /*!< Division Ratio 1/6 */
dkato 0:853f5b7408a7 176 VDC5_PANEL_CLKDIV_1_7, /*!< Division Ratio 1/7 */
dkato 0:853f5b7408a7 177 VDC5_PANEL_CLKDIV_1_8, /*!< Division Ratio 1/8 */
dkato 0:853f5b7408a7 178 VDC5_PANEL_CLKDIV_1_9, /*!< Division Ratio 1/9 */
dkato 0:853f5b7408a7 179 VDC5_PANEL_CLKDIV_1_12, /*!< Division Ratio 1/12 */
dkato 0:853f5b7408a7 180 VDC5_PANEL_CLKDIV_1_16, /*!< Division Ratio 1/16 */
dkato 0:853f5b7408a7 181 VDC5_PANEL_CLKDIV_1_24, /*!< Division Ratio 1/24 */
dkato 0:853f5b7408a7 182 VDC5_PANEL_CLKDIV_1_32, /*!< Division Ratio 1/32 */
dkato 0:853f5b7408a7 183 VDC5_PANEL_CLKDIV_NUM /*!< The number of division ratio settings */
dkato 0:853f5b7408a7 184 } vdc5_panel_clk_dcdr_t;
dkato 0:853f5b7408a7 185 /*! The clock input to frequency divider 1 */
dkato 0:853f5b7408a7 186 typedef enum {
dkato 0:853f5b7408a7 187 VDC5_LVDS_INCLK_SEL_IMG = 0, /*!< Video image clock (VIDEO_X1) */
dkato 0:853f5b7408a7 188 VDC5_LVDS_INCLK_SEL_DV_0, /*!< Video image clock (DV0_CLK) */
dkato 0:853f5b7408a7 189 VDC5_LVDS_INCLK_SEL_DV_1, /*!< Video image clock (DV1_CLK) */
dkato 0:853f5b7408a7 190 VDC5_LVDS_INCLK_SEL_EXT_0, /*!< External clock (LCD0_EXTCLK) */
dkato 0:853f5b7408a7 191 VDC5_LVDS_INCLK_SEL_EXT_1, /*!< External clock (LCD1_EXTCLK) */
dkato 0:853f5b7408a7 192 VDC5_LVDS_INCLK_SEL_PERI, /*!< Peripheral clock 1 */
dkato 0:853f5b7408a7 193 VDC5_LVDS_INCLK_SEL_NUM
dkato 0:853f5b7408a7 194 } vdc5_lvds_in_clk_sel_t;
dkato 0:853f5b7408a7 195 /*! The frequency dividing value (NIDIV or NODIV) */
dkato 0:853f5b7408a7 196 typedef enum {
dkato 0:853f5b7408a7 197 VDC5_LVDS_NDIV_1 = 0, /*!< Div 1 */
dkato 0:853f5b7408a7 198 VDC5_LVDS_NDIV_2, /*!< Div 2 */
dkato 0:853f5b7408a7 199 VDC5_LVDS_NDIV_4, /*!< Div 4 */
dkato 0:853f5b7408a7 200 VDC5_LVDS_NDIV_NUM
dkato 0:853f5b7408a7 201 } vdc5_lvds_ndiv_t;
dkato 0:853f5b7408a7 202 /*! The frequency dividing value (NOD) for the output frequency */
dkato 0:853f5b7408a7 203 typedef enum {
dkato 0:853f5b7408a7 204 VDC5_LVDS_PLL_NOD_1 = 0, /*!< Div 1 */
dkato 0:853f5b7408a7 205 VDC5_LVDS_PLL_NOD_2, /*!< Div 2 */
dkato 0:853f5b7408a7 206 VDC5_LVDS_PLL_NOD_4, /*!< Div 4 */
dkato 0:853f5b7408a7 207 VDC5_LVDS_PLL_NOD_8, /*!< Div 8 */
dkato 0:853f5b7408a7 208 VDC5_LVDS_PLL_NOD_NUM
dkato 0:853f5b7408a7 209 } vdc5_lvds_pll_nod_t;
dkato 0:853f5b7408a7 210 /*! LVDS parameter */
dkato 0:853f5b7408a7 211 typedef struct {
dkato 0:853f5b7408a7 212 vdc5_lvds_in_clk_sel_t lvds_in_clk_sel;/*!< The clock input to frequency divider 1 */
dkato 0:853f5b7408a7 213 vdc5_lvds_ndiv_t lvds_idiv_set; /*!< The frequency dividing value (NIDIV) for frequency divider 1 */
dkato 0:853f5b7408a7 214 uint16_t lvdspll_tst; /*!< Internal parameter setting for LVDS PLL */
dkato 0:853f5b7408a7 215 vdc5_lvds_ndiv_t lvds_odiv_set; /*!< The frequency dividing value (NODIV) for frequency divider 2 */
dkato 0:853f5b7408a7 216 vdc5_channel_t lvds_vdc_sel; /*!< A channel in VDC5 whose data is to be output through the LVDS */
dkato 0:853f5b7408a7 217 uint16_t lvdspll_fd; /*!< The frequency dividing value (NFD) for the feedback frequency */
dkato 0:853f5b7408a7 218 uint16_t lvdspll_rd; /*!< The frequency dividing value (NRD) for the input frequency */
dkato 0:853f5b7408a7 219 vdc5_lvds_pll_nod_t lvdspll_od; /*!< The frequency dividing value (NOD) for the output frequency */
dkato 0:853f5b7408a7 220 } vdc5_lvds_t;
dkato 0:853f5b7408a7 221 /*! Initialization parameter */
dkato 0:853f5b7408a7 222 typedef struct {
dkato 0:853f5b7408a7 223 vdc5_panel_clksel_t panel_icksel; /*!< Panel clock select */
dkato 0:853f5b7408a7 224 vdc5_panel_clk_dcdr_t panel_dcdr; /*!< Clock frequency division ratio */
dkato 0:853f5b7408a7 225 const vdc5_lvds_t * lvds; /*!< LVDS-related parameter */
dkato 0:853f5b7408a7 226 } vdc5_init_t;
dkato 0:853f5b7408a7 227
dkato 0:853f5b7408a7 228 /*********************** For R_VDC5_VideoInput ***********************/
dkato 0:853f5b7408a7 229 /*! Input select */
dkato 0:853f5b7408a7 230 typedef enum {
dkato 0:853f5b7408a7 231 VDC5_INPUT_SEL_VDEC = 0, /*!< Video decoder output signals */
dkato 0:853f5b7408a7 232 VDC5_INPUT_SEL_EXT = 1 /*!< Signals supplied via the external input pins */
dkato 0:853f5b7408a7 233 } vdc5_input_sel_t;
dkato 0:853f5b7408a7 234 /*! Sync signal delay adjustment parameter */
dkato 0:853f5b7408a7 235 typedef struct {
dkato 0:853f5b7408a7 236 uint16_t inp_vs_dly_l; /*!< Number of lines for delaying Vsync signal and field differentiation signal */
dkato 0:853f5b7408a7 237 uint16_t inp_fld_dly; /*!< Field differentiation signal delay amount */
dkato 0:853f5b7408a7 238 uint16_t inp_vs_dly; /*!< Vsync signal delay amount */
dkato 0:853f5b7408a7 239 uint16_t inp_hs_dly; /*!< Hsync signal delay amount */
dkato 0:853f5b7408a7 240 } vdc5_sync_delay_t;
dkato 0:853f5b7408a7 241 /*! External input format select */
dkato 0:853f5b7408a7 242 typedef enum {
dkato 0:853f5b7408a7 243 VDC5_EXTIN_FORMAT_RGB888 = 0, /*!< RGB888 */
dkato 0:853f5b7408a7 244 VDC5_EXTIN_FORMAT_RGB666, /*!< RGB666 */
dkato 0:853f5b7408a7 245 VDC5_EXTIN_FORMAT_RGB565, /*!< RGB565 */
dkato 0:853f5b7408a7 246 VDC5_EXTIN_FORMAT_BT656, /*!< BT6556 */
dkato 0:853f5b7408a7 247 VDC5_EXTIN_FORMAT_BT601, /*!< BT6501 */
dkato 0:853f5b7408a7 248 VDC5_EXTIN_FORMAT_YCBCR422, /*!< YCbCr422 */
dkato 0:853f5b7408a7 249 VDC5_EXTIN_FORMAT_YCBCR444, /*!< YCbCr444 */
dkato 0:853f5b7408a7 250 VDC5_EXTIN_FORMAT_NUM
dkato 0:853f5b7408a7 251 } vdc5_extin_format_t;
dkato 0:853f5b7408a7 252 /*! Reference select for external input BT.656 Hsync signal */
dkato 0:853f5b7408a7 253 typedef enum {
dkato 0:853f5b7408a7 254 VDC5_EXTIN_REF_H_EAV = 0, /*!< EAV */
dkato 0:853f5b7408a7 255 VDC5_EXTIN_REF_H_SAV = 1 /*!< SAV */
dkato 0:853f5b7408a7 256 } vdc5_extin_ref_hsync_t;
dkato 0:853f5b7408a7 257 /*! Number of lines for BT.656 external input */
dkato 0:853f5b7408a7 258 typedef enum {
dkato 0:853f5b7408a7 259 VDC5_EXTIN_LINE_525 = 0, /*!< 525 lines */
dkato 0:853f5b7408a7 260 VDC5_EXTIN_LINE_625 = 1 /*!< 625 lines */
dkato 0:853f5b7408a7 261 } vdc5_extin_input_line_t;
dkato 0:853f5b7408a7 262 /*! Y/Cb/Y/Cr data string start timing */
dkato 0:853f5b7408a7 263 typedef enum {
dkato 0:853f5b7408a7 264 VDC5_EXTIN_H_POS_CBYCRY = 0, /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
dkato 0:853f5b7408a7 265 VDC5_EXTIN_H_POS_YCRYCB, /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
dkato 0:853f5b7408a7 266 VDC5_EXTIN_H_POS_CRYCBY, /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
dkato 0:853f5b7408a7 267 VDC5_EXTIN_H_POS_YCBYCR, /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
dkato 0:853f5b7408a7 268 VDC5_EXTIN_H_POS_NUM
dkato 0:853f5b7408a7 269 } vdc5_extin_h_pos_t;
dkato 0:853f5b7408a7 270 /*! External input signal parameter */
dkato 0:853f5b7408a7 271 typedef struct {
dkato 0:853f5b7408a7 272 vdc5_extin_format_t inp_format; /*!< External input format select */
dkato 0:853f5b7408a7 273 vdc5_edge_t inp_pxd_edge; /*!< Clock edge select for capturing external input video image signals */
dkato 0:853f5b7408a7 274 vdc5_edge_t inp_vs_edge; /*!< Clock edge select for capturing external input Vsync signals */
dkato 0:853f5b7408a7 275 vdc5_edge_t inp_hs_edge; /*!< Clock edge select for capturing external input Hsync signals */
dkato 0:853f5b7408a7 276 vdc5_onoff_t inp_endian_on; /*!< External input bit endian change on/off control */
dkato 0:853f5b7408a7 277 vdc5_onoff_t inp_swap_on; /*!< External input B/R signal swap on/off control */
dkato 0:853f5b7408a7 278 vdc5_sig_pol_t inp_vs_inv; /*!< External input Vsync signal DV_VSYNC inversion control */
dkato 0:853f5b7408a7 279 vdc5_sig_pol_t inp_hs_inv; /*!< External input Hsync signal DV_HSYNC inversion control */
dkato 0:853f5b7408a7 280 vdc5_extin_ref_hsync_t inp_h_edge_sel; /*!< Reference select for external input BT.656 Hsync signal */
dkato 0:853f5b7408a7 281 vdc5_extin_input_line_t inp_f525_625; /*!< Number of lines for BT.656 external input */
dkato 0:853f5b7408a7 282 vdc5_extin_h_pos_t inp_h_pos; /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
dkato 0:853f5b7408a7 283 } vdc5_ext_in_sig_t;
dkato 0:853f5b7408a7 284 /*! Video input setup parameter */
dkato 0:853f5b7408a7 285 typedef struct {
dkato 0:853f5b7408a7 286 vdc5_input_sel_t inp_sel; /*!< Input select */
dkato 0:853f5b7408a7 287 uint16_t inp_fh50; /*!< Vsync signal 1/2fH phase timing */
dkato 0:853f5b7408a7 288 uint16_t inp_fh25; /*!< Vsync signal 1/4fH phase timing */
dkato 0:853f5b7408a7 289 const vdc5_sync_delay_t * dly; /*!< Sync signal delay adjustment parameter */
dkato 0:853f5b7408a7 290 const vdc5_ext_in_sig_t * ext_sig; /*!< External input signal parameter */
dkato 0:853f5b7408a7 291 } vdc5_input_t;
dkato 0:853f5b7408a7 292
dkato 0:853f5b7408a7 293 /*********************** For R_VDC5_SyncControl ***********************/
dkato 0:853f5b7408a7 294 /*! Horizontal/vertical sync signal output and full-screen enable signal select */
dkato 0:853f5b7408a7 295 typedef enum {
dkato 0:853f5b7408a7 296 VDC5_RES_VS_IN_SEL_SC0 = 0, /*!< Sync signal output and full-screen enable signal from scaler 0 */
dkato 0:853f5b7408a7 297 VDC5_RES_VS_IN_SEL_SC1 = 1 /*!< Sync signal output and full-screen enable signal from scaler 1 */
dkato 0:853f5b7408a7 298 } vdc5_res_vs_in_sel_t;
dkato 0:853f5b7408a7 299 /*! Vsync signal compensation parameter */
dkato 0:853f5b7408a7 300 typedef struct {
dkato 0:853f5b7408a7 301 uint16_t res_vmask; /*!< Repeated Vsync signal masking period */
dkato 0:853f5b7408a7 302 uint16_t res_vlack; /*!< Missing-Sync compensating pulse output wait time */
dkato 0:853f5b7408a7 303 } vdc5_vsync_cpmpe_t;
dkato 0:853f5b7408a7 304 /*! Sync signal control parameter */
dkato 0:853f5b7408a7 305 typedef struct {
dkato 0:853f5b7408a7 306 vdc5_onoff_t res_vs_sel; /*!< Vsync signal output select (free-running Vsync on/off control) */
dkato 0:853f5b7408a7 307 vdc5_res_vs_in_sel_t res_vs_in_sel; /*!< Horizontal/vertical sync signal output
dkato 0:853f5b7408a7 308 and full-screen enable signal select */
dkato 0:853f5b7408a7 309 uint16_t res_fv; /*!< Free-running Vsync period setting */
dkato 0:853f5b7408a7 310 uint16_t res_fh; /*!< Hsync period setting */
dkato 0:853f5b7408a7 311 uint16_t res_vsdly; /*!< Vsync signal delay control */
dkato 0:853f5b7408a7 312 vdc5_period_rect_t res_f; /*!< Full-screen enable signal */
dkato 0:853f5b7408a7 313 const vdc5_vsync_cpmpe_t * vsync_cpmpe; /*!< Vsync signal compensation parameter */
dkato 0:853f5b7408a7 314 } vdc5_sync_ctrl_t;
dkato 0:853f5b7408a7 315
dkato 0:853f5b7408a7 316 /*********************** For R_VDC5_DisplayOutput ***********************/
dkato 0:853f5b7408a7 317 /*! POLA/POLB signal generation mode select */
dkato 0:853f5b7408a7 318 typedef enum {
dkato 0:853f5b7408a7 319 VDC5_LCD_TCON_POLMD_NORMAL = 0, /*!< Normal mode */
dkato 0:853f5b7408a7 320 VDC5_LCD_TCON_POLMD_1X1REV, /*!< 1x1 reverse mode */
dkato 0:853f5b7408a7 321 VDC5_LCD_TCON_POLMD_1X2REV, /*!< 1x2 reverse mode */
dkato 0:853f5b7408a7 322 VDC5_LCD_TCON_POLMD_2X2REV, /*!< 2x2 reverse mode */
dkato 0:853f5b7408a7 323 VDC5_LCD_TCON_POLMD_NUM
dkato 0:853f5b7408a7 324 } vdc5_lcd_tcon_polmode_t;
dkato 0:853f5b7408a7 325 /*! Signal operating reference select */
dkato 0:853f5b7408a7 326 typedef enum {
dkato 0:853f5b7408a7 327 VDC5_LCD_TCON_REFSEL_HSYNC = 0, /*!< Hsync signal reference */
dkato 0:853f5b7408a7 328 VDC5_LCD_TCON_REFSEL_OFFSET_H = 1 /*!< Offset Hsync signal reference */
dkato 0:853f5b7408a7 329 } vdc5_lcd_tcon_refsel_t;
dkato 0:853f5b7408a7 330 /*! LCD TCON output pin select */
dkato 0:853f5b7408a7 331 typedef enum {
dkato 0:853f5b7408a7 332 VDC5_LCD_TCON_PIN_NON = -1, /*!< Nothing output */
dkato 0:853f5b7408a7 333 VDC5_LCD_TCON_PIN_0, /*!< LCD_TCON0 */
dkato 0:853f5b7408a7 334 VDC5_LCD_TCON_PIN_1, /*!< LCD_TCON1 */
dkato 0:853f5b7408a7 335 VDC5_LCD_TCON_PIN_2, /*!< LCD_TCON2 */
dkato 0:853f5b7408a7 336 VDC5_LCD_TCON_PIN_3, /*!< LCD_TCON3 */
dkato 0:853f5b7408a7 337 VDC5_LCD_TCON_PIN_4, /*!< LCD_TCON4 */
dkato 0:853f5b7408a7 338 VDC5_LCD_TCON_PIN_5, /*!< LCD_TCON5 */
dkato 0:853f5b7408a7 339 VDC5_LCD_TCON_PIN_6, /*!< LCD_TCON6 */
dkato 0:853f5b7408a7 340 VDC5_LCD_TCON_PIN_NUM
dkato 0:853f5b7408a7 341 } vdc5_lcd_tcon_pin_t;
dkato 0:853f5b7408a7 342 /*! LCD TCON timing signal parameter */
dkato 0:853f5b7408a7 343 typedef struct {
dkato 0:853f5b7408a7 344 uint16_t tcon_hsvs; /*!< Signal pulse start position */
dkato 0:853f5b7408a7 345 uint16_t tcon_hwvw; /*!< Pulse width */
dkato 0:853f5b7408a7 346 vdc5_lcd_tcon_polmode_t tcon_md; /*!< POLA/POLB signal generation mode select */
dkato 0:853f5b7408a7 347 vdc5_lcd_tcon_refsel_t tcon_hs_sel; /*!< Signal operating reference select */
dkato 0:853f5b7408a7 348 vdc5_sig_pol_t tcon_inv; /*!< Polarity inversion control of signal */
dkato 0:853f5b7408a7 349 vdc5_lcd_tcon_pin_t tcon_pin; /*!< LCD TCON output pin select */
dkato 0:853f5b7408a7 350 vdc5_edge_t outcnt_edge; /*!< Output phase control of signal */
dkato 0:853f5b7408a7 351 } vdc5_lcd_tcon_timing_t;
dkato 0:853f5b7408a7 352 /*! Timing signals for driving the LCD panel */
dkato 0:853f5b7408a7 353 typedef enum {
dkato 0:853f5b7408a7 354 VDC5_LCD_TCONSIG_STVA_VS = 0, /*!< STVA/VS */
dkato 0:853f5b7408a7 355 VDC5_LCD_TCONSIG_STVB_VE, /*!< STVB/VE */
dkato 0:853f5b7408a7 356 VDC5_LCD_TCONSIG_STH_SP_HS, /*!< STH/SP/HS */
dkato 0:853f5b7408a7 357 VDC5_LCD_TCONSIG_STB_LP_HE, /*!< STB/LP/HE */
dkato 0:853f5b7408a7 358 VDC5_LCD_TCONSIG_CPV_GCK, /*!< CPV/GCK */
dkato 0:853f5b7408a7 359 VDC5_LCD_TCONSIG_POLA, /*!< POLA */
dkato 0:853f5b7408a7 360 VDC5_LCD_TCONSIG_POLB, /*!< POLB */
dkato 0:853f5b7408a7 361 VDC5_LCD_TCONSIG_DE, /*!< DE */
dkato 0:853f5b7408a7 362 VDC5_LCD_TCONSIG_NUM
dkato 0:853f5b7408a7 363 } vdc5_lcd_tcon_sigsel_t;
dkato 0:853f5b7408a7 364 /*! Output format select */
dkato 0:853f5b7408a7 365 typedef enum {
dkato 0:853f5b7408a7 366 VDC5_LCD_OUTFORMAT_RGB888 = 0, /*!< RGB888 */
dkato 0:853f5b7408a7 367 VDC5_LCD_OUTFORMAT_RGB666, /*!< RGB666 */
dkato 0:853f5b7408a7 368 VDC5_LCD_OUTFORMAT_RGB565, /*!< RGB565 */
dkato 0:853f5b7408a7 369 VDC5_LCD_OUTFORMAT_SERIAL_RGB, /*!< Serial RGB */
dkato 0:853f5b7408a7 370 VDC5_LCD_OUTFORMAT_NUM
dkato 0:853f5b7408a7 371 } vdc5_lcd_outformat_t;
dkato 0:853f5b7408a7 372 /*! Clock frequency control */
dkato 0:853f5b7408a7 373 typedef enum {
dkato 0:853f5b7408a7 374 VDC5_LCD_PARALLEL_CLKFRQ_1 = 0, /*!< 100% speed (parallel RGB) */
dkato 0:853f5b7408a7 375 VDC5_LCD_SERIAL_CLKFRQ_3, /*!< Triple speed (serial RGB) */
dkato 0:853f5b7408a7 376 VDC5_LCD_SERIAL_CLKFRQ_4, /*!< Quadruple speed (serial RGB) */
dkato 0:853f5b7408a7 377 VDC5_LCD_SERIAL_CLKFRQ_NUM
dkato 0:853f5b7408a7 378 } vdc5_lcd_clkfreqsel_t;
dkato 0:853f5b7408a7 379 /*! Scan direction select */
dkato 0:853f5b7408a7 380 typedef enum {
dkato 0:853f5b7408a7 381 VDC5_LCD_SERIAL_SCAN_FORWARD = 0, /*!< Forward scan */
dkato 0:853f5b7408a7 382 VDC5_LCD_SERIAL_SCAN_REVERSE = 1 /*!< Reverse scan */
dkato 0:853f5b7408a7 383 } vdc5_lcd_scan_t;
dkato 0:853f5b7408a7 384 /*! Clock phase adjustment for serial RGB output */
dkato 0:853f5b7408a7 385 typedef enum {
dkato 0:853f5b7408a7 386 VDC5_LCD_SERIAL_CLKPHASE_0 = 0, /*!< 0[clk] */
dkato 0:853f5b7408a7 387 VDC5_LCD_SERIAL_CLKPHASE_1, /*!< 1[clk] */
dkato 0:853f5b7408a7 388 VDC5_LCD_SERIAL_CLKPHASE_2, /*!< 2[clk] */
dkato 0:853f5b7408a7 389 VDC5_LCD_SERIAL_CLKPHASE_3, /*!< 3[clk] */
dkato 0:853f5b7408a7 390 VDC5_LCD_SERIAL_CLKPHASE_NUM
dkato 0:853f5b7408a7 391 } vdc5_lcd_clkphase_t;
dkato 0:853f5b7408a7 392 /*! Display output configuration parameter */
dkato 0:853f5b7408a7 393 typedef struct {
dkato 0:853f5b7408a7 394 uint16_t tcon_half; /*!< 1/2fH timing */
dkato 0:853f5b7408a7 395 uint16_t tcon_offset; /*!< Offset Hsync signal timing */
dkato 0:853f5b7408a7 396 const vdc5_lcd_tcon_timing_t * outctrl[VDC5_LCD_TCONSIG_NUM]; /*!< LCD TCON timing signal parameter */
dkato 0:853f5b7408a7 397 vdc5_edge_t outcnt_lcd_edge; /*!< Output phase control of LCD_DATA23
dkato 0:853f5b7408a7 398 to LCD_DATA0 pin */
dkato 0:853f5b7408a7 399 vdc5_onoff_t out_endian_on; /*!< Bit endian change on/off control */
dkato 0:853f5b7408a7 400 vdc5_onoff_t out_swap_on; /*!< B/R signal swap on/off control */
dkato 0:853f5b7408a7 401 vdc5_lcd_outformat_t out_format; /*!< Output format select */
dkato 0:853f5b7408a7 402 vdc5_lcd_clkfreqsel_t out_frq_sel; /*!< Clock frequency control */
dkato 0:853f5b7408a7 403 vdc5_lcd_scan_t out_dir_sel; /*!< Scan direction select */
dkato 0:853f5b7408a7 404 vdc5_lcd_clkphase_t out_phase; /*!< Clock phase adjustment
dkato 0:853f5b7408a7 405 for serial RGB output */
dkato 0:853f5b7408a7 406 uint32_t bg_color; /*!< Background color in 24-bit RGB color format */
dkato 0:853f5b7408a7 407 } vdc5_output_t;
dkato 0:853f5b7408a7 408
dkato 0:853f5b7408a7 409 /*********************** For R_VDC5_CallbackISR ***********************/
dkato 0:853f5b7408a7 410 /*! VDC5 interrupt type */
dkato 0:853f5b7408a7 411 typedef enum {
dkato 0:853f5b7408a7 412 VDC5_INT_TYPE_S0_VI_VSYNC = 0, /*!< Vsync signal input to scaler 0 */
dkato 0:853f5b7408a7 413 VDC5_INT_TYPE_S0_LO_VSYNC, /*!< Vsync signal output from scaler 0 */
dkato 0:853f5b7408a7 414 VDC5_INT_TYPE_S0_VSYNCERR, /*!< Missing Vsync signal for scaler 0 */
dkato 0:853f5b7408a7 415 VDC5_INT_TYPE_VLINE, /*!< Specified line signal for panel output in graphics 3 */
dkato 0:853f5b7408a7 416 VDC5_INT_TYPE_S0_VFIELD, /*!< Field end signal for recording function in scaler 0 */
dkato 0:853f5b7408a7 417 VDC5_INT_TYPE_IV1_VBUFERR, /*!< Frame buffer write overflow signal for scaler 0 */
dkato 0:853f5b7408a7 418 VDC5_INT_TYPE_IV3_VBUFERR, /*!< Frame buffer read underflow signal for graphics 0 */
dkato 0:853f5b7408a7 419 VDC5_INT_TYPE_IV5_VBUFERR, /*!< Frame buffer read underflow signal for graphics 2 */
dkato 0:853f5b7408a7 420 VDC5_INT_TYPE_IV6_VBUFERR, /*!< Frame buffer read underflow signal for graphics 3 */
dkato 0:853f5b7408a7 421 VDC5_INT_TYPE_S0_WLINE, /*!< Write specification line signal input to scaling-down control block
dkato 0:853f5b7408a7 422 in scaler 0 */
dkato 0:853f5b7408a7 423 VDC5_INT_TYPE_S1_VI_VSYNC, /*!< Vsync signal input to scaler 1 */
dkato 0:853f5b7408a7 424 VDC5_INT_TYPE_S1_LO_VSYNC, /*!< Vsync signal output from scaler 1 */
dkato 0:853f5b7408a7 425 VDC5_INT_TYPE_S1_VSYNCERR, /*!< Missing Vsync signal for scaler 1 */
dkato 0:853f5b7408a7 426 VDC5_INT_TYPE_S1_VFIELD, /*!< Field end signal for recording function in scaler 1 */
dkato 0:853f5b7408a7 427 VDC5_INT_TYPE_IV2_VBUFERR, /*!< Frame buffer write overflow signal for scaler 1 */
dkato 0:853f5b7408a7 428 VDC5_INT_TYPE_IV4_VBUFERR, /*!< Frame buffer read underflow signal for graphics 1 */
dkato 0:853f5b7408a7 429 VDC5_INT_TYPE_S1_WLINE, /*!< Write specification line signal input to scaling-down control block
dkato 0:853f5b7408a7 430 in scaler 1 */
dkato 0:853f5b7408a7 431 VDC5_INT_TYPE_OIR_VI_VSYNC, /*!< Vsync signal input to output image generator */
dkato 0:853f5b7408a7 432 VDC5_INT_TYPE_OIR_LO_VSYNC, /*!< Vsync signal output from output image generator */
dkato 0:853f5b7408a7 433 VDC5_INT_TYPE_OIR_VLINE, /*!< Specified line signal for panel output in output image generator */
dkato 0:853f5b7408a7 434 VDC5_INT_TYPE_OIR_VFIELD, /*!< Field end signal for recording function in output image generator */
dkato 0:853f5b7408a7 435 VDC5_INT_TYPE_IV7_VBUFERR, /*!< Frame buffer write overflow signal for output image generator */
dkato 0:853f5b7408a7 436 VDC5_INT_TYPE_IV8_VBUFERR, /*!< Frame buffer read underflow signal for graphics (OIR) */
dkato 0:853f5b7408a7 437 VDC5_INT_TYPE_NUM /*!< The number of VDC5 interrupt types */
dkato 0:853f5b7408a7 438 } vdc5_int_type_t;
dkato 0:853f5b7408a7 439 /*! Interrupt callback setup parameter */
dkato 0:853f5b7408a7 440 typedef struct {
dkato 0:853f5b7408a7 441 vdc5_int_type_t type; /*!< VDC5 interrupt type */
dkato 0:853f5b7408a7 442 void (* callback)(vdc5_int_type_t); /*!< Interrupt callback function pointer */
dkato 0:853f5b7408a7 443 uint16_t line_num; /*!< Line interrupt set */
dkato 0:853f5b7408a7 444 } vdc5_int_t;
dkato 0:853f5b7408a7 445
dkato 0:853f5b7408a7 446 /*********************** For R_VDC5_WriteDataControl ***********************/
dkato 0:853f5b7408a7 447 /*! Frame buffer writing mode for image processing */
dkato 0:853f5b7408a7 448 typedef enum {
dkato 0:853f5b7408a7 449 VDC5_WR_MD_NORMAL = 0, /*!< Normal */
dkato 0:853f5b7408a7 450 VDC5_WR_MD_MIRROR, /*!< Horizontal mirroring */
dkato 0:853f5b7408a7 451 VDC5_WR_MD_ROT_90DEG, /*!< 90 degree rotation */
dkato 0:853f5b7408a7 452 VDC5_WR_MD_ROT_180DEG, /*!< 180 degree rotation */
dkato 0:853f5b7408a7 453 VDC5_WR_MD_ROT_270DEG, /*!< 270 degree rotation */
dkato 0:853f5b7408a7 454 VDC5_WR_MD_NUM
dkato 0:853f5b7408a7 455 } vdc5_wr_md_t;
dkato 0:853f5b7408a7 456 /*! Scaling-down and rotation parameter */
dkato 0:853f5b7408a7 457 typedef struct {
dkato 0:853f5b7408a7 458 vdc5_period_rect_t res; /*!< Image area to be captured */
dkato 0:853f5b7408a7 459 vdc5_onoff_t res_pfil_sel; /*!< Prefilter mode select for brightness signals (on/off) */
dkato 0:853f5b7408a7 460 uint16_t res_out_vw; /*!< Number of valid lines in vertical direction
dkato 0:853f5b7408a7 461 output by scaling-down control block */
dkato 0:853f5b7408a7 462 uint16_t res_out_hw; /*!< Number of valid horizontal pixels
dkato 0:853f5b7408a7 463 output by scaling-down control block */
dkato 0:853f5b7408a7 464 vdc5_onoff_t adj_sel; /*!< Handling for lack of last-input line (on/off) */
dkato 0:853f5b7408a7 465 vdc5_wr_md_t res_ds_wr_md; /*!< Frame buffer writing mode for image processing */
dkato 0:853f5b7408a7 466 } vdc5_scalingdown_rot_t;
dkato 0:853f5b7408a7 467 /*! Frame buffer swap setting */
dkato 0:853f5b7408a7 468 typedef enum {
dkato 0:853f5b7408a7 469 VDC5_WR_RD_WRSWA_NON = 0, /*!< Not swapped: 1-2-3-4-5-6-7-8 */
dkato 0:853f5b7408a7 470 VDC5_WR_RD_WRSWA_8BIT, /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
dkato 0:853f5b7408a7 471 VDC5_WR_RD_WRSWA_16BIT, /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
dkato 0:853f5b7408a7 472 VDC5_WR_RD_WRSWA_16_8BIT, /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
dkato 0:853f5b7408a7 473 VDC5_WR_RD_WRSWA_32BIT, /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
dkato 0:853f5b7408a7 474 VDC5_WR_RD_WRSWA_32_8BIT, /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
dkato 0:853f5b7408a7 475 VDC5_WR_RD_WRSWA_32_16BIT, /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
dkato 0:853f5b7408a7 476 VDC5_WR_RD_WRSWA_32_16_8BIT, /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
dkato 0:853f5b7408a7 477 VDC5_WR_RD_WRSWA_NUM
dkato 0:853f5b7408a7 478 } vdc5_wr_rd_swa_t;
dkato 0:853f5b7408a7 479 /*! Frame buffer video-signal writing format */
dkato 0:853f5b7408a7 480 typedef enum {
dkato 0:853f5b7408a7 481 VDC5_RES_MD_YCBCR422 = 0, /*!< YCbCr422 */
dkato 0:853f5b7408a7 482 VDC5_RES_MD_RGB565, /*!< RGB565 */
dkato 0:853f5b7408a7 483 VDC5_RES_MD_RGB888, /*!< RGB888 */
dkato 0:853f5b7408a7 484 VDC5_RES_MD_YCBCR444, /*!< YCbCr444 */
dkato 0:853f5b7408a7 485 VDC5_RES_MD_NUM
dkato 0:853f5b7408a7 486 } vdc5_res_md_t;
dkato 0:853f5b7408a7 487 /*! Transfer burst length */
dkato 0:853f5b7408a7 488 typedef enum {
dkato 0:853f5b7408a7 489 VDC5_BST_MD_32BYTE = 0, /*!< 32-byte transfer (4 bursts) */
dkato 0:853f5b7408a7 490 VDC5_BST_MD_128BYTE /*!< 128-byte transfer (16 bursts) */
dkato 0:853f5b7408a7 491 } vdc5_bst_md_t;
dkato 0:853f5b7408a7 492 /*! Field operating mode select */
dkato 0:853f5b7408a7 493 typedef enum {
dkato 0:853f5b7408a7 494 VDC5_RES_INTER_PROGRESSIVE = 0, /*!< Progressive */
dkato 0:853f5b7408a7 495 VDC5_RES_INTER_INTERLACE = 1 /*!< Interlace */
dkato 0:853f5b7408a7 496 } vdc5_res_inter_t;
dkato 0:853f5b7408a7 497 /*! Writing rate */
dkato 0:853f5b7408a7 498 typedef enum {
dkato 0:853f5b7408a7 499 VDC5_RES_FS_RATE_PER1 = 0, /* 1/1 an input signal */
dkato 0:853f5b7408a7 500 VDC5_RES_FS_RATE_PER2, /* 1/2 an input signal */
dkato 0:853f5b7408a7 501 VDC5_RES_FS_RATE_PER4, /* 1/4 an input signal */
dkato 0:853f5b7408a7 502 VDC5_RES_FS_RATE_PER8, /* 1/8 an input signal */
dkato 0:853f5b7408a7 503 VDC5_RES_FS_RATE_NUM
dkato 0:853f5b7408a7 504 } vdc5_res_fs_rate_t;
dkato 0:853f5b7408a7 505 /*! Write field select */
dkato 0:853f5b7408a7 506 typedef enum {
dkato 0:853f5b7408a7 507 VDC5_RES_FLD_SEL_TOP = 0, /*!< Top field */
dkato 0:853f5b7408a7 508 VDC5_RES_FLD_SEL_BOTTOM = 1 /*!< Bottom field */
dkato 0:853f5b7408a7 509 } vdc5_res_fld_sel_t;
dkato 0:853f5b7408a7 510 /*! Data write control parameter */
dkato 0:853f5b7408a7 511 typedef struct {
dkato 0:853f5b7408a7 512 vdc5_scalingdown_rot_t scalingdown_rot;/*!< Scaling-down and rotation parameter */
dkato 0:853f5b7408a7 513 vdc5_wr_rd_swa_t res_wrswa; /*!< Swap setting in frame buffer writing */
dkato 0:853f5b7408a7 514 vdc5_res_md_t res_md; /*!< Frame buffer video-signal writing format */
dkato 0:853f5b7408a7 515 vdc5_bst_md_t res_bst_md; /*!< Transfer burst length for frame buffer writing */
dkato 0:853f5b7408a7 516 vdc5_res_inter_t res_inter; /*!< Field operating mode select */
dkato 0:853f5b7408a7 517 vdc5_res_fs_rate_t res_fs_rate; /*!< Writing rate */
dkato 0:853f5b7408a7 518 vdc5_res_fld_sel_t res_fld_sel; /*!< Write field select */
dkato 0:853f5b7408a7 519 vdc5_onoff_t res_dth_on; /*!< Dither correction on/off */
dkato 0:853f5b7408a7 520 void * base; /*!< Frame buffer base address */
dkato 0:853f5b7408a7 521 uint32_t ln_off; /*!< Frame buffer line offset address [byte] */
dkato 0:853f5b7408a7 522 uint32_t flm_num; /*!< Number of frames of buffer to be written to (res_flm_num + 1) */
dkato 0:853f5b7408a7 523 uint32_t flm_off; /*!< Frame buffer frame offset address [byte] */
dkato 0:853f5b7408a7 524 void * btm_base; /*!< Frame buffer base address for bottom */
dkato 0:853f5b7408a7 525 } vdc5_write_t;
dkato 0:853f5b7408a7 526
dkato 0:853f5b7408a7 527 /*********************** For R_VDC5_ChangeWriteProcess ***********************/
dkato 0:853f5b7408a7 528 /*! Data write change parameter */
dkato 0:853f5b7408a7 529 typedef struct {
dkato 0:853f5b7408a7 530 vdc5_scalingdown_rot_t scalingdown_rot;/*!< Scaling-down and rotation parameter */
dkato 0:853f5b7408a7 531 } vdc5_write_chg_t;
dkato 0:853f5b7408a7 532
dkato 0:853f5b7408a7 533 /*********************** For R_VDC5_ReadDataControl ***********************/
dkato 0:853f5b7408a7 534 /*! Line offset address direction of the frame buffer */
dkato 0:853f5b7408a7 535 typedef enum {
dkato 0:853f5b7408a7 536 VDC5_GR_LN_OFF_DIR_INC = 0, /*!< Increments the address by the line offset address */
dkato 0:853f5b7408a7 537 VDC5_GR_LN_OFF_DIR_DEC /*!< Decrements the address by the line offset address */
dkato 0:853f5b7408a7 538 } vdc5_gr_ln_off_dir_t;
dkato 0:853f5b7408a7 539 /*! Frame buffer address setting signal */
dkato 0:853f5b7408a7 540 typedef enum {
dkato 0:853f5b7408a7 541 VDC5_GR_FLM_SEL_SCALE_DOWN = 0, /*!< Links to scaling-down process */
dkato 0:853f5b7408a7 542 VDC5_GR_FLM_SEL_FLM_NUM, /*!< Selects frame 0 (graphics display) */
dkato 0:853f5b7408a7 543 VDC5_GR_FLM_SEL_DISTORTION, /*!< Links to distortion correction */
dkato 0:853f5b7408a7 544 VDC5_GR_FLM_SEL_POINTER_BUFF, /*!< Links to pointer buffer */
dkato 0:853f5b7408a7 545 VDC5_GR_FLM_SEL_NUM
dkato 0:853f5b7408a7 546 } vdc5_gr_flm_sel_t;
dkato 0:853f5b7408a7 547 /*! Size of the frame buffer to be read */
dkato 0:853f5b7408a7 548 typedef struct {
dkato 0:853f5b7408a7 549 uint16_t in_vw; /*!< Number of lines in a frame */
dkato 0:853f5b7408a7 550 uint16_t in_hw; /*!< Width of the horizontal valid period */
dkato 0:853f5b7408a7 551 } vdc5_width_read_fb_t;
dkato 0:853f5b7408a7 552 /*! Format of the frame buffer read signal */
dkato 0:853f5b7408a7 553 typedef enum {
dkato 0:853f5b7408a7 554 VDC5_GR_FORMAT_RGB565 = 0, /*!< RGB565 */
dkato 0:853f5b7408a7 555 VDC5_GR_FORMAT_RGB888, /*!< RGB888 */
dkato 0:853f5b7408a7 556 VDC5_GR_FORMAT_ARGB1555, /*!< ARGB1555 */
dkato 0:853f5b7408a7 557 VDC5_GR_FORMAT_ARGB4444, /*!< ARGB4444 */
dkato 0:853f5b7408a7 558 VDC5_GR_FORMAT_ARGB8888, /*!< ARGB8888 */
dkato 0:853f5b7408a7 559 VDC5_GR_FORMAT_CLUT8, /*!< CLUT8 */
dkato 0:853f5b7408a7 560 VDC5_GR_FORMAT_CLUT4, /*!< CLUT4 */
dkato 0:853f5b7408a7 561 VDC5_GR_FORMAT_CLUT1, /*!< CLUT1 */
dkato 0:853f5b7408a7 562 VDC5_GR_FORMAT_YCBCR422, /*!< YCbCr422: This setting is prohibited for the graphics 2 and 3 */
dkato 0:853f5b7408a7 563 VDC5_GR_FORMAT_YCBCR444, /*!< YCbCr444: This setting is prohibited for the graphics 2 and 3 */
dkato 0:853f5b7408a7 564 VDC5_GR_FORMAT_RGBA5551, /*!< RGBA5551 */
dkato 0:853f5b7408a7 565 VDC5_GR_FORMAT_RGBA8888, /*!< RGBA8888 */
dkato 0:853f5b7408a7 566 VDC5_GR_FORMAT_NUM /*!< The number of signal formats */
dkato 0:853f5b7408a7 567 } vdc5_gr_format_t;
dkato 0:853f5b7408a7 568 /*! Swapping of data read from buffer in the YCbCr422 format */
dkato 0:853f5b7408a7 569 typedef enum {
dkato 0:853f5b7408a7 570 VDC5_GR_YCCSWAP_CBY0CRY1 = 0,
dkato 0:853f5b7408a7 571 VDC5_GR_YCCSWAP_Y0CBY1CR,
dkato 0:853f5b7408a7 572 VDC5_GR_YCCSWAP_CRY0CBY1,
dkato 0:853f5b7408a7 573 VDC5_GR_YCCSWAP_Y0CRY1CB,
dkato 0:853f5b7408a7 574 VDC5_GR_YCCSWAP_Y1CRY0CB,
dkato 0:853f5b7408a7 575 VDC5_GR_YCCSWAP_CRY1CBY0,
dkato 0:853f5b7408a7 576 VDC5_GR_YCCSWAP_Y1CBY0CR,
dkato 0:853f5b7408a7 577 VDC5_GR_YCCSWAP_CBY1CRY0,
dkato 0:853f5b7408a7 578 VDC5_GR_YCCSWAP_NUM
dkato 0:853f5b7408a7 579 } vdc5_gr_ycc_swap_t;
dkato 0:853f5b7408a7 580 /*! Data read control parameter */
dkato 0:853f5b7408a7 581 typedef struct {
dkato 0:853f5b7408a7 582 vdc5_gr_ln_off_dir_t gr_ln_off_dir; /*!< Line offset address direction of the frame buffer */
dkato 0:853f5b7408a7 583 vdc5_gr_flm_sel_t gr_flm_sel; /*!< Frame buffer address setting signal */
dkato 0:853f5b7408a7 584 vdc5_onoff_t gr_imr_flm_inv; /*!< Frame buffer number for distortion correction */
dkato 0:853f5b7408a7 585 vdc5_bst_md_t gr_bst_md; /*!< Frame buffer burst transfer mode */
dkato 0:853f5b7408a7 586 void * gr_base; /*!< Frame buffer base address */
dkato 0:853f5b7408a7 587 uint32_t gr_ln_off; /*!< Frame buffer line offset address */
dkato 0:853f5b7408a7 588 const vdc5_width_read_fb_t * width_read_fb; /*!< Size of the frame buffer to be read */
dkato 0:853f5b7408a7 589 vdc5_onoff_t adj_sel; /*!< Folding handling (on/off) */
dkato 0:853f5b7408a7 590 vdc5_gr_format_t gr_format; /*!< Format of the frame buffer read signal */
dkato 0:853f5b7408a7 591 vdc5_gr_ycc_swap_t gr_ycc_swap; /*!< Swapping of data read from buffer
dkato 0:853f5b7408a7 592 in the YCbCr422 format */
dkato 0:853f5b7408a7 593 vdc5_wr_rd_swa_t gr_rdswa; /*!< Swap setting in frame buffer reading */
dkato 0:853f5b7408a7 594 vdc5_period_rect_t gr_grc; /*!< Graphics display area */
dkato 0:853f5b7408a7 595 } vdc5_read_t;
dkato 0:853f5b7408a7 596
dkato 0:853f5b7408a7 597 /******************************* For R_VDC5_ChangeReadProcess *******************************/
dkato 0:853f5b7408a7 598 /*! The type of graphics display modes */
dkato 0:853f5b7408a7 599 typedef enum {
dkato 0:853f5b7408a7 600 VDC5_DISPSEL_IGNORED = -1, /*!< Ignored */
dkato 0:853f5b7408a7 601 VDC5_DISPSEL_BACK = 0, /*!< Background color display */
dkato 0:853f5b7408a7 602 VDC5_DISPSEL_LOWER = 1, /*!< Lower-layer graphics display */
dkato 0:853f5b7408a7 603 VDC5_DISPSEL_CURRENT = 2, /*!< Current graphics display */
dkato 0:853f5b7408a7 604 VDC5_DISPSEL_BLEND = 3, /*!< Blended display of lower-layer graphics and current graphics */
dkato 0:853f5b7408a7 605 VDC5_DISPSEL_NUM = 4 /*!< The number of graphics display modes */
dkato 0:853f5b7408a7 606 } vdc5_gr_disp_sel_t;
dkato 0:853f5b7408a7 607 /*! Data read change parameter */
dkato 0:853f5b7408a7 608 typedef struct {
dkato 0:853f5b7408a7 609 void * gr_base; /*!< Frame buffer base address */
dkato 0:853f5b7408a7 610 const vdc5_width_read_fb_t * width_read_fb; /*!< Size of the frame buffer to be read */
dkato 0:853f5b7408a7 611 const vdc5_period_rect_t * gr_grc; /*!< Graphics display area */
dkato 0:853f5b7408a7 612 const vdc5_gr_disp_sel_t * gr_disp_sel; /*!< Graphics display mode */
dkato 0:853f5b7408a7 613 } vdc5_read_chg_t;
dkato 0:853f5b7408a7 614
dkato 0:853f5b7408a7 615 /******************************* For R_VDC5_StartProcess *******************************/
dkato 0:853f5b7408a7 616 /*! Data write/read start parameter */
dkato 0:853f5b7408a7 617 typedef struct {
dkato 0:853f5b7408a7 618 const vdc5_gr_disp_sel_t * gr_disp_sel; /*!< Graphics display mode */
dkato 0:853f5b7408a7 619 } vdc5_start_t;
dkato 0:853f5b7408a7 620
dkato 0:853f5b7408a7 621 /******************************* For R_VDC5_VideoNoiseReduction *******************************/
dkato 0:853f5b7408a7 622 /*! TAP select */
dkato 0:853f5b7408a7 623 typedef enum {
dkato 0:853f5b7408a7 624 VDC5_NR_TAPSEL_1 = 0, /*!< Adjacent pixel */
dkato 0:853f5b7408a7 625 VDC5_NR_TAPSEL_2, /*!< 2 adjacent pixels */
dkato 0:853f5b7408a7 626 VDC5_NR_TAPSEL_3, /*!< 3 adjacent pixels */
dkato 0:853f5b7408a7 627 VDC5_NR_TAPSEL_4, /*!< 4 adjacent pixels */
dkato 0:853f5b7408a7 628 VDC5_NR_TAPSEL_NUM
dkato 0:853f5b7408a7 629 } vdc5_nr_tap_t;
dkato 0:853f5b7408a7 630 /*! Noise reduction gain adjustment */
dkato 0:853f5b7408a7 631 typedef enum {
dkato 0:853f5b7408a7 632 VDC5_NR_GAIN_1_2 = 0, /*!< 1/2 */
dkato 0:853f5b7408a7 633 VDC5_NR_GAIN_1_4, /*!< 1/4 */
dkato 0:853f5b7408a7 634 VDC5_NR_GAIN_1_8, /*!< 1/8 */
dkato 0:853f5b7408a7 635 VDC5_NR_GAIN_1_16, /*!< 1/16 */
dkato 0:853f5b7408a7 636 VDC5_NR_GAIN_NUM
dkato 0:853f5b7408a7 637 } vdc5_nr_gain_t;
dkato 0:853f5b7408a7 638 /*! Noise reduction parameter */
dkato 0:853f5b7408a7 639 typedef struct {
dkato 0:853f5b7408a7 640 vdc5_nr_tap_t nr1d_tap; /*!< TAP select */
dkato 0:853f5b7408a7 641 uint32_t nr1d_th; /*!< Maximum value of coring (absolute value) */
dkato 0:853f5b7408a7 642 vdc5_nr_gain_t nr1d_gain; /*!< Noise reduction gain adjustment */
dkato 0:853f5b7408a7 643 } vdc5_nr_param_t;
dkato 0:853f5b7408a7 644 /*! Noise reduction setup parameter */
dkato 0:853f5b7408a7 645 typedef struct {
dkato 0:853f5b7408a7 646 vdc5_nr_param_t y; /*!< Y/G signal noise reduction parameter */
dkato 0:853f5b7408a7 647 vdc5_nr_param_t cb; /*!< Cb/B signal noise reduction parameter */
dkato 0:853f5b7408a7 648 vdc5_nr_param_t cr; /*!< Cr/R signal noise reduction parameter */
dkato 0:853f5b7408a7 649 } vdc5_noise_reduction_t;
dkato 0:853f5b7408a7 650
dkato 0:853f5b7408a7 651 /******************************* For R_VDC5_ImageColorMatrix *******************************/
dkato 0:853f5b7408a7 652 /*! Color matrix module */
dkato 0:853f5b7408a7 653 typedef enum {
dkato 0:853f5b7408a7 654 VDC5_COLORMTX_IMGCNT = 0, /*!< Input Controller (input video signal) */
dkato 0:853f5b7408a7 655 VDC5_COLORMTX_ADJ_0, /*!< Image quality improver 0 (scaler 0 output) */
dkato 0:853f5b7408a7 656 VDC5_COLORMTX_ADJ_1, /*!< Image quality improver 1 (scaler 1 output) */
dkato 0:853f5b7408a7 657 VDC5_COLORMTX_NUM
dkato 0:853f5b7408a7 658 } vdc5_colormtx_module_t;
dkato 0:853f5b7408a7 659 /*! Operating mode */
dkato 0:853f5b7408a7 660 typedef enum {
dkato 0:853f5b7408a7 661 VDC5_COLORMTX_GBR_GBR = 0, /*!< GBR to GBR */
dkato 0:853f5b7408a7 662 VDC5_COLORMTX_GBR_YCBCR, /*!< GBR to YCbCr */
dkato 0:853f5b7408a7 663 VDC5_COLORMTX_YCBCR_GBR, /*!< YCbCr to GBR */
dkato 0:853f5b7408a7 664 VDC5_COLORMTX_YCBCR_YCBCR, /*!< YCbCr to YCbCr */
dkato 0:853f5b7408a7 665 VDC5_COLORMTX_MODE_NUM /*!< The number of operating modes */
dkato 0:853f5b7408a7 666 } vdc5_colormtx_mode_t;
dkato 0:853f5b7408a7 667 /*! Color matrix offset (DC) adjustment */
dkato 0:853f5b7408a7 668 typedef enum {
dkato 0:853f5b7408a7 669 VDC5_COLORMTX_OFFST_YG = 0, /*!< YG */
dkato 0:853f5b7408a7 670 VDC5_COLORMTX_OFFST_B, /*!< B */
dkato 0:853f5b7408a7 671 VDC5_COLORMTX_OFFST_R, /*!< R */
dkato 0:853f5b7408a7 672 VDC5_COLORMTX_OFFST_NUM /*!< The number of the color matrix DC offset values */
dkato 0:853f5b7408a7 673 } vdc5_colormtx_offset_t;
dkato 0:853f5b7408a7 674 /*! Color matrix signal gain adjustment */
dkato 0:853f5b7408a7 675 typedef enum {
dkato 0:853f5b7408a7 676 VDC5_COLORMTX_GAIN_GG = 0, /*!< GG */
dkato 0:853f5b7408a7 677 VDC5_COLORMTX_GAIN_GB, /*!< GB */
dkato 0:853f5b7408a7 678 VDC5_COLORMTX_GAIN_GR, /*!< GR */
dkato 0:853f5b7408a7 679 VDC5_COLORMTX_GAIN_BG, /*!< BG */
dkato 0:853f5b7408a7 680 VDC5_COLORMTX_GAIN_BB, /*!< BB */
dkato 0:853f5b7408a7 681 VDC5_COLORMTX_GAIN_BR, /*!< BR */
dkato 0:853f5b7408a7 682 VDC5_COLORMTX_GAIN_RG, /*!< RG */
dkato 0:853f5b7408a7 683 VDC5_COLORMTX_GAIN_RB, /*!< RB */
dkato 0:853f5b7408a7 684 VDC5_COLORMTX_GAIN_RR, /*!< RR */
dkato 0:853f5b7408a7 685 VDC5_COLORMTX_GAIN_NUM /*!< The number of the color matrix gain values */
dkato 0:853f5b7408a7 686 } vdc5_colormtx_gain_t;
dkato 0:853f5b7408a7 687 /*! Color matrix setup parameter */
dkato 0:853f5b7408a7 688 typedef struct {
dkato 0:853f5b7408a7 689 vdc5_colormtx_module_t module; /*!< Color matrix module */
dkato 0:853f5b7408a7 690 vdc5_colormtx_mode_t mtx_mode; /*!< Operating mode */
dkato 0:853f5b7408a7 691 uint16_t offset[VDC5_COLORMTX_OFFST_NUM];/*!< Offset (DC) adjustment of Y/G, B, and R signal */
dkato 0:853f5b7408a7 692 uint16_t gain[VDC5_COLORMTX_GAIN_NUM]; /*!< GG, GB, GR, BG, BB, BR, RG, RB, and RR signal
dkato 0:853f5b7408a7 693 gain adjustment */
dkato 0:853f5b7408a7 694 } vdc5_color_matrix_t;
dkato 0:853f5b7408a7 695
dkato 0:853f5b7408a7 696 /******************************* For R_VDC5_ImageEnhancement *******************************/
dkato 0:853f5b7408a7 697 /*! Image quality improver ID */
dkato 0:853f5b7408a7 698 typedef enum {
dkato 0:853f5b7408a7 699 VDC5_IMG_IMPRV_0 = 0, /*!< Image quality improver 0 */
dkato 0:853f5b7408a7 700 VDC5_IMG_IMPRV_1, /*!< Image quality improver 1 */
dkato 0:853f5b7408a7 701 VDC5_IMG_IMPRV_NUM /*!< The number of image quality improvers */
dkato 0:853f5b7408a7 702 } vdc5_imgimprv_id_t;
dkato 0:853f5b7408a7 703
dkato 0:853f5b7408a7 704 /*! Sharpness band */
dkato 0:853f5b7408a7 705 typedef enum {
dkato 0:853f5b7408a7 706 VDC5_IMGENH_SHARP_H1 = 0, /*!< H1: Adjacent pixel used as reference */
dkato 0:853f5b7408a7 707 VDC5_IMGENH_SHARP_H2, /*!< H2: Second adjacent pixel used as reference */
dkato 0:853f5b7408a7 708 VDC5_IMGENH_SHARP_H3, /*!< H3: Third adjacent pixel used as reference */
dkato 0:853f5b7408a7 709 VDC5_IMGENH_SHARP_NUM /*!< The number of horizontal sharpness bands */
dkato 0:853f5b7408a7 710 } vdc5_img_enh_sh_t;
dkato 0:853f5b7408a7 711 /*! Sharpness control parameter */
dkato 0:853f5b7408a7 712 typedef struct {
dkato 0:853f5b7408a7 713 uint8_t shp_clip_o; /*!< Sharpness correction value clipping (on the overshoot side) */
dkato 0:853f5b7408a7 714 uint8_t shp_clip_u; /*!< Sharpness correction value clipping (on the undershoot side) */
dkato 0:853f5b7408a7 715 uint8_t shp_gain_o; /*!< Sharpness edge amplitude value gain (on the overshoot side) */
dkato 0:853f5b7408a7 716 uint8_t shp_gain_u; /*!< Sharpness edge amplitude value gain (on the undershoot side) */
dkato 0:853f5b7408a7 717 uint8_t shp_core; /*!< Active sharpness range */
dkato 0:853f5b7408a7 718 } vdc5_sharpness_ctrl_t;
dkato 0:853f5b7408a7 719 /*! Sharpness setup parameter */
dkato 0:853f5b7408a7 720 typedef struct {
dkato 0:853f5b7408a7 721 vdc5_onoff_t shp_h2_lpf_sel; /*!< LPF selection for folding prevention
dkato 0:853f5b7408a7 722 before H2 edge detection */
dkato 0:853f5b7408a7 723 vdc5_sharpness_ctrl_t hrz_sharp[VDC5_IMGENH_SHARP_NUM]; /*!< Sharpness control parameter (H1, H2, and H3) */
dkato 0:853f5b7408a7 724 } vdc5_enhance_sharp_t;
dkato 0:853f5b7408a7 725 /*! LTI band */
dkato 0:853f5b7408a7 726 typedef enum {
dkato 0:853f5b7408a7 727 VDC5_IMGENH_LTI1 = 0, /*!< H2: Second adjacent pixel used as reference */
dkato 0:853f5b7408a7 728 VDC5_IMGENH_LTI2, /*!< H4: Fourth adjacent pixel used as reference */
dkato 0:853f5b7408a7 729 VDC5_IMGENH_LTI_NUM /*!< The number of horizontal LTI bands */
dkato 0:853f5b7408a7 730 } vdc5_img_enh_lti_t;
dkato 0:853f5b7408a7 731 /*! Median filter reference pixel select */
dkato 0:853f5b7408a7 732 typedef enum {
dkato 0:853f5b7408a7 733 VDC5_LTI_MDFIL_SEL_ADJ2 = 0, /*!< Second adjacent pixel selected as reference */
dkato 0:853f5b7408a7 734 VDC5_LTI_MDFIL_SEL_ADJ1 /*!< Adjacent pixel selected as reference */
dkato 0:853f5b7408a7 735 } vdc5_lti_mdfil_sel_t;
dkato 0:853f5b7408a7 736 /*! LTI control parameter */
dkato 0:853f5b7408a7 737 typedef struct {
dkato 0:853f5b7408a7 738 uint8_t lti_inc_zero; /*!< Median filter LTI correction threshold */
dkato 0:853f5b7408a7 739 uint8_t lti_gain; /*!< LTI edge amplitude value gain */
dkato 0:853f5b7408a7 740 uint8_t lti_core; /*!< LTI coring (maximum core value of 255) */
dkato 0:853f5b7408a7 741 } vdc5_lti_ctrl_t;
dkato 0:853f5b7408a7 742 /*! Luminance Transient Improvement setup parameter */
dkato 0:853f5b7408a7 743 typedef struct {
dkato 0:853f5b7408a7 744 vdc5_onoff_t lti_h2_lpf_sel; /*!< LPF selection for folding prevention
dkato 0:853f5b7408a7 745 before H2 edge detection */
dkato 0:853f5b7408a7 746 vdc5_lti_mdfil_sel_t lti_h4_median_tap_sel; /*!< Median filter reference pixel select */
dkato 0:853f5b7408a7 747 vdc5_lti_ctrl_t lti[VDC5_IMGENH_LTI_NUM]; /*!< LTI control parameter (H2 and H4) */
dkato 0:853f5b7408a7 748 } vdc5_enhance_lti_t;
dkato 0:853f5b7408a7 749
dkato 0:853f5b7408a7 750 /******************************* For R_VDC5_ImageBlackStretch *******************************/
dkato 0:853f5b7408a7 751 /*! Black stretch setup parameter */
dkato 0:853f5b7408a7 752 typedef struct {
dkato 0:853f5b7408a7 753 uint16_t bkstr_st; /*!< Black stretch start point */
dkato 0:853f5b7408a7 754 uint16_t bkstr_d; /*!< Black stretch depth */
dkato 0:853f5b7408a7 755 uint16_t bkstr_t1; /*!< Black stretch time constant (T1) */
dkato 0:853f5b7408a7 756 uint16_t bkstr_t2; /*!< Black stretch time constant (T2) */
dkato 0:853f5b7408a7 757 } vdc5_black_t;
dkato 0:853f5b7408a7 758
dkato 0:853f5b7408a7 759 /******************************* For R_VDC5_AlphaBlending *******************************/
dkato 0:853f5b7408a7 760 /*! Alpha signal of the ARGB1555/ARGB5551 format */
dkato 0:853f5b7408a7 761 typedef struct {
dkato 0:853f5b7408a7 762 uint8_t gr_a0; /*!< Alpha signal when alpha is set to '0' */
dkato 0:853f5b7408a7 763 uint8_t gr_a1; /*!< Alpha signal when alpha is set to '1' */
dkato 0:853f5b7408a7 764 } vdc5_alpha_argb1555_t;
dkato 0:853f5b7408a7 765 /*! Alpha blending in one-pixel units */
dkato 0:853f5b7408a7 766 typedef struct {
dkato 0:853f5b7408a7 767 vdc5_onoff_t gr_acalc_md; /*!< Premultiplication processing at alpha blending
dkato 0:853f5b7408a7 768 in one-pixel units (on/off) */
dkato 0:853f5b7408a7 769 } vdc5_alpha_pixel_t;
dkato 0:853f5b7408a7 770 /*! Alpha blending setup parameter */
dkato 0:853f5b7408a7 771 typedef struct {
dkato 0:853f5b7408a7 772 const vdc5_alpha_argb1555_t * alpha_1bit; /*!< Alpha signal of the ARGB1555/ARGB5551 format */
dkato 0:853f5b7408a7 773 const vdc5_alpha_pixel_t * alpha_pixel;/*!< Premultiplication processing at alpha blending in one-pixel */
dkato 0:853f5b7408a7 774 } vdc5_alpha_blending_t;
dkato 0:853f5b7408a7 775
dkato 0:853f5b7408a7 776 /******************************* For R_VDC5_AlphaBlendingRect *******************************/
dkato 0:853f5b7408a7 777 /*! Parameter for alpha blending in a rectangular area */
dkato 0:853f5b7408a7 778 typedef struct {
dkato 0:853f5b7408a7 779 int16_t gr_arc_coef; /*!< Alpha coefficient for alpha blending in a rectangular area
dkato 0:853f5b7408a7 780 (-255 to 255) */
dkato 0:853f5b7408a7 781 uint8_t gr_arc_rate; /*!< Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
dkato 0:853f5b7408a7 782 uint8_t gr_arc_def; /*!< Initial alpha value for alpha blending in a rectangular area */
dkato 0:853f5b7408a7 783 vdc5_onoff_t gr_arc_mul; /*!< Multiplication processing with current alpha at alpha blending
dkato 0:853f5b7408a7 784 in a rectangular area (on/off) */
dkato 0:853f5b7408a7 785 } vdc5_alpha_rect_t;
dkato 0:853f5b7408a7 786 /*! Selection of lower-layer plane in scaler */
dkato 0:853f5b7408a7 787 typedef struct {
dkato 0:853f5b7408a7 788 vdc5_onoff_t gr_vin_scl_und_sel; /*!< Selection of lower-layer plane in scaler
dkato 0:853f5b7408a7 789 - VDC5_OFF: Selects graphics 0 as lower-layer graphics
dkato 0:853f5b7408a7 790 and graphics 1 as current graphics
dkato 0:853f5b7408a7 791 - VDC5_ON: Selects graphics 1 as lower-layer graphics
dkato 0:853f5b7408a7 792 and graphics 0 as current graphics */
dkato 0:853f5b7408a7 793 } vdc5_scl_und_sel_t;
dkato 0:853f5b7408a7 794 /*! Setup parameter for alpha blending in a rectangular area */
dkato 0:853f5b7408a7 795 typedef struct {
dkato 0:853f5b7408a7 796 const vdc5_pd_disp_rect_t * gr_arc; /*!< Rectangular area subjected to alpha blending */
dkato 0:853f5b7408a7 797 const vdc5_alpha_rect_t * alpha_rect; /*!< Parameter for alpha blending in a rectangular area */
dkato 0:853f5b7408a7 798 const vdc5_scl_und_sel_t * scl_und_sel;/*!< Selection of lower-layer plane in scaler */
dkato 0:853f5b7408a7 799 } vdc5_alpha_blending_rect_t;
dkato 0:853f5b7408a7 800
dkato 0:853f5b7408a7 801 /******************************* For R_VDC5_Chromakey *******************************/
dkato 0:853f5b7408a7 802 /*! Chroma-key setup parameter */
dkato 0:853f5b7408a7 803 typedef struct {
dkato 0:853f5b7408a7 804 uint32_t ck_color; /*!< RGB/CLUT signal for RGB/CLUT-index chroma-key processing */
dkato 0:853f5b7408a7 805 uint32_t rep_color; /*!< Replaced ARGB signal after RGB/CLUT-index chroma-key processing */
dkato 0:853f5b7408a7 806 uint8_t rep_alpha; /*!< Replaced alpha signal after RGB-index chroma-key processing (in 8 bits) */
dkato 0:853f5b7408a7 807 } vdc5_chromakey_t;
dkato 0:853f5b7408a7 808
dkato 0:853f5b7408a7 809 /******************************* For R_VDC5_CLUT *******************************/
dkato 0:853f5b7408a7 810 /*! CLUT setup parameter */
dkato 0:853f5b7408a7 811 typedef struct {
dkato 0:853f5b7408a7 812 uint32_t color_num; /*!< The number of colors in CLUT */
dkato 0:853f5b7408a7 813 const uint32_t * clut; /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
dkato 0:853f5b7408a7 814 } vdc5_clut_t;
dkato 0:853f5b7408a7 815
dkato 0:853f5b7408a7 816 /******************************* For R_VDC5_DisplayCalibration *******************************/
dkato 0:853f5b7408a7 817 /*! Correction circuit sequence control */
dkato 0:853f5b7408a7 818 typedef enum {
dkato 0:853f5b7408a7 819 VDC5_CALIBR_ROUTE_BCG = 0, /*!< Brightness -> contrast -> gamma correction */
dkato 0:853f5b7408a7 820 VDC5_CALIBR_ROUTE_GBC /*!< Gamma correction -> brightness -> contrast */
dkato 0:853f5b7408a7 821 } vdc5_calibr_route_t;
dkato 0:853f5b7408a7 822 /*! Brightness (DC) adjustment parameter */
dkato 0:853f5b7408a7 823 typedef struct {
dkato 0:853f5b7408a7 824 uint16_t pbrt_g; /*!< Brightness (DC) adjustment of G signal */
dkato 0:853f5b7408a7 825 uint16_t pbrt_b; /*!< Brightness (DC) adjustment of B signal */
dkato 0:853f5b7408a7 826 uint16_t pbrt_r; /*!< Brightness (DC) adjustment of R signal */
dkato 0:853f5b7408a7 827 } vdc5_calibr_bright_t;
dkato 0:853f5b7408a7 828 /*! Contrast (gain) adjustment parameter */
dkato 0:853f5b7408a7 829 typedef struct {
dkato 0:853f5b7408a7 830 uint8_t cont_g; /*!< Contrast (gain) adjustment of G signal */
dkato 0:853f5b7408a7 831 uint8_t cont_b; /*!< Contrast (gain) adjustment of B signal */
dkato 0:853f5b7408a7 832 uint8_t cont_r; /*!< Contrast (gain) adjustment of R signal */
dkato 0:853f5b7408a7 833 } vdc5_calibr_contrast_t;
dkato 0:853f5b7408a7 834 /*! Panel dither operation mode */
dkato 0:853f5b7408a7 835 typedef enum {
dkato 0:853f5b7408a7 836 VDC5_PDTH_MD_TRU = 0, /*!< Truncate */
dkato 0:853f5b7408a7 837 VDC5_PDTH_MD_RDOF, /*!< Round-off */
dkato 0:853f5b7408a7 838 VDC5_PDTH_MD_2X2, /*!< 2 x 2 pattern dither */
dkato 0:853f5b7408a7 839 VDC5_PDTH_MD_RAND, /*!< Random pattern dither */
dkato 0:853f5b7408a7 840 VDC5_PDTH_MD_NUM
dkato 0:853f5b7408a7 841 } vdc5_panel_dither_md_t;
dkato 0:853f5b7408a7 842 /*! Panel dithering parameter */
dkato 0:853f5b7408a7 843 typedef struct {
dkato 0:853f5b7408a7 844 vdc5_panel_dither_md_t pdth_sel; /*!< Panel dither operation mode */
dkato 0:853f5b7408a7 845 uint8_t pdth_pa; /*!< Pattern value (A) of 2x2 pattern dither */
dkato 0:853f5b7408a7 846 uint8_t pdth_pb; /*!< Pattern value (B) of 2x2 pattern dither */
dkato 0:853f5b7408a7 847 uint8_t pdth_pc; /*!< Pattern value (C) of 2x2 pattern dither */
dkato 0:853f5b7408a7 848 uint8_t pdth_pd; /*!< Pattern value (D) of 2x2 pattern dither */
dkato 0:853f5b7408a7 849 } vdc5_calibr_dither_t;
dkato 0:853f5b7408a7 850 /*! Display calibration parameter */
dkato 0:853f5b7408a7 851 typedef struct {
dkato 0:853f5b7408a7 852 vdc5_calibr_route_t route; /*!< Correction circuit sequence control */
dkato 0:853f5b7408a7 853 const vdc5_calibr_bright_t * bright; /*!< Brightness (DC) adjustment parameter */
dkato 0:853f5b7408a7 854 const vdc5_calibr_contrast_t * contrast; /*!< Contrast (gain) adjustment parameter */
dkato 0:853f5b7408a7 855 const vdc5_calibr_dither_t * panel_dither; /*!< Panel dithering parameter */
dkato 0:853f5b7408a7 856 } vdc5_disp_calibration_t;
dkato 0:853f5b7408a7 857
dkato 0:853f5b7408a7 858 /******************************* For R_VDC5_GammaCorrection *******************************/
dkato 0:853f5b7408a7 859 /*! Gamma correction setup parameter */
dkato 0:853f5b7408a7 860 typedef struct {
dkato 0:853f5b7408a7 861 const uint16_t * gam_g_gain; /*!< Gain adjustment of area 0 to 31 of G signal */
dkato 0:853f5b7408a7 862 const uint8_t * gam_g_th; /*!< Start threshold of area 1 to 31 of G signal */
dkato 0:853f5b7408a7 863 const uint16_t * gam_b_gain; /*!< Gain adjustment of area 0 to 31 of B signal */
dkato 0:853f5b7408a7 864 const uint8_t * gam_b_th; /*!< Start threshold of area 1 to 31 of B signal */
dkato 0:853f5b7408a7 865 const uint16_t * gam_r_gain; /*!< Gain adjustment of area 0 to 31 of R signal */
dkato 0:853f5b7408a7 866 const uint8_t * gam_r_th; /*!< Start threshold of area 1 to 31 of R signal */
dkato 0:853f5b7408a7 867 } vdc5_gamma_correction_t;
dkato 0:853f5b7408a7 868
dkato 0:853f5b7408a7 869
dkato 0:853f5b7408a7 870 /******************************************************************************
dkato 0:853f5b7408a7 871 Exported global variables
dkato 0:853f5b7408a7 872 ******************************************************************************/
dkato 0:853f5b7408a7 873
dkato 0:853f5b7408a7 874 /******************************************************************************
dkato 0:853f5b7408a7 875 Exported global functions (to be accessed by other files)
dkato 0:853f5b7408a7 876 ******************************************************************************/
dkato 0:853f5b7408a7 877 vdc5_error_t R_VDC5_Initialize(
dkato 0:853f5b7408a7 878 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 879 const vdc5_init_t * const param,
dkato 0:853f5b7408a7 880 void (* const init_func)(uint32_t),
dkato 0:853f5b7408a7 881 const uint32_t user_num);
dkato 0:853f5b7408a7 882 vdc5_error_t R_VDC5_Terminate(const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
dkato 0:853f5b7408a7 883 vdc5_error_t R_VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
dkato 0:853f5b7408a7 884 vdc5_error_t R_VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
dkato 0:853f5b7408a7 885 vdc5_error_t R_VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
dkato 0:853f5b7408a7 886 vdc5_error_t R_VDC5_CallbackISR(const vdc5_channel_t ch, const vdc5_int_t * const param);
dkato 0:853f5b7408a7 887 vdc5_error_t R_VDC5_WriteDataControl(
dkato 0:853f5b7408a7 888 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 889 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 890 const vdc5_write_t * const param);
dkato 0:853f5b7408a7 891 vdc5_error_t R_VDC5_ChangeWriteProcess(
dkato 0:853f5b7408a7 892 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 893 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 894 const vdc5_write_chg_t * const param);
dkato 0:853f5b7408a7 895 vdc5_error_t R_VDC5_ReadDataControl(
dkato 0:853f5b7408a7 896 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 897 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 898 const vdc5_read_t * const param);
dkato 0:853f5b7408a7 899 vdc5_error_t R_VDC5_ChangeReadProcess(
dkato 0:853f5b7408a7 900 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 901 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 902 const vdc5_read_chg_t * const param);
dkato 0:853f5b7408a7 903 vdc5_error_t R_VDC5_StartProcess(
dkato 0:853f5b7408a7 904 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 905 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 906 const vdc5_start_t * const param);
dkato 0:853f5b7408a7 907 vdc5_error_t R_VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 908 vdc5_error_t R_VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
dkato 0:853f5b7408a7 909 vdc5_error_t R_VDC5_VideoNoiseReduction(
dkato 0:853f5b7408a7 910 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 911 const vdc5_onoff_t nr1d_on,
dkato 0:853f5b7408a7 912 const vdc5_noise_reduction_t * const param);
dkato 0:853f5b7408a7 913 vdc5_error_t R_VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
dkato 0:853f5b7408a7 914 vdc5_error_t R_VDC5_ImageEnhancement(
dkato 0:853f5b7408a7 915 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 916 const vdc5_imgimprv_id_t imgimprv_id,
dkato 0:853f5b7408a7 917 const vdc5_onoff_t shp_h_on,
dkato 0:853f5b7408a7 918 const vdc5_enhance_sharp_t * const sharp_param,
dkato 0:853f5b7408a7 919 const vdc5_onoff_t lti_h_on,
dkato 0:853f5b7408a7 920 const vdc5_enhance_lti_t * const lti_param,
dkato 0:853f5b7408a7 921 const vdc5_period_rect_t * const enh_area);
dkato 0:853f5b7408a7 922 vdc5_error_t R_VDC5_ImageBlackStretch(
dkato 0:853f5b7408a7 923 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 924 const vdc5_imgimprv_id_t imgimprv_id,
dkato 0:853f5b7408a7 925 const vdc5_onoff_t bkstr_on,
dkato 0:853f5b7408a7 926 const vdc5_black_t * const param);
dkato 0:853f5b7408a7 927 vdc5_error_t R_VDC5_AlphaBlending(
dkato 0:853f5b7408a7 928 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 929 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 930 const vdc5_alpha_blending_t * const param);
dkato 0:853f5b7408a7 931 vdc5_error_t R_VDC5_AlphaBlendingRect(
dkato 0:853f5b7408a7 932 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 933 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 934 const vdc5_onoff_t gr_arc_on,
dkato 0:853f5b7408a7 935 const vdc5_alpha_blending_rect_t * const param);
dkato 0:853f5b7408a7 936 vdc5_error_t R_VDC5_Chromakey(
dkato 0:853f5b7408a7 937 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 938 const vdc5_layer_id_t layer_id,
dkato 0:853f5b7408a7 939 const vdc5_onoff_t gr_ck_on,
dkato 0:853f5b7408a7 940 const vdc5_chromakey_t * const param);
dkato 0:853f5b7408a7 941 vdc5_error_t R_VDC5_CLUT(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param);
dkato 0:853f5b7408a7 942 vdc5_error_t R_VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
dkato 0:853f5b7408a7 943 vdc5_error_t R_VDC5_GammaCorrection(
dkato 0:853f5b7408a7 944 const vdc5_channel_t ch,
dkato 0:853f5b7408a7 945 const vdc5_onoff_t gam_on,
dkato 0:853f5b7408a7 946 const vdc5_gamma_correction_t * const param);
dkato 0:853f5b7408a7 947
dkato 0:853f5b7408a7 948 void (*R_VDC5_GetISR(const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense);
dkato 0:853f5b7408a7 949
dkato 0:853f5b7408a7 950
dkato 0:853f5b7408a7 951 #ifdef __cplusplus
dkato 0:853f5b7408a7 952 }
dkato 0:853f5b7408a7 953 #endif /* __cplusplus */
dkato 0:853f5b7408a7 954
dkato 0:853f5b7408a7 955
dkato 0:853f5b7408a7 956 #endif /* R_VDC5_H */
dkato 0:853f5b7408a7 957