karthick B / GR-PEACH_video

vedio_gr_peach

Fork of GR-PEACH_video by Renesas

inc/lcd_analog_rgb_ch0.h@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
0:853f5b7408a7 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file lcd_analog_rgb_ch0.h
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief LCD panel for vdc5 channel 0 definition header
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 #ifndef LCD_ANALOG_RGB_CH0_H
dkato 0:853f5b7408a7 32 #define LCD_ANALOG_RGB_CH0_H
dkato 0:853f5b7408a7 33
dkato 0:853f5b7408a7 34 #ifndef LCD_PANEL_H
dkato 0:853f5b7408a7 35 #error Do not include this file directly!
dkato 0:853f5b7408a7 36 #else
dkato 0:853f5b7408a7 37 /******************************************************************************
dkato 0:853f5b7408a7 38 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 39 ******************************************************************************/
dkato 0:853f5b7408a7 40 #include <stdlib.h>
dkato 0:853f5b7408a7 41
dkato 0:853f5b7408a7 42 #include "r_typedefs.h"
dkato 0:853f5b7408a7 43
dkato 0:853f5b7408a7 44 #include "r_vdc5.h"
dkato 0:853f5b7408a7 45
dkato 0:853f5b7408a7 46 #include "lcd_analog_rgb.h"
dkato 0:853f5b7408a7 47
dkato 0:853f5b7408a7 48
dkato 0:853f5b7408a7 49 /******************************************************************************
dkato 0:853f5b7408a7 50 Macro definitions
dkato 0:853f5b7408a7 51 ******************************************************************************/
dkato 0:853f5b7408a7 52 /* Option board (part number: RTK7721000B00000BR)
dkato 0:853f5b7408a7 53 ADV7123 (Video DAC), U8
dkato 0:853f5b7408a7 54 Analog RGB D-sub15 (RGB888), J15 */
dkato 0:853f5b7408a7 55 #define LCD_CH0_S_HSYNC (0u) /* Hsync start position */
dkato 0:853f5b7408a7 56 #define LCD_CH0_W_HSYNC (LCD_SVGA_H_SYNC_WIDTH) /* Hsync width */
dkato 0:853f5b7408a7 57 #define LCD_CH0_POL_HSYNC (LCD_SVGA_H_POLARITY) /* Polarity of Hsync pulse */
dkato 0:853f5b7408a7 58 /* LCD display area size, horizontal start position */
dkato 0:853f5b7408a7 59 #define LCD_CH0_DISP_HS (LCD_SVGA_H_SYNC_WIDTH + LCD_SVGA_H_BACK_PORCH)
dkato 0:853f5b7408a7 60 #define LCD_CH0_DISP_HW (LCD_SVGA_H_VISIBLE_AREA) /* LCD display area size, horizontal width */
dkato 0:853f5b7408a7 61
dkato 0:853f5b7408a7 62 /* Vsync start position */
dkato 0:853f5b7408a7 63 #define LCD_CH0_S_VSYNC (LCD_SVGA_V_BACK_PORCH + LCD_SVGA_V_VISIBLE_AREA + LCD_SVGA_V_FRONT_PORCH)
dkato 0:853f5b7408a7 64 #define LCD_CH0_W_VSYNC (LCD_SVGA_V_SYNC_WIDTH) /* Vsync width */
dkato 0:853f5b7408a7 65 #define LCD_CH0_POL_VSYNC (LCD_SVGA_V_POLARITY) /* Polarity of Vsync pulse */
dkato 0:853f5b7408a7 66 #define LCD_CH0_DISP_VS (LCD_SVGA_V_BACK_PORCH) /* LCD display area size, vertical start position */
dkato 0:853f5b7408a7 67 #define LCD_CH0_DISP_VW (LCD_SVGA_V_VISIBLE_AREA) /* LCD display area size, height (vertical width) */
dkato 0:853f5b7408a7 68
dkato 0:853f5b7408a7 69 #define LCD_CH0_SIG_FV (LCD_SVGA_V_TOTAL - 1u) /* Free-running Vsync period */
dkato 0:853f5b7408a7 70 #define LCD_CH0_SIG_FH (LCD_SVGA_H_TOTAL - 1u) /* Hsync period */
dkato 0:853f5b7408a7 71 /* Pixel data is latched in the rising edge of pixel clock on ADV7123.
dkato 0:853f5b7408a7 72 Therefore, pixel data should be output from VDC5 at the falling edge of the clock. */
dkato 0:853f5b7408a7 73 #define LCD_CH0_OUT_EDGE VDC5_EDGE_FALLING /* Output phase control of LCD_DATA[23:0] signal */
dkato 0:853f5b7408a7 74 #define LCD_CH0_OUT_FORMAT VDC5_LCD_OUTFORMAT_RGB888 /* LCD output format select */
dkato 0:853f5b7408a7 75
dkato 0:853f5b7408a7 76 #define LCD_CH0_PANEL_CLK VDC5_PANEL_ICKSEL_LVDS /* Panel clock select */
dkato 0:853f5b7408a7 77 #define LCD_CH0_PANEL_CLK_DIV VDC5_PANEL_CLKDIV_1_1 /* Panel clock frequency division ratio */
dkato 0:853f5b7408a7 78
dkato 0:853f5b7408a7 79 #define LCD_CH0_TCON_HALF (LCD_CH0_SIG_FH / 2u) /* TCON reference timing, 1/2fH timing */
dkato 0:853f5b7408a7 80 #define LCD_CH0_TCON_OFFSET (0u) /* TCON reference timing, offset Hsync signal timing */
dkato 0:853f5b7408a7 81
dkato 0:853f5b7408a7 82
dkato 0:853f5b7408a7 83 /******************************************************************************
dkato 0:853f5b7408a7 84 Typedef definitions
dkato 0:853f5b7408a7 85 ******************************************************************************/
dkato 0:853f5b7408a7 86
dkato 0:853f5b7408a7 87 /******************************************************************************
dkato 0:853f5b7408a7 88 Exported global functions (to be accessed by other files)
dkato 0:853f5b7408a7 89 ******************************************************************************/
dkato 0:853f5b7408a7 90 void GRAPHICS_SetLcdPanel_Ch0(void);
dkato 0:853f5b7408a7 91 void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t * * const outctrl);
dkato 0:853f5b7408a7 92
dkato 0:853f5b7408a7 93
dkato 0:853f5b7408a7 94 #endif /* LCD_PANEL_H not defined */
dkato 0:853f5b7408a7 95 #endif /* LCD_ANALOG_RGB_CH0_H */