karthick B / GR-PEACH_video

vedio_gr_peach

Fork of GR-PEACH_video by Renesas

drivers/vdec/include/r_vdec.h@4:aeefe5171463, 2016-06-30 (annotated)

Committer:
dkato
Date:
Thu Jun 30 11:00:37 2016 +0000
Revision:
4:aeefe5171463
Parent:
0:853f5b7408a7 
Add ARGB4444 to graphics layer read format.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file r_vdec.h
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief VDEC driver API definitions
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 #ifndef R_VDEC_H
dkato 0:853f5b7408a7 32 #define R_VDEC_H
dkato 0:853f5b7408a7 33
dkato 0:853f5b7408a7 34 /******************************************************************************
dkato 0:853f5b7408a7 35 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 36 ******************************************************************************/
dkato 0:853f5b7408a7 37 #include "r_vdec_user.h"
dkato 0:853f5b7408a7 38
dkato 0:853f5b7408a7 39
dkato 0:853f5b7408a7 40 #ifdef __cplusplus
dkato 0:853f5b7408a7 41 extern "C"
dkato 0:853f5b7408a7 42 {
dkato 0:853f5b7408a7 43 #endif /* __cplusplus */
dkato 0:853f5b7408a7 44
dkato 0:853f5b7408a7 45
dkato 0:853f5b7408a7 46 /******************************************************************************
dkato 0:853f5b7408a7 47 Macro definitions
dkato 0:853f5b7408a7 48 ******************************************************************************/
dkato 0:853f5b7408a7 49 /*! The number of chroma filter TAP coefficient values for Y/C separation */
dkato 0:853f5b7408a7 50 #define VDEC_CHRFIL_TAPCOEF_NUM (9)
dkato 0:853f5b7408a7 51
dkato 0:853f5b7408a7 52
dkato 0:853f5b7408a7 53 /******************************************************************************
dkato 0:853f5b7408a7 54 Typedef definitions
dkato 0:853f5b7408a7 55 ******************************************************************************/
dkato 0:853f5b7408a7 56 /*! Error codes of the VDEC driver */
dkato 0:853f5b7408a7 57 typedef enum {
dkato 0:853f5b7408a7 58 VDEC_OK = 0, /*!< Normal termination */
dkato 0:853f5b7408a7 59 VDEC_ERR_CHANNEL, /*!< Invalid channel error */
dkato 0:853f5b7408a7 60 VDEC_ERR_PARAM, /*!< Parameter error */
dkato 0:853f5b7408a7 61 VDEC_ERR_NUM /*!< The number of the error codes */
dkato 0:853f5b7408a7 62 } vdec_error_t;
dkato 0:853f5b7408a7 63
dkato 0:853f5b7408a7 64 /*! VDEC channel */
dkato 0:853f5b7408a7 65 typedef enum {
dkato 0:853f5b7408a7 66 VDEC_CHANNEL_0 = 0, /*!< Channel 0 */
dkato 0:853f5b7408a7 67 VDEC_CHANNEL_1, /*!< Channel 1 */
dkato 0:853f5b7408a7 68 VDEC_CHANNEL_NUM /*!< The number of channels */
dkato 0:853f5b7408a7 69 } vdec_channel_t;
dkato 0:853f5b7408a7 70
dkato 0:853f5b7408a7 71 /*! On/Off */
dkato 0:853f5b7408a7 72 typedef enum {
dkato 0:853f5b7408a7 73 VDEC_OFF = 0, /*!< Off */
dkato 0:853f5b7408a7 74 VDEC_ON = 1 /*!< On */
dkato 0:853f5b7408a7 75 } vdec_onoff_t;
dkato 0:853f5b7408a7 76
dkato 0:853f5b7408a7 77 /*********************** For R_VDEC_Initialize ***********************/
dkato 0:853f5b7408a7 78 /*! Input pin control */
dkato 0:853f5b7408a7 79 typedef enum {
dkato 0:853f5b7408a7 80 VDEC_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input */
dkato 0:853f5b7408a7 81 VDEC_ADC_VINSEL_VIN2, /*!< VIN2 input */
dkato 0:853f5b7408a7 82 VDEC_ADC_VINSEL_NUM /*!< The number of input pins */
dkato 0:853f5b7408a7 83 } vdec_adc_vinsel_t;
dkato 0:853f5b7408a7 84
dkato 0:853f5b7408a7 85 /*********************** For R_VDEC_ActivePeriod ***********************/
dkato 0:853f5b7408a7 86 /*! Active image period parameter */
dkato 0:853f5b7408a7 87 typedef struct {
dkato 0:853f5b7408a7 88 uint16_t srcleft; /*!< Left end of input video signal capturing area */
dkato 0:853f5b7408a7 89 uint16_t srctop; /*!< Top end of input video signal capturing area */
dkato 0:853f5b7408a7 90 uint16_t srcheight; /*!< Height of input video signal capturing area */
dkato 0:853f5b7408a7 91 uint16_t srcwidth; /*!< Width of input video signal capturing area */
dkato 0:853f5b7408a7 92 } vdec_active_period_t;
dkato 0:853f5b7408a7 93
dkato 0:853f5b7408a7 94 /*********************** For R_VDEC_SyncSeparation ***********************/
dkato 0:853f5b7408a7 95 /*! LPF cutoff frequency before vertical sync separation */
dkato 0:853f5b7408a7 96 typedef enum {
dkato 0:853f5b7408a7 97 VDEC_LPF_VSYNC_NONE = 0, /*!< None */
dkato 0:853f5b7408a7 98 VDEC_LPF_VSYNC_0_94, /*!< 0.94 MHz */
dkato 0:853f5b7408a7 99 VDEC_LPF_VSYNC_0_67, /*!< 0.67 MHz */
dkato 0:853f5b7408a7 100 VDEC_LPF_VSYNC_0_54, /*!< 0.54 MHz */
dkato 0:853f5b7408a7 101 VDEC_LPF_VSYNC_0_47, /*!< 0.47 MHz */
dkato 0:853f5b7408a7 102 VDEC_LPF_VSYNC_0_34, /*!< 0.34 MHz */
dkato 0:853f5b7408a7 103 VDEC_LPF_VSYNC_0_27, /*!< 0.27 MHz */
dkato 0:853f5b7408a7 104 VDEC_LPF_VSYNC_0_23, /*!< 0.23 MHz */
dkato 0:853f5b7408a7 105 VDEC_LPF_VSYNC_NUM
dkato 0:853f5b7408a7 106 } vdec_lpfvsync_t;
dkato 0:853f5b7408a7 107 /*! LPF cutoff frequency before horizontal sync separation */
dkato 0:853f5b7408a7 108 typedef enum {
dkato 0:853f5b7408a7 109 VDEC_LPF_HSYNC_NONE = 0, /*!< None */
dkato 0:853f5b7408a7 110 VDEC_LPF_HSYNC_2_15, /*!< 2.15 MHz */
dkato 0:853f5b7408a7 111 VDEC_LPF_HSYNC_1_88, /*!< 1.88 MHz */
dkato 0:853f5b7408a7 112 VDEC_LPF_HSYNC_1_34, /*!< 1.34 MHz */
dkato 0:853f5b7408a7 113 VDEC_LPF_HSYNC_1_07, /*!< 1.07 MHz */
dkato 0:853f5b7408a7 114 VDEC_LPF_HSYNC_0_94, /*!< 0.94 MHz */
dkato 0:853f5b7408a7 115 VDEC_LPF_HSYNC_0_67, /*!< 0.67 MHz */
dkato 0:853f5b7408a7 116 VDEC_LPF_HSYNC_0_54, /*!< 0.54 MHz */
dkato 0:853f5b7408a7 117 VDEC_LPF_HSYNC_NUM
dkato 0:853f5b7408a7 118 } vdec_lpfhsync_t;
dkato 0:853f5b7408a7 119 /*! Noise reduction LPF parameter */
dkato 0:853f5b7408a7 120 typedef struct {
dkato 0:853f5b7408a7 121 vdec_lpfvsync_t lpfvsync; /*!< LPF cutoff frequency before vertical sync separation */
dkato 0:853f5b7408a7 122 vdec_lpfhsync_t lpfhsync; /*!< LPF cutoff frequency before horizontal sync separation */
dkato 0:853f5b7408a7 123 } vdec_noise_rd_lpf_t;
dkato 0:853f5b7408a7 124 /*! Reference level operation speed control for composite sync separation (for Hsync signal) */
dkato 0:853f5b7408a7 125 typedef enum {
dkato 0:853f5b7408a7 126 VDEC_VELOCITY_SHIFT_1 = 0, /*!< x1 */
dkato 0:853f5b7408a7 127 VDEC_VELOCITY_SHIFT_2, /*!< x2 */
dkato 0:853f5b7408a7 128 VDEC_VELOCITY_SHIFT_4, /*!< x4 */
dkato 0:853f5b7408a7 129 VDEC_VELOCITY_SHIFT_8, /*!< x8 */
dkato 0:853f5b7408a7 130 VDEC_VELOCITY_SHIFT_16, /*!< x16 */
dkato 0:853f5b7408a7 131 VDEC_VELOCITY_SHIFT_32, /*!< x32 */
dkato 0:853f5b7408a7 132 VDEC_VELOCITY_SHIFT_64, /*!< x64 */
dkato 0:853f5b7408a7 133 VDEC_VELOCITY_SHIFT_128, /*!< x128 */
dkato 0:853f5b7408a7 134 VDEC_VELOCITY_SHIFT_256, /*!< x256 */
dkato 0:853f5b7408a7 135 VDEC_VELOCITY_SHIFT_NUM
dkato 0:853f5b7408a7 136 } vdec_velocityshift_h_t;
dkato 0:853f5b7408a7 137 /*! Auto-slice level setting for composite sync separation circuit */
dkato 0:853f5b7408a7 138 typedef enum {
dkato 0:853f5b7408a7 139 VDEC_SLICE_MODE_MANULAL = 0, /*!< Manual setting */
dkato 0:853f5b7408a7 140 VDEC_SLICE_MODE_AUTO_25, /*!< 25% of sync depth (Auto) */
dkato 0:853f5b7408a7 141 VDEC_SLICE_MODE_AUTO_50, /*!< 50% of sync depth (Auto) */
dkato 0:853f5b7408a7 142 VDEC_SLICE_MODE_AUTO_75, /*!< 75% of sync depth (Auto) */
dkato 0:853f5b7408a7 143 VDEC_SLICE_MODE_NUM
dkato 0:853f5b7408a7 144 } vdec_slicermode_t;
dkato 0:853f5b7408a7 145 /*! Clipping level */
dkato 0:853f5b7408a7 146 typedef enum {
dkato 0:853f5b7408a7 147 VDEC_CLIP_LV_512 = 0, /*!< 512 */
dkato 0:853f5b7408a7 148 VDEC_CLIP_LV_546, /*!< 546 */
dkato 0:853f5b7408a7 149 VDEC_CLIP_LV_580, /*!< 580 */
dkato 0:853f5b7408a7 150 VDEC_CLIP_LV_614, /*!< 614 */
dkato 0:853f5b7408a7 151 VDEC_CLIP_LV_648, /*!< 648 */
dkato 0:853f5b7408a7 152 VDEC_CLIP_LV_682, /*!< 682 */
dkato 0:853f5b7408a7 153 VDEC_CLIP_LV_716, /*!< 716 */
dkato 0:853f5b7408a7 154 VDEC_CLIP_LV_750, /*!< 750 */
dkato 0:853f5b7408a7 155 VDEC_CLIP_LV_785, /*!< 785 */
dkato 0:853f5b7408a7 156 VDEC_CLIP_LV_819, /*!< 819 */
dkato 0:853f5b7408a7 157 VDEC_CLIP_LV_853, /*!< 853 */
dkato 0:853f5b7408a7 158 VDEC_CLIP_LV_887, /*!< 887 */
dkato 0:853f5b7408a7 159 VDEC_CLIP_LV_921, /*!< 921 */
dkato 0:853f5b7408a7 160 VDEC_CLIP_LV_955, /*!< 955 */
dkato 0:853f5b7408a7 161 VDEC_CLIP_LV_989, /*!< 989 */
dkato 0:853f5b7408a7 162 VDEC_CLIP_LV_1023, /*!< 1023 */
dkato 0:853f5b7408a7 163 VDEC_CLIP_LV_NUM
dkato 0:853f5b7408a7 164 } vdec_ssclipsel_t;
dkato 0:853f5b7408a7 165 /*! Sync slicer */
dkato 0:853f5b7408a7 166 typedef struct {
dkato 0:853f5b7408a7 167 vdec_velocityshift_h_t velocityshift_h; /*!< Reference level operation speed control for
dkato 0:853f5b7408a7 168 composite sync separation (for Hsync signal) */
dkato 0:853f5b7408a7 169 vdec_slicermode_t slicermode_h; /*!< Auto-slice level setting for composite sync separation circuit
dkato 0:853f5b7408a7 170 (for Hsync signal) */
dkato 0:853f5b7408a7 171 vdec_slicermode_t slicermode_v; /*!< Auto-slice level setting for composite sync separation circuit
dkato 0:853f5b7408a7 172 (for Vsync signal) */
dkato 0:853f5b7408a7 173 uint16_t syncmaxduty_h; /*!< Max ratio of horizontal cycle
dkato 0:853f5b7408a7 174 to horizontal sync signal pulse width */
dkato 0:853f5b7408a7 175 uint16_t syncminduty_h; /*!< Min ratio of horizontal cycle
dkato 0:853f5b7408a7 176 to horizontal sync signal pulse width */
dkato 0:853f5b7408a7 177 vdec_ssclipsel_t ssclipsel; /*!< Clipping level */
dkato 0:853f5b7408a7 178 uint16_t csyncslice_h; /*!< Slice level for composite sync signal separation
dkato 0:853f5b7408a7 179 (for Hsync signal) */
dkato 0:853f5b7408a7 180 uint16_t syncmaxduty_v; /*!< Max ratio of horizontal cycle
dkato 0:853f5b7408a7 181 to vertical sync signal pulse width */
dkato 0:853f5b7408a7 182 uint16_t syncminduty_v; /*!< Min ratio of horizontal cycle
dkato 0:853f5b7408a7 183 to horizontal sync signal pulse width */
dkato 0:853f5b7408a7 184 vdec_onoff_t vsyncdelay; /*!< Delays the separated vertical sync signal
dkato 0:853f5b7408a7 185 for 1/4 horizontal cycle */
dkato 0:853f5b7408a7 186 uint16_t vsyncslice; /*!< Threshold for vertical sync separation */
dkato 0:853f5b7408a7 187 uint16_t csyncslice_v; /*!< Slice level for composite sync signal separation
dkato 0:853f5b7408a7 188 (for Vsync signal) */
dkato 0:853f5b7408a7 189 } vdec_sync_slicer_t;
dkato 0:853f5b7408a7 190 /*! Horizontal AFC VBI period operating mode */
dkato 0:853f5b7408a7 191 typedef enum {
dkato 0:853f5b7408a7 192 VDEC_HAFCMD_FIX_PHST = 0, /*!< Loop gain is fixed and phase comparison is stopped
dkato 0:853f5b7408a7 193 during VBI period */
dkato 0:853f5b7408a7 194 VDEC_HAFCMD_FIX_LGRD, /*!< Loop gain is fixed and loop gain is reduced during VBI period */
dkato 0:853f5b7408a7 195 VDEC_HAFCMD_AUTO_PHST, /*!< Loop gain is automatically controlled and
dkato 0:853f5b7408a7 196 phase comparison is stopped during VBI period */
dkato 0:853f5b7408a7 197 VDEC_HAFCMD_AUTO_LGRD, /*!< Loop gain is automatically controlled and loop gain is reduced
dkato 0:853f5b7408a7 198 during VBI period */
dkato 0:853f5b7408a7 199 VDEC_HAFCMD_NUM
dkato 0:853f5b7408a7 200 } vdec_hafcmode_t;
dkato 0:853f5b7408a7 201 /*! Phase comparator feedback adjust for low sync signal lock stability */
dkato 0:853f5b7408a7 202 typedef enum {
dkato 0:853f5b7408a7 203 VDEC_PHDET_DIV_1_1 = 0, /*!< 1/1 */
dkato 0:853f5b7408a7 204 VDEC_PHDET_DIV_1_2, /*!< 1/2 */
dkato 0:853f5b7408a7 205 VDEC_PHDET_DIV_1_4, /*!< 1/4 */
dkato 0:853f5b7408a7 206 VDEC_PHDET_DIV_1_8, /*!< 1/8 */
dkato 0:853f5b7408a7 207 VDEC_PHDET_DIV_1_16, /*!< 1/16 */
dkato 0:853f5b7408a7 208 VDEC_PHDET_DIV_1_32, /*!< 1/32 */
dkato 0:853f5b7408a7 209 VDEC_PHDET_DIV_NUM
dkato 0:853f5b7408a7 210 } vdec_phdet_div_t;
dkato 0:853f5b7408a7 211 /*! Horizontal AFC parameter */
dkato 0:853f5b7408a7 212 typedef struct {
dkato 0:853f5b7408a7 213 uint16_t hafcgain; /*!< Horizontal AFC loop gain */
dkato 0:853f5b7408a7 214 uint16_t hafctyp; /*!< Horizontal AFC center oscillation frequency */
dkato 0:853f5b7408a7 215 uint16_t hafcstart; /*!< Start line of horizontal AFC normal operation
dkato 0:853f5b7408a7 216 (VBI process end line) */
dkato 0:853f5b7408a7 217 vdec_onoff_t nox2hosc; /*!< Disable of horizontal AFC double speed detection */
dkato 0:853f5b7408a7 218 uint16_t hafcmax; /*!< Maximum oscillation frequency of horizontal AFC */
dkato 0:853f5b7408a7 219 uint16_t hafcend; /*!< End line of horizontal AFC normal operation
dkato 0:853f5b7408a7 220 (VBI process start line) */
dkato 0:853f5b7408a7 221 vdec_hafcmode_t hafcmode; /*!< Horizontal AFC VBI period operating mode */
dkato 0:853f5b7408a7 222 uint16_t hafcmin; /*!< Min oscillation frequency of horizontal AFC */
dkato 0:853f5b7408a7 223 vdec_onoff_t phdet_fix; /*!< Forcible or LOWGAIN control */
dkato 0:853f5b7408a7 224 vdec_phdet_div_t phdet_div; /*!< Phase comparator feedback adjust for low sync signal lock stability */
dkato 0:853f5b7408a7 225 } vdec_horizontal_afc_t;
dkato 0:853f5b7408a7 226 /*! Vertical countdown center oscillation frequency */
dkato 0:853f5b7408a7 227 typedef enum {
dkato 0:853f5b7408a7 228 VDEC_VCD_FRQ_AUTO = 0, /*!< Auto-detection */
dkato 0:853f5b7408a7 229 VDEC_VCD_FRQ_50HZ, /*!< 50.00 Hz */
dkato 0:853f5b7408a7 230 VDEC_VCD_FRQ_59_94HZ, /*!< 59.94 Hz */
dkato 0:853f5b7408a7 231 VDEC_VCD_FRQ_60HZ, /*!< 60.00 Hz */
dkato 0:853f5b7408a7 232 VDEC_VCD_FRQ_NUM
dkato 0:853f5b7408a7 233 } vdec_vcddefault_t;
dkato 0:853f5b7408a7 234 /*! Vertical count-down parameter */
dkato 0:853f5b7408a7 235 typedef struct {
dkato 0:853f5b7408a7 236 vdec_onoff_t novcd50_; /*!< Vertical countdown 50-Hz oscillation mode */
dkato 0:853f5b7408a7 237 vdec_onoff_t novcd60_; /*!< Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
dkato 0:853f5b7408a7 238 vdec_vcddefault_t vcddefault; /*!< Vertical countdown center oscillation frequency */
dkato 0:853f5b7408a7 239 uint16_t vcdwindow; /*!< Vertical countdown sync area */
dkato 0:853f5b7408a7 240 uint16_t vcdoffset; /*!< Vertical countdown minimum oscillation frequency */
dkato 0:853f5b7408a7 241 } vdec_vcount_down_t;
dkato 0:853f5b7408a7 242 /*! AGC/PGA parameter */
dkato 0:853f5b7408a7 243 typedef struct {
dkato 0:853f5b7408a7 244 vdec_onoff_t agcmode; /*!< A/D converter AGC ON/OFF control & PGA switch */
dkato 0:853f5b7408a7 245 vdec_onoff_t doreduce; /*!< Manual control of sync signal amplitude detection during VBI period */
dkato 0:853f5b7408a7 246 vdec_onoff_t noreduce_; /*!< Control of sync signal amplitude detection during VBI period */
dkato 0:853f5b7408a7 247 uint16_t agcresponse; /*!< AGC response speed */
dkato 0:853f5b7408a7 248 uint16_t agclevel; /*!< Sync signal reference amplitude */
dkato 0:853f5b7408a7 249 uint16_t agcprecis; /*!< AGC gain adjustment accuracy */
dkato 0:853f5b7408a7 250 uint16_t pga_gain; /*!< PGA gain */
dkato 0:853f5b7408a7 251 } vdec_agc_t;
dkato 0:853f5b7408a7 252 /*! Peak luminance value to operate peak limiter */
dkato 0:853f5b7408a7 253 typedef enum {
dkato 0:853f5b7408a7 254 VDEC_PEAKLV_LIM_OFF =0, /*!< Limiter OFF */
dkato 0:853f5b7408a7 255 VDEC_PEAKLV_1008, /*!< 1008 LSB */
dkato 0:853f5b7408a7 256 VDEC_PEAKLV_992, /*!< 992 LSB */
dkato 0:853f5b7408a7 257 VDEC_PEAKLV_960, /*!< 960 LSB */
dkato 0:853f5b7408a7 258 VDEC_PEAKLV_NUM
dkato 0:853f5b7408a7 259 } vdec_peaklevel_t;
dkato 0:853f5b7408a7 260 /*! Maximum compression rate of peak limiter */
dkato 0:853f5b7408a7 261 typedef enum {
dkato 0:853f5b7408a7 262 VDEC_PEAKRATIO_50 = 0, /*!< Compressed up to 50% */
dkato 0:853f5b7408a7 263 VDEC_PEAKRATIO_25, /*!< Compressed up to 25% */
dkato 0:853f5b7408a7 264 VDEC_PEAKRATIO_12_5, /*!< Compressed up to 12.5% */
dkato 0:853f5b7408a7 265 VDEC_PEAKRATIO_0, /*!< Compressed up to 0% */
dkato 0:853f5b7408a7 266 VDEC_PEAKRATIO_NUM
dkato 0:853f5b7408a7 267 } vdec_peakratio_t;
dkato 0:853f5b7408a7 268 /*! Peak limiter control parameter */
dkato 0:853f5b7408a7 269 typedef struct {
dkato 0:853f5b7408a7 270 vdec_peaklevel_t peaklevel; /*!< Peak luminance value limited by peak limiter (video signal level) */
dkato 0:853f5b7408a7 271 uint16_t peakattack; /*!< Response speed with peak limiter gain decreased */
dkato 0:853f5b7408a7 272 uint16_t peakrelease; /*!< Response speed with peak limiter gain increased */
dkato 0:853f5b7408a7 273 vdec_peakratio_t peakratio; /*!< Maximum compression rate of peak limiter */
dkato 0:853f5b7408a7 274 uint16_t maxpeaksamples; /*!< Allowable number of overflowing pixels */
dkato 0:853f5b7408a7 275 } vdec_peak_limiter_t;
dkato 0:853f5b7408a7 276 /*! Sync separation parameter */
dkato 0:853f5b7408a7 277 typedef struct {
dkato 0:853f5b7408a7 278 vdec_noise_rd_lpf_t * noise_rd_lpf; /*!< Noise reduction LPF parameter */
dkato 0:853f5b7408a7 279 vdec_sync_slicer_t * sync_slicer; /*!< Auto level control sync slicer parameter */
dkato 0:853f5b7408a7 280 vdec_horizontal_afc_t * horizontal_afc; /*!< Horizontal AFC parameter */
dkato 0:853f5b7408a7 281 vdec_vcount_down_t * vcount_down; /*!< Vertical count-down parameter */
dkato 0:853f5b7408a7 282 vdec_agc_t * agc; /*!< AGC/PGA parameter */
dkato 0:853f5b7408a7 283 vdec_peak_limiter_t * peak_limiter; /*!< Peak limiter control parameter */
dkato 0:853f5b7408a7 284 } vdec_sync_separation_t;
dkato 0:853f5b7408a7 285
dkato 0:853f5b7408a7 286 /*********************** For R_VDEC_YcSeparation ***********************/
dkato 0:853f5b7408a7 287 /*! Over-range control parameter */
dkato 0:853f5b7408a7 288 typedef struct {
dkato 0:853f5b7408a7 289 uint16_t radj_o_level0; /*!< A/D over-threshold level (between levels 0 and 1) */
dkato 0:853f5b7408a7 290 uint16_t radj_u_level0; /*!< A/D under-threshold level (between levels 2 and 3) */
dkato 0:853f5b7408a7 291 uint16_t radj_o_level1; /*!< A/D over-threshold level (between levels 1 and 2) */
dkato 0:853f5b7408a7 292 uint16_t radj_u_level1; /*!< A/D under-threshold level (between levels 1 and 2) */
dkato 0:853f5b7408a7 293 uint16_t radj_o_level2; /*!< A/D over-threshold level (between levels 2 and 3) */
dkato 0:853f5b7408a7 294 uint16_t radj_u_level2; /*!< A/D under-threshold level (between levels 0 and 1) */
dkato 0:853f5b7408a7 295 vdec_onoff_t ucmp_sw; /*!< Over-range detection enable */
dkato 0:853f5b7408a7 296 vdec_onoff_t dcmp_sw; /*!< Under-range detection enable */
dkato 0:853f5b7408a7 297 vdec_onoff_t hwide_sw; /*!< Horizontal enlargement of over/under-range level */
dkato 0:853f5b7408a7 298 } vdec_over_range_t;
dkato 0:853f5b7408a7 299 /*! Latter-stage BPF select */
dkato 0:853f5b7408a7 300 typedef enum {
dkato 0:853f5b7408a7 301 VDEC_LSTG_BPFSEL_BYPASS = 0, /*!< Bypass */
dkato 0:853f5b7408a7 302 VDEC_LSTG_BPFSEL_17TAP = 1 /*!< 17 TAP */
dkato 0:853f5b7408a7 303 } vdec_lstg_bpfsel_t;
dkato 0:853f5b7408a7 304 /*! Former-stage BPF select */
dkato 0:853f5b7408a7 305 typedef enum {
dkato 0:853f5b7408a7 306 VDEC_FSTG_BPFSEL_17TAP = 0, /*!< 17 TAP */
dkato 0:853f5b7408a7 307 VDEC_FSTG_BPFSEL_9TAP = 1 /*!< 9 TAP */
dkato 0:853f5b7408a7 308 } vdec_fstg_bpfsel_t;
dkato 0:853f5b7408a7 309 /*! Horizontal filter and horizontal/vertical filter bandwidth switch signal */
dkato 0:853f5b7408a7 310 typedef enum {
dkato 0:853f5b7408a7 311 VDEC_HFIL_TAP_SEL_17TAP = 0, /*!< 17 TAP */
dkato 0:853f5b7408a7 312 VDEC_HFIL_TAP_SEL_9TAP = 1 /*!< 9 TAP */
dkato 0:853f5b7408a7 313 } vdec_hfil_tap_sel_t;
dkato 0:853f5b7408a7 314 /*! Mixing ratio of signals after passing filters */
dkato 0:853f5b7408a7 315 typedef enum {
dkato 0:853f5b7408a7 316 VDEC_FILMIX_RATIO_0 = 0, /*!< 0% */
dkato 0:853f5b7408a7 317 VDEC_FILMIX_RATIO_12_5, /*!< 12.5% */
dkato 0:853f5b7408a7 318 VDEC_FILMIX_RATIO_25, /*!< 25% */
dkato 0:853f5b7408a7 319 VDEC_FILMIX_RATIO_37_5, /*!< 37.5% */
dkato 0:853f5b7408a7 320 VDEC_FILMIX_RATIO_50, /*!< 50% */
dkato 0:853f5b7408a7 321 VDEC_FILMIX_RATIO_62_5, /*!< 62.5% */
dkato 0:853f5b7408a7 322 VDEC_FILMIX_RATIO_75, /*!< 75% */
dkato 0:853f5b7408a7 323 VDEC_FILMIX_RATIO_87_5, /*!< 87.5% */
dkato 0:853f5b7408a7 324 VDEC_FILMIX_RATIO_100, /*!< 100% */
dkato 0:853f5b7408a7 325 VDEC_FILMIX_RATIO_NUM
dkato 0:853f5b7408a7 326 } vdec_filmix_ratio_t;
dkato 0:853f5b7408a7 327 /*! Two-dimensional cascade/TAKE-OFF filter mode select */
dkato 0:853f5b7408a7 328 typedef enum {
dkato 0:853f5b7408a7 329 VDEC_2DFIL_MDSEL_BYPASS = 0, /*!< Bypass */
dkato 0:853f5b7408a7 330 VDEC_2DFIL_MDSEL_CASCADE, /*!< Cascade filter */
dkato 0:853f5b7408a7 331 VDEC_2DFIL_MDSEL_TAKEOFF, /*!< TAKE-OFF filter */
dkato 0:853f5b7408a7 332 VDEC_2DFIL_MDSEL_NUM
dkato 0:853f5b7408a7 333 } vdec_2dfil_mdsel_t;
dkato 0:853f5b7408a7 334 /*! Two-dimensional cascade filter select */
dkato 0:853f5b7408a7 335 typedef enum {
dkato 0:853f5b7408a7 336 VDEC_2D_FIL_SEL_BYPASS = 0, /*!< Bypass */
dkato 0:853f5b7408a7 337 VDEC_2D_FIL_SEL_17TAP = 1 /*!< 17 TAP */
dkato 0:853f5b7408a7 338 } vdec_2d_fil_sel_t;
dkato 0:853f5b7408a7 339 /*! Y/C separation control parameter */
dkato 0:853f5b7408a7 340 typedef struct {
dkato 0:853f5b7408a7 341 uint16_t k15; /*!< Two-dimensional Y/C separation filter select coefficient, K15 */
dkato 0:853f5b7408a7 342 uint16_t k13; /*!< Two-dimensional Y/C separation filter select coefficient, K13 */
dkato 0:853f5b7408a7 343 uint16_t k11; /*!< Two-dimensional Y/C separation filter select coefficient, K11 */
dkato 0:853f5b7408a7 344 uint16_t k16; /*!< Two-dimensional Y/C separation filter select coefficient, K16 */
dkato 0:853f5b7408a7 345 uint16_t k14; /*!< Two-dimensional Y/C separation filter select coefficient, K14 */
dkato 0:853f5b7408a7 346 uint16_t k12; /*!< Two-dimensional Y/C separation filter select coefficient, K12 */
dkato 0:853f5b7408a7 347 uint16_t k22a; /*!< Two-dimensional Y/C separation filter select coefficient, K22A */
dkato 0:853f5b7408a7 348 uint16_t k21a; /*!< Two-dimensional Y/C separation filter select coefficient, K21A */
dkato 0:853f5b7408a7 349 uint16_t k22b; /*!< Two-dimensional Y/C separation filter select coefficient, K22B */
dkato 0:853f5b7408a7 350 uint16_t k21b; /*!< Two-dimensional Y/C separation filter select coefficient, K21B */
dkato 0:853f5b7408a7 351 uint16_t k23b; /*!< Two-dimensional Y/C separation filter select coefficient, K23B */
dkato 0:853f5b7408a7 352 uint16_t k23a; /*!< Two-dimensional Y/C separation filter select coefficient, K23A */
dkato 0:853f5b7408a7 353 uint16_t k24; /*!< Two-dimensional Y/C separation filter select coefficient, K24 */
dkato 0:853f5b7408a7 354 vdec_lstg_bpfsel_t hbpf_narrow; /*!< Latter-stage horizontal BPF select */
dkato 0:853f5b7408a7 355 vdec_lstg_bpfsel_t hvbpf_narrow; /*!< Latter-stage horizontal/vertical BPF select */
dkato 0:853f5b7408a7 356 vdec_fstg_bpfsel_t hbpf1_9tap_on; /*!< Former-stage horizontal BPF select */
dkato 0:853f5b7408a7 357 vdec_fstg_bpfsel_t hvbpf1_9tap_on; /*!< Former-stage horizontal/vertical BPF select */
dkato 0:853f5b7408a7 358 vdec_hfil_tap_sel_t hfil_tap_sel; /*!< Horizontal filter and horizontal/vertical filter
dkato 0:853f5b7408a7 359 bandwidth switch signal */
dkato 0:853f5b7408a7 360 vdec_onoff_t det2_on; /*!< Two-dimensional filter mixing select */
dkato 0:853f5b7408a7 361 vdec_filmix_ratio_t hsel_mix_y; /*!< Mixing ratio of signal after passing horizontal filter
dkato 0:853f5b7408a7 362 to signal after passing former-stage horizontal filter */
dkato 0:853f5b7408a7 363 vdec_filmix_ratio_t vsel_mix_y; /*!< Mixing ratio of signal after passing vertical filter
dkato 0:853f5b7408a7 364 to signal after passing former-stage horizontal/vertical filter */
dkato 0:853f5b7408a7 365 vdec_filmix_ratio_t hvsel_mix_y; /*!< Mixing ratio of signal after passing horizontal/vertical filter
dkato 0:853f5b7408a7 366 to signal after passing former-stage horizontal/vertical filter */
dkato 0:853f5b7408a7 367 uint16_t v_y_level; /*!< Vertical luminance detection level for correlation detection filter */
dkato 0:853f5b7408a7 368 vdec_filmix_ratio_t det2_mix_c; /*!< Mixing ratio of C signal after passing horizontal/vertical adaptive filter
dkato 0:853f5b7408a7 369 to signal after passing correlation detection filter */
dkato 0:853f5b7408a7 370 vdec_filmix_ratio_t det2_mix_y; /*!< Mixing ratio of C signal for Y generation after passing
dkato 0:853f5b7408a7 371 horizontal/vertical adaptive filter to signal
dkato 0:853f5b7408a7 372 after passing correlation detection filter */
dkato 0:853f5b7408a7 373 vdec_2dfil_mdsel_t fil2_mode_2d; /*!< Two-dimensional cascade/TAKE-OFF filter mode select */
dkato 0:853f5b7408a7 374 vdec_2d_fil_sel_t fil2_narrow_2d; /*!< Two-dimensional cascade filter select */
dkato 0:853f5b7408a7 375 } vdec_yc_sep_ctrl_t;
dkato 0:853f5b7408a7 376 /*! Chroma filter TAP coefficient for Y/C separation */
dkato 0:853f5b7408a7 377 typedef struct {
dkato 0:853f5b7408a7 378 uint16_t fil2_2d_f[VDEC_CHRFIL_TAPCOEF_NUM]; /*!< Chroma filter TAP coefficient 0 to 8 */
dkato 0:853f5b7408a7 379 } vdec_chrfil_tap_t;
dkato 0:853f5b7408a7 380 /*! Y/C separation parameter */
dkato 0:853f5b7408a7 381 typedef struct {
dkato 0:853f5b7408a7 382 vdec_over_range_t * over_range; /*!< Over-range control parameter */
dkato 0:853f5b7408a7 383 vdec_yc_sep_ctrl_t * yc_sep_ctrl; /*!< Y/C separation control parameter */
dkato 0:853f5b7408a7 384 const vdec_chrfil_tap_t * fil2_2d_wa; /*!< Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF
dkato 0:853f5b7408a7 385 filter TAP coefficient */
dkato 0:853f5b7408a7 386 const vdec_chrfil_tap_t * fil2_2d_wb; /*!< Two-dimensional cascade broadband (SECAM-DB) filter
dkato 0:853f5b7408a7 387 TAP coefficient */
dkato 0:853f5b7408a7 388 const vdec_chrfil_tap_t * fil2_2d_na; /*!< Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter
dkato 0:853f5b7408a7 389 TAP coefficient */
dkato 0:853f5b7408a7 390 const vdec_chrfil_tap_t * fil2_2d_nb; /*!< Two-dimensional cascade narrowband (SECAMDB) filter
dkato 0:853f5b7408a7 391 TAP coefficient */
dkato 0:853f5b7408a7 392 } vdec_yc_separation_t;
dkato 0:853f5b7408a7 393
dkato 0:853f5b7408a7 394 /*********************** For R_VDEC_ChromaDecoding ***********************/
dkato 0:853f5b7408a7 395 /*! Color system */
dkato 0:853f5b7408a7 396 typedef enum {
dkato 0:853f5b7408a7 397 VDEC_COL_SYS_NTSC = 0, /*!< NTSC */
dkato 0:853f5b7408a7 398 VDEC_COL_SYS_PAL, /*!< PAL */
dkato 0:853f5b7408a7 399 VDEC_COL_SYS_SECAM, /*!< SECAM */
dkato 0:853f5b7408a7 400 VDEC_COL_SYS_NON, /*!< Not specified/undetectable */
dkato 0:853f5b7408a7 401 VDEC_COL_SYS_NUM /*!< The number of color system settings */
dkato 0:853f5b7408a7 402 } vdec_color_sys_t;
dkato 0:853f5b7408a7 403 /*! Averaging processing for pre-demodulated line */
dkato 0:853f5b7408a7 404 typedef enum {
dkato 0:853f5b7408a7 405 VDEC_DEMOD_MD_NO = 0, /*!< No processing */
dkato 0:853f5b7408a7 406 VDEC_DEMOD_MD_PAL = 2 /*!< For PAL */
dkato 0:853f5b7408a7 407 } vdec_demodmode_t;
dkato 0:853f5b7408a7 408 /*! Color system detection parameter */
dkato 0:853f5b7408a7 409 typedef struct {
dkato 0:853f5b7408a7 410 vdec_color_sys_t defaultsys; /*!< Default color system */
dkato 0:853f5b7408a7 411 vdec_onoff_t nontsc358_; /*!< NTSC-M detection control */
dkato 0:853f5b7408a7 412 vdec_onoff_t nontsc443_; /*!< NTSC-4.43 detection control */
dkato 0:853f5b7408a7 413 vdec_onoff_t nopalm_; /*!< PAL-M detection control */
dkato 0:853f5b7408a7 414 vdec_onoff_t nopaln_; /*!< PAL-N detection control */
dkato 0:853f5b7408a7 415 vdec_onoff_t nopal443_; /*!< PAL-B, G, H, I, D detection control */
dkato 0:853f5b7408a7 416 vdec_onoff_t nosecam_; /*!< SECAM detection control */
dkato 0:853f5b7408a7 417 uint16_t lumadelay; /*!< Luminance signal delay adjustment */
dkato 0:853f5b7408a7 418 vdec_onoff_t chromalpf; /*!< LPF for demodulated chroma */
dkato 0:853f5b7408a7 419 vdec_demodmode_t demodmode; /*!< Averaging processing for pre-demodulated line */
dkato 0:853f5b7408a7 420 } vdec_chrmdec_ctrl_t;
dkato 0:853f5b7408a7 421 /*! Burst lock PLL lock range */
dkato 0:853f5b7408a7 422 typedef enum {
dkato 0:853f5b7408a7 423 VDEC_LOCK_RANGE_400HZ = 0, /*!< +-400 Hz */
dkato 0:853f5b7408a7 424 VDEC_LOCK_RANGE_800HZ, /*!< +-800 Hz */
dkato 0:853f5b7408a7 425 VDEC_LOCK_RANGE_1200HZ, /*!< +-1200 Hz */
dkato 0:853f5b7408a7 426 VDEC_LOCK_RANGE_1600HZ, /*!< +-1600 Hz */
dkato 0:853f5b7408a7 427 VDEC_LOCK_RANGE_NUM
dkato 0:853f5b7408a7 428 } vdec_lockrange_t;
dkato 0:853f5b7408a7 429 /*! BCO parameter */
dkato 0:853f5b7408a7 430 typedef struct {
dkato 0:853f5b7408a7 431 vdec_lockrange_t lockrange; /*!< Burst lock PLL lock range */
dkato 0:853f5b7408a7 432 uint16_t loopgain; /*!< Burst lock PLL loop gain */
dkato 0:853f5b7408a7 433 uint16_t locklimit; /*!< Level for burst lock PLL to re-search free-run frequency */
dkato 0:853f5b7408a7 434 uint16_t bgpcheck; /*!< burst gate pulse position check */
dkato 0:853f5b7408a7 435 uint16_t bgpwidth; /*!< burst gate pulse width */
dkato 0:853f5b7408a7 436 uint16_t bgpstart; /*!< burst gate pulse start position */
dkato 0:853f5b7408a7 437 } vdec_burst_lock_t;
dkato 0:853f5b7408a7 438 /*! ACC operating mode */
dkato 0:853f5b7408a7 439 typedef enum {
dkato 0:853f5b7408a7 440 VDEC_ACC_MD_AUTO = 0, /*!< Auto gain */
dkato 0:853f5b7408a7 441 VDEC_ACC_MD_MANUAL = 1 /*!< Manual gain */
dkato 0:853f5b7408a7 442 } vdec_accmode_t;
dkato 0:853f5b7408a7 443 /*! Maximum ACC gain */
dkato 0:853f5b7408a7 444 typedef enum {
dkato 0:853f5b7408a7 445 VDEC_ACC_MAX_GAIN_6 = 0, /*!< 6 times */
dkato 0:853f5b7408a7 446 VDEC_ACC_MAX_GAIN_8, /*!< 8 times */
dkato 0:853f5b7408a7 447 VDEC_ACC_MAX_GAIN_12, /*!< 12 times */
dkato 0:853f5b7408a7 448 VDEC_ACC_MAX_GAIN_16, /*!< 16 times */
dkato 0:853f5b7408a7 449 VDEC_ACC_MAX_GAIN_NUM
dkato 0:853f5b7408a7 450 } vdec_accmaxgain_t;
dkato 0:853f5b7408a7 451 /*! Chroma manual gain (sub) */
dkato 0:853f5b7408a7 452 typedef enum {
dkato 0:853f5b7408a7 453 VDEC_CHRM_SB_GAIN_1 = 0, /*!< 1 time */
dkato 0:853f5b7408a7 454 VDEC_CHRM_SB_GAIN_2, /*!< 2 times */
dkato 0:853f5b7408a7 455 VDEC_CHRM_SB_GAIN_4, /*!< 4 times */
dkato 0:853f5b7408a7 456 VDEC_CHRM_SB_GAIN_8, /*!< 8 times */
dkato 0:853f5b7408a7 457 VDEC_CHRM_SB_GAIN_NUM
dkato 0:853f5b7408a7 458 } vdec_chrm_subgain_t;
dkato 0:853f5b7408a7 459 /*! ACC and color killer parameter */
dkato 0:853f5b7408a7 460 typedef struct {
dkato 0:853f5b7408a7 461 vdec_accmode_t accmode; /*!< ACC operating mode */
dkato 0:853f5b7408a7 462 vdec_accmaxgain_t accmaxgain; /*!< Maximum ACC Gain */
dkato 0:853f5b7408a7 463 uint16_t acclevel; /*!< ACC reference color burst amplitude */
dkato 0:853f5b7408a7 464 vdec_chrm_subgain_t chromasubgain; /*!< Chroma manual gain (sub) */
dkato 0:853f5b7408a7 465 uint16_t chromamaingain; /*!< Chroma manual gain (main) */
dkato 0:853f5b7408a7 466 uint16_t accresponse; /*!< ACC response speed */
dkato 0:853f5b7408a7 467 uint16_t accprecis; /*!< ACC gain adjustment accuracy */
dkato 0:853f5b7408a7 468 vdec_onoff_t killermode; /*!< Forced color killer mode ON/OFF */
dkato 0:853f5b7408a7 469 uint16_t killerlevel; /*!< Color killer operation start point */
dkato 0:853f5b7408a7 470 uint16_t killeroffset; /*!< Color killer offset */
dkato 0:853f5b7408a7 471 } vdec_acc_t;
dkato 0:853f5b7408a7 472 /*! TINT correction/R-Y axis correction parameter (only valid for NTSC/PAL) */
dkato 0:853f5b7408a7 473 typedef struct {
dkato 0:853f5b7408a7 474 uint16_t tintsub; /*!< Fine adjustment of R-Y demodulation axis */
dkato 0:853f5b7408a7 475 uint16_t tintmain; /*!< Hue adjustment level */
dkato 0:853f5b7408a7 476 } vdec_tint_ry_t;
dkato 0:853f5b7408a7 477 /*! Chroma decoding parameter */
dkato 0:853f5b7408a7 478 typedef struct {
dkato 0:853f5b7408a7 479 vdec_chrmdec_ctrl_t * chrmdec_ctrl; /*!< Color system detection parameter */
dkato 0:853f5b7408a7 480 vdec_burst_lock_t * burst_lock; /*!< BCO parameter */
dkato 0:853f5b7408a7 481 vdec_acc_t * acc; /*!< ACC and color killer parameter */
dkato 0:853f5b7408a7 482 vdec_tint_ry_t * tint_ry; /*!< TINT correction/R-Y axis correction parameter */
dkato 0:853f5b7408a7 483 } vdec_chroma_decoding_t;
dkato 0:853f5b7408a7 484
dkato 0:853f5b7408a7 485 /*********************** For R_VDEC_DigitalClamp ***********************/
dkato 0:853f5b7408a7 486 /*! Clamp level setting mode */
dkato 0:853f5b7408a7 487 typedef enum {
dkato 0:853f5b7408a7 488 VDEC_DCPMODE_MANUAL = 0, /*!< Manual clamp level setting */
dkato 0:853f5b7408a7 489 VDEC_DCPMODE_AUTO = 1 /*!< Auto clamp level setting */
dkato 0:853f5b7408a7 490 } vdec_dcpmode_t;
dkato 0:853f5b7408a7 491 /*! Pedestal clamp parameter */
dkato 0:853f5b7408a7 492 typedef struct {
dkato 0:853f5b7408a7 493 vdec_dcpmode_t dcpmode_y; /*!< Clamp level setting mode (Y signal) */
dkato 0:853f5b7408a7 494 uint16_t blanklevel_y; /*!< Clamp offset level (Y signal) */
dkato 0:853f5b7408a7 495 uint16_t dcppos_y; /*!< Digital clamp pulse horizontal start position (Y signal) */
dkato 0:853f5b7408a7 496 } vdec_pedestal_clamp_t;
dkato 0:853f5b7408a7 497 /*! Center clamp parameter */
dkato 0:853f5b7408a7 498 typedef struct {
dkato 0:853f5b7408a7 499 vdec_dcpmode_t dcpmode_c; /*!< Clamp level setting mode (Cb/Cr signal) */
dkato 0:853f5b7408a7 500 uint16_t blanklevel_cb; /*!< Clamp offset level (Cb signal) */
dkato 0:853f5b7408a7 501 uint16_t blanklevel_cr; /*!< Clamp offset level (Cr signal) */
dkato 0:853f5b7408a7 502 uint16_t dcppos_c; /*!< Digital clamp pulse horizontal start position (Cb/Cr signal) */
dkato 0:853f5b7408a7 503 } vdec_center_clamp_t;
dkato 0:853f5b7408a7 504 /*! Video signal for autocorrelation function */
dkato 0:853f5b7408a7 505 typedef enum {
dkato 0:853f5b7408a7 506 VDEC_ACFINPUT_Y = 0, /*!< Y signal */
dkato 0:853f5b7408a7 507 VDEC_ACFINPUT_CB, /*!< Cb signal */
dkato 0:853f5b7408a7 508 VDEC_ACFINPUT_CR, /*!< Cr signal */
dkato 0:853f5b7408a7 509 VDEC_ACFINPUT_NUM
dkato 0:853f5b7408a7 510 } vdec_acfinput_t;
dkato 0:853f5b7408a7 511 /*! Noise detection parameter */
dkato 0:853f5b7408a7 512 typedef struct {
dkato 0:853f5b7408a7 513 vdec_acfinput_t acfinput; /*!< Video signal for autocorrelation function */
dkato 0:853f5b7408a7 514 uint16_t acflagtime; /*!< Delay time for autocorrelation function calculation */
dkato 0:853f5b7408a7 515 uint16_t acffilter; /*!< Smoothing parameter of autocorrelation function data */
dkato 0:853f5b7408a7 516 } vdec_noise_det_t;
dkato 0:853f5b7408a7 517 /*! Digital clamp parameter */
dkato 0:853f5b7408a7 518 typedef struct {
dkato 0:853f5b7408a7 519 vdec_onoff_t dcpcheck; /*!< Digital clamp pulse position check */
dkato 0:853f5b7408a7 520 uint16_t dcpresponse; /*!< Digital clamp response speed */
dkato 0:853f5b7408a7 521 uint16_t dcpstart; /*!< Digital clamp start line */
dkato 0:853f5b7408a7 522 uint16_t dcpend; /*!< Digital clamp end line */
dkato 0:853f5b7408a7 523 uint16_t dcpwidth; /*!< Digital clamp pulse width */
dkato 0:853f5b7408a7 524 vdec_pedestal_clamp_t * pedestal_clamp; /*!< Pedestal clamp parameter */
dkato 0:853f5b7408a7 525 vdec_center_clamp_t * center_clamp; /*!< Center clamp parameter */
dkato 0:853f5b7408a7 526 vdec_noise_det_t * noise_det; /*!< Noise detection parameter */
dkato 0:853f5b7408a7 527 } vdec_degital_clamp_t;
dkato 0:853f5b7408a7 528
dkato 0:853f5b7408a7 529 /*********************** For R_VDEC_Output ***********************/
dkato 0:853f5b7408a7 530 /*! Output adjustment parameter */
dkato 0:853f5b7408a7 531 typedef struct {
dkato 0:853f5b7408a7 532 uint16_t y_gain2; /*!< Y signal gain coefficient */
dkato 0:853f5b7408a7 533 uint16_t cb_gain2; /*!< Cb signal gain coefficient */
dkato 0:853f5b7408a7 534 uint16_t cr_gain2; /*!< Cr signal gain coefficient */
dkato 0:853f5b7408a7 535 } vdec_output_t;
dkato 0:853f5b7408a7 536
dkato 0:853f5b7408a7 537 /*********************** For R_VDEC_Query ***********************/
dkato 0:853f5b7408a7 538 /*! Answer */
dkato 0:853f5b7408a7 539 typedef enum {
dkato 0:853f5b7408a7 540 VDEC_NO = 0, /*!< No */
dkato 0:853f5b7408a7 541 VDEC_YES = 1 /*!< Yes */
dkato 0:853f5b7408a7 542 } vdec_answer_t;
dkato 0:853f5b7408a7 543 /*! Lock state */
dkato 0:853f5b7408a7 544 typedef enum {
dkato 0:853f5b7408a7 545 VDEC_UNLOCK = 0, /*!< Unlocked */
dkato 0:853f5b7408a7 546 VDEC_LOCK = 1 /*!< Locked */
dkato 0:853f5b7408a7 547 } vdec_lock_t;
dkato 0:853f5b7408a7 548 /*! Speed detection result */
dkato 0:853f5b7408a7 549 typedef enum {
dkato 0:853f5b7408a7 550 VDEC_FHMD_NORMAL = 0, /*!< Normal speed */
dkato 0:853f5b7408a7 551 VDEC_FHMD_MULTIPLIED = 1 /*!< Multiplied speed */
dkato 0:853f5b7408a7 552 } vdec_fhmode_t;
dkato 0:853f5b7408a7 553 /*! Vertical countdown oscillation mode */
dkato 0:853f5b7408a7 554 typedef enum {
dkato 0:853f5b7408a7 555 VDEC_FVMD_50HZ = 0, /*!< 50 Hz */
dkato 0:853f5b7408a7 556 VDEC_FVMD_60HZ = 1 /*!< 60 Hz */
dkato 0:853f5b7408a7 557 } vdec_fvmode_t;
dkato 0:853f5b7408a7 558 /*! Color sub-carrier frequency detection result */
dkato 0:853f5b7408a7 559 typedef enum {
dkato 0:853f5b7408a7 560 VDEC_FSCMD_3_58 = 0, /*!< 3.58 MHz */
dkato 0:853f5b7408a7 561 VDEC_FSCMD_4_43 = 1 /*!< 4.43 MHz */
dkato 0:853f5b7408a7 562 } vdec_fscmode_t;
dkato 0:853f5b7408a7 563 /*! Sync separation parameters (for query) */
dkato 0:853f5b7408a7 564 typedef struct {
dkato 0:853f5b7408a7 565 vdec_lock_t fhlock; /*!< Horizontal AFC lock detection result */
dkato 0:853f5b7408a7 566 vdec_answer_t isnoisy; /*!< Detection result of low S/N signal by sync separation */
dkato 0:853f5b7408a7 567 vdec_fhmode_t fhmode; /*!< Speed detection result */
dkato 0:853f5b7408a7 568 vdec_answer_t nosignal_; /*!< No-signal detection result */
dkato 0:853f5b7408a7 569 vdec_lock_t fvlock; /*!< Vertical countdown lock detection result */
dkato 0:853f5b7408a7 570 vdec_fvmode_t fvmode; /*!< Vertical countdown oscillation mode */
dkato 0:853f5b7408a7 571 vdec_answer_t interlaced; /*!< Interlace detection result */
dkato 0:853f5b7408a7 572 uint16_t fvcount; /*!< Vertical cycle measurement result */
dkato 0:853f5b7408a7 573 uint32_t fhcount; /*!< Horizontal AFC oscillation cycle */
dkato 0:853f5b7408a7 574 vdec_answer_t isreduced; /*!< Sync amplitude detection result during VBI period */
dkato 0:853f5b7408a7 575 uint16_t syncdepth; /*!< Sync pulse amplitude detection result */
dkato 0:853f5b7408a7 576 } vdec_q_sync_sep_t;
dkato 0:853f5b7408a7 577 /*! AGC parameters (for query) */
dkato 0:853f5b7408a7 578 typedef struct {
dkato 0:853f5b7408a7 579 uint16_t highsamples; /*!< Number of pixels which have larger luminance value than peak luminance
dkato 0:853f5b7408a7 580 limited by peak limiter */
dkato 0:853f5b7408a7 581 uint16_t peaksamples; /*!< Number of overflowing pixels */
dkato 0:853f5b7408a7 582 uint16_t agcconverge; /*!< AGC convergence detection result */
dkato 0:853f5b7408a7 583 uint16_t agcgain; /*!< Current AGC gain value */
dkato 0:853f5b7408a7 584 } vdec_q_agc_t;
dkato 0:853f5b7408a7 585 /*! Chroma decoding parameters (for query) */
dkato 0:853f5b7408a7 586 typedef struct {
dkato 0:853f5b7408a7 587 vdec_color_sys_t colorsys; /*!< Color system detection result */
dkato 0:853f5b7408a7 588 vdec_fscmode_t fscmode; /*!< Color sub-carrier frequency detection result */
dkato 0:853f5b7408a7 589 vdec_lock_t fsclock; /*!< Burst lock PLL lock state detection result */
dkato 0:853f5b7408a7 590 vdec_answer_t noburst_; /*!< Color burst detection result */
dkato 0:853f5b7408a7 591 vdec_chrm_subgain_t accsubgain; /*!< Current ACC gain value (sub) */
dkato 0:853f5b7408a7 592 uint16_t accmaingain;/*!< Current ACC gain value (main) */
dkato 0:853f5b7408a7 593 vdec_answer_t issecam; /*!< SECAM detection result */
dkato 0:853f5b7408a7 594 vdec_answer_t ispal; /*!< PAL detection result */
dkato 0:853f5b7408a7 595 vdec_answer_t isntsc; /*!< NTSC detection result */
dkato 0:853f5b7408a7 596 uint16_t locklevel; /*!< Low S/N signal detection result by burst lock PLL */
dkato 0:853f5b7408a7 597 } vdec_q_chroma_dec_t;
dkato 0:853f5b7408a7 598 /*! Digital clamp parameters (for query) */
dkato 0:853f5b7408a7 599 typedef struct {
dkato 0:853f5b7408a7 600 uint16_t clamplevel_cb; /*!< Digital clamp subtraction value (Cb signal) */
dkato 0:853f5b7408a7 601 uint16_t clamplevel_y; /*!< Digital clamp subtraction value (Y signal) */
dkato 0:853f5b7408a7 602 uint16_t clamplevel_cr; /*!< Digital clamp subtraction value (Cr signal) */
dkato 0:853f5b7408a7 603 uint16_t acfstrength; /*!< Noise autocorrelation strength at digital clamp pulse position */
dkato 0:853f5b7408a7 604 } vdec_q_digital_clamp_t;
dkato 0:853f5b7408a7 605
dkato 0:853f5b7408a7 606
dkato 0:853f5b7408a7 607 /******************************************************************************
dkato 0:853f5b7408a7 608 Functions Prototypes
dkato 0:853f5b7408a7 609 ******************************************************************************/
dkato 0:853f5b7408a7 610 vdec_error_t R_VDEC_Initialize(
dkato 0:853f5b7408a7 611 const vdec_channel_t ch,
dkato 0:853f5b7408a7 612 const vdec_adc_vinsel_t vinsel,
dkato 0:853f5b7408a7 613 void (* const init_func)(uint32_t),
dkato 0:853f5b7408a7 614 const uint32_t user_num);
dkato 0:853f5b7408a7 615 vdec_error_t R_VDEC_Terminate(const vdec_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
dkato 0:853f5b7408a7 616 vdec_error_t R_VDEC_ActivePeriod(const vdec_channel_t ch, const vdec_active_period_t * const param);
dkato 0:853f5b7408a7 617 vdec_error_t R_VDEC_SyncSeparation(const vdec_channel_t ch, const vdec_sync_separation_t * const param);
dkato 0:853f5b7408a7 618 vdec_error_t R_VDEC_YcSeparation(const vdec_channel_t ch, const vdec_yc_separation_t * const param);
dkato 0:853f5b7408a7 619 vdec_error_t R_VDEC_ChromaDecoding(const vdec_channel_t ch, const vdec_chroma_decoding_t * const param);
dkato 0:853f5b7408a7 620 vdec_error_t R_VDEC_DigitalClamp(const vdec_channel_t ch, const vdec_degital_clamp_t * const param);
dkato 0:853f5b7408a7 621 vdec_error_t R_VDEC_Output(const vdec_channel_t ch, const vdec_output_t * const param);
dkato 0:853f5b7408a7 622 vdec_error_t R_VDEC_Query(
dkato 0:853f5b7408a7 623 const vdec_channel_t ch,
dkato 0:853f5b7408a7 624 vdec_q_sync_sep_t * const q_sync_sep,
dkato 0:853f5b7408a7 625 vdec_q_agc_t * const q_agc,
dkato 0:853f5b7408a7 626 vdec_q_chroma_dec_t * const q_chroma_dec,
dkato 0:853f5b7408a7 627 vdec_q_digital_clamp_t * const q_digital_clamp);
dkato 0:853f5b7408a7 628
dkato 0:853f5b7408a7 629
dkato 0:853f5b7408a7 630 #ifdef __cplusplus
dkato 0:853f5b7408a7 631 }
dkato 0:853f5b7408a7 632 #endif /* __cplusplus */
dkato 0:853f5b7408a7 633
dkato 0:853f5b7408a7 634
dkato 0:853f5b7408a7 635 #endif /* R_VDEC_H */
dkato 0:853f5b7408a7 636