Diff: TARGET_NUCLEO_L152RE/stm32l1xx_ll_fsmc.h

Revision:

122:f9eeca106725

Parent:

90:cb3d968589d8

diff -r 6c34061e7c34 -r f9eeca106725 TARGET_NUCLEO_L152RE/stm32l1xx_ll_fsmc.h
--- a/TARGET_NUCLEO_L152RE/stm32l1xx_ll_fsmc.h	Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_NUCLEO_L152RE/stm32l1xx_ll_fsmc.h	Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_fsmc.h
   * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
+  * @version V1.1.3
+  * @date    04-March-2016
   * @brief   Header file of FSMC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -43,8 +43,6 @@
  extern "C" {
 #endif
 
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l1xx_hal_def.h"
 
@@ -52,18 +50,142 @@
   * @{
   */
 
+#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
+
 /** @addtogroup FSMC_LL
   * @{
   */ 
 
+/** @addtogroup FSMC_LL_Private_Macros
+  * @{
+  */
+
+#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
+                                        ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+                                        ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+                                        ((__BANK__) == FSMC_NORSRAM_BANK4))
+
+#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+                              ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
+                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
+                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
+                                       ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+                                       ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+                                       ((__MODE__) == FSMC_ACCESS_MODE_D))
+
+/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
+  * @{
+  */
+  
+#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
+
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
+  * @{
+  */
+  
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
+
+/**
+  * @}
+  */
+
+#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+                                      ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+                                             ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
+                                     ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+                                                ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 
+
+#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
+                                                ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))                        
+
+#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
+                                          ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 
+
+#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
+                                         ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+                                     ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+
+/** @defgroup FSMC_Data_Latency FSMC Data Latency
+  * @{
+  */
+  
+#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+/**
+  * @}
+  */  
+
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
+                                        ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 
+/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
+  * @{
+  */
+  
+#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
+  * @{
+  */
+  
+#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
+  * @{
+  */
+  
+#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
+  * @{
+  */
+  
+#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
 /* Exported typedef ----------------------------------------------------------*/ 
 
-/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC NOR/SRAM Exported typedef
+/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
   * @{
   */ 
   
-#define FSMC_NORSRAM_TYPEDEF            FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF   FSMC_Bank1E_TypeDef
+#define FSMC_NORSRAM_TypeDef            FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef   FSMC_Bank1E_TypeDef
 
 #define FSMC_NORSRAM_DEVICE             FSMC_Bank1
 #define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
@@ -174,6 +296,10 @@
 
 /* Exported constants --------------------------------------------------------*/
 
+/** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
+  * @{
+  */ 
+  
 /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
   * @{
   */ 
@@ -181,21 +307,11 @@
 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
   * @{
   */
-#define FSMC_BANK1_NORSRAM1                       ((uint32_t)0x00000000)
-#define FSMC_BANK1_NORSRAM2                       ((uint32_t)0x00000002)
-#define FSMC_BANK1_NORSRAM3                       ((uint32_t)0x00000004)
-#define FSMC_BANK1_NORSRAM4                       ((uint32_t)0x00000006)
+#define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
+#define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
+#define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
 
-/* To keep compatibility with previous families */
-#define FSMC_NORSRAM_BANK1                        FSMC_BANK1_NORSRAM1
-#define FSMC_NORSRAM_BANK2                        FSMC_BANK1_NORSRAM2
-#define FSMC_NORSRAM_BANK3                        FSMC_BANK1_NORSRAM3
-#define FSMC_NORSRAM_BANK4                        FSMC_BANK1_NORSRAM4
-
-#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_BANK1_NORSRAM1) || \
-                                        ((__BANK__) == FSMC_BANK1_NORSRAM2) || \
-                                        ((__BANK__) == FSMC_BANK1_NORSRAM3) || \
-                                        ((__BANK__) == FSMC_BANK1_NORSRAM4))
 /**
   * @}
   */
@@ -207,8 +323,6 @@
 #define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
 #define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FSMC_BCRx_MUXEN)
 
-#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
-                              ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
 /**
   * @}
   */
@@ -222,9 +336,6 @@
 #define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)FSMC_BCRx_MTYP_1)
 
 
-#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
-                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
-                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
 /**
   * @}
   */
@@ -237,9 +348,6 @@
 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FSMC_BCRx_MWID_0)
 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FSMC_BCRx_MWID_1)
 
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
-                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
-                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
 /**
   * @}
   */
@@ -261,8 +369,6 @@
 #define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000) 
 #define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FSMC_BCRx_BURSTEN)
 
-#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
-                                      ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
 /**
   * @}
   */
@@ -275,8 +381,6 @@
 #define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FSMC_BCRx_WAITPOL)
 
-#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
-                                             ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
 /**
   * @}
   */
@@ -288,8 +392,6 @@
 #define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
 #define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)FSMC_BCRx_WRAPMOD)
 
-#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
-                                     ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 
 /**
   * @}
   */
@@ -301,8 +403,6 @@
 #define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
 #define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)FSMC_BCRx_WAITCFG)
 
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
-                                                ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 
 /**
   * @}
   */
@@ -314,8 +414,6 @@
 #define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
 #define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)FSMC_BCRx_WREN)
 
-#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
-                                                ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))                        
 /**
   * @}
   */
@@ -327,9 +425,6 @@
 #define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
 #define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FSMC_BCRx_WAITEN)
 
-#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
-                                          ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 
-
 /**
   * @}
   */
@@ -341,8 +436,6 @@
 #define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
 #define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)FSMC_BCRx_EXTMOD)
 
-#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
-                                         ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
 /**
   * @}
   */
@@ -354,9 +447,6 @@
 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FSMC_BCRx_ASYNCWAIT)
 
-#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
-                                     ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-
 /**
   * @}
   */  
@@ -368,81 +458,10 @@
 #define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
 #define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)FSMC_BCRx_CBURSTRW)
 
-#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
-                                        ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
-  * @{
-  */
-  
-#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
-  * @{
-  */
-  
-#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
-  * @{
-  */
-  
-#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
 /**
   * @}
   */
 
-/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
-  * @{
-  */
-  
-#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_CLK_Division FSMC CLK Division
-  * @{
-  */
-  
-#define FSMC_CLK_DIV2                        ((uint32_t)0x00000002)
-#define FSMC_CLK_DIV3                        ((uint32_t)0x00000003)
-#define FSMC_CLK_DIV4                        ((uint32_t)0x00000004)
-#define FSMC_CLK_DIV5                        ((uint32_t)0x00000005)
-#define FSMC_CLK_DIV6                        ((uint32_t)0x00000006)
-#define FSMC_CLK_DIV7                        ((uint32_t)0x00000007)
-#define FSMC_CLK_DIV8                        ((uint32_t)0x00000008)
-#define FSMC_CLK_DIV9                        ((uint32_t)0x00000009)
-#define FSMC_CLK_DIV10                       ((uint32_t)0x0000000A)
-#define FSMC_CLK_DIV11                       ((uint32_t)0x0000000B)
-#define FSMC_CLK_DIV12                       ((uint32_t)0x0000000C)
-#define FSMC_CLK_DIV13                       ((uint32_t)0x0000000D)
-#define FSMC_CLK_DIV14                       ((uint32_t)0x0000000E)
-#define FSMC_CLK_DIV15                       ((uint32_t)0x0000000F)
-#define FSMC_CLK_DIV16                       ((uint32_t)0x00000010)
-#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Latency FSMC Data Latency
-  * @{
-  */
-  
-#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-/**
-  * @}
-  */  
-
 /** @defgroup FSMC_Access_Mode FSMC Access Mode
   * @{
   */
@@ -452,40 +471,20 @@
 #define FSMC_ACCESS_MODE_C                        ((uint32_t)FSMC_BTRx_ACCMOD_1)
 #define FSMC_ACCESS_MODE_D                        ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
 
-#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_B) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_C) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_D))
 /**
   * @}
   */
     
-/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
-  * @{
-  */
-  
-#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
-  * @{
-  */
-  
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-/**
-  * @}
-  */
-
 /**
   * @}
   */
 
 /* Exported macro ------------------------------------------------------------*/
 
+/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
+  * @{
+  */ 
+  
 /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
  *  @brief macros to handle NOR device enable/disable and read/write operations
  *  @{
@@ -497,7 +496,7 @@
   * @param  __BANK__: FSMC_NORSRAM Bank    
   * @retval none
   */ 
-#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN)
+#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
 
 /**
   * @brief  Disable the NORSRAM device access.
@@ -505,7 +504,12 @@
   * @param  __BANK__: FSMC_NORSRAM Bank   
   * @retval none
   */ 
-#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN)  
+#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
+
+/**
+  * @}
+  */ 
+
 
 /**
   * @}
@@ -513,38 +517,36 @@
 
 /* Exported functions --------------------------------------------------------*/
 
-/** @addtogroup FSMC_Exported_Functions
+/** @addtogroup FSMC_LL_Exported_Functions
  *  @{
  */
 
-/** @addtogroup HAL_FSMC_NORSRAM_Group1
+/** @addtogroup FSMC_NORSRAM
+ *  @{
+ */
+
+/** @addtogroup FSMC_NORSRAM_Group1
  *  @{
  */
 
 /* FSMC_NORSRAM Controller functions ******************************************/
 /* Initialization/de-initialization functions */
-HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
 
 /**
   * @}
   */ 
 
-/** @addtogroup HAL_FSMC_NORSRAM_Group2
+/** @addtogroup FSMC_NORSRAM_Group2
  *  @{
  */
 
 /* FSMC_NORSRAM Control functions */
-HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank);
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
+HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 
 /**
   * @}
@@ -554,6 +556,17 @@
   * @}
   */ 
 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
+
 /**
   * @}
   */
@@ -565,3 +578,4 @@
 #endif /* __STM32L1xx_LL_FSMC_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+