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Diff: TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h
- Revision:
- 122:f9eeca106725
- Parent:
- 110:165afa46840b
diff -r 6c34061e7c34 -r f9eeca106725 TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h
--- a/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.4.1
- * @date 09-October-2015
+ * @version V1.5.0
+ * @date 06-May-2016
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -123,12 +123,10 @@
This parameter is only enabled through the FMC_BCR1 register, and don't care
through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Write_FIFO
- This mode is available only for the STM32F446/469/479xx devices */
+ This mode is available only for the STM32F446/469/479xx devices */
uint32_t PageSize; /*!< Specifies the memory page size.
- This parameter can be a value of @ref FMC_Page_Size
- This mode is available only for the STM32F446xx devices */
-
+ This parameter can be a value of @ref FMC_Page_Size */
}FMC_NORSRAM_InitTypeDef;
/**
@@ -354,10 +352,10 @@
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
-#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
-#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
-#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
+#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
+#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
+#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
+#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
/**
* @}
*/
@@ -365,8 +363,8 @@
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
-#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
-#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
+#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
+#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
/**
* @}
*/
@@ -374,9 +372,9 @@
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
-#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
-#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
-#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
+#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
+#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
+#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
/**
* @}
*/
@@ -384,9 +382,9 @@
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
-#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
+#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
/**
* @}
*/
@@ -394,8 +392,8 @@
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
-#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
-#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
/**
* @}
*/
@@ -403,8 +401,8 @@
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
-#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
+#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
+#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
/**
* @}
*/
@@ -412,8 +410,8 @@
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
-#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
+#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
+#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
/**
* @}
*/
@@ -423,8 +421,8 @@
*/
/** @note This mode is not available for the STM32F446/469/479xx devices
*/
-#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
+#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
+#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
/**
* @}
*/
@@ -432,8 +430,8 @@
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
-#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
-#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
+#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
+#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
/**
* @}
*/
@@ -441,8 +439,8 @@
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
-#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
+#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
+#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
/**
* @}
*/
@@ -450,8 +448,8 @@
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
-#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
-#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
+#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
+#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
/**
* @}
*/
@@ -459,8 +457,8 @@
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
-#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
-#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
+#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
+#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
/**
* @}
*/
@@ -468,19 +466,19 @@
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
-#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
-#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
+#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
+#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
/**
* @}
*/
/** @defgroup FMC_Page_Size FMC Page Size
- * @note These values are available only for the STM32F446/469/479xx devices.
* @{
*/
-#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
+#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
+#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
/**
* @}
@@ -490,8 +488,8 @@
* @note These values are available only for the STM32F446/469/479xx devices.
* @{
*/
-#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
+#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
+#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
/**
* @}
*/
@@ -499,8 +497,8 @@
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
-#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
-#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
+#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
+#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
/**
* @}
*/
@@ -508,8 +506,8 @@
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
-#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
-#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
/**
* @}
*/
@@ -517,10 +515,10 @@
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
-#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
-#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
-#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
-#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
+#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
+#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
+#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
+#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
/**
* @}
*/
@@ -535,8 +533,8 @@
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
-#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
-#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
+#define FMC_NAND_BANK2 ((uint32_t)0x00000010U)
+#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
/**
* @}
*/
@@ -544,8 +542,8 @@
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
/**
* @}
*/
@@ -553,8 +551,8 @@
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
-#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
-#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
+#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
+#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
/**
* @}
*/
@@ -562,8 +560,8 @@
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
/**
* @}
*/
@@ -571,8 +569,8 @@
/** @defgroup FMC_ECC FMC ECC
* @{
*/
-#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
+#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
+#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
/**
* @}
*/
@@ -580,12 +578,12 @@
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
-#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
-#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
-#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
-#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
-#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
-#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
/**
* @}
*/
@@ -600,8 +598,8 @@
/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
* @{
*/
-#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
-#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
+#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
+#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
/**
* @}
*/
@@ -609,10 +607,10 @@
/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
* @{
*/
-#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
-#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
-#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
-#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
+#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
+#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
/**
* @}
*/
@@ -620,9 +618,9 @@
/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
* @{
*/
-#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
-#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
-#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
+#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
+#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
+#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
/**
* @}
*/
@@ -630,9 +628,9 @@
/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
* @{
*/
-#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
-#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
-#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
+#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
+#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
/**
* @}
*/
@@ -640,8 +638,8 @@
/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
* @{
*/
-#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
-#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
+#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
+#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
/**
* @}
*/
@@ -649,9 +647,9 @@
/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
* @{
*/
-#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
-#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
-#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
+#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
+#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
+#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U)
/**
* @}
*/
@@ -659,8 +657,8 @@
/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
* @{
*/
-#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
-#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
/**
* @}
@@ -669,9 +667,9 @@
/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
* @{
*/
-#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
-#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
-#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
+#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
+#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
+#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U)
/**
* @}
*/
@@ -679,8 +677,8 @@
/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
* @{
*/
-#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
-#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
+#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
+#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
/**
* @}
*/
@@ -688,9 +686,9 @@
/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
* @{
*/
-#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
-#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
-#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
+#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
+#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
+#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
/**
* @}
*/
@@ -698,13 +696,13 @@
/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
* @{
*/
-#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
-#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
-#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
-#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
-#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
-#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
-#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
+#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
+#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
+#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
+#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
+#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
+#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
/**
* @}
*/
@@ -714,7 +712,7 @@
*/
#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
-#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
+#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
/**
* @}
*/
@@ -722,7 +720,7 @@
/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
* @{
*/
-#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
+#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
/**
@@ -736,10 +734,10 @@
/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
* @{
*/
-#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
-#define FMC_IT_LEVEL ((uint32_t)0x00000010)
-#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
-#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
+#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
+#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
+#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
+#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
/**
* @}
*/
@@ -747,10 +745,10 @@
/** @defgroup FMC_LL_Flag_definition FMC Flag definition
* @{
*/
-#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
-#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
-#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
+#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
+#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
+#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
@@ -854,7 +852,7 @@
* @retval None
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
- ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
+ ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
/**
@@ -913,7 +911,7 @@
* @retval None
*/
#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
-
+
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__: FMC_NAND Instance
@@ -953,7 +951,7 @@
* @retval None
*/
#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
+ ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
/**
* @brief Disable the NAND device interrupt.
@@ -967,8 +965,8 @@
* @retval None
*/
#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
- ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
-
+ ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
+
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__: FMC_NAND Instance
@@ -982,7 +980,7 @@
* @retval The state of FLAG (SET or RESET).
*/
#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
- (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
+ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
/**
* @brief Clear flag status of the NAND device.
* @param __INSTANCE__: FMC_NAND Instance
@@ -996,7 +994,7 @@
* @retval None
*/
#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
- ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
+ ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
@@ -1139,17 +1137,17 @@
((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
-#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
-#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
-#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
-#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
-#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
+#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
@@ -1160,15 +1158,15 @@
#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
((__MODE__) == FMC_WRAP_MODE_ENABLE))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
@@ -1191,17 +1189,17 @@
#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
-#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
-#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
-#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
-#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
-#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
-#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
+#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
((BANK) == FMC_SDRAM_BANK2))
@@ -1239,19 +1237,19 @@
((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
-#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
-#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
-#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
-#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
-#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
+#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
-#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
-#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
+#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
@@ -1265,26 +1263,27 @@
((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
-#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
+#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
-#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
+#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
-#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
+#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
-
-#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
- ((SIZE) == FMC_PAGE_SIZE_128) || \
- ((SIZE) == FMC_PAGE_SIZE_256) || \
+ ((SIZE) == FMC_PAGE_SIZE_128) || \
+ ((SIZE) == FMC_PAGE_SIZE_256) || \
+ ((SIZE) == FMC_PAGE_SIZE_512) || \
((SIZE) == FMC_PAGE_SIZE_1024))
+#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
((FIFO) == FMC_WRITE_FIFO_ENABLE))
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
/**
* @}