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Diff: TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h
- Revision:
- 122:f9eeca106725
- Parent:
- 110:165afa46840b
diff -r 6c34061e7c34 -r f9eeca106725 TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h
--- a/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_i2s.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.4.1
- * @date 09-October-2015
+ * @version V1.5.0
+ * @date 06-May-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -95,14 +95,14 @@
*/
typedef enum
{
- HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
- HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
- HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
- HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
- HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
- HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
+ HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x03U, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x04U /*!< I2S error state */
}HAL_I2S_StateTypeDef;
@@ -151,13 +151,13 @@
* @brief I2S Error Code
* @{
*/
-#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000001) /*!< I2S Underrun error */
-#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< I2S Overrun error */
-#define HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004) /*!< I2S extended Underrun error */
-#define HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008) /*!< I2S extended Overrun error */
-#define HAL_I2S_ERROR_FRE ((uint32_t)0x00000010) /*!< I2S Frame format error */
-#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000020) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000001U) /*!< I2S Underrun error */
+#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) /*!< I2S Overrun error */
+#define HAL_I2SEX_ERROR_UDR ((uint32_t)0x00000004U) /*!< I2S extended Underrun error */
+#define HAL_I2SEX_ERROR_OVR ((uint32_t)0x00000008U) /*!< I2S extended Overrun error */
+#define HAL_I2S_ERROR_FRE ((uint32_t)0x00000010U) /*!< I2S Frame format error */
+#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000020U) /*!< DMA transfer error */
/**
* @}
*/
@@ -165,10 +165,10 @@
/** @defgroup I2S_Mode I2S Mode
* @{
*/
-#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
-#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
-#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
-#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
+#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)
+#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)
+#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)
+#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)
/**
* @}
*/
@@ -176,11 +176,11 @@
/** @defgroup I2S_Standard I2S Standard
* @{
*/
-#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
-#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
-#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
-#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
-#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
+#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)
+#define I2S_STANDARD_MSB ((uint32_t)0x00000010U)
+#define I2S_STANDARD_LSB ((uint32_t)0x00000020U)
+#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)
+#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)
/**
* @}
*/
@@ -188,10 +188,10 @@
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
-#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
-#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
-#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
-#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
+#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)
+#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)
+#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)
/**
* @}
*/
@@ -200,7 +200,7 @@
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
+#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
/**
* @}
*/
@@ -208,16 +208,16 @@
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
-#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
-#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
-#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
-#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
-#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
-#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
-#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
-#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
-#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
-#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
+#define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
+#define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
+#define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
+#define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
+#define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
+#define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
+#define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
+#define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
+#define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
+#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
/**
* @}
*/
@@ -225,8 +225,8 @@
/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
* @{
*/
-#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
-#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
+#define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000U)
+#define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001U)
/**
* @}
*/
@@ -234,7 +234,7 @@
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
-#define I2S_CPOL_LOW ((uint32_t)0x00000000)
+#define I2S_CPOL_LOW ((uint32_t)0x00000000U)
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
/**
* @}
@@ -333,7 +333,7 @@
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg; \
+ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->DR; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
@@ -344,8 +344,8 @@
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg; \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
} while(0)