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Diff: TARGET_NUCLEO_F072RB/stm32f0xx_hal_wwdg.h

Revision:
122:f9eeca106725
Parent:
108:34e6b704fe68
diff -r 6c34061e7c34 -r f9eeca106725 TARGET_NUCLEO_F072RB/stm32f0xx_hal_wwdg.h
--- a/TARGET_NUCLEO_F072RB/stm32f0xx_hal_wwdg.h	Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_NUCLEO_F072RB/stm32f0xx_hal_wwdg.h	Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32f0xx_hal_wwdg.h
   * @author  MCD Application Team
-  * @version V1.3.0
-  * @date    26-June-2015
+  * @version V1.4.0
+  * @date    27-May-2016
   * @brief   Header file of WWDG HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -133,8 +133,8 @@
   * @{
   */ 
 #define WWDG_PRESCALER_1                  ((uint32_t)0x00000000)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_2                  WWDG_CFR_WDGTB_0  /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4                  WWDG_CFR_WDGTB_1  /*!< WWDG counter clock = (PCLK1/4096)/4 */
 #define WWDG_PRESCALER_8                  WWDG_CFR_WDGTB  /*!< WWDG counter clock = (PCLK1/4096)/8 */
 /**
   * @}