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Diff: TARGET_EFM32ZG_STK3200/efm32zg_dma.h
- Revision:
- 113:f141b2784e32
- Parent:
- 98:8ab26030e058
diff -r 6f327212ef96 -r f141b2784e32 TARGET_EFM32ZG_STK3200/efm32zg_dma.h
--- a/TARGET_EFM32ZG_STK3200/efm32zg_dma.h Wed Jan 13 09:48:29 2016 +0000
+++ b/TARGET_EFM32ZG_STK3200/efm32zg_dma.h Tue Feb 02 14:43:35 2016 +0000
@@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32zg_dma.h
* @brief EFM32ZG_DMA register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
******************************************************************************
* @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
*
*****************************************************************************/
/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
* @defgroup EFM32ZG_DMA
* @{
* @brief EFM32ZG_DMA Register Declaration
@@ -67,7 +71,6 @@
__IO uint32_t IEN; /**< Interrupt Enable register */
uint32_t RESERVED4[60]; /**< Reserved registers */
-
DMA_CH_TypeDef CH[4]; /**< Channel registers */
} DMA_TypeDef; /** @} */
@@ -687,5 +690,5 @@
#define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
/** @} End of group EFM32ZG_DMA */
+/** @} End of group Parts */
-