Diff: TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/stm32f746zg.icf

Revision:

116:c0f6e94411f5

diff -r 87f2f5183dfb -r c0f6e94411f5 TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/stm32f746zg.icf
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_NUCLEO_F746ZG/TOOLCHAIN_IAR/stm32f746zg.icf	Tue Mar 15 14:34:00 2016 +0000
@@ -0,0 +1,35 @@
+/* [ROM = 1024kb = 0x100000] */
+define symbol __intvec_start__     = 0x08000000;
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__   = 0x080FFFFF;
+
+/* [RAM = 320kb = 0x50000] Vector table dynamic copy: 114 vectors = 456 bytes (0x1C8) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x200001C7; /* Aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x200001C8;
+define symbol __region_RAM_end__      = 0x2004FFFF;
+
+define symbol __region_ITCMRAM_start__ = 0x00000000;
+define symbol __region_ITCMRAM_end__   = 0x00003FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__];
+
+/* Stack and Heap */
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __size_cstack__ = 0x4000;
+define symbol __size_heap__   = 0x8000;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block STACKHEAP };