Diff: TARGET_KL05Z/core_cm3.h

Revision:

128:9bcdf88f62b0

Parent:

127:25aea2a3f4e3

Child:

131:faff56e089b2

diff -r 25aea2a3f4e3 -r 9bcdf88f62b0 TARGET_KL05Z/core_cm3.h
--- a/TARGET_KL05Z/core_cm3.h	Fri Sep 30 16:49:46 2016 +0100
+++ b/TARGET_KL05Z/core_cm3.h	Thu Oct 27 16:45:56 2016 +0100
@@ -202,6 +202,14 @@
 #define     __O     volatile             /*!< Defines 'write only' permissions                */
 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
+#ifdef __cplusplus
+  #define   __IM    volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __IM    volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __OM    volatile             /*!< Defines 'write only' permissions                */
+#define     __IOM   volatile             /*!< Defines 'read / write' permissions              */
+
 /*@} end of group Cortex_M3 */
 
 
@@ -1353,6 +1361,7 @@
   #define NVIC_GetActive              __NVIC_GetActive
   #define NVIC_SetPriority            __NVIC_SetPriority
   #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
 #endif /* CMSIS_NVIC_VIRTUAL */
 
 #ifdef CMSIS_VECTAB_VIRTUAL
@@ -1581,7 +1590,7 @@
 
     The function initiates a system reset request to reset the MCU.
  */
-__STATIC_INLINE void NVIC_SystemReset(void)
+__STATIC_INLINE void __NVIC_SystemReset(void)
 {
   __DSB();                                                          /* Ensure all outstanding memory accesses included
                                                                        buffered write are completed before reset */