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Diff: TARGET_ARCH_BLE/nrf51.h
- Revision:
- 97:433970e64889
- Parent:
- 93:e188a91d3eaa
- Child:
- 122:f9eeca106725
diff -r 487b796308b0 -r 433970e64889 TARGET_ARCH_BLE/nrf51.h
--- a/TARGET_ARCH_BLE/nrf51.h Tue Mar 17 14:27:45 2015 +0000
+++ b/TARGET_ARCH_BLE/nrf51.h Tue Apr 14 10:58:58 2015 +0200
@@ -1,14 +1,46 @@
-/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
+
+/****************************************************************************************************//**
+ * @file nRF51.h
+ *
+ * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
+ * nRF51 from Nordic Semiconductor.
+ *
+ * @version V522
+ * @date 31. October 2014
*
- * The information contained herein is property of Nordic Semiconductor ASA.
- * Terms and conditions of usage are described in detail in NORDIC
- * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ * @note Generated with SVDConv V2.81d
+ * from CMSIS SVD File 'nRF51.xml' Version 522,
+ *
+ * @par Copyright (c) 2013, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
*
- * Licensees are granted free, non-transferable use of the information. NO
- * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
- * the file.
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Nordic Semiconductor ASA nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
*
- */
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ *******************************************************************************************************/
@@ -58,7 +90,7 @@
WDT_IRQn = 16, /*!< 16 WDT */
RTC1_IRQn = 17, /*!< 17 RTC1 */
QDEC_IRQn = 18, /*!< 18 QDEC */
- LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
+ LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
SWI0_IRQn = 20, /*!< 20 SWI0 */
SWI1_IRQn = 21, /*!< 21 SWI1 */
SWI2_IRQn = 22, /*!< 22 SWI2 */
@@ -77,16 +109,15 @@
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
-/* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
+/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */
-#include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
-#include "system_nrf51822.h" /*!< nRF51 System */
-
+#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
+#include "system_nrf51.h" /*!< nRF51 System */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
@@ -125,6 +156,24 @@
} AMLI_RAMPRI_Type;
typedef struct {
+ __IO uint32_t SCK; /*!< Pin select for SCK. */
+ __IO uint32_t MOSI; /*!< Pin select for MOSI. */
+ __IO uint32_t MISO; /*!< Pin select for MISO. */
+} SPIM_PSEL_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer. */
+ __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
+ __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
+} SPIM_RXD_Type;
+
+typedef struct {
+ __IO uint32_t PTR; /*!< Data pointer. */
+ __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
+ __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
+} SPIM_TXD_Type;
+
+typedef struct {
__O uint32_t EN; /*!< Enable channel group. */
__O uint32_t DIS; /*!< Disable channel group. */
} PPI_TASKS_CHG_Type;
@@ -134,6 +183,15 @@
__IO uint32_t TEP; /*!< Channel task end-point. */
} PPI_CH_Type;
+typedef struct {
+ __I uint32_t PART; /*!< Part code */
+ __I uint32_t VARIANT; /*!< Part variant */
+ __I uint32_t PACKAGE; /*!< Package option */
+ __I uint32_t RAM; /*!< RAM variant */
+ __I uint32_t FLASH; /*!< Flash variant */
+ __I uint32_t RESERVED[3]; /*!< Reserved */
+} FICR_INFO_Type;
+
/* ================================================================================ */
/* ================ POWER ================ */
@@ -155,20 +213,26 @@
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED3[61];
__IO uint32_t RESETREAS; /*!< Reset reason. */
- __I uint32_t RESERVED4[63];
+ __I uint32_t RESERVED4[9];
+ __I uint32_t RAMSTATUS; /*!< Ram status register. */
+ __I uint32_t RESERVED5[53];
__O uint32_t SYSTEMOFF; /*!< System off register. */
- __I uint32_t RESERVED5[3];
+ __I uint32_t RESERVED6[3];
__IO uint32_t POFCON; /*!< Power failure configuration. */
- __I uint32_t RESERVED6[2];
+ __I uint32_t RESERVED7[2];
__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
register. */
- __I uint32_t RESERVED7;
+ __I uint32_t RESERVED8;
__IO uint32_t RAMON; /*!< Ram on/off. */
- __I uint32_t RESERVED8[7];
+ __I uint32_t RESERVED9[7];
__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
is a retained register. */
- __I uint32_t RESERVED9[12];
+ __I uint32_t RESERVED10[3];
+ __IO uint32_t RAMONB; /*!< Ram on/off. */
+ __I uint32_t RESERVED11[8];
__IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
+ __I uint32_t RESERVED12[291];
+ __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
} NRF_POWER_Type;
@@ -193,16 +257,20 @@
__IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
__IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
__I uint32_t RESERVED1;
- __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
- __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
+ __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
+ __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
__I uint32_t RESERVED2[124];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[64];
+ __I uint32_t RESERVED3[63];
+ __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
__I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
- __I uint32_t RESERVED4[2];
+ __I uint32_t RESERVED4;
+ __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
__I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
- __I uint32_t RESERVED5[63];
+ __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
+ triggered. */
+ __I uint32_t RESERVED5[62];
__IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
__I uint32_t RESERVED6[7];
__IO uint32_t CTIV; /*!< Calibration timer interval. */
@@ -225,9 +293,10 @@
__IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
__IO uint32_t RLENR0; /*!< Length of RAM region 0. */
__I uint32_t RESERVED1[52];
- __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
- __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
- __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
+ __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
+ __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
+ __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
+ __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
} NRF_MPU_Type;
@@ -299,17 +368,17 @@
__I uint32_t RESERVED1[2];
__IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
__I uint32_t RESERVED2[53];
- __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
+ __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
__I uint32_t RESERVED3[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED4[61];
__I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
- __I uint32_t RESERVED5;
+ __I uint32_t CD; /*!< Carrier detect. */
__I uint32_t RXMATCH; /*!< Received address. */
__I uint32_t RXCRC; /*!< Received CRC. */
- __IO uint32_t DAI; /*!< Device address match index. */
- __I uint32_t RESERVED6[60];
+ __I uint32_t DAI; /*!< Device address match index. */
+ __I uint32_t RESERVED5[60];
__IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
__IO uint32_t FREQUENCY; /*!< Frequency. */
__IO uint32_t TXPOWER; /*!< Output power. */
@@ -327,23 +396,23 @@
__IO uint32_t CRCINIT; /*!< CRC initial value. */
__IO uint32_t TEST; /*!< Test features enable register. */
__IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
- __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
- __I uint32_t RESERVED7;
+ __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
+ __I uint32_t RESERVED6;
__I uint32_t STATE; /*!< Current radio state. */
__IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
- __I uint32_t RESERVED8[2];
+ __I uint32_t RESERVED7[2];
__IO uint32_t BCC; /*!< Bit counter compare. */
- __I uint32_t RESERVED9[39];
+ __I uint32_t RESERVED8[39];
__IO uint32_t DAB[8]; /*!< Device address base segment. */
__IO uint32_t DAP[8]; /*!< Device address prefix. */
__IO uint32_t DACNF; /*!< Device address match configuration. */
- __I uint32_t RESERVED10[56];
+ __I uint32_t RESERVED9[56];
__IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
__IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
__IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
__IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
__IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
- __I uint32_t RESERVED11[561];
+ __I uint32_t RESERVED10[561];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_RADIO_Type;
@@ -375,9 +444,8 @@
__I uint32_t RESERVED4[7];
__IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
__I uint32_t RESERVED5[46];
- __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
- __I uint32_t RESERVED6[63];
- __IO uint32_t INTEN; /*!< Interrupt enable register. */
+ __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
+ __I uint32_t RESERVED6[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED7[93];
@@ -390,7 +458,7 @@
__IO uint32_t PSELCTS; /*!< Pin select for CTS. */
__IO uint32_t PSELRXD; /*!< Pin select for RXD. */
__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
- Once read the character is consummed. If read when no character
+ Once read the character is consumed. If read when no character
available, the UART will stop working. */
__O uint32_t TXD; /*!< TXD register. */
__I uint32_t RESERVED10;
@@ -424,7 +492,7 @@
__IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
__IO uint32_t PSELMISO; /*!< Pin select for MISO. */
__I uint32_t RESERVED4;
- __IO uint32_t RXD; /*!< RX data. */
+ __I uint32_t RXD; /*!< RX data. */
__IO uint32_t TXD; /*!< TX data. */
__I uint32_t RESERVED5;
__IO uint32_t FREQUENCY; /*!< SPI frequency */
@@ -462,26 +530,28 @@
__IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
__I uint32_t RESERVED6[4];
__IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
- __I uint32_t RESERVED7[49];
+ __I uint32_t RESERVED7[3];
+ __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
+ __I uint32_t RESERVED8[45];
__IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
- __I uint32_t RESERVED8[64];
+ __I uint32_t RESERVED9[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED9[110];
+ __I uint32_t RESERVED10[110];
__IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
- __I uint32_t RESERVED10[14];
+ __I uint32_t RESERVED11[14];
__IO uint32_t ENABLE; /*!< Enable two-wire master. */
- __I uint32_t RESERVED11;
+ __I uint32_t RESERVED12;
__IO uint32_t PSELSCL; /*!< Pin select for SCL. */
__IO uint32_t PSELSDA; /*!< Pin select for SDA. */
- __I uint32_t RESERVED12[2];
- __IO uint32_t RXD; /*!< RX data register. */
+ __I uint32_t RESERVED13[2];
+ __I uint32_t RXD; /*!< RX data register. */
__IO uint32_t TXD; /*!< TX data register. */
- __I uint32_t RESERVED13;
+ __I uint32_t RESERVED14;
__IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
- __I uint32_t RESERVED14[24];
+ __I uint32_t RESERVED15[24];
__IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
- __I uint32_t RESERVED15[668];
+ __I uint32_t RESERVED16[668];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_TWI_Type;
@@ -522,11 +592,11 @@
__I uint32_t RESERVED9[7];
__IO uint32_t RXDPTR; /*!< RX data pointer. */
__IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
- __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
+ __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
__I uint32_t RESERVED10;
__IO uint32_t TXDPTR; /*!< TX data pointer. */
__IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
- __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
+ __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
__I uint32_t RESERVED11;
__IO uint32_t CONFIG; /*!< Configuration register. */
__I uint32_t RESERVED12;
@@ -539,6 +609,59 @@
/* ================================================================================ */
+/* ================ SPIM ================ */
+/* ================================================================================ */
+
+
+/**
+ * @brief SPI master with easyDMA 1. (SPIM)
+ */
+
+typedef struct { /*!< SPIM Structure */
+ __I uint32_t RESERVED0[4];
+ __O uint32_t TASKS_START; /*!< Start SPI transaction. */
+ __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
+ __I uint32_t RESERVED1;
+ __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
+ __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
+ __I uint32_t RESERVED2[56];
+ __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
+ __I uint32_t RESERVED3[2];
+ __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
+ __I uint32_t RESERVED4;
+ __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
+ __I uint32_t RESERVED5;
+ __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
+ __I uint32_t RESERVED6[10];
+ __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
+ __I uint32_t RESERVED7[44];
+ __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
+ __I uint32_t RESERVED8[64];
+ __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
+ __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
+ __I uint32_t RESERVED9[125];
+ __IO uint32_t ENABLE; /*!< Enable SPIM. */
+ __I uint32_t RESERVED10;
+ SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
+ __I uint32_t RESERVED11;
+ __I uint32_t RXDDATA; /*!< RXD register. */
+ __IO uint32_t TXDDATA; /*!< TXD register. */
+ __I uint32_t RESERVED12;
+ __IO uint32_t FREQUENCY; /*!< SPI frequency. */
+ __I uint32_t RESERVED13[3];
+ SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
+ __I uint32_t RESERVED14;
+ SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
+ __I uint32_t RESERVED15;
+ __IO uint32_t CONFIG; /*!< Configuration register. */
+ __I uint32_t RESERVED16[26];
+ __IO uint32_t ORC; /*!< Over-read character. */
+ __I uint32_t RESERVED17[654];
+ __IO uint32_t POWER; /*!< Peripheral power control. */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
/* ================ GPIOTE ================ */
/* ================================================================================ */
@@ -605,7 +728,8 @@
__O uint32_t TASKS_STOP; /*!< Stop Timer. */
__O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
__O uint32_t TASKS_CLEAR; /*!< Clear timer. */
- __I uint32_t RESERVED0[12];
+ __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
+ __I uint32_t RESERVED0[11];
__O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
__I uint32_t RESERVED1[60];
__IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
@@ -656,7 +780,7 @@
__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
gives the value of EVTEN. */
__I uint32_t RESERVED4[110];
- __IO uint32_t COUNTER; /*!< Current COUNTER value. */
+ __I uint32_t COUNTER; /*!< Current COUNTER value. */
__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
Must be written when RTC is STOPed. */
__I uint32_t RESERVED5[13];
@@ -705,7 +829,7 @@
__I uint32_t RESERVED0[62];
__IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
__I uint32_t RESERVED1[63];
- __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
+ __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
__I uint32_t RESERVED2[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
@@ -775,8 +899,8 @@
__IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
__I uint32_t RESERVED5;
__IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
- resolution. A minimum of 3 bytes must be reserved. */
+ __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
+ during resolution. A minimum of 3 bytes must be reserved. */
__I uint32_t RESERVED6[697];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_AAR_Type;
@@ -802,7 +926,7 @@
__IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
__IO uint32_t EVENTS_ERROR; /*!< Error happened. */
__I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
+ __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
__I uint32_t RESERVED2[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
@@ -811,11 +935,11 @@
__I uint32_t RESERVED4[63];
__IO uint32_t ENABLE; /*!< CCM enable. */
__IO uint32_t MODE; /*!< Operation mode. */
- __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
- __IO uint32_t INPTR; /*!< Pointer to input packet. */
- __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
- __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
- resolution. A minimum of 43 bytes must be reserved. */
+ __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
+ __IO uint32_t INPTR; /*!< Pointer to the input packet. */
+ __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
+ __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
+ during resolution. A minimum of 43 bytes must be reserved. */
__I uint32_t RESERVED5[697];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_CCM_Type;
@@ -871,7 +995,7 @@
ACC register different than zero. */
__IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
__I uint32_t RESERVED1[61];
- __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
+ __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
__I uint32_t RESERVED2[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
@@ -904,7 +1028,7 @@
/**
- * @brief Wakeup Comparator. (LPCOMP)
+ * @brief Low power comparator. (LPCOMP)
*/
typedef struct { /*!< LPCOMP Structure */
@@ -917,7 +1041,7 @@
__IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
__IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
__I uint32_t RESERVED1[60];
- __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
+ __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
__I uint32_t RESERVED2[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
@@ -936,44 +1060,6 @@
/* ================================================================================ */
-/* ================ COMP ================ */
-/* ================================================================================ */
-
-
-/**
- * @brief Comparator. (COMP)
- */
-
-typedef struct { /*!< COMP Structure */
- __O uint32_t TASKS_START; /*!< Start the comparator. */
- __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
- __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
- __I uint32_t RESERVED0[61];
- __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
- __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
- __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
- __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
- __I uint32_t RESERVED1[60];
- __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
- __I uint32_t RESERVED2[64];
- __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
- __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
- __I uint32_t RESERVED3[61];
- __I uint32_t RESULT; /*!< Compare result. */
- __I uint32_t RESERVED4[63];
- __IO uint32_t ENABLE; /*!< Enable the COMP. */
- __IO uint32_t PSEL; /*!< Input pin select. */
- __IO uint32_t REFSEL; /*!< Reference select. */
- __IO uint32_t EXTREFSEL; /*!< External reference select. */
- __I uint32_t RESERVED5[8];
- __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
- __IO uint32_t MODE; /*!< Mode configuration. */
- __I uint32_t RESERVED6[689];
- __IO uint32_t POWER; /*!< Peripheral power control. */
-} NRF_COMP_Type;
-
-
-/* ================================================================================ */
/* ================ SWI ================ */
/* ================================================================================ */
@@ -1048,7 +1134,13 @@
__I uint32_t PPFC; /*!< Pre-programmed factory code present. */
__I uint32_t RESERVED2;
__I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
- __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
+
+ union {
+ __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
+ kept for backward compatinility purposes. Use SIZERAMBLOCKS
+ instead. */
+ __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
+ };
__I uint32_t RESERVED3[5];
__I uint32_t CONFIGID; /*!< Configuration identifier. */
__I uint32_t DEVICEID[2]; /*!< Device identifier. */
@@ -1058,9 +1150,12 @@
__I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
__I uint32_t DEVICEADDR[2]; /*!< Device address. */
__I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
- __I uint32_t RESERVED5[15];
+ __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
+ mode. */
+ __I uint32_t RESERVED5[10];
__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
mode. */
+ FICR_INFO_Type INFO; /*!< Device info */
} NRF_FICR_Type;
@@ -1140,6 +1235,7 @@
#define NRF_SPI1_BASE 0x40004000UL
#define NRF_TWI1_BASE 0x40004000UL
#define NRF_SPIS1_BASE 0x40004000UL
+#define NRF_SPIM1_BASE 0x40004000UL
#define NRF_GPIOTE_BASE 0x40006000UL
#define NRF_ADC_BASE 0x40007000UL
#define NRF_TIMER0_BASE 0x40008000UL
@@ -1155,7 +1251,6 @@
#define NRF_RTC1_BASE 0x40011000UL
#define NRF_QDEC_BASE 0x40012000UL
#define NRF_LPCOMP_BASE 0x40013000UL
-#define NRF_COMP_BASE 0x40013000UL
#define NRF_SWI_BASE 0x40014000UL
#define NRF_NVMC_BASE 0x4001E000UL
#define NRF_PPI_BASE 0x4001F000UL
@@ -1180,6 +1275,7 @@
#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
+#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
@@ -1195,7 +1291,6 @@
#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
-#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
@@ -1214,3 +1309,4 @@
#endif /* nRF51_H */
+