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TARGET_NRF51_DONGLE/nrf51_bitfields.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:: Kojto
Date:: Thu Jul 07 14:34:11 2016 +0100
Revision:: 122:f9eeca106725
Parent:: 97:433970e64889

Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/*
Kojto	122:f9eeca106725	2	* Copyright (c) Nordic Semiconductor ASA
Kojto	97:433970e64889	3	* All rights reserved.
Kojto	97:433970e64889	4	*
Kojto	122:f9eeca106725	5	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	6	* are permitted provided that the following conditions are met:
Kojto	97:433970e64889	7	*
Kojto	122:f9eeca106725	8	* 1. Redistributions of source code must retain the above copyright notice, this
Kojto	122:f9eeca106725	9	* list of conditions and the following disclaimer.
Kojto	97:433970e64889	10	*
Kojto	122:f9eeca106725	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
Kojto	122:f9eeca106725	12	* list of conditions and the following disclaimer in the documentation and/or
Kojto	122:f9eeca106725	13	* other materials provided with the distribution.
Kojto	91:031413cf7a89	14	*
Kojto	122:f9eeca106725	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
Kojto	122:f9eeca106725	16	* contributors to this software may be used to endorse or promote products
Kojto	122:f9eeca106725	17	* derived from this software without specific prior written permission.
Kojto	122:f9eeca106725	18	*
Kojto	91:031413cf7a89	19	*
Kojto	122:f9eeca106725	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	122:f9eeca106725	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	122:f9eeca106725	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	122:f9eeca106725	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	122:f9eeca106725	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	122:f9eeca106725	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	122:f9eeca106725	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	122:f9eeca106725	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	122:f9eeca106725	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	91:031413cf7a89	30	*
Kojto	91:031413cf7a89	31	*/
Kojto	91:031413cf7a89	32	#ifndef __NRF51_BITS_H
Kojto	91:031413cf7a89	33	#define __NRF51_BITS_H
Kojto	91:031413cf7a89	34
Kojto	122:f9eeca106725	35	/lint ++flb "Enter library region" /
Kojto	91:031413cf7a89	36
Kojto	91:031413cf7a89	37	/* Peripheral: AAR */
Kojto	91:031413cf7a89	38	/* Description: Accelerated Address Resolver. */
Kojto	91:031413cf7a89	39
Kojto	91:031413cf7a89	40	/* Register: AAR_INTENSET */
Kojto	91:031413cf7a89	41	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	42
Kojto	91:031413cf7a89	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
Kojto	91:031413cf7a89	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
Kojto	91:031413cf7a89	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
Kojto	91:031413cf7a89	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	49
Kojto	91:031413cf7a89	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
Kojto	91:031413cf7a89	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
Kojto	91:031413cf7a89	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
Kojto	91:031413cf7a89	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	56
Kojto	91:031413cf7a89	57	/* Bit 0 : Enable interrupt on END event. */
Kojto	91:031413cf7a89	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
Kojto	91:031413cf7a89	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	91:031413cf7a89	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	63
Kojto	91:031413cf7a89	64	/* Register: AAR_INTENCLR */
Kojto	91:031413cf7a89	65	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	66
Kojto	91:031413cf7a89	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
Kojto	91:031413cf7a89	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
Kojto	91:031413cf7a89	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
Kojto	91:031413cf7a89	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	73
Kojto	91:031413cf7a89	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
Kojto	91:031413cf7a89	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
Kojto	91:031413cf7a89	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
Kojto	91:031413cf7a89	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	80
Kojto	91:031413cf7a89	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
Kojto	91:031413cf7a89	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
Kojto	91:031413cf7a89	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	91:031413cf7a89	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	87
Kojto	91:031413cf7a89	88	/* Register: AAR_STATUS */
Kojto	91:031413cf7a89	89	/* Description: Resolution status. */
Kojto	91:031413cf7a89	90
Kojto	91:031413cf7a89	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
Kojto	91:031413cf7a89	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	91:031413cf7a89	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	91:031413cf7a89	94
Kojto	91:031413cf7a89	95	/* Register: AAR_ENABLE */
Kojto	91:031413cf7a89	96	/* Description: Enable AAR. */
Kojto	91:031413cf7a89	97
Kojto	91:031413cf7a89	98	/* Bits 1..0 : Enable AAR. */
Kojto	91:031413cf7a89	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
Kojto	91:031413cf7a89	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
Kojto	91:031413cf7a89	103
Kojto	91:031413cf7a89	104	/* Register: AAR_NIRK */
Kojto	91:031413cf7a89	105	/* Description: Number of Identity root Keys in the IRK data structure. */
Kojto	91:031413cf7a89	106
Kojto	91:031413cf7a89	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
Kojto	91:031413cf7a89	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
Kojto	91:031413cf7a89	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
Kojto	91:031413cf7a89	110
Kojto	91:031413cf7a89	111	/* Register: AAR_POWER */
Kojto	91:031413cf7a89	112	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	113
Kojto	91:031413cf7a89	114	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	119
Kojto	91:031413cf7a89	120
Kojto	91:031413cf7a89	121	/* Peripheral: ADC */
Kojto	91:031413cf7a89	122	/* Description: Analog to digital converter. */
Kojto	91:031413cf7a89	123
Kojto	91:031413cf7a89	124	/* Register: ADC_INTENSET */
Kojto	91:031413cf7a89	125	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	126
Kojto	91:031413cf7a89	127	/* Bit 0 : Enable interrupt on END event. */
Kojto	91:031413cf7a89	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
Kojto	91:031413cf7a89	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	91:031413cf7a89	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	133
Kojto	91:031413cf7a89	134	/* Register: ADC_INTENCLR */
Kojto	91:031413cf7a89	135	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	136
Kojto	91:031413cf7a89	137	/* Bit 0 : Disable interrupt on END event. */
Kojto	91:031413cf7a89	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
Kojto	91:031413cf7a89	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	91:031413cf7a89	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	143
Kojto	91:031413cf7a89	144	/* Register: ADC_BUSY */
Kojto	91:031413cf7a89	145	/* Description: ADC busy register. */
Kojto	91:031413cf7a89	146
Kojto	91:031413cf7a89	147	/* Bit 0 : ADC busy register. */
Kojto	91:031413cf7a89	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
Kojto	91:031413cf7a89	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
Kojto	91:031413cf7a89	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
Kojto	91:031413cf7a89	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
Kojto	91:031413cf7a89	152
Kojto	91:031413cf7a89	153	/* Register: ADC_ENABLE */
Kojto	91:031413cf7a89	154	/* Description: ADC enable. */
Kojto	91:031413cf7a89	155
Kojto	91:031413cf7a89	156	/* Bits 1..0 : ADC enable. */
Kojto	91:031413cf7a89	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
Kojto	91:031413cf7a89	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
Kojto	91:031413cf7a89	161
Kojto	91:031413cf7a89	162	/* Register: ADC_CONFIG */
Kojto	91:031413cf7a89	163	/* Description: ADC configuration register. */
Kojto	91:031413cf7a89	164
Kojto	91:031413cf7a89	165	/* Bits 17..16 : ADC external reference pin selection. */
Kojto	91:031413cf7a89	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
Kojto	91:031413cf7a89	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
Kojto	91:031413cf7a89	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
Kojto	91:031413cf7a89	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
Kojto	91:031413cf7a89	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
Kojto	91:031413cf7a89	171
Kojto	91:031413cf7a89	172	/* Bits 15..8 : ADC analog pin selection. */
Kojto	91:031413cf7a89	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
Kojto	91:031413cf7a89	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
Kojto	91:031413cf7a89	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
Kojto	91:031413cf7a89	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
Kojto	91:031413cf7a89	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
Kojto	91:031413cf7a89	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
Kojto	91:031413cf7a89	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
Kojto	91:031413cf7a89	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
Kojto	91:031413cf7a89	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
Kojto	91:031413cf7a89	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
Kojto	91:031413cf7a89	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
Kojto	91:031413cf7a89	184
Kojto	91:031413cf7a89	185	/* Bits 6..5 : ADC reference selection. */
Kojto	91:031413cf7a89	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
Kojto	91:031413cf7a89	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
Kojto	91:031413cf7a89	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
Kojto	91:031413cf7a89	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
Kojto	91:031413cf7a89	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
Kojto	91:031413cf7a89	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
Kojto	91:031413cf7a89	192
Kojto	91:031413cf7a89	193	/* Bits 4..2 : ADC input selection. */
Kojto	91:031413cf7a89	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
Kojto	91:031413cf7a89	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
Kojto	91:031413cf7a89	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
Kojto	91:031413cf7a89	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
Kojto	91:031413cf7a89	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
Kojto	91:031413cf7a89	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
Kojto	91:031413cf7a89	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
Kojto	91:031413cf7a89	201
Kojto	91:031413cf7a89	202	/* Bits 1..0 : ADC resolution. */
Kojto	91:031413cf7a89	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
Kojto	91:031413cf7a89	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
Kojto	91:031413cf7a89	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
Kojto	91:031413cf7a89	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
Kojto	91:031413cf7a89	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
Kojto	91:031413cf7a89	208
Kojto	91:031413cf7a89	209	/* Register: ADC_RESULT */
Kojto	91:031413cf7a89	210	/* Description: Result of ADC conversion. */
Kojto	91:031413cf7a89	211
Kojto	91:031413cf7a89	212	/* Bits 9..0 : Result of ADC conversion. */
Kojto	91:031413cf7a89	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
Kojto	91:031413cf7a89	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
Kojto	91:031413cf7a89	215
Kojto	91:031413cf7a89	216	/* Register: ADC_POWER */
Kojto	91:031413cf7a89	217	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	218
Kojto	91:031413cf7a89	219	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	224
Kojto	91:031413cf7a89	225
Kojto	91:031413cf7a89	226	/* Peripheral: AMLI */
Kojto	91:031413cf7a89	227	/* Description: AHB Multi-Layer Interface. */
Kojto	91:031413cf7a89	228
Kojto	91:031413cf7a89	229	/* Register: AMLI_RAMPRI_CPU0 */
Kojto	91:031413cf7a89	230	/* Description: Configurable priority configuration register for CPU0. */
Kojto	91:031413cf7a89	231
Kojto	97:433970e64889	232	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	243
Kojto	97:433970e64889	244	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	255
Kojto	97:433970e64889	256	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	267
Kojto	97:433970e64889	268	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	279
Kojto	91:031413cf7a89	280	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	91:031413cf7a89	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	91:031413cf7a89	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	291
Kojto	91:031413cf7a89	292	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	91:031413cf7a89	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	91:031413cf7a89	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	303
Kojto	91:031413cf7a89	304	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	91:031413cf7a89	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	91:031413cf7a89	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	315
Kojto	91:031413cf7a89	316	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	91:031413cf7a89	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	91:031413cf7a89	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	327
Kojto	91:031413cf7a89	328	/* Register: AMLI_RAMPRI_SPIS1 */
Kojto	91:031413cf7a89	329	/* Description: Configurable priority configuration register for SPIS1. */
Kojto	91:031413cf7a89	330
Kojto	97:433970e64889	331	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	342
Kojto	97:433970e64889	343	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	354
Kojto	97:433970e64889	355	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	366
Kojto	97:433970e64889	367	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	378
Kojto	91:031413cf7a89	379	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	91:031413cf7a89	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	91:031413cf7a89	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	390
Kojto	91:031413cf7a89	391	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	91:031413cf7a89	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	91:031413cf7a89	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	402
Kojto	91:031413cf7a89	403	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	91:031413cf7a89	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	91:031413cf7a89	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	414
Kojto	91:031413cf7a89	415	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	91:031413cf7a89	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	91:031413cf7a89	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	426
Kojto	91:031413cf7a89	427	/* Register: AMLI_RAMPRI_RADIO */
Kojto	91:031413cf7a89	428	/* Description: Configurable priority configuration register for RADIO. */
Kojto	91:031413cf7a89	429
Kojto	97:433970e64889	430	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	441
Kojto	97:433970e64889	442	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	453
Kojto	97:433970e64889	454	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	465
Kojto	97:433970e64889	466	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	477
Kojto	91:031413cf7a89	478	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	91:031413cf7a89	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	91:031413cf7a89	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	489
Kojto	91:031413cf7a89	490	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	91:031413cf7a89	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	91:031413cf7a89	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	501
Kojto	91:031413cf7a89	502	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	91:031413cf7a89	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	91:031413cf7a89	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	513
Kojto	91:031413cf7a89	514	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	91:031413cf7a89	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	91:031413cf7a89	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	525
Kojto	91:031413cf7a89	526	/* Register: AMLI_RAMPRI_ECB */
Kojto	91:031413cf7a89	527	/* Description: Configurable priority configuration register for ECB. */
Kojto	91:031413cf7a89	528
Kojto	97:433970e64889	529	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	540
Kojto	97:433970e64889	541	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	552
Kojto	97:433970e64889	553	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	564
Kojto	97:433970e64889	565	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	576
Kojto	91:031413cf7a89	577	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	91:031413cf7a89	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	91:031413cf7a89	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	588
Kojto	91:031413cf7a89	589	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	91:031413cf7a89	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	91:031413cf7a89	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	600
Kojto	91:031413cf7a89	601	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	91:031413cf7a89	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	91:031413cf7a89	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	612
Kojto	91:031413cf7a89	613	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	91:031413cf7a89	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	91:031413cf7a89	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	624
Kojto	91:031413cf7a89	625	/* Register: AMLI_RAMPRI_CCM */
Kojto	91:031413cf7a89	626	/* Description: Configurable priority configuration register for CCM. */
Kojto	91:031413cf7a89	627
Kojto	97:433970e64889	628	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	639
Kojto	97:433970e64889	640	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	651
Kojto	97:433970e64889	652	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	663
Kojto	97:433970e64889	664	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	675
Kojto	91:031413cf7a89	676	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	91:031413cf7a89	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	91:031413cf7a89	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	687
Kojto	91:031413cf7a89	688	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	91:031413cf7a89	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	91:031413cf7a89	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	699
Kojto	91:031413cf7a89	700	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	91:031413cf7a89	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	91:031413cf7a89	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	711
Kojto	91:031413cf7a89	712	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	91:031413cf7a89	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	91:031413cf7a89	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	723
Kojto	91:031413cf7a89	724	/* Register: AMLI_RAMPRI_AAR */
Kojto	91:031413cf7a89	725	/* Description: Configurable priority configuration register for AAR. */
Kojto	91:031413cf7a89	726
Kojto	97:433970e64889	727	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	738
Kojto	97:433970e64889	739	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	750
Kojto	97:433970e64889	751	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	762
Kojto	97:433970e64889	763	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	774
Kojto	91:031413cf7a89	775	/* Bits 15..12 : Configuration field for RAM block 3. */
Kojto	91:031413cf7a89	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
Kojto	91:031413cf7a89	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	786
Kojto	91:031413cf7a89	787	/* Bits 11..8 : Configuration field for RAM block 2. */
Kojto	91:031413cf7a89	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
Kojto	91:031413cf7a89	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	798
Kojto	91:031413cf7a89	799	/* Bits 7..4 : Configuration field for RAM block 1. */
Kojto	91:031413cf7a89	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
Kojto	91:031413cf7a89	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	810
Kojto	91:031413cf7a89	811	/* Bits 3..0 : Configuration field for RAM block 0. */
Kojto	91:031413cf7a89	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
Kojto	91:031413cf7a89	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
Kojto	91:031413cf7a89	822
Kojto	122:f9eeca106725	823
Kojto	91:031413cf7a89	824	/* Peripheral: CCM */
Kojto	91:031413cf7a89	825	/* Description: AES CCM Mode Encryption. */
Kojto	91:031413cf7a89	826
Kojto	91:031413cf7a89	827	/* Register: CCM_SHORTS */
Kojto	97:433970e64889	828	/* Description: Shortcuts for the CCM. */
Kojto	97:433970e64889	829
Kojto	97:433970e64889	830	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
Kojto	91:031413cf7a89	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
Kojto	91:031413cf7a89	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
Kojto	91:031413cf7a89	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	834	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	835
Kojto	91:031413cf7a89	836	/* Register: CCM_INTENSET */
Kojto	91:031413cf7a89	837	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	838
Kojto	91:031413cf7a89	839	/* Bit 2 : Enable interrupt on ERROR event. */
Kojto	91:031413cf7a89	840	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
Kojto	91:031413cf7a89	841	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	91:031413cf7a89	842	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	843	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	844	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	845
Kojto	91:031413cf7a89	846	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
Kojto	91:031413cf7a89	847	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
Kojto	91:031413cf7a89	848	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
Kojto	91:031413cf7a89	849	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	850	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	851	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	852
Kojto	91:031413cf7a89	853	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
Kojto	91:031413cf7a89	854	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
Kojto	91:031413cf7a89	855	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
Kojto	91:031413cf7a89	856	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	857	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	858	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	859
Kojto	91:031413cf7a89	860	/* Register: CCM_INTENCLR */
Kojto	91:031413cf7a89	861	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	862
Kojto	91:031413cf7a89	863	/* Bit 2 : Disable interrupt on ERROR event. */
Kojto	91:031413cf7a89	864	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
Kojto	91:031413cf7a89	865	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	91:031413cf7a89	866	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	867	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	868	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	869
Kojto	91:031413cf7a89	870	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
Kojto	91:031413cf7a89	871	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
Kojto	91:031413cf7a89	872	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
Kojto	91:031413cf7a89	873	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	874	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	875	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	876
Kojto	91:031413cf7a89	877	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
Kojto	91:031413cf7a89	878	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
Kojto	91:031413cf7a89	879	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
Kojto	91:031413cf7a89	880	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	881	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	882	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	883
Kojto	91:031413cf7a89	884	/* Register: CCM_MICSTATUS */
Kojto	91:031413cf7a89	885	/* Description: CCM RX MIC check result. */
Kojto	91:031413cf7a89	886
Kojto	91:031413cf7a89	887	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
Kojto	91:031413cf7a89	888	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
Kojto	91:031413cf7a89	889	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
Kojto	91:031413cf7a89	890	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
Kojto	91:031413cf7a89	891	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
Kojto	91:031413cf7a89	892
Kojto	91:031413cf7a89	893	/* Register: CCM_ENABLE */
Kojto	91:031413cf7a89	894	/* Description: CCM enable. */
Kojto	91:031413cf7a89	895
Kojto	91:031413cf7a89	896	/* Bits 1..0 : CCM enable. */
Kojto	91:031413cf7a89	897	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	898	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	899	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
Kojto	91:031413cf7a89	900	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
Kojto	91:031413cf7a89	901
Kojto	91:031413cf7a89	902	/* Register: CCM_MODE */
Kojto	91:031413cf7a89	903	/* Description: Operation mode. */
Kojto	91:031413cf7a89	904
Kojto	91:031413cf7a89	905	/* Bit 0 : CCM mode operation. */
Kojto	91:031413cf7a89	906	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
Kojto	91:031413cf7a89	907	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
Kojto	91:031413cf7a89	908	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
Kojto	91:031413cf7a89	909	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
Kojto	91:031413cf7a89	910
Kojto	91:031413cf7a89	911	/* Register: CCM_POWER */
Kojto	91:031413cf7a89	912	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	913
Kojto	91:031413cf7a89	914	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	915	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	916	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	917	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	918	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	919
Kojto	91:031413cf7a89	920
Kojto	91:031413cf7a89	921	/* Peripheral: CLOCK */
Kojto	91:031413cf7a89	922	/* Description: Clock control. */
Kojto	91:031413cf7a89	923
Kojto	91:031413cf7a89	924	/* Register: CLOCK_INTENSET */
Kojto	91:031413cf7a89	925	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	926
Kojto	91:031413cf7a89	927	/* Bit 4 : Enable interrupt on CTTO event. */
Kojto	91:031413cf7a89	928	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
Kojto	91:031413cf7a89	929	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
Kojto	91:031413cf7a89	930	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	931	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	932	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	933
Kojto	91:031413cf7a89	934	/* Bit 3 : Enable interrupt on DONE event. */
Kojto	91:031413cf7a89	935	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
Kojto	91:031413cf7a89	936	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
Kojto	91:031413cf7a89	937	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	938	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	939	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	940
Kojto	91:031413cf7a89	941	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
Kojto	91:031413cf7a89	942	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
Kojto	91:031413cf7a89	943	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
Kojto	91:031413cf7a89	944	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	945	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	946	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	947
Kojto	91:031413cf7a89	948	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
Kojto	91:031413cf7a89	949	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
Kojto	91:031413cf7a89	950	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
Kojto	91:031413cf7a89	951	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	952	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	953	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	954
Kojto	91:031413cf7a89	955	/* Register: CLOCK_INTENCLR */
Kojto	91:031413cf7a89	956	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	957
Kojto	91:031413cf7a89	958	/* Bit 4 : Disable interrupt on CTTO event. */
Kojto	91:031413cf7a89	959	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
Kojto	91:031413cf7a89	960	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
Kojto	91:031413cf7a89	961	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	962	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	963	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	964
Kojto	91:031413cf7a89	965	/* Bit 3 : Disable interrupt on DONE event. */
Kojto	91:031413cf7a89	966	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
Kojto	91:031413cf7a89	967	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
Kojto	91:031413cf7a89	968	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	969	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	970	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	971
Kojto	91:031413cf7a89	972	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
Kojto	91:031413cf7a89	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
Kojto	91:031413cf7a89	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
Kojto	91:031413cf7a89	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	977	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	978
Kojto	91:031413cf7a89	979	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
Kojto	91:031413cf7a89	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
Kojto	91:031413cf7a89	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
Kojto	91:031413cf7a89	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	984	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	985
Kojto	97:433970e64889	986	/* Register: CLOCK_HFCLKRUN */
Kojto	97:433970e64889	987	/* Description: Task HFCLKSTART trigger status. */
Kojto	97:433970e64889	988
Kojto	97:433970e64889	989	/* Bit 0 : Task HFCLKSTART trigger status. */
Kojto	97:433970e64889	990	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	97:433970e64889	991	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	97:433970e64889	992	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
Kojto	97:433970e64889	993	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
Kojto	97:433970e64889	994
Kojto	91:031413cf7a89	995	/* Register: CLOCK_HFCLKSTAT */
Kojto	91:031413cf7a89	996	/* Description: High frequency clock status. */
Kojto	91:031413cf7a89	997
Kojto	91:031413cf7a89	998	/* Bit 16 : State for the HFCLK. */
Kojto	91:031413cf7a89	999	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
Kojto	91:031413cf7a89	1000	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
Kojto	91:031413cf7a89	1001	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
Kojto	91:031413cf7a89	1002	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
Kojto	91:031413cf7a89	1003
Kojto	91:031413cf7a89	1004	/* Bit 0 : Active clock source for the HF clock. */
Kojto	91:031413cf7a89	1005	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	91:031413cf7a89	1006	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	91:031413cf7a89	1007	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
Kojto	91:031413cf7a89	1008	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
Kojto	91:031413cf7a89	1009
Kojto	97:433970e64889	1010	/* Register: CLOCK_LFCLKRUN */
Kojto	97:433970e64889	1011	/* Description: Task LFCLKSTART triggered status. */
Kojto	97:433970e64889	1012
Kojto	97:433970e64889	1013	/* Bit 0 : Task LFCLKSTART triggered status. */
Kojto	97:433970e64889	1014	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	97:433970e64889	1015	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	97:433970e64889	1016	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
Kojto	97:433970e64889	1017	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
Kojto	97:433970e64889	1018
Kojto	91:031413cf7a89	1019	/* Register: CLOCK_LFCLKSTAT */
Kojto	91:031413cf7a89	1020	/* Description: Low frequency clock status. */
Kojto	91:031413cf7a89	1021
Kojto	91:031413cf7a89	1022	/* Bit 16 : State for the LF clock. */
Kojto	91:031413cf7a89	1023	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
Kojto	91:031413cf7a89	1024	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
Kojto	91:031413cf7a89	1025	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
Kojto	91:031413cf7a89	1026	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
Kojto	91:031413cf7a89	1027
Kojto	91:031413cf7a89	1028	/* Bits 1..0 : Active clock source for the LF clock. */
Kojto	91:031413cf7a89	1029	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	91:031413cf7a89	1030	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	91:031413cf7a89	1031	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
Kojto	91:031413cf7a89	1032	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
Kojto	91:031413cf7a89	1033	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
Kojto	91:031413cf7a89	1034
Kojto	97:433970e64889	1035	/* Register: CLOCK_LFCLKSRCCOPY */
Kojto	97:433970e64889	1036	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto	97:433970e64889	1037
Kojto	97:433970e64889	1038	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto	97:433970e64889	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	97:433970e64889	1040	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	97:433970e64889	1041	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
Kojto	97:433970e64889	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
Kojto	97:433970e64889	1043	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
Kojto	97:433970e64889	1044
Kojto	91:031413cf7a89	1045	/* Register: CLOCK_LFCLKSRC */
Kojto	91:031413cf7a89	1046	/* Description: Clock source for the LFCLK clock. */
Kojto	91:031413cf7a89	1047
Kojto	91:031413cf7a89	1048	/* Bits 1..0 : Clock source. */
Kojto	91:031413cf7a89	1049	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	91:031413cf7a89	1050	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	91:031413cf7a89	1051	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
Kojto	91:031413cf7a89	1052	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
Kojto	91:031413cf7a89	1053	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
Kojto	91:031413cf7a89	1054
Kojto	91:031413cf7a89	1055	/* Register: CLOCK_CTIV */
Kojto	91:031413cf7a89	1056	/* Description: Calibration timer interval. */
Kojto	91:031413cf7a89	1057
Kojto	91:031413cf7a89	1058	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
Kojto	91:031413cf7a89	1059	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
Kojto	91:031413cf7a89	1060	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
Kojto	91:031413cf7a89	1061
Kojto	91:031413cf7a89	1062	/* Register: CLOCK_XTALFREQ */
Kojto	91:031413cf7a89	1063	/* Description: Crystal frequency. */
Kojto	91:031413cf7a89	1064
Kojto	91:031413cf7a89	1065	/* Bits 7..0 : External Xtal frequency selection. */
Kojto	91:031413cf7a89	1066	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
Kojto	91:031413cf7a89	1067	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
Kojto	122:f9eeca106725	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
Kojto	97:433970e64889	1069	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
Kojto	91:031413cf7a89	1070
Kojto	91:031413cf7a89	1071
Kojto	91:031413cf7a89	1072	/* Peripheral: ECB */
Kojto	91:031413cf7a89	1073	/* Description: AES ECB Mode Encryption. */
Kojto	91:031413cf7a89	1074
Kojto	91:031413cf7a89	1075	/* Register: ECB_INTENSET */
Kojto	91:031413cf7a89	1076	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	1077
Kojto	91:031413cf7a89	1078	/* Bit 1 : Enable interrupt on ERRORECB event. */
Kojto	91:031413cf7a89	1079	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
Kojto	91:031413cf7a89	1080	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
Kojto	91:031413cf7a89	1081	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	1082	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	1083	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	1084
Kojto	91:031413cf7a89	1085	/* Bit 0 : Enable interrupt on ENDECB event. */
Kojto	91:031413cf7a89	1086	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
Kojto	91:031413cf7a89	1087	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
Kojto	91:031413cf7a89	1088	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	1089	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	1090	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	1091
Kojto	91:031413cf7a89	1092	/* Register: ECB_INTENCLR */
Kojto	91:031413cf7a89	1093	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	1094
Kojto	91:031413cf7a89	1095	/* Bit 1 : Disable interrupt on ERRORECB event. */
Kojto	91:031413cf7a89	1096	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
Kojto	91:031413cf7a89	1097	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
Kojto	91:031413cf7a89	1098	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	1099	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	1100	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	1101
Kojto	91:031413cf7a89	1102	/* Bit 0 : Disable interrupt on ENDECB event. */
Kojto	91:031413cf7a89	1103	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
Kojto	91:031413cf7a89	1104	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
Kojto	91:031413cf7a89	1105	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	1106	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	1107	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	1108
Kojto	91:031413cf7a89	1109	/* Register: ECB_POWER */
Kojto	91:031413cf7a89	1110	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	1111
Kojto	91:031413cf7a89	1112	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	1113	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	1114	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	1115	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	1116	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	1117
Kojto	91:031413cf7a89	1118
Kojto	91:031413cf7a89	1119	/* Peripheral: FICR */
Kojto	91:031413cf7a89	1120	/* Description: Factory Information Configuration. */
Kojto	91:031413cf7a89	1121
Kojto	91:031413cf7a89	1122	/* Register: FICR_PPFC */
Kojto	91:031413cf7a89	1123	/* Description: Pre-programmed factory code present. */
Kojto	91:031413cf7a89	1124
Kojto	91:031413cf7a89	1125	/* Bits 7..0 : Pre-programmed factory code present. */
Kojto	91:031413cf7a89	1126	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
Kojto	91:031413cf7a89	1127	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
Kojto	122:f9eeca106725	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
Kojto	91:031413cf7a89	1129	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
Kojto	91:031413cf7a89	1130
Kojto	91:031413cf7a89	1131	/* Register: FICR_CONFIGID */
Kojto	91:031413cf7a89	1132	/* Description: Configuration identifier. */
Kojto	91:031413cf7a89	1133
Kojto	91:031413cf7a89	1134	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
Kojto	91:031413cf7a89	1135	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
Kojto	91:031413cf7a89	1136	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
Kojto	91:031413cf7a89	1137
Kojto	91:031413cf7a89	1138	/* Bits 15..0 : Hardware Identification Number. */
Kojto	91:031413cf7a89	1139	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
Kojto	91:031413cf7a89	1140	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
Kojto	91:031413cf7a89	1141
Kojto	91:031413cf7a89	1142	/* Register: FICR_DEVICEADDRTYPE */
Kojto	91:031413cf7a89	1143	/* Description: Device address type. */
Kojto	91:031413cf7a89	1144
Kojto	91:031413cf7a89	1145	/* Bit 0 : Device address type. */
Kojto	91:031413cf7a89	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
Kojto	91:031413cf7a89	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
Kojto	91:031413cf7a89	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
Kojto	91:031413cf7a89	1149	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
Kojto	91:031413cf7a89	1150
Kojto	91:031413cf7a89	1151	/* Register: FICR_OVERRIDEEN */
Kojto	91:031413cf7a89	1152	/* Description: Radio calibration override enable. */
Kojto	91:031413cf7a89	1153
Kojto	91:031413cf7a89	1154	/* Bit 3 : Override default values for BLE_1Mbit mode. */
Kojto	91:031413cf7a89	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
Kojto	91:031413cf7a89	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
Kojto	91:031413cf7a89	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
Kojto	91:031413cf7a89	1158	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
Kojto	91:031413cf7a89	1159
Kojto	97:433970e64889	1160	/* Bit 0 : Override default values for NRF_1Mbit mode. */
Kojto	97:433970e64889	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
Kojto	97:433970e64889	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
Kojto	97:433970e64889	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
Kojto	97:433970e64889	1164	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
Kojto	97:433970e64889	1165
Kojto	91:031413cf7a89	1166
Kojto	91:031413cf7a89	1167	/* Peripheral: GPIO */
Kojto	91:031413cf7a89	1168	/* Description: General purpose input and output. */
Kojto	91:031413cf7a89	1169
Kojto	91:031413cf7a89	1170	/* Register: GPIO_OUT */
Kojto	91:031413cf7a89	1171	/* Description: Write GPIO port. */
Kojto	91:031413cf7a89	1172
Kojto	91:031413cf7a89	1173	/* Bit 31 : Pin 31. */
Kojto	91:031413cf7a89	1174	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	91:031413cf7a89	1175	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	91:031413cf7a89	1176	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1177	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1178
Kojto	91:031413cf7a89	1179	/* Bit 30 : Pin 30. */
Kojto	91:031413cf7a89	1180	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	91:031413cf7a89	1181	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	91:031413cf7a89	1182	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1183	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1184
Kojto	91:031413cf7a89	1185	/* Bit 29 : Pin 29. */
Kojto	91:031413cf7a89	1186	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	91:031413cf7a89	1187	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	91:031413cf7a89	1188	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1189	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1190
Kojto	91:031413cf7a89	1191	/* Bit 28 : Pin 28. */
Kojto	91:031413cf7a89	1192	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	91:031413cf7a89	1193	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	91:031413cf7a89	1194	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1195	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1196
Kojto	91:031413cf7a89	1197	/* Bit 27 : Pin 27. */
Kojto	91:031413cf7a89	1198	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	91:031413cf7a89	1199	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	91:031413cf7a89	1200	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1201	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1202
Kojto	91:031413cf7a89	1203	/* Bit 26 : Pin 26. */
Kojto	91:031413cf7a89	1204	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	91:031413cf7a89	1205	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	91:031413cf7a89	1206	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1207	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1208
Kojto	91:031413cf7a89	1209	/* Bit 25 : Pin 25. */
Kojto	91:031413cf7a89	1210	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	91:031413cf7a89	1211	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	91:031413cf7a89	1212	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1213	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1214
Kojto	91:031413cf7a89	1215	/* Bit 24 : Pin 24. */
Kojto	91:031413cf7a89	1216	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	91:031413cf7a89	1217	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	91:031413cf7a89	1218	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1219	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1220
Kojto	91:031413cf7a89	1221	/* Bit 23 : Pin 23. */
Kojto	91:031413cf7a89	1222	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	91:031413cf7a89	1223	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	91:031413cf7a89	1224	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1225	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1226
Kojto	91:031413cf7a89	1227	/* Bit 22 : Pin 22. */
Kojto	91:031413cf7a89	1228	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	91:031413cf7a89	1229	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	91:031413cf7a89	1230	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1231	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1232
Kojto	91:031413cf7a89	1233	/* Bit 21 : Pin 21. */
Kojto	91:031413cf7a89	1234	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	91:031413cf7a89	1235	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	91:031413cf7a89	1236	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1237	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1238
Kojto	91:031413cf7a89	1239	/* Bit 20 : Pin 20. */
Kojto	91:031413cf7a89	1240	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	91:031413cf7a89	1241	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	91:031413cf7a89	1242	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1243	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1244
Kojto	91:031413cf7a89	1245	/* Bit 19 : Pin 19. */
Kojto	91:031413cf7a89	1246	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	91:031413cf7a89	1247	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	91:031413cf7a89	1248	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1249	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1250
Kojto	91:031413cf7a89	1251	/* Bit 18 : Pin 18. */
Kojto	91:031413cf7a89	1252	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	91:031413cf7a89	1253	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	91:031413cf7a89	1254	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1255	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1256
Kojto	91:031413cf7a89	1257	/* Bit 17 : Pin 17. */
Kojto	91:031413cf7a89	1258	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	91:031413cf7a89	1259	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	91:031413cf7a89	1260	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1261	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1262
Kojto	91:031413cf7a89	1263	/* Bit 16 : Pin 16. */
Kojto	91:031413cf7a89	1264	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	91:031413cf7a89	1265	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	91:031413cf7a89	1266	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1267	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1268
Kojto	91:031413cf7a89	1269	/* Bit 15 : Pin 15. */
Kojto	91:031413cf7a89	1270	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	91:031413cf7a89	1271	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	91:031413cf7a89	1272	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1273	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1274
Kojto	91:031413cf7a89	1275	/* Bit 14 : Pin 14. */
Kojto	91:031413cf7a89	1276	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	91:031413cf7a89	1277	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	91:031413cf7a89	1278	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1279	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1280
Kojto	91:031413cf7a89	1281	/* Bit 13 : Pin 13. */
Kojto	91:031413cf7a89	1282	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	91:031413cf7a89	1283	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	91:031413cf7a89	1284	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1285	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1286
Kojto	91:031413cf7a89	1287	/* Bit 12 : Pin 12. */
Kojto	91:031413cf7a89	1288	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	91:031413cf7a89	1289	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	91:031413cf7a89	1290	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1291	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1292
Kojto	91:031413cf7a89	1293	/* Bit 11 : Pin 11. */
Kojto	91:031413cf7a89	1294	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	91:031413cf7a89	1295	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	91:031413cf7a89	1296	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1297	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1298
Kojto	91:031413cf7a89	1299	/* Bit 10 : Pin 10. */
Kojto	91:031413cf7a89	1300	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	91:031413cf7a89	1301	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	91:031413cf7a89	1302	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1303	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1304
Kojto	91:031413cf7a89	1305	/* Bit 9 : Pin 9. */
Kojto	91:031413cf7a89	1306	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	91:031413cf7a89	1307	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	91:031413cf7a89	1308	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1309	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1310
Kojto	91:031413cf7a89	1311	/* Bit 8 : Pin 8. */
Kojto	91:031413cf7a89	1312	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	91:031413cf7a89	1313	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	91:031413cf7a89	1314	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1315	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1316
Kojto	91:031413cf7a89	1317	/* Bit 7 : Pin 7. */
Kojto	91:031413cf7a89	1318	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	91:031413cf7a89	1319	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	91:031413cf7a89	1320	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1321	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1322
Kojto	91:031413cf7a89	1323	/* Bit 6 : Pin 6. */
Kojto	91:031413cf7a89	1324	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	91:031413cf7a89	1325	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	91:031413cf7a89	1326	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1327	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1328
Kojto	91:031413cf7a89	1329	/* Bit 5 : Pin 5. */
Kojto	91:031413cf7a89	1330	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	91:031413cf7a89	1331	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	91:031413cf7a89	1332	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1333	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1334
Kojto	91:031413cf7a89	1335	/* Bit 4 : Pin 4. */
Kojto	91:031413cf7a89	1336	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	91:031413cf7a89	1337	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	91:031413cf7a89	1338	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1339	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1340
Kojto	91:031413cf7a89	1341	/* Bit 3 : Pin 3. */
Kojto	91:031413cf7a89	1342	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	91:031413cf7a89	1343	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	91:031413cf7a89	1344	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1345	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1346
Kojto	91:031413cf7a89	1347	/* Bit 2 : Pin 2. */
Kojto	91:031413cf7a89	1348	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	91:031413cf7a89	1349	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	91:031413cf7a89	1350	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1351	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1352
Kojto	91:031413cf7a89	1353	/* Bit 1 : Pin 1. */
Kojto	91:031413cf7a89	1354	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	91:031413cf7a89	1355	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	91:031413cf7a89	1356	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1357	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1358
Kojto	91:031413cf7a89	1359	/* Bit 0 : Pin 0. */
Kojto	91:031413cf7a89	1360	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	91:031413cf7a89	1361	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	91:031413cf7a89	1362	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1363	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1364
Kojto	91:031413cf7a89	1365	/* Register: GPIO_OUTSET */
Kojto	91:031413cf7a89	1366	/* Description: Set individual bits in GPIO port. */
Kojto	91:031413cf7a89	1367
Kojto	91:031413cf7a89	1368	/* Bit 31 : Pin 31. */
Kojto	91:031413cf7a89	1369	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	91:031413cf7a89	1370	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	91:031413cf7a89	1371	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1372	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1373	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1374
Kojto	91:031413cf7a89	1375	/* Bit 30 : Pin 30. */
Kojto	91:031413cf7a89	1376	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	91:031413cf7a89	1377	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	91:031413cf7a89	1378	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1379	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1380	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1381
Kojto	91:031413cf7a89	1382	/* Bit 29 : Pin 29. */
Kojto	91:031413cf7a89	1383	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	91:031413cf7a89	1384	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	91:031413cf7a89	1385	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1386	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1387	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1388
Kojto	91:031413cf7a89	1389	/* Bit 28 : Pin 28. */
Kojto	91:031413cf7a89	1390	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	91:031413cf7a89	1391	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	91:031413cf7a89	1392	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1393	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1394	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1395
Kojto	91:031413cf7a89	1396	/* Bit 27 : Pin 27. */
Kojto	91:031413cf7a89	1397	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	91:031413cf7a89	1398	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	91:031413cf7a89	1399	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1400	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1401	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1402
Kojto	91:031413cf7a89	1403	/* Bit 26 : Pin 26. */
Kojto	91:031413cf7a89	1404	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	91:031413cf7a89	1405	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	91:031413cf7a89	1406	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1407	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1408	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1409
Kojto	91:031413cf7a89	1410	/* Bit 25 : Pin 25. */
Kojto	91:031413cf7a89	1411	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	91:031413cf7a89	1412	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	91:031413cf7a89	1413	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1414	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1415	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1416
Kojto	91:031413cf7a89	1417	/* Bit 24 : Pin 24. */
Kojto	91:031413cf7a89	1418	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	91:031413cf7a89	1419	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	91:031413cf7a89	1420	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1421	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1422	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1423
Kojto	91:031413cf7a89	1424	/* Bit 23 : Pin 23. */
Kojto	91:031413cf7a89	1425	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	91:031413cf7a89	1426	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	91:031413cf7a89	1427	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1428	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1429	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1430
Kojto	91:031413cf7a89	1431	/* Bit 22 : Pin 22. */
Kojto	91:031413cf7a89	1432	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	91:031413cf7a89	1433	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	91:031413cf7a89	1434	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1435	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1436	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1437
Kojto	91:031413cf7a89	1438	/* Bit 21 : Pin 21. */
Kojto	91:031413cf7a89	1439	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	91:031413cf7a89	1440	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	91:031413cf7a89	1441	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1442	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1443	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1444
Kojto	91:031413cf7a89	1445	/* Bit 20 : Pin 20. */
Kojto	91:031413cf7a89	1446	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	91:031413cf7a89	1447	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	91:031413cf7a89	1448	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1449	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1450	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1451
Kojto	91:031413cf7a89	1452	/* Bit 19 : Pin 19. */
Kojto	91:031413cf7a89	1453	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	91:031413cf7a89	1454	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	91:031413cf7a89	1455	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1456	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1457	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1458
Kojto	91:031413cf7a89	1459	/* Bit 18 : Pin 18. */
Kojto	91:031413cf7a89	1460	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	91:031413cf7a89	1461	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	91:031413cf7a89	1462	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1463	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1464	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1465
Kojto	91:031413cf7a89	1466	/* Bit 17 : Pin 17. */
Kojto	91:031413cf7a89	1467	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	91:031413cf7a89	1468	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	91:031413cf7a89	1469	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1470	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1471	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1472
Kojto	91:031413cf7a89	1473	/* Bit 16 : Pin 16. */
Kojto	91:031413cf7a89	1474	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	91:031413cf7a89	1475	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	91:031413cf7a89	1476	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1477	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1478	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1479
Kojto	91:031413cf7a89	1480	/* Bit 15 : Pin 15. */
Kojto	91:031413cf7a89	1481	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	91:031413cf7a89	1482	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	91:031413cf7a89	1483	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1484	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1485	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1486
Kojto	91:031413cf7a89	1487	/* Bit 14 : Pin 14. */
Kojto	91:031413cf7a89	1488	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	91:031413cf7a89	1489	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	91:031413cf7a89	1490	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1491	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1492	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1493
Kojto	91:031413cf7a89	1494	/* Bit 13 : Pin 13. */
Kojto	91:031413cf7a89	1495	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	91:031413cf7a89	1496	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	91:031413cf7a89	1497	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1498	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1499	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1500
Kojto	91:031413cf7a89	1501	/* Bit 12 : Pin 12. */
Kojto	91:031413cf7a89	1502	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	91:031413cf7a89	1503	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	91:031413cf7a89	1504	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1505	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1506	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1507
Kojto	91:031413cf7a89	1508	/* Bit 11 : Pin 11. */
Kojto	91:031413cf7a89	1509	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	91:031413cf7a89	1510	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	91:031413cf7a89	1511	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1512	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1513	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1514
Kojto	91:031413cf7a89	1515	/* Bit 10 : Pin 10. */
Kojto	91:031413cf7a89	1516	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	91:031413cf7a89	1517	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	91:031413cf7a89	1518	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1519	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1520	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1521
Kojto	91:031413cf7a89	1522	/* Bit 9 : Pin 9. */
Kojto	91:031413cf7a89	1523	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	91:031413cf7a89	1524	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	91:031413cf7a89	1525	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1526	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1527	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1528
Kojto	91:031413cf7a89	1529	/* Bit 8 : Pin 8. */
Kojto	91:031413cf7a89	1530	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	91:031413cf7a89	1531	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	91:031413cf7a89	1532	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1533	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1534	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1535
Kojto	91:031413cf7a89	1536	/* Bit 7 : Pin 7. */
Kojto	91:031413cf7a89	1537	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	91:031413cf7a89	1538	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	91:031413cf7a89	1539	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1540	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1541	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1542
Kojto	91:031413cf7a89	1543	/* Bit 6 : Pin 6. */
Kojto	91:031413cf7a89	1544	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	91:031413cf7a89	1545	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	91:031413cf7a89	1546	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1547	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1548	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1549
Kojto	91:031413cf7a89	1550	/* Bit 5 : Pin 5. */
Kojto	91:031413cf7a89	1551	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	91:031413cf7a89	1552	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	91:031413cf7a89	1553	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1554	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1555	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1556
Kojto	91:031413cf7a89	1557	/* Bit 4 : Pin 4. */
Kojto	91:031413cf7a89	1558	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	91:031413cf7a89	1559	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	91:031413cf7a89	1560	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1561	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1562	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1563
Kojto	91:031413cf7a89	1564	/* Bit 3 : Pin 3. */
Kojto	91:031413cf7a89	1565	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	91:031413cf7a89	1566	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	91:031413cf7a89	1567	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1568	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1569	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1570
Kojto	91:031413cf7a89	1571	/* Bit 2 : Pin 2. */
Kojto	91:031413cf7a89	1572	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	91:031413cf7a89	1573	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	91:031413cf7a89	1574	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1575	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1576	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1577
Kojto	91:031413cf7a89	1578	/* Bit 1 : Pin 1. */
Kojto	91:031413cf7a89	1579	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	91:031413cf7a89	1580	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	91:031413cf7a89	1581	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1582	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1583	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1584
Kojto	91:031413cf7a89	1585	/* Bit 0 : Pin 0. */
Kojto	91:031413cf7a89	1586	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	91:031413cf7a89	1587	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	91:031413cf7a89	1588	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1589	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1590	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
Kojto	91:031413cf7a89	1591
Kojto	91:031413cf7a89	1592	/* Register: GPIO_OUTCLR */
Kojto	91:031413cf7a89	1593	/* Description: Clear individual bits in GPIO port. */
Kojto	91:031413cf7a89	1594
Kojto	91:031413cf7a89	1595	/* Bit 31 : Pin 31. */
Kojto	91:031413cf7a89	1596	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	91:031413cf7a89	1597	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	91:031413cf7a89	1598	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1599	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1600	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1601
Kojto	91:031413cf7a89	1602	/* Bit 30 : Pin 30. */
Kojto	91:031413cf7a89	1603	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	91:031413cf7a89	1604	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	91:031413cf7a89	1605	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1606	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1607	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1608
Kojto	91:031413cf7a89	1609	/* Bit 29 : Pin 29. */
Kojto	91:031413cf7a89	1610	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	91:031413cf7a89	1611	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	91:031413cf7a89	1612	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1613	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1614	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1615
Kojto	91:031413cf7a89	1616	/* Bit 28 : Pin 28. */
Kojto	91:031413cf7a89	1617	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	91:031413cf7a89	1618	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	91:031413cf7a89	1619	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1620	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1621	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1622
Kojto	91:031413cf7a89	1623	/* Bit 27 : Pin 27. */
Kojto	91:031413cf7a89	1624	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	91:031413cf7a89	1625	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	91:031413cf7a89	1626	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1627	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1628	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1629
Kojto	91:031413cf7a89	1630	/* Bit 26 : Pin 26. */
Kojto	91:031413cf7a89	1631	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	91:031413cf7a89	1632	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	91:031413cf7a89	1633	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1634	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1635	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1636
Kojto	91:031413cf7a89	1637	/* Bit 25 : Pin 25. */
Kojto	91:031413cf7a89	1638	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	91:031413cf7a89	1639	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	91:031413cf7a89	1640	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1641	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1642	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1643
Kojto	91:031413cf7a89	1644	/* Bit 24 : Pin 24. */
Kojto	91:031413cf7a89	1645	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	91:031413cf7a89	1646	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	91:031413cf7a89	1647	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1648	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1649	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1650
Kojto	91:031413cf7a89	1651	/* Bit 23 : Pin 23. */
Kojto	91:031413cf7a89	1652	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	91:031413cf7a89	1653	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	91:031413cf7a89	1654	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1655	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1656	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1657
Kojto	91:031413cf7a89	1658	/* Bit 22 : Pin 22. */
Kojto	91:031413cf7a89	1659	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	91:031413cf7a89	1660	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	91:031413cf7a89	1661	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1662	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1663	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1664
Kojto	91:031413cf7a89	1665	/* Bit 21 : Pin 21. */
Kojto	91:031413cf7a89	1666	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	91:031413cf7a89	1667	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	91:031413cf7a89	1668	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1669	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1670	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1671
Kojto	91:031413cf7a89	1672	/* Bit 20 : Pin 20. */
Kojto	91:031413cf7a89	1673	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	91:031413cf7a89	1674	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	91:031413cf7a89	1675	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1676	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1677	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1678
Kojto	91:031413cf7a89	1679	/* Bit 19 : Pin 19. */
Kojto	91:031413cf7a89	1680	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	91:031413cf7a89	1681	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	91:031413cf7a89	1682	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1683	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1684	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1685
Kojto	91:031413cf7a89	1686	/* Bit 18 : Pin 18. */
Kojto	91:031413cf7a89	1687	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	91:031413cf7a89	1688	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	91:031413cf7a89	1689	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1690	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1691	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1692
Kojto	91:031413cf7a89	1693	/* Bit 17 : Pin 17. */
Kojto	91:031413cf7a89	1694	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	91:031413cf7a89	1695	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	91:031413cf7a89	1696	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1697	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1698	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1699
Kojto	91:031413cf7a89	1700	/* Bit 16 : Pin 16. */
Kojto	91:031413cf7a89	1701	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	91:031413cf7a89	1702	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	91:031413cf7a89	1703	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1704	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1705	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1706
Kojto	91:031413cf7a89	1707	/* Bit 15 : Pin 15. */
Kojto	91:031413cf7a89	1708	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	91:031413cf7a89	1709	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	91:031413cf7a89	1710	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1711	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1712	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1713
Kojto	91:031413cf7a89	1714	/* Bit 14 : Pin 14. */
Kojto	91:031413cf7a89	1715	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	91:031413cf7a89	1716	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	91:031413cf7a89	1717	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1718	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1719	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1720
Kojto	91:031413cf7a89	1721	/* Bit 13 : Pin 13. */
Kojto	91:031413cf7a89	1722	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	91:031413cf7a89	1723	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	91:031413cf7a89	1724	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1725	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1726	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1727
Kojto	91:031413cf7a89	1728	/* Bit 12 : Pin 12. */
Kojto	91:031413cf7a89	1729	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	91:031413cf7a89	1730	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	91:031413cf7a89	1731	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1732	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1733	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1734
Kojto	91:031413cf7a89	1735	/* Bit 11 : Pin 11. */
Kojto	91:031413cf7a89	1736	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	91:031413cf7a89	1737	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	91:031413cf7a89	1738	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1739	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1740	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1741
Kojto	91:031413cf7a89	1742	/* Bit 10 : Pin 10. */
Kojto	91:031413cf7a89	1743	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	91:031413cf7a89	1744	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	91:031413cf7a89	1745	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1746	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1747	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1748
Kojto	91:031413cf7a89	1749	/* Bit 9 : Pin 9. */
Kojto	91:031413cf7a89	1750	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	91:031413cf7a89	1751	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	91:031413cf7a89	1752	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1753	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1754	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1755
Kojto	91:031413cf7a89	1756	/* Bit 8 : Pin 8. */
Kojto	91:031413cf7a89	1757	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	91:031413cf7a89	1758	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	91:031413cf7a89	1759	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1760	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1761	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1762
Kojto	91:031413cf7a89	1763	/* Bit 7 : Pin 7. */
Kojto	91:031413cf7a89	1764	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	91:031413cf7a89	1765	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	91:031413cf7a89	1766	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1767	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1768	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1769
Kojto	91:031413cf7a89	1770	/* Bit 6 : Pin 6. */
Kojto	91:031413cf7a89	1771	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	91:031413cf7a89	1772	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	91:031413cf7a89	1773	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1774	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1775	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1776
Kojto	91:031413cf7a89	1777	/* Bit 5 : Pin 5. */
Kojto	91:031413cf7a89	1778	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	91:031413cf7a89	1779	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	91:031413cf7a89	1780	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1781	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1782	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1783
Kojto	91:031413cf7a89	1784	/* Bit 4 : Pin 4. */
Kojto	91:031413cf7a89	1785	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	91:031413cf7a89	1786	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	91:031413cf7a89	1787	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1788	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1789	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1790
Kojto	91:031413cf7a89	1791	/* Bit 3 : Pin 3. */
Kojto	91:031413cf7a89	1792	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	91:031413cf7a89	1793	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	91:031413cf7a89	1794	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1795	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1796	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1797
Kojto	91:031413cf7a89	1798	/* Bit 2 : Pin 2. */
Kojto	91:031413cf7a89	1799	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	91:031413cf7a89	1800	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	91:031413cf7a89	1801	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1802	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1803	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1804
Kojto	91:031413cf7a89	1805	/* Bit 1 : Pin 1. */
Kojto	91:031413cf7a89	1806	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	91:031413cf7a89	1807	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	91:031413cf7a89	1808	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1809	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1810	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1811
Kojto	91:031413cf7a89	1812	/* Bit 0 : Pin 0. */
Kojto	91:031413cf7a89	1813	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	91:031413cf7a89	1814	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	91:031413cf7a89	1815	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
Kojto	91:031413cf7a89	1816	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
Kojto	91:031413cf7a89	1817	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
Kojto	91:031413cf7a89	1818
Kojto	91:031413cf7a89	1819	/* Register: GPIO_IN */
Kojto	91:031413cf7a89	1820	/* Description: Read GPIO port. */
Kojto	91:031413cf7a89	1821
Kojto	91:031413cf7a89	1822	/* Bit 31 : Pin 31. */
Kojto	91:031413cf7a89	1823	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	91:031413cf7a89	1824	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	91:031413cf7a89	1825	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1826	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1827
Kojto	91:031413cf7a89	1828	/* Bit 30 : Pin 30. */
Kojto	91:031413cf7a89	1829	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	91:031413cf7a89	1830	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	91:031413cf7a89	1831	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1832	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1833
Kojto	91:031413cf7a89	1834	/* Bit 29 : Pin 29. */
Kojto	91:031413cf7a89	1835	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	91:031413cf7a89	1836	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	91:031413cf7a89	1837	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1838	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1839
Kojto	91:031413cf7a89	1840	/* Bit 28 : Pin 28. */
Kojto	91:031413cf7a89	1841	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	91:031413cf7a89	1842	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	91:031413cf7a89	1843	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1844	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1845
Kojto	91:031413cf7a89	1846	/* Bit 27 : Pin 27. */
Kojto	91:031413cf7a89	1847	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	91:031413cf7a89	1848	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	91:031413cf7a89	1849	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1850	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1851
Kojto	91:031413cf7a89	1852	/* Bit 26 : Pin 26. */
Kojto	91:031413cf7a89	1853	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	91:031413cf7a89	1854	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	91:031413cf7a89	1855	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1856	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1857
Kojto	91:031413cf7a89	1858	/* Bit 25 : Pin 25. */
Kojto	91:031413cf7a89	1859	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	91:031413cf7a89	1860	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	91:031413cf7a89	1861	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1862	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1863
Kojto	91:031413cf7a89	1864	/* Bit 24 : Pin 24. */
Kojto	91:031413cf7a89	1865	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	91:031413cf7a89	1866	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	91:031413cf7a89	1867	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1868	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1869
Kojto	91:031413cf7a89	1870	/* Bit 23 : Pin 23. */
Kojto	91:031413cf7a89	1871	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	91:031413cf7a89	1872	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	91:031413cf7a89	1873	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1874	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1875
Kojto	91:031413cf7a89	1876	/* Bit 22 : Pin 22. */
Kojto	91:031413cf7a89	1877	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	91:031413cf7a89	1878	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	91:031413cf7a89	1879	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1880	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1881
Kojto	91:031413cf7a89	1882	/* Bit 21 : Pin 21. */
Kojto	91:031413cf7a89	1883	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	91:031413cf7a89	1884	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	91:031413cf7a89	1885	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1886	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1887
Kojto	91:031413cf7a89	1888	/* Bit 20 : Pin 20. */
Kojto	91:031413cf7a89	1889	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	91:031413cf7a89	1890	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	91:031413cf7a89	1891	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1892	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1893
Kojto	91:031413cf7a89	1894	/* Bit 19 : Pin 19. */
Kojto	91:031413cf7a89	1895	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	91:031413cf7a89	1896	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	91:031413cf7a89	1897	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1898	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1899
Kojto	91:031413cf7a89	1900	/* Bit 18 : Pin 18. */
Kojto	91:031413cf7a89	1901	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	91:031413cf7a89	1902	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	91:031413cf7a89	1903	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1904	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1905
Kojto	91:031413cf7a89	1906	/* Bit 17 : Pin 17. */
Kojto	91:031413cf7a89	1907	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	91:031413cf7a89	1908	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	91:031413cf7a89	1909	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1910	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1911
Kojto	91:031413cf7a89	1912	/* Bit 16 : Pin 16. */
Kojto	91:031413cf7a89	1913	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	91:031413cf7a89	1914	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	91:031413cf7a89	1915	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1916	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1917
Kojto	91:031413cf7a89	1918	/* Bit 15 : Pin 15. */
Kojto	91:031413cf7a89	1919	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	91:031413cf7a89	1920	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	91:031413cf7a89	1921	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1922	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1923
Kojto	91:031413cf7a89	1924	/* Bit 14 : Pin 14. */
Kojto	91:031413cf7a89	1925	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	91:031413cf7a89	1926	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	91:031413cf7a89	1927	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1928	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1929
Kojto	91:031413cf7a89	1930	/* Bit 13 : Pin 13. */
Kojto	91:031413cf7a89	1931	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	91:031413cf7a89	1932	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	91:031413cf7a89	1933	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1934	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1935
Kojto	91:031413cf7a89	1936	/* Bit 12 : Pin 12. */
Kojto	91:031413cf7a89	1937	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	91:031413cf7a89	1938	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	91:031413cf7a89	1939	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1940	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1941
Kojto	91:031413cf7a89	1942	/* Bit 11 : Pin 11. */
Kojto	91:031413cf7a89	1943	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	91:031413cf7a89	1944	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	91:031413cf7a89	1945	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1946	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1947
Kojto	91:031413cf7a89	1948	/* Bit 10 : Pin 10. */
Kojto	91:031413cf7a89	1949	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	91:031413cf7a89	1950	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	91:031413cf7a89	1951	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1952	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1953
Kojto	91:031413cf7a89	1954	/* Bit 9 : Pin 9. */
Kojto	91:031413cf7a89	1955	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	91:031413cf7a89	1956	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	91:031413cf7a89	1957	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1958	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1959
Kojto	91:031413cf7a89	1960	/* Bit 8 : Pin 8. */
Kojto	91:031413cf7a89	1961	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	91:031413cf7a89	1962	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	91:031413cf7a89	1963	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1964	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1965
Kojto	91:031413cf7a89	1966	/* Bit 7 : Pin 7. */
Kojto	91:031413cf7a89	1967	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	91:031413cf7a89	1968	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	91:031413cf7a89	1969	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1970	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1971
Kojto	91:031413cf7a89	1972	/* Bit 6 : Pin 6. */
Kojto	91:031413cf7a89	1973	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	91:031413cf7a89	1974	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	91:031413cf7a89	1975	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1976	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1977
Kojto	91:031413cf7a89	1978	/* Bit 5 : Pin 5. */
Kojto	91:031413cf7a89	1979	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	91:031413cf7a89	1980	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	91:031413cf7a89	1981	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1982	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1983
Kojto	91:031413cf7a89	1984	/* Bit 4 : Pin 4. */
Kojto	91:031413cf7a89	1985	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	91:031413cf7a89	1986	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	91:031413cf7a89	1987	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1988	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1989
Kojto	91:031413cf7a89	1990	/* Bit 3 : Pin 3. */
Kojto	91:031413cf7a89	1991	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	91:031413cf7a89	1992	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	91:031413cf7a89	1993	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	1994	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	1995
Kojto	91:031413cf7a89	1996	/* Bit 2 : Pin 2. */
Kojto	91:031413cf7a89	1997	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	91:031413cf7a89	1998	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	91:031413cf7a89	1999	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	2000	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	2001
Kojto	91:031413cf7a89	2002	/* Bit 1 : Pin 1. */
Kojto	91:031413cf7a89	2003	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	91:031413cf7a89	2004	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	91:031413cf7a89	2005	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	2006	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	2007
Kojto	91:031413cf7a89	2008	/* Bit 0 : Pin 0. */
Kojto	91:031413cf7a89	2009	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	91:031413cf7a89	2010	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	91:031413cf7a89	2011	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
Kojto	91:031413cf7a89	2012	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
Kojto	91:031413cf7a89	2013
Kojto	91:031413cf7a89	2014	/* Register: GPIO_DIR */
Kojto	91:031413cf7a89	2015	/* Description: Direction of GPIO pins. */
Kojto	91:031413cf7a89	2016
Kojto	91:031413cf7a89	2017	/* Bit 31 : Pin 31. */
Kojto	91:031413cf7a89	2018	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	91:031413cf7a89	2019	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	91:031413cf7a89	2020	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2021	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2022
Kojto	91:031413cf7a89	2023	/* Bit 30 : Pin 30. */
Kojto	91:031413cf7a89	2024	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	91:031413cf7a89	2025	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	91:031413cf7a89	2026	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2027	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2028
Kojto	91:031413cf7a89	2029	/* Bit 29 : Pin 29. */
Kojto	91:031413cf7a89	2030	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	91:031413cf7a89	2031	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	91:031413cf7a89	2032	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2033	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2034
Kojto	91:031413cf7a89	2035	/* Bit 28 : Pin 28. */
Kojto	91:031413cf7a89	2036	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	91:031413cf7a89	2037	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	91:031413cf7a89	2038	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2039	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2040
Kojto	91:031413cf7a89	2041	/* Bit 27 : Pin 27. */
Kojto	91:031413cf7a89	2042	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	91:031413cf7a89	2043	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	91:031413cf7a89	2044	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2045	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2046
Kojto	91:031413cf7a89	2047	/* Bit 26 : Pin 26. */
Kojto	91:031413cf7a89	2048	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	91:031413cf7a89	2049	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	91:031413cf7a89	2050	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2051	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2052
Kojto	91:031413cf7a89	2053	/* Bit 25 : Pin 25. */
Kojto	91:031413cf7a89	2054	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	91:031413cf7a89	2055	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	91:031413cf7a89	2056	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2057	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2058
Kojto	91:031413cf7a89	2059	/* Bit 24 : Pin 24. */
Kojto	91:031413cf7a89	2060	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	91:031413cf7a89	2061	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	91:031413cf7a89	2062	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2063	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2064
Kojto	91:031413cf7a89	2065	/* Bit 23 : Pin 23. */
Kojto	91:031413cf7a89	2066	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	91:031413cf7a89	2067	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	91:031413cf7a89	2068	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2069	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2070
Kojto	91:031413cf7a89	2071	/* Bit 22 : Pin 22. */
Kojto	91:031413cf7a89	2072	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	91:031413cf7a89	2073	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	91:031413cf7a89	2074	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2075	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2076
Kojto	91:031413cf7a89	2077	/* Bit 21 : Pin 21. */
Kojto	91:031413cf7a89	2078	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	91:031413cf7a89	2079	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	91:031413cf7a89	2080	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2081	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2082
Kojto	91:031413cf7a89	2083	/* Bit 20 : Pin 20. */
Kojto	91:031413cf7a89	2084	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	91:031413cf7a89	2085	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	91:031413cf7a89	2086	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2087	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2088
Kojto	91:031413cf7a89	2089	/* Bit 19 : Pin 19. */
Kojto	91:031413cf7a89	2090	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	91:031413cf7a89	2091	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	91:031413cf7a89	2092	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2093	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2094
Kojto	91:031413cf7a89	2095	/* Bit 18 : Pin 18. */
Kojto	91:031413cf7a89	2096	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	91:031413cf7a89	2097	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	91:031413cf7a89	2098	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2099	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2100
Kojto	91:031413cf7a89	2101	/* Bit 17 : Pin 17. */
Kojto	91:031413cf7a89	2102	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	91:031413cf7a89	2103	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	91:031413cf7a89	2104	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2105	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2106
Kojto	91:031413cf7a89	2107	/* Bit 16 : Pin 16. */
Kojto	91:031413cf7a89	2108	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	91:031413cf7a89	2109	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	91:031413cf7a89	2110	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2111	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2112
Kojto	91:031413cf7a89	2113	/* Bit 15 : Pin 15. */
Kojto	91:031413cf7a89	2114	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	91:031413cf7a89	2115	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	91:031413cf7a89	2116	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2117	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2118
Kojto	91:031413cf7a89	2119	/* Bit 14 : Pin 14. */
Kojto	91:031413cf7a89	2120	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	91:031413cf7a89	2121	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	91:031413cf7a89	2122	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2123	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2124
Kojto	91:031413cf7a89	2125	/* Bit 13 : Pin 13. */
Kojto	91:031413cf7a89	2126	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	91:031413cf7a89	2127	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	91:031413cf7a89	2128	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2129	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2130
Kojto	91:031413cf7a89	2131	/* Bit 12 : Pin 12. */
Kojto	91:031413cf7a89	2132	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	91:031413cf7a89	2133	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	91:031413cf7a89	2134	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2135	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2136
Kojto	91:031413cf7a89	2137	/* Bit 11 : Pin 11. */
Kojto	91:031413cf7a89	2138	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	91:031413cf7a89	2139	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	91:031413cf7a89	2140	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2141	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2142
Kojto	91:031413cf7a89	2143	/* Bit 10 : Pin 10. */
Kojto	91:031413cf7a89	2144	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	91:031413cf7a89	2145	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	91:031413cf7a89	2146	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2147	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2148
Kojto	91:031413cf7a89	2149	/* Bit 9 : Pin 9. */
Kojto	91:031413cf7a89	2150	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	91:031413cf7a89	2151	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	91:031413cf7a89	2152	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2153	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2154
Kojto	91:031413cf7a89	2155	/* Bit 8 : Pin 8. */
Kojto	91:031413cf7a89	2156	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	91:031413cf7a89	2157	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	91:031413cf7a89	2158	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2159	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2160
Kojto	91:031413cf7a89	2161	/* Bit 7 : Pin 7. */
Kojto	91:031413cf7a89	2162	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	91:031413cf7a89	2163	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	91:031413cf7a89	2164	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2165	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2166
Kojto	91:031413cf7a89	2167	/* Bit 6 : Pin 6. */
Kojto	91:031413cf7a89	2168	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	91:031413cf7a89	2169	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	91:031413cf7a89	2170	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2171	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2172
Kojto	91:031413cf7a89	2173	/* Bit 5 : Pin 5. */
Kojto	91:031413cf7a89	2174	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	91:031413cf7a89	2175	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	91:031413cf7a89	2176	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2177	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2178
Kojto	91:031413cf7a89	2179	/* Bit 4 : Pin 4. */
Kojto	91:031413cf7a89	2180	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	91:031413cf7a89	2181	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	91:031413cf7a89	2182	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2183	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2184
Kojto	91:031413cf7a89	2185	/* Bit 3 : Pin 3. */
Kojto	91:031413cf7a89	2186	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	91:031413cf7a89	2187	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	91:031413cf7a89	2188	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2189	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2190
Kojto	91:031413cf7a89	2191	/* Bit 2 : Pin 2. */
Kojto	91:031413cf7a89	2192	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	91:031413cf7a89	2193	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	91:031413cf7a89	2194	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2195	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2196
Kojto	91:031413cf7a89	2197	/* Bit 1 : Pin 1. */
Kojto	91:031413cf7a89	2198	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	91:031413cf7a89	2199	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	91:031413cf7a89	2200	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2201	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2202
Kojto	91:031413cf7a89	2203	/* Bit 0 : Pin 0. */
Kojto	91:031413cf7a89	2204	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	91:031413cf7a89	2205	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	91:031413cf7a89	2206	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2207	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2208
Kojto	91:031413cf7a89	2209	/* Register: GPIO_DIRSET */
Kojto	91:031413cf7a89	2210	/* Description: DIR set register. */
Kojto	91:031413cf7a89	2211
Kojto	91:031413cf7a89	2212	/* Bit 31 : Set as output pin 31. */
Kojto	91:031413cf7a89	2213	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	91:031413cf7a89	2214	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	91:031413cf7a89	2215	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2216	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2217	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2218
Kojto	91:031413cf7a89	2219	/* Bit 30 : Set as output pin 30. */
Kojto	91:031413cf7a89	2220	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	91:031413cf7a89	2221	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	91:031413cf7a89	2222	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2223	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2224	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2225
Kojto	91:031413cf7a89	2226	/* Bit 29 : Set as output pin 29. */
Kojto	91:031413cf7a89	2227	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	91:031413cf7a89	2228	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	91:031413cf7a89	2229	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2230	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2231	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2232
Kojto	91:031413cf7a89	2233	/* Bit 28 : Set as output pin 28. */
Kojto	91:031413cf7a89	2234	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	91:031413cf7a89	2235	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	91:031413cf7a89	2236	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2237	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2238	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2239
Kojto	91:031413cf7a89	2240	/* Bit 27 : Set as output pin 27. */
Kojto	91:031413cf7a89	2241	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	91:031413cf7a89	2242	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	91:031413cf7a89	2243	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2244	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2245	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2246
Kojto	91:031413cf7a89	2247	/* Bit 26 : Set as output pin 26. */
Kojto	91:031413cf7a89	2248	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	91:031413cf7a89	2249	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	91:031413cf7a89	2250	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2251	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2252	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2253
Kojto	91:031413cf7a89	2254	/* Bit 25 : Set as output pin 25. */
Kojto	91:031413cf7a89	2255	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	91:031413cf7a89	2256	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	91:031413cf7a89	2257	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2258	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2259	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2260
Kojto	91:031413cf7a89	2261	/* Bit 24 : Set as output pin 24. */
Kojto	91:031413cf7a89	2262	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	91:031413cf7a89	2263	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	91:031413cf7a89	2264	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2265	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2266	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2267
Kojto	91:031413cf7a89	2268	/* Bit 23 : Set as output pin 23. */
Kojto	91:031413cf7a89	2269	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	91:031413cf7a89	2270	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	91:031413cf7a89	2271	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2272	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2273	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2274
Kojto	91:031413cf7a89	2275	/* Bit 22 : Set as output pin 22. */
Kojto	91:031413cf7a89	2276	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	91:031413cf7a89	2277	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	91:031413cf7a89	2278	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2279	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2280	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2281
Kojto	91:031413cf7a89	2282	/* Bit 21 : Set as output pin 21. */
Kojto	91:031413cf7a89	2283	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	91:031413cf7a89	2284	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	91:031413cf7a89	2285	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2286	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2287	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2288
Kojto	91:031413cf7a89	2289	/* Bit 20 : Set as output pin 20. */
Kojto	91:031413cf7a89	2290	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	91:031413cf7a89	2291	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	91:031413cf7a89	2292	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2293	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2294	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2295
Kojto	91:031413cf7a89	2296	/* Bit 19 : Set as output pin 19. */
Kojto	91:031413cf7a89	2297	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	91:031413cf7a89	2298	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	91:031413cf7a89	2299	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2300	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2301	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2302
Kojto	91:031413cf7a89	2303	/* Bit 18 : Set as output pin 18. */
Kojto	91:031413cf7a89	2304	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	91:031413cf7a89	2305	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	91:031413cf7a89	2306	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2307	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2308	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2309
Kojto	91:031413cf7a89	2310	/* Bit 17 : Set as output pin 17. */
Kojto	91:031413cf7a89	2311	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	91:031413cf7a89	2312	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	91:031413cf7a89	2313	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2314	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2315	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2316
Kojto	91:031413cf7a89	2317	/* Bit 16 : Set as output pin 16. */
Kojto	91:031413cf7a89	2318	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	91:031413cf7a89	2319	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	91:031413cf7a89	2320	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2321	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2322	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2323
Kojto	91:031413cf7a89	2324	/* Bit 15 : Set as output pin 15. */
Kojto	91:031413cf7a89	2325	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	91:031413cf7a89	2326	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	91:031413cf7a89	2327	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2328	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2329	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2330
Kojto	91:031413cf7a89	2331	/* Bit 14 : Set as output pin 14. */
Kojto	91:031413cf7a89	2332	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	91:031413cf7a89	2333	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	91:031413cf7a89	2334	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2335	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2336	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2337
Kojto	91:031413cf7a89	2338	/* Bit 13 : Set as output pin 13. */
Kojto	91:031413cf7a89	2339	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	91:031413cf7a89	2340	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	91:031413cf7a89	2341	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2342	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2343	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2344
Kojto	91:031413cf7a89	2345	/* Bit 12 : Set as output pin 12. */
Kojto	91:031413cf7a89	2346	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	91:031413cf7a89	2347	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	91:031413cf7a89	2348	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2349	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2350	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2351
Kojto	91:031413cf7a89	2352	/* Bit 11 : Set as output pin 11. */
Kojto	91:031413cf7a89	2353	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	91:031413cf7a89	2354	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	91:031413cf7a89	2355	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2356	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2357	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2358
Kojto	91:031413cf7a89	2359	/* Bit 10 : Set as output pin 10. */
Kojto	91:031413cf7a89	2360	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	91:031413cf7a89	2361	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	91:031413cf7a89	2362	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2363	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2364	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2365
Kojto	91:031413cf7a89	2366	/* Bit 9 : Set as output pin 9. */
Kojto	91:031413cf7a89	2367	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	91:031413cf7a89	2368	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	91:031413cf7a89	2369	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2370	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2371	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2372
Kojto	91:031413cf7a89	2373	/* Bit 8 : Set as output pin 8. */
Kojto	91:031413cf7a89	2374	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	91:031413cf7a89	2375	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	91:031413cf7a89	2376	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2377	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2378	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2379
Kojto	91:031413cf7a89	2380	/* Bit 7 : Set as output pin 7. */
Kojto	91:031413cf7a89	2381	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	91:031413cf7a89	2382	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	91:031413cf7a89	2383	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2384	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2385	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2386
Kojto	91:031413cf7a89	2387	/* Bit 6 : Set as output pin 6. */
Kojto	91:031413cf7a89	2388	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	91:031413cf7a89	2389	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	91:031413cf7a89	2390	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2391	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2392	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2393
Kojto	91:031413cf7a89	2394	/* Bit 5 : Set as output pin 5. */
Kojto	91:031413cf7a89	2395	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	91:031413cf7a89	2396	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	91:031413cf7a89	2397	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2398	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2399	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2400
Kojto	91:031413cf7a89	2401	/* Bit 4 : Set as output pin 4. */
Kojto	91:031413cf7a89	2402	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	91:031413cf7a89	2403	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	91:031413cf7a89	2404	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2405	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2406	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2407
Kojto	91:031413cf7a89	2408	/* Bit 3 : Set as output pin 3. */
Kojto	91:031413cf7a89	2409	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	91:031413cf7a89	2410	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	91:031413cf7a89	2411	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2412	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2413	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2414
Kojto	91:031413cf7a89	2415	/* Bit 2 : Set as output pin 2. */
Kojto	91:031413cf7a89	2416	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	91:031413cf7a89	2417	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	91:031413cf7a89	2418	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2419	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2420	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2421
Kojto	91:031413cf7a89	2422	/* Bit 1 : Set as output pin 1. */
Kojto	91:031413cf7a89	2423	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	91:031413cf7a89	2424	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	91:031413cf7a89	2425	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2426	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2427	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2428
Kojto	91:031413cf7a89	2429	/* Bit 0 : Set as output pin 0. */
Kojto	91:031413cf7a89	2430	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	91:031413cf7a89	2431	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	91:031413cf7a89	2432	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2433	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2434	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
Kojto	91:031413cf7a89	2435
Kojto	91:031413cf7a89	2436	/* Register: GPIO_DIRCLR */
Kojto	91:031413cf7a89	2437	/* Description: DIR clear register. */
Kojto	91:031413cf7a89	2438
Kojto	91:031413cf7a89	2439	/* Bit 31 : Set as input pin 31. */
Kojto	91:031413cf7a89	2440	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
Kojto	91:031413cf7a89	2441	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
Kojto	91:031413cf7a89	2442	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2443	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2444	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2445
Kojto	91:031413cf7a89	2446	/* Bit 30 : Set as input pin 30. */
Kojto	91:031413cf7a89	2447	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
Kojto	91:031413cf7a89	2448	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
Kojto	91:031413cf7a89	2449	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2450	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2451	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2452
Kojto	91:031413cf7a89	2453	/* Bit 29 : Set as input pin 29. */
Kojto	91:031413cf7a89	2454	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
Kojto	91:031413cf7a89	2455	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
Kojto	91:031413cf7a89	2456	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2457	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2458	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2459
Kojto	91:031413cf7a89	2460	/* Bit 28 : Set as input pin 28. */
Kojto	91:031413cf7a89	2461	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
Kojto	91:031413cf7a89	2462	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
Kojto	91:031413cf7a89	2463	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2464	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2465	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2466
Kojto	91:031413cf7a89	2467	/* Bit 27 : Set as input pin 27. */
Kojto	91:031413cf7a89	2468	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
Kojto	91:031413cf7a89	2469	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
Kojto	91:031413cf7a89	2470	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2471	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2472	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2473
Kojto	91:031413cf7a89	2474	/* Bit 26 : Set as input pin 26. */
Kojto	91:031413cf7a89	2475	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
Kojto	91:031413cf7a89	2476	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
Kojto	91:031413cf7a89	2477	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2478	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2479	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2480
Kojto	91:031413cf7a89	2481	/* Bit 25 : Set as input pin 25. */
Kojto	91:031413cf7a89	2482	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
Kojto	91:031413cf7a89	2483	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
Kojto	91:031413cf7a89	2484	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2485	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2486	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2487
Kojto	91:031413cf7a89	2488	/* Bit 24 : Set as input pin 24. */
Kojto	91:031413cf7a89	2489	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
Kojto	91:031413cf7a89	2490	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
Kojto	91:031413cf7a89	2491	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2492	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2493	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2494
Kojto	91:031413cf7a89	2495	/* Bit 23 : Set as input pin 23. */
Kojto	91:031413cf7a89	2496	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
Kojto	91:031413cf7a89	2497	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
Kojto	91:031413cf7a89	2498	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2499	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2500	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2501
Kojto	91:031413cf7a89	2502	/* Bit 22 : Set as input pin 22. */
Kojto	91:031413cf7a89	2503	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
Kojto	91:031413cf7a89	2504	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
Kojto	91:031413cf7a89	2505	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2506	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2507	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2508
Kojto	91:031413cf7a89	2509	/* Bit 21 : Set as input pin 21. */
Kojto	91:031413cf7a89	2510	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
Kojto	91:031413cf7a89	2511	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
Kojto	91:031413cf7a89	2512	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2513	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2514	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2515
Kojto	91:031413cf7a89	2516	/* Bit 20 : Set as input pin 20. */
Kojto	91:031413cf7a89	2517	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
Kojto	91:031413cf7a89	2518	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
Kojto	91:031413cf7a89	2519	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2520	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2521	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2522
Kojto	91:031413cf7a89	2523	/* Bit 19 : Set as input pin 19. */
Kojto	91:031413cf7a89	2524	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
Kojto	91:031413cf7a89	2525	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
Kojto	91:031413cf7a89	2526	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2527	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2528	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2529
Kojto	91:031413cf7a89	2530	/* Bit 18 : Set as input pin 18. */
Kojto	91:031413cf7a89	2531	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
Kojto	91:031413cf7a89	2532	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
Kojto	91:031413cf7a89	2533	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2534	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2535	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2536
Kojto	91:031413cf7a89	2537	/* Bit 17 : Set as input pin 17. */
Kojto	91:031413cf7a89	2538	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
Kojto	91:031413cf7a89	2539	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
Kojto	91:031413cf7a89	2540	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2541	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2542	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2543
Kojto	91:031413cf7a89	2544	/* Bit 16 : Set as input pin 16. */
Kojto	91:031413cf7a89	2545	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
Kojto	91:031413cf7a89	2546	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
Kojto	91:031413cf7a89	2547	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2548	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2549	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2550
Kojto	91:031413cf7a89	2551	/* Bit 15 : Set as input pin 15. */
Kojto	91:031413cf7a89	2552	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
Kojto	91:031413cf7a89	2553	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
Kojto	91:031413cf7a89	2554	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2555	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2556	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2557
Kojto	91:031413cf7a89	2558	/* Bit 14 : Set as input pin 14. */
Kojto	91:031413cf7a89	2559	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
Kojto	91:031413cf7a89	2560	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
Kojto	91:031413cf7a89	2561	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2562	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2563	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2564
Kojto	91:031413cf7a89	2565	/* Bit 13 : Set as input pin 13. */
Kojto	91:031413cf7a89	2566	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
Kojto	91:031413cf7a89	2567	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
Kojto	91:031413cf7a89	2568	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2569	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2570	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2571
Kojto	91:031413cf7a89	2572	/* Bit 12 : Set as input pin 12. */
Kojto	91:031413cf7a89	2573	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
Kojto	91:031413cf7a89	2574	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
Kojto	91:031413cf7a89	2575	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2576	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2577	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2578
Kojto	91:031413cf7a89	2579	/* Bit 11 : Set as input pin 11. */
Kojto	91:031413cf7a89	2580	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
Kojto	91:031413cf7a89	2581	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
Kojto	91:031413cf7a89	2582	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2583	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2584	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2585
Kojto	91:031413cf7a89	2586	/* Bit 10 : Set as input pin 10. */
Kojto	91:031413cf7a89	2587	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
Kojto	91:031413cf7a89	2588	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
Kojto	91:031413cf7a89	2589	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2590	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2591	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2592
Kojto	91:031413cf7a89	2593	/* Bit 9 : Set as input pin 9. */
Kojto	91:031413cf7a89	2594	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
Kojto	91:031413cf7a89	2595	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
Kojto	91:031413cf7a89	2596	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2597	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2598	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2599
Kojto	91:031413cf7a89	2600	/* Bit 8 : Set as input pin 8. */
Kojto	91:031413cf7a89	2601	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
Kojto	91:031413cf7a89	2602	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
Kojto	91:031413cf7a89	2603	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2604	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2605	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2606
Kojto	91:031413cf7a89	2607	/* Bit 7 : Set as input pin 7. */
Kojto	91:031413cf7a89	2608	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
Kojto	91:031413cf7a89	2609	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
Kojto	91:031413cf7a89	2610	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2611	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2612	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2613
Kojto	91:031413cf7a89	2614	/* Bit 6 : Set as input pin 6. */
Kojto	91:031413cf7a89	2615	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
Kojto	91:031413cf7a89	2616	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
Kojto	91:031413cf7a89	2617	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2618	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2619	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2620
Kojto	91:031413cf7a89	2621	/* Bit 5 : Set as input pin 5. */
Kojto	91:031413cf7a89	2622	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
Kojto	91:031413cf7a89	2623	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
Kojto	91:031413cf7a89	2624	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2625	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2626	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2627
Kojto	91:031413cf7a89	2628	/* Bit 4 : Set as input pin 4. */
Kojto	91:031413cf7a89	2629	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
Kojto	91:031413cf7a89	2630	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
Kojto	91:031413cf7a89	2631	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2632	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2633	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2634
Kojto	91:031413cf7a89	2635	/* Bit 3 : Set as input pin 3. */
Kojto	91:031413cf7a89	2636	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
Kojto	91:031413cf7a89	2637	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
Kojto	91:031413cf7a89	2638	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2639	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2640	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2641
Kojto	91:031413cf7a89	2642	/* Bit 2 : Set as input pin 2. */
Kojto	91:031413cf7a89	2643	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
Kojto	91:031413cf7a89	2644	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
Kojto	91:031413cf7a89	2645	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2646	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2647	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2648
Kojto	91:031413cf7a89	2649	/* Bit 1 : Set as input pin 1. */
Kojto	91:031413cf7a89	2650	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
Kojto	91:031413cf7a89	2651	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
Kojto	91:031413cf7a89	2652	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2653	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2654	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2655
Kojto	91:031413cf7a89	2656	/* Bit 0 : Set as input pin 0. */
Kojto	91:031413cf7a89	2657	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
Kojto	91:031413cf7a89	2658	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
Kojto	91:031413cf7a89	2659	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
Kojto	91:031413cf7a89	2660	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
Kojto	91:031413cf7a89	2661	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
Kojto	91:031413cf7a89	2662
Kojto	91:031413cf7a89	2663	/* Register: GPIO_PIN_CNF */
Kojto	91:031413cf7a89	2664	/* Description: Configuration of GPIO pins. */
Kojto	91:031413cf7a89	2665
Kojto	91:031413cf7a89	2666	/* Bits 17..16 : Pin sensing mechanism. */
Kojto	91:031413cf7a89	2667	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
Kojto	91:031413cf7a89	2668	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
Kojto	91:031413cf7a89	2669	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
Kojto	91:031413cf7a89	2670	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
Kojto	91:031413cf7a89	2671	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
Kojto	91:031413cf7a89	2672
Kojto	91:031413cf7a89	2673	/* Bits 10..8 : Drive configuration. */
Kojto	91:031413cf7a89	2674	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
Kojto	91:031413cf7a89	2675	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
Kojto	91:031413cf7a89	2676	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
Kojto	91:031413cf7a89	2677	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
Kojto	91:031413cf7a89	2678	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
Kojto	91:031413cf7a89	2679	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
Kojto	91:031413cf7a89	2680	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
Kojto	91:031413cf7a89	2681	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
Kojto	91:031413cf7a89	2682	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
Kojto	91:031413cf7a89	2683	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
Kojto	91:031413cf7a89	2684
Kojto	91:031413cf7a89	2685	/* Bits 3..2 : Pull-up or -down configuration. */
Kojto	91:031413cf7a89	2686	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
Kojto	91:031413cf7a89	2687	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
Kojto	91:031413cf7a89	2688	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
Kojto	91:031413cf7a89	2689	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
Kojto	91:031413cf7a89	2690	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
Kojto	91:031413cf7a89	2691
Kojto	91:031413cf7a89	2692	/* Bit 1 : Connect or disconnect input path. */
Kojto	91:031413cf7a89	2693	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
Kojto	91:031413cf7a89	2694	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
Kojto	91:031413cf7a89	2695	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
Kojto	91:031413cf7a89	2696	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
Kojto	91:031413cf7a89	2697
Kojto	91:031413cf7a89	2698	/* Bit 0 : Pin direction. */
Kojto	91:031413cf7a89	2699	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
Kojto	91:031413cf7a89	2700	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
Kojto	91:031413cf7a89	2701	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
Kojto	91:031413cf7a89	2702	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
Kojto	91:031413cf7a89	2703
Kojto	91:031413cf7a89	2704
Kojto	91:031413cf7a89	2705	/* Peripheral: GPIOTE */
Kojto	91:031413cf7a89	2706	/* Description: GPIO tasks and events. */
Kojto	91:031413cf7a89	2707
Kojto	91:031413cf7a89	2708	/* Register: GPIOTE_INTENSET */
Kojto	91:031413cf7a89	2709	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	2710
Kojto	91:031413cf7a89	2711	/* Bit 31 : Enable interrupt on PORT event. */
Kojto	91:031413cf7a89	2712	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
Kojto	91:031413cf7a89	2713	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
Kojto	91:031413cf7a89	2714	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2715	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2716	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2717
Kojto	91:031413cf7a89	2718	/* Bit 3 : Enable interrupt on IN[3] event. */
Kojto	91:031413cf7a89	2719	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
Kojto	91:031413cf7a89	2720	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
Kojto	91:031413cf7a89	2721	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2722	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2723	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2724
Kojto	91:031413cf7a89	2725	/* Bit 2 : Enable interrupt on IN[2] event. */
Kojto	91:031413cf7a89	2726	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
Kojto	91:031413cf7a89	2727	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
Kojto	91:031413cf7a89	2728	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2729	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2730	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2731
Kojto	91:031413cf7a89	2732	/* Bit 1 : Enable interrupt on IN[1] event. */
Kojto	91:031413cf7a89	2733	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
Kojto	91:031413cf7a89	2734	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
Kojto	91:031413cf7a89	2735	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2736	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2737	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2738
Kojto	91:031413cf7a89	2739	/* Bit 0 : Enable interrupt on IN[0] event. */
Kojto	91:031413cf7a89	2740	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
Kojto	91:031413cf7a89	2741	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
Kojto	91:031413cf7a89	2742	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2743	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2744	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2745
Kojto	91:031413cf7a89	2746	/* Register: GPIOTE_INTENCLR */
Kojto	91:031413cf7a89	2747	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	2748
Kojto	91:031413cf7a89	2749	/* Bit 31 : Disable interrupt on PORT event. */
Kojto	91:031413cf7a89	2750	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
Kojto	91:031413cf7a89	2751	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
Kojto	91:031413cf7a89	2752	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2753	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2754	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2755
Kojto	91:031413cf7a89	2756	/* Bit 3 : Disable interrupt on IN[3] event. */
Kojto	91:031413cf7a89	2757	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
Kojto	91:031413cf7a89	2758	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
Kojto	91:031413cf7a89	2759	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2760	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2761	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2762
Kojto	91:031413cf7a89	2763	/* Bit 2 : Disable interrupt on IN[2] event. */
Kojto	91:031413cf7a89	2764	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
Kojto	91:031413cf7a89	2765	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
Kojto	91:031413cf7a89	2766	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2767	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2768	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2769
Kojto	91:031413cf7a89	2770	/* Bit 1 : Disable interrupt on IN[1] event. */
Kojto	91:031413cf7a89	2771	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
Kojto	91:031413cf7a89	2772	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
Kojto	91:031413cf7a89	2773	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2774	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2775	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2776
Kojto	91:031413cf7a89	2777	/* Bit 0 : Disable interrupt on IN[0] event. */
Kojto	91:031413cf7a89	2778	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
Kojto	91:031413cf7a89	2779	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
Kojto	91:031413cf7a89	2780	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2781	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2782	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2783
Kojto	91:031413cf7a89	2784	/* Register: GPIOTE_CONFIG */
Kojto	91:031413cf7a89	2785	/* Description: Channel configuration registers. */
Kojto	91:031413cf7a89	2786
Kojto	91:031413cf7a89	2787	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
Kojto	91:031413cf7a89	2788	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
Kojto	91:031413cf7a89	2789	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
Kojto	91:031413cf7a89	2790	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
Kojto	91:031413cf7a89	2791	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
Kojto	91:031413cf7a89	2792
Kojto	91:031413cf7a89	2793	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
Kojto	91:031413cf7a89	2794	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
Kojto	91:031413cf7a89	2795	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
Kojto	122:f9eeca106725	2796	#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /!< No task or event. /
Kojto	91:031413cf7a89	2797	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
Kojto	91:031413cf7a89	2798	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
Kojto	91:031413cf7a89	2799	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
Kojto	91:031413cf7a89	2800
Kojto	91:031413cf7a89	2801	/* Bits 12..8 : Pin select. */
Kojto	91:031413cf7a89	2802	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
Kojto	91:031413cf7a89	2803	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
Kojto	91:031413cf7a89	2804
Kojto	91:031413cf7a89	2805	/* Bits 1..0 : Mode */
Kojto	91:031413cf7a89	2806	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
Kojto	91:031413cf7a89	2807	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
Kojto	91:031413cf7a89	2808	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
Kojto	91:031413cf7a89	2809	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
Kojto	91:031413cf7a89	2810	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
Kojto	91:031413cf7a89	2811
Kojto	91:031413cf7a89	2812	/* Register: GPIOTE_POWER */
Kojto	91:031413cf7a89	2813	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	2814
Kojto	91:031413cf7a89	2815	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	2816	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	2817	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	2818	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	2819	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	2820
Kojto	91:031413cf7a89	2821
Kojto	91:031413cf7a89	2822	/* Peripheral: LPCOMP */
Kojto	97:433970e64889	2823	/* Description: Low power comparator. */
Kojto	91:031413cf7a89	2824
Kojto	91:031413cf7a89	2825	/* Register: LPCOMP_SHORTS */
Kojto	97:433970e64889	2826	/* Description: Shortcuts for the LPCOMP. */
Kojto	97:433970e64889	2827
Kojto	97:433970e64889	2828	/* Bit 4 : Shortcut between CROSS event and STOP task. */
Kojto	91:031413cf7a89	2829	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
Kojto	91:031413cf7a89	2830	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
Kojto	91:031413cf7a89	2831	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	2832	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	2833
Kojto	97:433970e64889	2834	/* Bit 3 : Shortcut between UP event and STOP task. */
Kojto	91:031413cf7a89	2835	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
Kojto	91:031413cf7a89	2836	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
Kojto	91:031413cf7a89	2837	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	2838	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	2839
Kojto	97:433970e64889	2840	/* Bit 2 : Shortcut between DOWN event and STOP task. */
Kojto	91:031413cf7a89	2841	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
Kojto	91:031413cf7a89	2842	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
Kojto	91:031413cf7a89	2843	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	2844	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	2845
Kojto	97:433970e64889	2846	/* Bit 1 : Shortcut between RADY event and STOP task. */
Kojto	91:031413cf7a89	2847	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
Kojto	91:031413cf7a89	2848	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
Kojto	91:031413cf7a89	2849	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	2850	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	2851
Kojto	97:433970e64889	2852	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
Kojto	91:031413cf7a89	2853	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
Kojto	91:031413cf7a89	2854	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
Kojto	91:031413cf7a89	2855	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	2856	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	2857
Kojto	91:031413cf7a89	2858	/* Register: LPCOMP_INTENSET */
Kojto	91:031413cf7a89	2859	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	2860
Kojto	91:031413cf7a89	2861	/* Bit 3 : Enable interrupt on CROSS event. */
Kojto	91:031413cf7a89	2862	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
Kojto	91:031413cf7a89	2863	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
Kojto	91:031413cf7a89	2864	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2865	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2866	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2867
Kojto	91:031413cf7a89	2868	/* Bit 2 : Enable interrupt on UP event. */
Kojto	91:031413cf7a89	2869	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
Kojto	91:031413cf7a89	2870	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
Kojto	91:031413cf7a89	2871	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2872	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2873	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2874
Kojto	91:031413cf7a89	2875	/* Bit 1 : Enable interrupt on DOWN event. */
Kojto	91:031413cf7a89	2876	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
Kojto	91:031413cf7a89	2877	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
Kojto	91:031413cf7a89	2878	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2879	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2880	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2881
Kojto	91:031413cf7a89	2882	/* Bit 0 : Enable interrupt on READY event. */
Kojto	91:031413cf7a89	2883	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
Kojto	91:031413cf7a89	2884	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
Kojto	91:031413cf7a89	2885	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2886	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2887	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	2888
Kojto	91:031413cf7a89	2889	/* Register: LPCOMP_INTENCLR */
Kojto	91:031413cf7a89	2890	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	2891
Kojto	91:031413cf7a89	2892	/* Bit 3 : Disable interrupt on CROSS event. */
Kojto	91:031413cf7a89	2893	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
Kojto	91:031413cf7a89	2894	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
Kojto	91:031413cf7a89	2895	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2896	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2897	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2898
Kojto	91:031413cf7a89	2899	/* Bit 2 : Disable interrupt on UP event. */
Kojto	91:031413cf7a89	2900	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
Kojto	91:031413cf7a89	2901	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
Kojto	91:031413cf7a89	2902	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2903	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2904	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2905
Kojto	91:031413cf7a89	2906	/* Bit 1 : Disable interrupt on DOWN event. */
Kojto	91:031413cf7a89	2907	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
Kojto	91:031413cf7a89	2908	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
Kojto	91:031413cf7a89	2909	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2910	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2911	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2912
Kojto	91:031413cf7a89	2913	/* Bit 0 : Disable interrupt on READY event. */
Kojto	91:031413cf7a89	2914	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
Kojto	91:031413cf7a89	2915	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
Kojto	91:031413cf7a89	2916	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	2917	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	2918	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	2919
Kojto	91:031413cf7a89	2920	/* Register: LPCOMP_RESULT */
Kojto	91:031413cf7a89	2921	/* Description: Result of last compare. */
Kojto	91:031413cf7a89	2922
Kojto	91:031413cf7a89	2923	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
Kojto	91:031413cf7a89	2924	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
Kojto	91:031413cf7a89	2925	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
Kojto	91:031413cf7a89	2926	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
Kojto	91:031413cf7a89	2927	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
Kojto	91:031413cf7a89	2928
Kojto	91:031413cf7a89	2929	/* Register: LPCOMP_ENABLE */
Kojto	91:031413cf7a89	2930	/* Description: Enable the LPCOMP. */
Kojto	91:031413cf7a89	2931
Kojto	91:031413cf7a89	2932	/* Bits 1..0 : Enable or disable LPCOMP. */
Kojto	91:031413cf7a89	2933	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	2934	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	2935	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
Kojto	91:031413cf7a89	2936	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
Kojto	91:031413cf7a89	2937
Kojto	91:031413cf7a89	2938	/* Register: LPCOMP_PSEL */
Kojto	91:031413cf7a89	2939	/* Description: Input pin select. */
Kojto	91:031413cf7a89	2940
Kojto	91:031413cf7a89	2941	/* Bits 2..0 : Analog input pin select. */
Kojto	91:031413cf7a89	2942	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
Kojto	91:031413cf7a89	2943	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
Kojto	91:031413cf7a89	2944	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
Kojto	91:031413cf7a89	2945	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
Kojto	91:031413cf7a89	2946	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
Kojto	91:031413cf7a89	2947	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
Kojto	91:031413cf7a89	2948	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
Kojto	91:031413cf7a89	2949	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
Kojto	91:031413cf7a89	2950	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
Kojto	91:031413cf7a89	2951	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
Kojto	91:031413cf7a89	2952
Kojto	91:031413cf7a89	2953	/* Register: LPCOMP_REFSEL */
Kojto	91:031413cf7a89	2954	/* Description: Reference select. */
Kojto	91:031413cf7a89	2955
Kojto	91:031413cf7a89	2956	/* Bits 2..0 : Reference select. */
Kojto	91:031413cf7a89	2957	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
Kojto	91:031413cf7a89	2958	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
Kojto	97:433970e64889	2959	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
Kojto	97:433970e64889	2960	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
Kojto	97:433970e64889	2961	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
Kojto	97:433970e64889	2962	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
Kojto	97:433970e64889	2963	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
Kojto	97:433970e64889	2964	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
Kojto	97:433970e64889	2965	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
Kojto	91:031413cf7a89	2966	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
Kojto	91:031413cf7a89	2967
Kojto	91:031413cf7a89	2968	/* Register: LPCOMP_EXTREFSEL */
Kojto	91:031413cf7a89	2969	/* Description: External reference select. */
Kojto	91:031413cf7a89	2970
Kojto	91:031413cf7a89	2971	/* Bit 0 : External analog reference pin selection. */
Kojto	91:031413cf7a89	2972	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
Kojto	91:031413cf7a89	2973	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
Kojto	91:031413cf7a89	2974	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
Kojto	91:031413cf7a89	2975	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
Kojto	91:031413cf7a89	2976
Kojto	91:031413cf7a89	2977	/* Register: LPCOMP_ANADETECT */
Kojto	91:031413cf7a89	2978	/* Description: Analog detect configuration. */
Kojto	91:031413cf7a89	2979
Kojto	91:031413cf7a89	2980	/* Bits 1..0 : Analog detect configuration. */
Kojto	91:031413cf7a89	2981	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
Kojto	91:031413cf7a89	2982	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
Kojto	91:031413cf7a89	2983	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
Kojto	91:031413cf7a89	2984	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
Kojto	91:031413cf7a89	2985	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
Kojto	91:031413cf7a89	2986
Kojto	91:031413cf7a89	2987	/* Register: LPCOMP_POWER */
Kojto	91:031413cf7a89	2988	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	2989
Kojto	91:031413cf7a89	2990	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	2991	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	2992	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	2993	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	2994	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	2995
Kojto	91:031413cf7a89	2996
Kojto	91:031413cf7a89	2997	/* Peripheral: MPU */
Kojto	91:031413cf7a89	2998	/* Description: Memory Protection Unit. */
Kojto	91:031413cf7a89	2999
Kojto	91:031413cf7a89	3000	/* Register: MPU_PERR0 */
Kojto	91:031413cf7a89	3001	/* Description: Configuration of peripherals in mpu regions. */
Kojto	91:031413cf7a89	3002
Kojto	91:031413cf7a89	3003	/* Bit 31 : PPI region configuration. */
Kojto	91:031413cf7a89	3004	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
Kojto	91:031413cf7a89	3005	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
Kojto	91:031413cf7a89	3006	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3007	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3008
Kojto	91:031413cf7a89	3009	/* Bit 30 : NVMC region configuration. */
Kojto	91:031413cf7a89	3010	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
Kojto	91:031413cf7a89	3011	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
Kojto	91:031413cf7a89	3012	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3013	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3014
Kojto	97:433970e64889	3015	/* Bit 19 : LPCOMP region configuration. */
Kojto	97:433970e64889	3016	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
Kojto	97:433970e64889	3017	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
Kojto	97:433970e64889	3018	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	97:433970e64889	3019	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3020
Kojto	91:031413cf7a89	3021	/* Bit 18 : QDEC region configuration. */
Kojto	91:031413cf7a89	3022	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
Kojto	91:031413cf7a89	3023	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
Kojto	91:031413cf7a89	3024	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3025	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3026
Kojto	91:031413cf7a89	3027	/* Bit 17 : RTC1 region configuration. */
Kojto	91:031413cf7a89	3028	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
Kojto	91:031413cf7a89	3029	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
Kojto	91:031413cf7a89	3030	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3031	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3032
Kojto	91:031413cf7a89	3033	/* Bit 16 : WDT region configuration. */
Kojto	91:031413cf7a89	3034	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
Kojto	91:031413cf7a89	3035	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
Kojto	91:031413cf7a89	3036	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3037	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3038
Kojto	91:031413cf7a89	3039	/* Bit 15 : CCM and AAR region configuration. */
Kojto	91:031413cf7a89	3040	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
Kojto	91:031413cf7a89	3041	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
Kojto	91:031413cf7a89	3042	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3043	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3044
Kojto	91:031413cf7a89	3045	/* Bit 14 : ECB region configuration. */
Kojto	91:031413cf7a89	3046	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
Kojto	91:031413cf7a89	3047	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
Kojto	91:031413cf7a89	3048	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3049	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3050
Kojto	91:031413cf7a89	3051	/* Bit 13 : RNG region configuration. */
Kojto	91:031413cf7a89	3052	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
Kojto	91:031413cf7a89	3053	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
Kojto	91:031413cf7a89	3054	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3055	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3056
Kojto	91:031413cf7a89	3057	/* Bit 12 : TEMP region configuration. */
Kojto	91:031413cf7a89	3058	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
Kojto	91:031413cf7a89	3059	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
Kojto	91:031413cf7a89	3060	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3061	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3062
Kojto	91:031413cf7a89	3063	/* Bit 11 : RTC0 region configuration. */
Kojto	91:031413cf7a89	3064	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
Kojto	91:031413cf7a89	3065	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
Kojto	91:031413cf7a89	3066	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3067	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3068
Kojto	91:031413cf7a89	3069	/* Bit 10 : TIMER2 region configuration. */
Kojto	91:031413cf7a89	3070	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
Kojto	91:031413cf7a89	3071	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
Kojto	91:031413cf7a89	3072	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3073	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3074
Kojto	91:031413cf7a89	3075	/* Bit 9 : TIMER1 region configuration. */
Kojto	91:031413cf7a89	3076	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
Kojto	91:031413cf7a89	3077	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
Kojto	91:031413cf7a89	3078	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3079	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3080
Kojto	91:031413cf7a89	3081	/* Bit 8 : TIMER0 region configuration. */
Kojto	91:031413cf7a89	3082	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
Kojto	91:031413cf7a89	3083	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
Kojto	91:031413cf7a89	3084	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3085	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3086
Kojto	91:031413cf7a89	3087	/* Bit 7 : ADC region configuration. */
Kojto	91:031413cf7a89	3088	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
Kojto	91:031413cf7a89	3089	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
Kojto	91:031413cf7a89	3090	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3091	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3092
Kojto	91:031413cf7a89	3093	/* Bit 6 : GPIOTE region configuration. */
Kojto	91:031413cf7a89	3094	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
Kojto	91:031413cf7a89	3095	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
Kojto	91:031413cf7a89	3096	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3097	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3098
Kojto	91:031413cf7a89	3099	/* Bit 4 : SPI1 and TWI1 region configuration. */
Kojto	91:031413cf7a89	3100	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
Kojto	91:031413cf7a89	3101	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
Kojto	91:031413cf7a89	3102	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3103	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3104
Kojto	91:031413cf7a89	3105	/* Bit 3 : SPI0 and TWI0 region configuration. */
Kojto	91:031413cf7a89	3106	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
Kojto	91:031413cf7a89	3107	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
Kojto	91:031413cf7a89	3108	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3109	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3110
Kojto	91:031413cf7a89	3111	/* Bit 2 : UART0 region configuration. */
Kojto	91:031413cf7a89	3112	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
Kojto	91:031413cf7a89	3113	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
Kojto	91:031413cf7a89	3114	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3115	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3116
Kojto	91:031413cf7a89	3117	/* Bit 1 : RADIO region configuration. */
Kojto	91:031413cf7a89	3118	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
Kojto	91:031413cf7a89	3119	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
Kojto	91:031413cf7a89	3120	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3121	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3122
Kojto	91:031413cf7a89	3123	/* Bit 0 : POWER_CLOCK region configuration. */
Kojto	91:031413cf7a89	3124	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
Kojto	91:031413cf7a89	3125	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
Kojto	91:031413cf7a89	3126	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	91:031413cf7a89	3127	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
Kojto	91:031413cf7a89	3128
Kojto	91:031413cf7a89	3129	/* Register: MPU_PROTENSET0 */
Kojto	97:433970e64889	3130	/* Description: Erase and write protection bit enable set register. */
Kojto	91:031413cf7a89	3131
Kojto	91:031413cf7a89	3132	/* Bit 31 : Protection enable for region 31. */
Kojto	91:031413cf7a89	3133	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
Kojto	91:031413cf7a89	3134	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
Kojto	91:031413cf7a89	3135	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3136	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3137	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3138
Kojto	91:031413cf7a89	3139	/* Bit 30 : Protection enable for region 30. */
Kojto	91:031413cf7a89	3140	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
Kojto	91:031413cf7a89	3141	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
Kojto	91:031413cf7a89	3142	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3143	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3144	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3145
Kojto	91:031413cf7a89	3146	/* Bit 29 : Protection enable for region 29. */
Kojto	91:031413cf7a89	3147	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
Kojto	91:031413cf7a89	3148	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
Kojto	91:031413cf7a89	3149	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3150	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3151	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3152
Kojto	91:031413cf7a89	3153	/* Bit 28 : Protection enable for region 28. */
Kojto	91:031413cf7a89	3154	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
Kojto	91:031413cf7a89	3155	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
Kojto	91:031413cf7a89	3156	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3157	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3158	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3159
Kojto	91:031413cf7a89	3160	/* Bit 27 : Protection enable for region 27. */
Kojto	91:031413cf7a89	3161	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
Kojto	91:031413cf7a89	3162	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
Kojto	91:031413cf7a89	3163	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3164	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3165	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3166
Kojto	91:031413cf7a89	3167	/* Bit 26 : Protection enable for region 26. */
Kojto	91:031413cf7a89	3168	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
Kojto	91:031413cf7a89	3169	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
Kojto	91:031413cf7a89	3170	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3171	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3172	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3173
Kojto	91:031413cf7a89	3174	/* Bit 25 : Protection enable for region 25. */
Kojto	91:031413cf7a89	3175	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
Kojto	91:031413cf7a89	3176	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
Kojto	91:031413cf7a89	3177	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3178	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3179	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3180
Kojto	91:031413cf7a89	3181	/* Bit 24 : Protection enable for region 24. */
Kojto	91:031413cf7a89	3182	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
Kojto	91:031413cf7a89	3183	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
Kojto	91:031413cf7a89	3184	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3185	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3186	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3187
Kojto	91:031413cf7a89	3188	/* Bit 23 : Protection enable for region 23. */
Kojto	91:031413cf7a89	3189	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
Kojto	91:031413cf7a89	3190	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
Kojto	91:031413cf7a89	3191	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3192	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3193	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3194
Kojto	91:031413cf7a89	3195	/* Bit 22 : Protection enable for region 22. */
Kojto	91:031413cf7a89	3196	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
Kojto	91:031413cf7a89	3197	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
Kojto	91:031413cf7a89	3198	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3199	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3200	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3201
Kojto	91:031413cf7a89	3202	/* Bit 21 : Protection enable for region 21. */
Kojto	91:031413cf7a89	3203	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
Kojto	91:031413cf7a89	3204	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
Kojto	91:031413cf7a89	3205	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3206	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3207	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3208
Kojto	91:031413cf7a89	3209	/* Bit 20 : Protection enable for region 20. */
Kojto	91:031413cf7a89	3210	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
Kojto	91:031413cf7a89	3211	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
Kojto	91:031413cf7a89	3212	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3213	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3214	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3215
Kojto	91:031413cf7a89	3216	/* Bit 19 : Protection enable for region 19. */
Kojto	91:031413cf7a89	3217	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
Kojto	91:031413cf7a89	3218	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
Kojto	91:031413cf7a89	3219	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3220	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3221	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3222
Kojto	91:031413cf7a89	3223	/* Bit 18 : Protection enable for region 18. */
Kojto	91:031413cf7a89	3224	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
Kojto	91:031413cf7a89	3225	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
Kojto	91:031413cf7a89	3226	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3227	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3228	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3229
Kojto	91:031413cf7a89	3230	/* Bit 17 : Protection enable for region 17. */
Kojto	91:031413cf7a89	3231	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
Kojto	91:031413cf7a89	3232	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
Kojto	91:031413cf7a89	3233	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3234	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3235	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3236
Kojto	91:031413cf7a89	3237	/* Bit 16 : Protection enable for region 16. */
Kojto	91:031413cf7a89	3238	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
Kojto	91:031413cf7a89	3239	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
Kojto	91:031413cf7a89	3240	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3241	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3242	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3243
Kojto	91:031413cf7a89	3244	/* Bit 15 : Protection enable for region 15. */
Kojto	91:031413cf7a89	3245	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
Kojto	91:031413cf7a89	3246	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
Kojto	91:031413cf7a89	3247	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3248	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3249	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3250
Kojto	91:031413cf7a89	3251	/* Bit 14 : Protection enable for region 14. */
Kojto	91:031413cf7a89	3252	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
Kojto	91:031413cf7a89	3253	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
Kojto	91:031413cf7a89	3254	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3255	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3256	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3257
Kojto	91:031413cf7a89	3258	/* Bit 13 : Protection enable for region 13. */
Kojto	91:031413cf7a89	3259	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
Kojto	91:031413cf7a89	3260	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
Kojto	91:031413cf7a89	3261	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3262	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3263	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3264
Kojto	91:031413cf7a89	3265	/* Bit 12 : Protection enable for region 12. */
Kojto	91:031413cf7a89	3266	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
Kojto	91:031413cf7a89	3267	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
Kojto	91:031413cf7a89	3268	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3269	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3270	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3271
Kojto	91:031413cf7a89	3272	/* Bit 11 : Protection enable for region 11. */
Kojto	91:031413cf7a89	3273	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
Kojto	91:031413cf7a89	3274	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
Kojto	91:031413cf7a89	3275	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3276	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3277	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3278
Kojto	91:031413cf7a89	3279	/* Bit 10 : Protection enable for region 10. */
Kojto	91:031413cf7a89	3280	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
Kojto	91:031413cf7a89	3281	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
Kojto	91:031413cf7a89	3282	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3283	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3284	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3285
Kojto	91:031413cf7a89	3286	/* Bit 9 : Protection enable for region 9. */
Kojto	91:031413cf7a89	3287	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
Kojto	91:031413cf7a89	3288	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
Kojto	91:031413cf7a89	3289	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3290	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3291	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3292
Kojto	91:031413cf7a89	3293	/* Bit 8 : Protection enable for region 8. */
Kojto	91:031413cf7a89	3294	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
Kojto	91:031413cf7a89	3295	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
Kojto	91:031413cf7a89	3296	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3297	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3298	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3299
Kojto	91:031413cf7a89	3300	/* Bit 7 : Protection enable for region 7. */
Kojto	91:031413cf7a89	3301	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
Kojto	91:031413cf7a89	3302	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
Kojto	91:031413cf7a89	3303	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3304	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3305	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3306
Kojto	91:031413cf7a89	3307	/* Bit 6 : Protection enable for region 6. */
Kojto	91:031413cf7a89	3308	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
Kojto	91:031413cf7a89	3309	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
Kojto	91:031413cf7a89	3310	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3311	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3312	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3313
Kojto	91:031413cf7a89	3314	/* Bit 5 : Protection enable for region 5. */
Kojto	91:031413cf7a89	3315	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
Kojto	91:031413cf7a89	3316	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
Kojto	91:031413cf7a89	3317	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3318	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3319	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3320
Kojto	91:031413cf7a89	3321	/* Bit 4 : Protection enable for region 4. */
Kojto	91:031413cf7a89	3322	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
Kojto	91:031413cf7a89	3323	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
Kojto	91:031413cf7a89	3324	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3325	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3326	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3327
Kojto	91:031413cf7a89	3328	/* Bit 3 : Protection enable for region 3. */
Kojto	91:031413cf7a89	3329	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
Kojto	91:031413cf7a89	3330	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
Kojto	91:031413cf7a89	3331	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3332	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3333	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3334
Kojto	91:031413cf7a89	3335	/* Bit 2 : Protection enable for region 2. */
Kojto	91:031413cf7a89	3336	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
Kojto	91:031413cf7a89	3337	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
Kojto	91:031413cf7a89	3338	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3339	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3340	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3341
Kojto	91:031413cf7a89	3342	/* Bit 1 : Protection enable for region 1. */
Kojto	91:031413cf7a89	3343	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
Kojto	91:031413cf7a89	3344	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
Kojto	91:031413cf7a89	3345	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3346	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3347	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3348
Kojto	91:031413cf7a89	3349	/* Bit 0 : Protection enable for region 0. */
Kojto	91:031413cf7a89	3350	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
Kojto	91:031413cf7a89	3351	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
Kojto	91:031413cf7a89	3352	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3353	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3354	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3355
Kojto	91:031413cf7a89	3356	/* Register: MPU_PROTENSET1 */
Kojto	97:433970e64889	3357	/* Description: Erase and write protection bit enable set register. */
Kojto	91:031413cf7a89	3358
Kojto	91:031413cf7a89	3359	/* Bit 31 : Protection enable for region 63. */
Kojto	91:031413cf7a89	3360	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
Kojto	91:031413cf7a89	3361	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
Kojto	91:031413cf7a89	3362	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3363	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3364	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3365
Kojto	91:031413cf7a89	3366	/* Bit 30 : Protection enable for region 62. */
Kojto	91:031413cf7a89	3367	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
Kojto	91:031413cf7a89	3368	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
Kojto	91:031413cf7a89	3369	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3370	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3371	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3372
Kojto	91:031413cf7a89	3373	/* Bit 29 : Protection enable for region 61. */
Kojto	91:031413cf7a89	3374	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
Kojto	91:031413cf7a89	3375	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
Kojto	91:031413cf7a89	3376	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3377	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3378	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3379
Kojto	91:031413cf7a89	3380	/* Bit 28 : Protection enable for region 60. */
Kojto	91:031413cf7a89	3381	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
Kojto	91:031413cf7a89	3382	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
Kojto	91:031413cf7a89	3383	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3384	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3385	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3386
Kojto	91:031413cf7a89	3387	/* Bit 27 : Protection enable for region 59. */
Kojto	91:031413cf7a89	3388	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
Kojto	91:031413cf7a89	3389	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
Kojto	91:031413cf7a89	3390	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3391	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3392	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3393
Kojto	91:031413cf7a89	3394	/* Bit 26 : Protection enable for region 58. */
Kojto	91:031413cf7a89	3395	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
Kojto	91:031413cf7a89	3396	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
Kojto	91:031413cf7a89	3397	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3398	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3399	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3400
Kojto	91:031413cf7a89	3401	/* Bit 25 : Protection enable for region 57. */
Kojto	91:031413cf7a89	3402	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
Kojto	91:031413cf7a89	3403	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
Kojto	91:031413cf7a89	3404	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3405	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3406	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3407
Kojto	91:031413cf7a89	3408	/* Bit 24 : Protection enable for region 56. */
Kojto	91:031413cf7a89	3409	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
Kojto	91:031413cf7a89	3410	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
Kojto	91:031413cf7a89	3411	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3412	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3413	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3414
Kojto	91:031413cf7a89	3415	/* Bit 23 : Protection enable for region 55. */
Kojto	91:031413cf7a89	3416	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
Kojto	91:031413cf7a89	3417	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
Kojto	91:031413cf7a89	3418	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3419	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3420	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3421
Kojto	91:031413cf7a89	3422	/* Bit 22 : Protection enable for region 54. */
Kojto	91:031413cf7a89	3423	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
Kojto	91:031413cf7a89	3424	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
Kojto	91:031413cf7a89	3425	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3426	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3427	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3428
Kojto	91:031413cf7a89	3429	/* Bit 21 : Protection enable for region 53. */
Kojto	91:031413cf7a89	3430	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
Kojto	91:031413cf7a89	3431	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
Kojto	91:031413cf7a89	3432	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3433	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3434	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3435
Kojto	91:031413cf7a89	3436	/* Bit 20 : Protection enable for region 52. */
Kojto	91:031413cf7a89	3437	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
Kojto	91:031413cf7a89	3438	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
Kojto	91:031413cf7a89	3439	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3440	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3441	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3442
Kojto	91:031413cf7a89	3443	/* Bit 19 : Protection enable for region 51. */
Kojto	91:031413cf7a89	3444	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
Kojto	91:031413cf7a89	3445	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
Kojto	91:031413cf7a89	3446	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3447	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3448	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3449
Kojto	91:031413cf7a89	3450	/* Bit 18 : Protection enable for region 50. */
Kojto	91:031413cf7a89	3451	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
Kojto	91:031413cf7a89	3452	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
Kojto	91:031413cf7a89	3453	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3454	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3455	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3456
Kojto	91:031413cf7a89	3457	/* Bit 17 : Protection enable for region 49. */
Kojto	91:031413cf7a89	3458	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
Kojto	91:031413cf7a89	3459	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
Kojto	91:031413cf7a89	3460	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3461	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3462	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3463
Kojto	91:031413cf7a89	3464	/* Bit 16 : Protection enable for region 48. */
Kojto	91:031413cf7a89	3465	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
Kojto	91:031413cf7a89	3466	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
Kojto	91:031413cf7a89	3467	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3468	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3469	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3470
Kojto	91:031413cf7a89	3471	/* Bit 15 : Protection enable for region 47. */
Kojto	91:031413cf7a89	3472	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
Kojto	91:031413cf7a89	3473	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
Kojto	91:031413cf7a89	3474	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3475	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3476	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3477
Kojto	91:031413cf7a89	3478	/* Bit 14 : Protection enable for region 46. */
Kojto	91:031413cf7a89	3479	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
Kojto	91:031413cf7a89	3480	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
Kojto	91:031413cf7a89	3481	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3482	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3483	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3484
Kojto	91:031413cf7a89	3485	/* Bit 13 : Protection enable for region 45. */
Kojto	91:031413cf7a89	3486	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
Kojto	91:031413cf7a89	3487	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
Kojto	91:031413cf7a89	3488	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3489	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3490	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3491
Kojto	91:031413cf7a89	3492	/* Bit 12 : Protection enable for region 44. */
Kojto	91:031413cf7a89	3493	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
Kojto	91:031413cf7a89	3494	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
Kojto	91:031413cf7a89	3495	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3496	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3497	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3498
Kojto	91:031413cf7a89	3499	/* Bit 11 : Protection enable for region 43. */
Kojto	91:031413cf7a89	3500	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
Kojto	91:031413cf7a89	3501	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
Kojto	91:031413cf7a89	3502	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3503	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3504	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3505
Kojto	91:031413cf7a89	3506	/* Bit 10 : Protection enable for region 42. */
Kojto	91:031413cf7a89	3507	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
Kojto	91:031413cf7a89	3508	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
Kojto	91:031413cf7a89	3509	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3510	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3511	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3512
Kojto	91:031413cf7a89	3513	/* Bit 9 : Protection enable for region 41. */
Kojto	91:031413cf7a89	3514	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
Kojto	91:031413cf7a89	3515	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
Kojto	91:031413cf7a89	3516	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3517	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3518	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3519
Kojto	91:031413cf7a89	3520	/* Bit 8 : Protection enable for region 40. */
Kojto	91:031413cf7a89	3521	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
Kojto	91:031413cf7a89	3522	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
Kojto	91:031413cf7a89	3523	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3524	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3525	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3526
Kojto	91:031413cf7a89	3527	/* Bit 7 : Protection enable for region 39. */
Kojto	91:031413cf7a89	3528	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
Kojto	91:031413cf7a89	3529	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
Kojto	91:031413cf7a89	3530	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3531	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3532	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3533
Kojto	91:031413cf7a89	3534	/* Bit 6 : Protection enable for region 38. */
Kojto	91:031413cf7a89	3535	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
Kojto	91:031413cf7a89	3536	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
Kojto	91:031413cf7a89	3537	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3538	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3539	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3540
Kojto	91:031413cf7a89	3541	/* Bit 5 : Protection enable for region 37. */
Kojto	91:031413cf7a89	3542	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
Kojto	91:031413cf7a89	3543	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
Kojto	91:031413cf7a89	3544	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3545	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3546	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3547
Kojto	91:031413cf7a89	3548	/* Bit 4 : Protection enable for region 36. */
Kojto	91:031413cf7a89	3549	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
Kojto	91:031413cf7a89	3550	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
Kojto	91:031413cf7a89	3551	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3552	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3553	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3554
Kojto	91:031413cf7a89	3555	/* Bit 3 : Protection enable for region 35. */
Kojto	91:031413cf7a89	3556	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
Kojto	91:031413cf7a89	3557	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
Kojto	91:031413cf7a89	3558	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3559	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3560	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3561
Kojto	91:031413cf7a89	3562	/* Bit 2 : Protection enable for region 34. */
Kojto	91:031413cf7a89	3563	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
Kojto	91:031413cf7a89	3564	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
Kojto	91:031413cf7a89	3565	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3566	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3567	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3568
Kojto	91:031413cf7a89	3569	/* Bit 1 : Protection enable for region 33. */
Kojto	91:031413cf7a89	3570	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
Kojto	91:031413cf7a89	3571	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
Kojto	91:031413cf7a89	3572	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3573	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3574	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3575
Kojto	91:031413cf7a89	3576	/* Bit 0 : Protection enable for region 32. */
Kojto	91:031413cf7a89	3577	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
Kojto	91:031413cf7a89	3578	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
Kojto	91:031413cf7a89	3579	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3580	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3581	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
Kojto	91:031413cf7a89	3582
Kojto	91:031413cf7a89	3583	/* Register: MPU_DISABLEINDEBUG */
Kojto	97:433970e64889	3584	/* Description: Disable erase and write protection mechanism in debug mode. */
Kojto	91:031413cf7a89	3585
Kojto	91:031413cf7a89	3586	/* Bit 0 : Disable protection mechanism in debug mode. */
Kojto	91:031413cf7a89	3587	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
Kojto	91:031413cf7a89	3588	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
Kojto	91:031413cf7a89	3589	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
Kojto	91:031413cf7a89	3590	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
Kojto	91:031413cf7a89	3591
Kojto	97:433970e64889	3592	/* Register: MPU_PROTBLOCKSIZE */
Kojto	97:433970e64889	3593	/* Description: Erase and write protection block size. */
Kojto	97:433970e64889	3594
Kojto	97:433970e64889	3595	/* Bits 1..0 : Erase and write protection block size. */
Kojto	97:433970e64889	3596	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
Kojto	97:433970e64889	3597	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
Kojto	97:433970e64889	3598	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
Kojto	97:433970e64889	3599
Kojto	91:031413cf7a89	3600
Kojto	91:031413cf7a89	3601	/* Peripheral: NVMC */
Kojto	91:031413cf7a89	3602	/* Description: Non Volatile Memory Controller. */
Kojto	91:031413cf7a89	3603
Kojto	91:031413cf7a89	3604	/* Register: NVMC_READY */
Kojto	91:031413cf7a89	3605	/* Description: Ready flag. */
Kojto	91:031413cf7a89	3606
Kojto	91:031413cf7a89	3607	/* Bit 0 : NVMC ready. */
Kojto	91:031413cf7a89	3608	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
Kojto	91:031413cf7a89	3609	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
Kojto	91:031413cf7a89	3610	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
Kojto	91:031413cf7a89	3611	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
Kojto	91:031413cf7a89	3612
Kojto	91:031413cf7a89	3613	/* Register: NVMC_CONFIG */
Kojto	91:031413cf7a89	3614	/* Description: Configuration register. */
Kojto	91:031413cf7a89	3615
Kojto	91:031413cf7a89	3616	/* Bits 1..0 : Program write enable. */
Kojto	91:031413cf7a89	3617	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
Kojto	91:031413cf7a89	3618	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
Kojto	91:031413cf7a89	3619	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
Kojto	91:031413cf7a89	3620	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
Kojto	91:031413cf7a89	3621	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
Kojto	91:031413cf7a89	3622
Kojto	91:031413cf7a89	3623	/* Register: NVMC_ERASEALL */
Kojto	91:031413cf7a89	3624	/* Description: Register for erasing all non-volatile user memory. */
Kojto	91:031413cf7a89	3625
Kojto	91:031413cf7a89	3626	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
Kojto	91:031413cf7a89	3627	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
Kojto	91:031413cf7a89	3628	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
Kojto	91:031413cf7a89	3629	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
Kojto	91:031413cf7a89	3630	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
Kojto	91:031413cf7a89	3631
Kojto	91:031413cf7a89	3632	/* Register: NVMC_ERASEUICR */
Kojto	91:031413cf7a89	3633	/* Description: Register for start erasing User Information Congfiguration Registers. */
Kojto	91:031413cf7a89	3634
Kojto	91:031413cf7a89	3635	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
Kojto	91:031413cf7a89	3636	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
Kojto	91:031413cf7a89	3637	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
Kojto	91:031413cf7a89	3638	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
Kojto	91:031413cf7a89	3639	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
Kojto	91:031413cf7a89	3640
Kojto	91:031413cf7a89	3641
Kojto	91:031413cf7a89	3642	/* Peripheral: POWER */
Kojto	91:031413cf7a89	3643	/* Description: Power Control. */
Kojto	91:031413cf7a89	3644
Kojto	91:031413cf7a89	3645	/* Register: POWER_INTENSET */
Kojto	91:031413cf7a89	3646	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	3647
Kojto	91:031413cf7a89	3648	/* Bit 2 : Enable interrupt on POFWARN event. */
Kojto	91:031413cf7a89	3649	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
Kojto	91:031413cf7a89	3650	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
Kojto	91:031413cf7a89	3651	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	3652	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	3653	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	3654
Kojto	91:031413cf7a89	3655	/* Register: POWER_INTENCLR */
Kojto	91:031413cf7a89	3656	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	3657
Kojto	91:031413cf7a89	3658	/* Bit 2 : Disable interrupt on POFWARN event. */
Kojto	91:031413cf7a89	3659	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
Kojto	91:031413cf7a89	3660	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
Kojto	91:031413cf7a89	3661	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	3662	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	3663	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	3664
Kojto	91:031413cf7a89	3665	/* Register: POWER_RESETREAS */
Kojto	91:031413cf7a89	3666	/* Description: Reset reason. */
Kojto	91:031413cf7a89	3667
Kojto	91:031413cf7a89	3668	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
Kojto	91:031413cf7a89	3669	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
Kojto	91:031413cf7a89	3670	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
Kojto	122:f9eeca106725	3671	#define POWER_RESETREAS_DIF_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3672	#define POWER_RESETREAS_DIF_Detected (1UL) /!< Reset detected. /
Kojto	91:031413cf7a89	3673
Kojto	91:031413cf7a89	3674	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
Kojto	91:031413cf7a89	3675	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
Kojto	91:031413cf7a89	3676	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
Kojto	122:f9eeca106725	3677	#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3678	#define POWER_RESETREAS_LPCOMP_Detected (1UL) /!< Reset detected. /
Kojto	91:031413cf7a89	3679
Kojto	91:031413cf7a89	3680	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
Kojto	91:031413cf7a89	3681	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
Kojto	91:031413cf7a89	3682	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
Kojto	122:f9eeca106725	3683	#define POWER_RESETREAS_OFF_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3684	#define POWER_RESETREAS_OFF_Detected (1UL) /!< Reset detected. /
Kojto	91:031413cf7a89	3685
Kojto	91:031413cf7a89	3686	/* Bit 3 : Reset from CPU lock-up detected. */
Kojto	91:031413cf7a89	3687	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
Kojto	91:031413cf7a89	3688	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
Kojto	122:f9eeca106725	3689	#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3690	#define POWER_RESETREAS_LOCKUP_Detected (1UL) /!< Reset detected. /
Kojto	91:031413cf7a89	3691
Kojto	91:031413cf7a89	3692	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
Kojto	91:031413cf7a89	3693	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
Kojto	91:031413cf7a89	3694	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
Kojto	122:f9eeca106725	3695	#define POWER_RESETREAS_SREQ_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3696	#define POWER_RESETREAS_SREQ_Detected (1UL) /!< Reset detected. /
Kojto	91:031413cf7a89	3697
Kojto	91:031413cf7a89	3698	/* Bit 1 : Reset from watchdog detected. */
Kojto	91:031413cf7a89	3699	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
Kojto	91:031413cf7a89	3700	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
Kojto	122:f9eeca106725	3701	#define POWER_RESETREAS_DOG_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3702	#define POWER_RESETREAS_DOG_Detected (1UL) /!< Reset detected. /
Kojto	91:031413cf7a89	3703
Kojto	91:031413cf7a89	3704	/* Bit 0 : Reset from pin-reset detected. */
Kojto	91:031413cf7a89	3705	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
Kojto	91:031413cf7a89	3706	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
Kojto	122:f9eeca106725	3707	#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3708	#define POWER_RESETREAS_RESETPIN_Detected (1UL) /!< Reset detected. /
Kojto	91:031413cf7a89	3709
Kojto	97:433970e64889	3710	/* Register: POWER_RAMSTATUS */
Kojto	97:433970e64889	3711	/* Description: Ram status register. */
Kojto	97:433970e64889	3712
Kojto	97:433970e64889	3713	/* Bit 3 : RAM block 3 status. */
Kojto	97:433970e64889	3714	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
Kojto	97:433970e64889	3715	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
Kojto	97:433970e64889	3716	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
Kojto	97:433970e64889	3717	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
Kojto	97:433970e64889	3718
Kojto	97:433970e64889	3719	/* Bit 2 : RAM block 2 status. */
Kojto	97:433970e64889	3720	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
Kojto	97:433970e64889	3721	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
Kojto	97:433970e64889	3722	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
Kojto	97:433970e64889	3723	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
Kojto	97:433970e64889	3724
Kojto	97:433970e64889	3725	/* Bit 1 : RAM block 1 status. */
Kojto	97:433970e64889	3726	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
Kojto	97:433970e64889	3727	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
Kojto	97:433970e64889	3728	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
Kojto	97:433970e64889	3729	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
Kojto	97:433970e64889	3730
Kojto	97:433970e64889	3731	/* Bit 0 : RAM block 0 status. */
Kojto	97:433970e64889	3732	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
Kojto	97:433970e64889	3733	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
Kojto	97:433970e64889	3734	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
Kojto	97:433970e64889	3735	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
Kojto	97:433970e64889	3736
Kojto	91:031413cf7a89	3737	/* Register: POWER_SYSTEMOFF */
Kojto	91:031413cf7a89	3738	/* Description: System off register. */
Kojto	91:031413cf7a89	3739
Kojto	91:031413cf7a89	3740	/* Bit 0 : Enter system off mode. */
Kojto	91:031413cf7a89	3741	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
Kojto	91:031413cf7a89	3742	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
Kojto	91:031413cf7a89	3743	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
Kojto	91:031413cf7a89	3744
Kojto	91:031413cf7a89	3745	/* Register: POWER_POFCON */
Kojto	91:031413cf7a89	3746	/* Description: Power failure configuration. */
Kojto	91:031413cf7a89	3747
Kojto	91:031413cf7a89	3748	/* Bits 2..1 : Set threshold level. */
Kojto	91:031413cf7a89	3749	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
Kojto	91:031413cf7a89	3750	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
Kojto	91:031413cf7a89	3751	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
Kojto	91:031413cf7a89	3752	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
Kojto	91:031413cf7a89	3753	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
Kojto	91:031413cf7a89	3754	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
Kojto	91:031413cf7a89	3755
Kojto	91:031413cf7a89	3756	/* Bit 0 : Power failure comparator enable. */
Kojto	91:031413cf7a89	3757	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
Kojto	91:031413cf7a89	3758	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
Kojto	91:031413cf7a89	3759	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	3760	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	3761
Kojto	91:031413cf7a89	3762	/* Register: POWER_GPREGRET */
Kojto	91:031413cf7a89	3763	/* Description: General purpose retention register. This register is a retained register. */
Kojto	91:031413cf7a89	3764
Kojto	91:031413cf7a89	3765	/* Bits 7..0 : General purpose retention register. */
Kojto	91:031413cf7a89	3766	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
Kojto	91:031413cf7a89	3767	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
Kojto	91:031413cf7a89	3768
Kojto	91:031413cf7a89	3769	/* Register: POWER_RAMON */
Kojto	91:031413cf7a89	3770	/* Description: Ram on/off. */
Kojto	91:031413cf7a89	3771
Kojto	91:031413cf7a89	3772	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
Kojto	91:031413cf7a89	3773	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
Kojto	91:031413cf7a89	3774	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
Kojto	91:031413cf7a89	3775	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
Kojto	91:031413cf7a89	3776	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
Kojto	91:031413cf7a89	3777
Kojto	91:031413cf7a89	3778	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
Kojto	91:031413cf7a89	3779	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
Kojto	91:031413cf7a89	3780	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
Kojto	91:031413cf7a89	3781	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
Kojto	91:031413cf7a89	3782	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
Kojto	91:031413cf7a89	3783
Kojto	91:031413cf7a89	3784	/* Bit 1 : RAM block 1 behaviour in ON mode. */
Kojto	91:031413cf7a89	3785	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
Kojto	91:031413cf7a89	3786	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
Kojto	91:031413cf7a89	3787	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
Kojto	91:031413cf7a89	3788	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
Kojto	91:031413cf7a89	3789
Kojto	91:031413cf7a89	3790	/* Bit 0 : RAM block 0 behaviour in ON mode. */
Kojto	91:031413cf7a89	3791	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
Kojto	91:031413cf7a89	3792	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
Kojto	91:031413cf7a89	3793	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
Kojto	91:031413cf7a89	3794	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
Kojto	91:031413cf7a89	3795
Kojto	91:031413cf7a89	3796	/* Register: POWER_RESET */
Kojto	91:031413cf7a89	3797	/* Description: Pin reset functionality configuration register. This register is a retained register. */
Kojto	91:031413cf7a89	3798
Kojto	97:433970e64889	3799	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
Kojto	91:031413cf7a89	3800	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
Kojto	91:031413cf7a89	3801	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
Kojto	91:031413cf7a89	3802	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
Kojto	91:031413cf7a89	3803	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
Kojto	91:031413cf7a89	3804
Kojto	97:433970e64889	3805	/* Register: POWER_RAMONB */
Kojto	97:433970e64889	3806	/* Description: Ram on/off. */
Kojto	97:433970e64889	3807
Kojto	97:433970e64889	3808	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
Kojto	97:433970e64889	3809	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
Kojto	97:433970e64889	3810	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
Kojto	97:433970e64889	3811	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
Kojto	97:433970e64889	3812	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
Kojto	97:433970e64889	3813
Kojto	97:433970e64889	3814	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
Kojto	97:433970e64889	3815	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
Kojto	97:433970e64889	3816	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
Kojto	97:433970e64889	3817	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
Kojto	97:433970e64889	3818	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
Kojto	97:433970e64889	3819
Kojto	97:433970e64889	3820	/* Bit 1 : RAM block 3 behaviour in ON mode. */
Kojto	97:433970e64889	3821	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
Kojto	97:433970e64889	3822	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
Kojto	97:433970e64889	3823	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
Kojto	97:433970e64889	3824	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
Kojto	97:433970e64889	3825
Kojto	97:433970e64889	3826	/* Bit 0 : RAM block 2 behaviour in ON mode. */
Kojto	97:433970e64889	3827	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
Kojto	97:433970e64889	3828	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
Kojto	97:433970e64889	3829	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
Kojto	97:433970e64889	3830	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
Kojto	97:433970e64889	3831
Kojto	91:031413cf7a89	3832	/* Register: POWER_DCDCEN */
Kojto	91:031413cf7a89	3833	/* Description: DCDC converter enable configuration register. */
Kojto	91:031413cf7a89	3834
Kojto	91:031413cf7a89	3835	/* Bit 0 : Enable DCDC converter. */
Kojto	91:031413cf7a89	3836	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
Kojto	91:031413cf7a89	3837	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
Kojto	91:031413cf7a89	3838	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
Kojto	91:031413cf7a89	3839	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
Kojto	91:031413cf7a89	3840
Kojto	97:433970e64889	3841	/* Register: POWER_DCDCFORCE */
Kojto	97:433970e64889	3842	/* Description: DCDC power-up force register. */
Kojto	97:433970e64889	3843
Kojto	97:433970e64889	3844	/* Bit 1 : DCDC power-up force on. */
Kojto	97:433970e64889	3845	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
Kojto	97:433970e64889	3846	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
Kojto	97:433970e64889	3847	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
Kojto	97:433970e64889	3848	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
Kojto	97:433970e64889	3849
Kojto	97:433970e64889	3850	/* Bit 0 : DCDC power-up force off. */
Kojto	97:433970e64889	3851	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
Kojto	97:433970e64889	3852	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
Kojto	97:433970e64889	3853	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
Kojto	97:433970e64889	3854	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
Kojto	97:433970e64889	3855
Kojto	91:031413cf7a89	3856
Kojto	91:031413cf7a89	3857	/* Peripheral: PPI */
Kojto	91:031413cf7a89	3858	/* Description: PPI controller. */
Kojto	91:031413cf7a89	3859
Kojto	91:031413cf7a89	3860	/* Register: PPI_CHEN */
Kojto	91:031413cf7a89	3861	/* Description: Channel enable. */
Kojto	91:031413cf7a89	3862
Kojto	91:031413cf7a89	3863	/* Bit 31 : Enable PPI channel 31. */
Kojto	91:031413cf7a89	3864	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
Kojto	91:031413cf7a89	3865	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
Kojto	91:031413cf7a89	3866	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3867	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3868
Kojto	91:031413cf7a89	3869	/* Bit 30 : Enable PPI channel 30. */
Kojto	91:031413cf7a89	3870	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
Kojto	91:031413cf7a89	3871	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
Kojto	91:031413cf7a89	3872	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3873	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3874
Kojto	91:031413cf7a89	3875	/* Bit 29 : Enable PPI channel 29. */
Kojto	91:031413cf7a89	3876	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
Kojto	91:031413cf7a89	3877	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
Kojto	91:031413cf7a89	3878	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3879	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3880
Kojto	91:031413cf7a89	3881	/* Bit 28 : Enable PPI channel 28. */
Kojto	91:031413cf7a89	3882	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
Kojto	91:031413cf7a89	3883	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
Kojto	91:031413cf7a89	3884	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3885	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3886
Kojto	91:031413cf7a89	3887	/* Bit 27 : Enable PPI channel 27. */
Kojto	91:031413cf7a89	3888	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
Kojto	91:031413cf7a89	3889	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
Kojto	91:031413cf7a89	3890	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3891	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3892
Kojto	91:031413cf7a89	3893	/* Bit 26 : Enable PPI channel 26. */
Kojto	91:031413cf7a89	3894	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
Kojto	91:031413cf7a89	3895	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
Kojto	91:031413cf7a89	3896	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3897	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3898
Kojto	91:031413cf7a89	3899	/* Bit 25 : Enable PPI channel 25. */
Kojto	91:031413cf7a89	3900	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
Kojto	91:031413cf7a89	3901	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
Kojto	91:031413cf7a89	3902	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3903	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3904
Kojto	91:031413cf7a89	3905	/* Bit 24 : Enable PPI channel 24. */
Kojto	91:031413cf7a89	3906	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
Kojto	91:031413cf7a89	3907	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
Kojto	91:031413cf7a89	3908	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3909	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3910
Kojto	91:031413cf7a89	3911	/* Bit 23 : Enable PPI channel 23. */
Kojto	91:031413cf7a89	3912	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
Kojto	91:031413cf7a89	3913	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
Kojto	91:031413cf7a89	3914	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3915	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3916
Kojto	91:031413cf7a89	3917	/* Bit 22 : Enable PPI channel 22. */
Kojto	91:031413cf7a89	3918	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
Kojto	91:031413cf7a89	3919	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
Kojto	91:031413cf7a89	3920	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3921	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3922
Kojto	91:031413cf7a89	3923	/* Bit 21 : Enable PPI channel 21. */
Kojto	91:031413cf7a89	3924	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
Kojto	91:031413cf7a89	3925	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
Kojto	91:031413cf7a89	3926	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3927	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3928
Kojto	91:031413cf7a89	3929	/* Bit 20 : Enable PPI channel 20. */
Kojto	91:031413cf7a89	3930	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
Kojto	91:031413cf7a89	3931	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
Kojto	91:031413cf7a89	3932	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3933	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3934
Kojto	91:031413cf7a89	3935	/* Bit 15 : Enable PPI channel 15. */
Kojto	91:031413cf7a89	3936	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
Kojto	91:031413cf7a89	3937	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
Kojto	91:031413cf7a89	3938	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3939	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3940
Kojto	91:031413cf7a89	3941	/* Bit 14 : Enable PPI channel 14. */
Kojto	91:031413cf7a89	3942	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
Kojto	91:031413cf7a89	3943	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
Kojto	91:031413cf7a89	3944	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3945	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3946
Kojto	91:031413cf7a89	3947	/* Bit 13 : Enable PPI channel 13. */
Kojto	91:031413cf7a89	3948	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
Kojto	91:031413cf7a89	3949	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
Kojto	91:031413cf7a89	3950	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3951	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3952
Kojto	91:031413cf7a89	3953	/* Bit 12 : Enable PPI channel 12. */
Kojto	91:031413cf7a89	3954	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
Kojto	91:031413cf7a89	3955	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
Kojto	91:031413cf7a89	3956	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3957	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3958
Kojto	91:031413cf7a89	3959	/* Bit 11 : Enable PPI channel 11. */
Kojto	91:031413cf7a89	3960	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
Kojto	91:031413cf7a89	3961	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
Kojto	91:031413cf7a89	3962	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3963	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3964
Kojto	91:031413cf7a89	3965	/* Bit 10 : Enable PPI channel 10. */
Kojto	91:031413cf7a89	3966	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
Kojto	91:031413cf7a89	3967	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
Kojto	91:031413cf7a89	3968	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3969	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3970
Kojto	91:031413cf7a89	3971	/* Bit 9 : Enable PPI channel 9. */
Kojto	91:031413cf7a89	3972	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
Kojto	91:031413cf7a89	3973	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
Kojto	91:031413cf7a89	3974	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3975	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3976
Kojto	91:031413cf7a89	3977	/* Bit 8 : Enable PPI channel 8. */
Kojto	91:031413cf7a89	3978	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
Kojto	91:031413cf7a89	3979	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
Kojto	91:031413cf7a89	3980	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3981	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3982
Kojto	91:031413cf7a89	3983	/* Bit 7 : Enable PPI channel 7. */
Kojto	91:031413cf7a89	3984	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
Kojto	91:031413cf7a89	3985	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
Kojto	91:031413cf7a89	3986	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3987	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3988
Kojto	91:031413cf7a89	3989	/* Bit 6 : Enable PPI channel 6. */
Kojto	91:031413cf7a89	3990	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
Kojto	91:031413cf7a89	3991	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
Kojto	91:031413cf7a89	3992	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3993	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	3994
Kojto	91:031413cf7a89	3995	/* Bit 5 : Enable PPI channel 5. */
Kojto	91:031413cf7a89	3996	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
Kojto	91:031413cf7a89	3997	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
Kojto	91:031413cf7a89	3998	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	3999	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4000
Kojto	91:031413cf7a89	4001	/* Bit 4 : Enable PPI channel 4. */
Kojto	91:031413cf7a89	4002	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
Kojto	91:031413cf7a89	4003	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
Kojto	91:031413cf7a89	4004	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4005	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4006
Kojto	91:031413cf7a89	4007	/* Bit 3 : Enable PPI channel 3. */
Kojto	91:031413cf7a89	4008	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
Kojto	91:031413cf7a89	4009	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
Kojto	91:031413cf7a89	4010	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
Kojto	91:031413cf7a89	4011	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
Kojto	91:031413cf7a89	4012
Kojto	91:031413cf7a89	4013	/* Bit 2 : Enable PPI channel 2. */
Kojto	91:031413cf7a89	4014	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
Kojto	91:031413cf7a89	4015	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
Kojto	91:031413cf7a89	4016	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4017	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4018
Kojto	91:031413cf7a89	4019	/* Bit 1 : Enable PPI channel 1. */
Kojto	91:031413cf7a89	4020	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
Kojto	91:031413cf7a89	4021	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
Kojto	91:031413cf7a89	4022	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4023	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4024
Kojto	91:031413cf7a89	4025	/* Bit 0 : Enable PPI channel 0. */
Kojto	91:031413cf7a89	4026	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
Kojto	91:031413cf7a89	4027	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
Kojto	91:031413cf7a89	4028	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4029	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4030
Kojto	91:031413cf7a89	4031	/* Register: PPI_CHENSET */
Kojto	91:031413cf7a89	4032	/* Description: Channel enable set. */
Kojto	91:031413cf7a89	4033
Kojto	91:031413cf7a89	4034	/* Bit 31 : Enable PPI channel 31. */
Kojto	91:031413cf7a89	4035	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
Kojto	91:031413cf7a89	4036	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
Kojto	91:031413cf7a89	4037	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4038	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4039	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4040
Kojto	91:031413cf7a89	4041	/* Bit 30 : Enable PPI channel 30. */
Kojto	91:031413cf7a89	4042	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
Kojto	91:031413cf7a89	4043	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
Kojto	91:031413cf7a89	4044	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4045	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4046	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4047
Kojto	91:031413cf7a89	4048	/* Bit 29 : Enable PPI channel 29. */
Kojto	91:031413cf7a89	4049	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
Kojto	91:031413cf7a89	4050	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
Kojto	91:031413cf7a89	4051	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4052	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4053	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4054
Kojto	91:031413cf7a89	4055	/* Bit 28 : Enable PPI channel 28. */
Kojto	91:031413cf7a89	4056	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
Kojto	91:031413cf7a89	4057	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
Kojto	91:031413cf7a89	4058	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4059	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4060	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4061
Kojto	91:031413cf7a89	4062	/* Bit 27 : Enable PPI channel 27. */
Kojto	91:031413cf7a89	4063	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
Kojto	91:031413cf7a89	4064	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
Kojto	91:031413cf7a89	4065	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4066	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4067	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4068
Kojto	91:031413cf7a89	4069	/* Bit 26 : Enable PPI channel 26. */
Kojto	91:031413cf7a89	4070	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
Kojto	91:031413cf7a89	4071	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
Kojto	91:031413cf7a89	4072	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4073	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4074	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4075
Kojto	91:031413cf7a89	4076	/* Bit 25 : Enable PPI channel 25. */
Kojto	91:031413cf7a89	4077	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
Kojto	91:031413cf7a89	4078	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
Kojto	91:031413cf7a89	4079	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4080	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4081	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4082
Kojto	91:031413cf7a89	4083	/* Bit 24 : Enable PPI channel 24. */
Kojto	91:031413cf7a89	4084	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
Kojto	91:031413cf7a89	4085	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
Kojto	91:031413cf7a89	4086	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4087	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4088	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4089
Kojto	91:031413cf7a89	4090	/* Bit 23 : Enable PPI channel 23. */
Kojto	91:031413cf7a89	4091	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
Kojto	91:031413cf7a89	4092	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
Kojto	91:031413cf7a89	4093	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4094	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4095	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4096
Kojto	91:031413cf7a89	4097	/* Bit 22 : Enable PPI channel 22. */
Kojto	91:031413cf7a89	4098	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
Kojto	91:031413cf7a89	4099	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
Kojto	91:031413cf7a89	4100	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4101	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4102	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4103
Kojto	91:031413cf7a89	4104	/* Bit 21 : Enable PPI channel 21. */
Kojto	91:031413cf7a89	4105	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
Kojto	91:031413cf7a89	4106	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
Kojto	91:031413cf7a89	4107	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4108	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4109	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4110
Kojto	91:031413cf7a89	4111	/* Bit 20 : Enable PPI channel 20. */
Kojto	91:031413cf7a89	4112	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
Kojto	91:031413cf7a89	4113	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
Kojto	91:031413cf7a89	4114	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4115	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4116	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4117
Kojto	91:031413cf7a89	4118	/* Bit 15 : Enable PPI channel 15. */
Kojto	91:031413cf7a89	4119	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
Kojto	91:031413cf7a89	4120	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
Kojto	91:031413cf7a89	4121	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4122	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4123	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4124
Kojto	91:031413cf7a89	4125	/* Bit 14 : Enable PPI channel 14. */
Kojto	91:031413cf7a89	4126	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
Kojto	91:031413cf7a89	4127	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
Kojto	91:031413cf7a89	4128	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4129	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4130	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4131
Kojto	91:031413cf7a89	4132	/* Bit 13 : Enable PPI channel 13. */
Kojto	91:031413cf7a89	4133	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
Kojto	91:031413cf7a89	4134	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
Kojto	91:031413cf7a89	4135	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4136	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4137	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4138
Kojto	91:031413cf7a89	4139	/* Bit 12 : Enable PPI channel 12. */
Kojto	91:031413cf7a89	4140	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
Kojto	91:031413cf7a89	4141	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
Kojto	91:031413cf7a89	4142	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4143	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4144	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4145
Kojto	91:031413cf7a89	4146	/* Bit 11 : Enable PPI channel 11. */
Kojto	91:031413cf7a89	4147	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
Kojto	91:031413cf7a89	4148	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
Kojto	91:031413cf7a89	4149	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4150	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4151	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4152
Kojto	91:031413cf7a89	4153	/* Bit 10 : Enable PPI channel 10. */
Kojto	91:031413cf7a89	4154	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
Kojto	91:031413cf7a89	4155	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
Kojto	91:031413cf7a89	4156	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4157	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4158	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4159
Kojto	91:031413cf7a89	4160	/* Bit 9 : Enable PPI channel 9. */
Kojto	91:031413cf7a89	4161	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
Kojto	91:031413cf7a89	4162	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
Kojto	91:031413cf7a89	4163	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4164	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4165	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4166
Kojto	91:031413cf7a89	4167	/* Bit 8 : Enable PPI channel 8. */
Kojto	91:031413cf7a89	4168	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
Kojto	91:031413cf7a89	4169	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
Kojto	91:031413cf7a89	4170	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4171	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4172	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4173
Kojto	91:031413cf7a89	4174	/* Bit 7 : Enable PPI channel 7. */
Kojto	91:031413cf7a89	4175	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
Kojto	91:031413cf7a89	4176	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
Kojto	91:031413cf7a89	4177	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4178	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4179	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4180
Kojto	91:031413cf7a89	4181	/* Bit 6 : Enable PPI channel 6. */
Kojto	91:031413cf7a89	4182	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
Kojto	91:031413cf7a89	4183	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
Kojto	91:031413cf7a89	4184	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4185	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4186	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4187
Kojto	91:031413cf7a89	4188	/* Bit 5 : Enable PPI channel 5. */
Kojto	91:031413cf7a89	4189	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
Kojto	91:031413cf7a89	4190	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
Kojto	91:031413cf7a89	4191	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4192	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4193	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4194
Kojto	91:031413cf7a89	4195	/* Bit 4 : Enable PPI channel 4. */
Kojto	91:031413cf7a89	4196	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
Kojto	91:031413cf7a89	4197	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
Kojto	91:031413cf7a89	4198	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4199	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4200	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4201
Kojto	91:031413cf7a89	4202	/* Bit 3 : Enable PPI channel 3. */
Kojto	91:031413cf7a89	4203	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
Kojto	91:031413cf7a89	4204	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
Kojto	91:031413cf7a89	4205	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4206	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4207	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4208
Kojto	91:031413cf7a89	4209	/* Bit 2 : Enable PPI channel 2. */
Kojto	91:031413cf7a89	4210	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
Kojto	91:031413cf7a89	4211	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
Kojto	91:031413cf7a89	4212	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4213	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4214	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4215
Kojto	91:031413cf7a89	4216	/* Bit 1 : Enable PPI channel 1. */
Kojto	91:031413cf7a89	4217	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
Kojto	91:031413cf7a89	4218	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
Kojto	91:031413cf7a89	4219	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4220	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4221	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4222
Kojto	91:031413cf7a89	4223	/* Bit 0 : Enable PPI channel 0. */
Kojto	91:031413cf7a89	4224	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
Kojto	91:031413cf7a89	4225	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
Kojto	91:031413cf7a89	4226	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4227	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4228	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
Kojto	91:031413cf7a89	4229
Kojto	91:031413cf7a89	4230	/* Register: PPI_CHENCLR */
Kojto	91:031413cf7a89	4231	/* Description: Channel enable clear. */
Kojto	91:031413cf7a89	4232
Kojto	91:031413cf7a89	4233	/* Bit 31 : Disable PPI channel 31. */
Kojto	91:031413cf7a89	4234	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
Kojto	91:031413cf7a89	4235	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
Kojto	91:031413cf7a89	4236	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4237	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4238	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4239
Kojto	91:031413cf7a89	4240	/* Bit 30 : Disable PPI channel 30. */
Kojto	91:031413cf7a89	4241	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
Kojto	91:031413cf7a89	4242	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
Kojto	91:031413cf7a89	4243	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4244	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4245	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4246
Kojto	91:031413cf7a89	4247	/* Bit 29 : Disable PPI channel 29. */
Kojto	91:031413cf7a89	4248	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
Kojto	91:031413cf7a89	4249	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
Kojto	91:031413cf7a89	4250	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4251	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4252	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4253
Kojto	91:031413cf7a89	4254	/* Bit 28 : Disable PPI channel 28. */
Kojto	91:031413cf7a89	4255	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
Kojto	91:031413cf7a89	4256	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
Kojto	91:031413cf7a89	4257	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4258	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4259	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4260
Kojto	91:031413cf7a89	4261	/* Bit 27 : Disable PPI channel 27. */
Kojto	91:031413cf7a89	4262	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
Kojto	91:031413cf7a89	4263	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
Kojto	91:031413cf7a89	4264	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4265	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4266	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4267
Kojto	91:031413cf7a89	4268	/* Bit 26 : Disable PPI channel 26. */
Kojto	91:031413cf7a89	4269	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
Kojto	91:031413cf7a89	4270	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
Kojto	91:031413cf7a89	4271	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4272	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4273	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4274
Kojto	91:031413cf7a89	4275	/* Bit 25 : Disable PPI channel 25. */
Kojto	91:031413cf7a89	4276	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
Kojto	91:031413cf7a89	4277	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
Kojto	91:031413cf7a89	4278	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4279	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4280	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4281
Kojto	91:031413cf7a89	4282	/* Bit 24 : Disable PPI channel 24. */
Kojto	91:031413cf7a89	4283	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
Kojto	91:031413cf7a89	4284	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
Kojto	91:031413cf7a89	4285	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4286	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4287	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4288
Kojto	91:031413cf7a89	4289	/* Bit 23 : Disable PPI channel 23. */
Kojto	91:031413cf7a89	4290	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
Kojto	91:031413cf7a89	4291	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
Kojto	91:031413cf7a89	4292	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4293	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4294	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4295
Kojto	91:031413cf7a89	4296	/* Bit 22 : Disable PPI channel 22. */
Kojto	91:031413cf7a89	4297	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
Kojto	91:031413cf7a89	4298	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
Kojto	91:031413cf7a89	4299	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4300	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4301	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4302
Kojto	91:031413cf7a89	4303	/* Bit 21 : Disable PPI channel 21. */
Kojto	91:031413cf7a89	4304	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
Kojto	91:031413cf7a89	4305	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
Kojto	91:031413cf7a89	4306	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4307	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4308	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4309
Kojto	91:031413cf7a89	4310	/* Bit 20 : Disable PPI channel 20. */
Kojto	91:031413cf7a89	4311	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
Kojto	91:031413cf7a89	4312	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
Kojto	91:031413cf7a89	4313	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4314	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4315	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4316
Kojto	91:031413cf7a89	4317	/* Bit 15 : Disable PPI channel 15. */
Kojto	91:031413cf7a89	4318	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
Kojto	91:031413cf7a89	4319	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
Kojto	91:031413cf7a89	4320	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4321	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4322	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4323
Kojto	91:031413cf7a89	4324	/* Bit 14 : Disable PPI channel 14. */
Kojto	91:031413cf7a89	4325	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
Kojto	91:031413cf7a89	4326	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
Kojto	91:031413cf7a89	4327	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4328	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4329	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4330
Kojto	91:031413cf7a89	4331	/* Bit 13 : Disable PPI channel 13. */
Kojto	91:031413cf7a89	4332	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
Kojto	91:031413cf7a89	4333	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
Kojto	91:031413cf7a89	4334	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4335	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4336	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4337
Kojto	91:031413cf7a89	4338	/* Bit 12 : Disable PPI channel 12. */
Kojto	91:031413cf7a89	4339	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
Kojto	91:031413cf7a89	4340	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
Kojto	91:031413cf7a89	4341	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4342	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4343	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4344
Kojto	91:031413cf7a89	4345	/* Bit 11 : Disable PPI channel 11. */
Kojto	91:031413cf7a89	4346	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
Kojto	91:031413cf7a89	4347	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
Kojto	91:031413cf7a89	4348	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4349	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4350	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4351
Kojto	91:031413cf7a89	4352	/* Bit 10 : Disable PPI channel 10. */
Kojto	91:031413cf7a89	4353	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
Kojto	91:031413cf7a89	4354	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
Kojto	91:031413cf7a89	4355	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4356	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4357	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4358
Kojto	91:031413cf7a89	4359	/* Bit 9 : Disable PPI channel 9. */
Kojto	91:031413cf7a89	4360	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
Kojto	91:031413cf7a89	4361	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
Kojto	91:031413cf7a89	4362	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4363	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4364	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4365
Kojto	91:031413cf7a89	4366	/* Bit 8 : Disable PPI channel 8. */
Kojto	91:031413cf7a89	4367	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
Kojto	91:031413cf7a89	4368	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
Kojto	91:031413cf7a89	4369	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4370	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4371	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4372
Kojto	91:031413cf7a89	4373	/* Bit 7 : Disable PPI channel 7. */
Kojto	91:031413cf7a89	4374	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
Kojto	91:031413cf7a89	4375	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
Kojto	91:031413cf7a89	4376	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4377	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4378	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4379
Kojto	91:031413cf7a89	4380	/* Bit 6 : Disable PPI channel 6. */
Kojto	91:031413cf7a89	4381	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
Kojto	91:031413cf7a89	4382	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
Kojto	91:031413cf7a89	4383	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4384	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4385	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4386
Kojto	91:031413cf7a89	4387	/* Bit 5 : Disable PPI channel 5. */
Kojto	91:031413cf7a89	4388	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
Kojto	91:031413cf7a89	4389	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
Kojto	91:031413cf7a89	4390	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4391	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4392	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4393
Kojto	91:031413cf7a89	4394	/* Bit 4 : Disable PPI channel 4. */
Kojto	91:031413cf7a89	4395	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
Kojto	91:031413cf7a89	4396	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
Kojto	91:031413cf7a89	4397	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4398	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4399	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4400
Kojto	91:031413cf7a89	4401	/* Bit 3 : Disable PPI channel 3. */
Kojto	91:031413cf7a89	4402	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
Kojto	91:031413cf7a89	4403	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
Kojto	91:031413cf7a89	4404	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4405	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4406	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4407
Kojto	91:031413cf7a89	4408	/* Bit 2 : Disable PPI channel 2. */
Kojto	91:031413cf7a89	4409	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
Kojto	91:031413cf7a89	4410	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
Kojto	91:031413cf7a89	4411	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4412	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4413	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4414
Kojto	91:031413cf7a89	4415	/* Bit 1 : Disable PPI channel 1. */
Kojto	91:031413cf7a89	4416	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
Kojto	91:031413cf7a89	4417	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
Kojto	91:031413cf7a89	4418	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4419	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4420	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4421
Kojto	91:031413cf7a89	4422	/* Bit 0 : Disable PPI channel 0. */
Kojto	91:031413cf7a89	4423	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
Kojto	91:031413cf7a89	4424	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
Kojto	91:031413cf7a89	4425	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
Kojto	91:031413cf7a89	4426	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
Kojto	91:031413cf7a89	4427	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
Kojto	91:031413cf7a89	4428
Kojto	91:031413cf7a89	4429	/* Register: PPI_CHG */
Kojto	91:031413cf7a89	4430	/* Description: Channel group configuration. */
Kojto	91:031413cf7a89	4431
Kojto	91:031413cf7a89	4432	/* Bit 31 : Include CH31 in channel group. */
Kojto	91:031413cf7a89	4433	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
Kojto	91:031413cf7a89	4434	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
Kojto	91:031413cf7a89	4435	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4436	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4437
Kojto	91:031413cf7a89	4438	/* Bit 30 : Include CH30 in channel group. */
Kojto	91:031413cf7a89	4439	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
Kojto	91:031413cf7a89	4440	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
Kojto	91:031413cf7a89	4441	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4442	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4443
Kojto	91:031413cf7a89	4444	/* Bit 29 : Include CH29 in channel group. */
Kojto	91:031413cf7a89	4445	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
Kojto	91:031413cf7a89	4446	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
Kojto	91:031413cf7a89	4447	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4448	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4449
Kojto	91:031413cf7a89	4450	/* Bit 28 : Include CH28 in channel group. */
Kojto	91:031413cf7a89	4451	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
Kojto	91:031413cf7a89	4452	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
Kojto	91:031413cf7a89	4453	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4454	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4455
Kojto	91:031413cf7a89	4456	/* Bit 27 : Include CH27 in channel group. */
Kojto	91:031413cf7a89	4457	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
Kojto	91:031413cf7a89	4458	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
Kojto	91:031413cf7a89	4459	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4460	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4461
Kojto	91:031413cf7a89	4462	/* Bit 26 : Include CH26 in channel group. */
Kojto	91:031413cf7a89	4463	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
Kojto	91:031413cf7a89	4464	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
Kojto	91:031413cf7a89	4465	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4466	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4467
Kojto	91:031413cf7a89	4468	/* Bit 25 : Include CH25 in channel group. */
Kojto	91:031413cf7a89	4469	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
Kojto	91:031413cf7a89	4470	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
Kojto	91:031413cf7a89	4471	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4472	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4473
Kojto	91:031413cf7a89	4474	/* Bit 24 : Include CH24 in channel group. */
Kojto	91:031413cf7a89	4475	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
Kojto	91:031413cf7a89	4476	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
Kojto	91:031413cf7a89	4477	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4478	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4479
Kojto	91:031413cf7a89	4480	/* Bit 23 : Include CH23 in channel group. */
Kojto	91:031413cf7a89	4481	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
Kojto	91:031413cf7a89	4482	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
Kojto	91:031413cf7a89	4483	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4484	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4485
Kojto	91:031413cf7a89	4486	/* Bit 22 : Include CH22 in channel group. */
Kojto	91:031413cf7a89	4487	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
Kojto	91:031413cf7a89	4488	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
Kojto	91:031413cf7a89	4489	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4490	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4491
Kojto	91:031413cf7a89	4492	/* Bit 21 : Include CH21 in channel group. */
Kojto	91:031413cf7a89	4493	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
Kojto	91:031413cf7a89	4494	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
Kojto	91:031413cf7a89	4495	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4496	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4497
Kojto	91:031413cf7a89	4498	/* Bit 20 : Include CH20 in channel group. */
Kojto	91:031413cf7a89	4499	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
Kojto	91:031413cf7a89	4500	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
Kojto	91:031413cf7a89	4501	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4502	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4503
Kojto	91:031413cf7a89	4504	/* Bit 15 : Include CH15 in channel group. */
Kojto	91:031413cf7a89	4505	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
Kojto	91:031413cf7a89	4506	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
Kojto	91:031413cf7a89	4507	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4508	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4509
Kojto	91:031413cf7a89	4510	/* Bit 14 : Include CH14 in channel group. */
Kojto	91:031413cf7a89	4511	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
Kojto	91:031413cf7a89	4512	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
Kojto	91:031413cf7a89	4513	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4514	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4515
Kojto	91:031413cf7a89	4516	/* Bit 13 : Include CH13 in channel group. */
Kojto	91:031413cf7a89	4517	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
Kojto	91:031413cf7a89	4518	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
Kojto	91:031413cf7a89	4519	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4520	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4521
Kojto	91:031413cf7a89	4522	/* Bit 12 : Include CH12 in channel group. */
Kojto	91:031413cf7a89	4523	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
Kojto	91:031413cf7a89	4524	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
Kojto	91:031413cf7a89	4525	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4526	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4527
Kojto	91:031413cf7a89	4528	/* Bit 11 : Include CH11 in channel group. */
Kojto	91:031413cf7a89	4529	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
Kojto	91:031413cf7a89	4530	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
Kojto	91:031413cf7a89	4531	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4532	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4533
Kojto	91:031413cf7a89	4534	/* Bit 10 : Include CH10 in channel group. */
Kojto	91:031413cf7a89	4535	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
Kojto	91:031413cf7a89	4536	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
Kojto	91:031413cf7a89	4537	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4538	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4539
Kojto	91:031413cf7a89	4540	/* Bit 9 : Include CH9 in channel group. */
Kojto	91:031413cf7a89	4541	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
Kojto	91:031413cf7a89	4542	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
Kojto	91:031413cf7a89	4543	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4544	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4545
Kojto	91:031413cf7a89	4546	/* Bit 8 : Include CH8 in channel group. */
Kojto	91:031413cf7a89	4547	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
Kojto	91:031413cf7a89	4548	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
Kojto	91:031413cf7a89	4549	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4550	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4551
Kojto	91:031413cf7a89	4552	/* Bit 7 : Include CH7 in channel group. */
Kojto	91:031413cf7a89	4553	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
Kojto	91:031413cf7a89	4554	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
Kojto	91:031413cf7a89	4555	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4556	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4557
Kojto	91:031413cf7a89	4558	/* Bit 6 : Include CH6 in channel group. */
Kojto	91:031413cf7a89	4559	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
Kojto	91:031413cf7a89	4560	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
Kojto	91:031413cf7a89	4561	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4562	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4563
Kojto	91:031413cf7a89	4564	/* Bit 5 : Include CH5 in channel group. */
Kojto	91:031413cf7a89	4565	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
Kojto	91:031413cf7a89	4566	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
Kojto	91:031413cf7a89	4567	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4568	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4569
Kojto	91:031413cf7a89	4570	/* Bit 4 : Include CH4 in channel group. */
Kojto	91:031413cf7a89	4571	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
Kojto	91:031413cf7a89	4572	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
Kojto	91:031413cf7a89	4573	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4574	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4575
Kojto	91:031413cf7a89	4576	/* Bit 3 : Include CH3 in channel group. */
Kojto	91:031413cf7a89	4577	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
Kojto	91:031413cf7a89	4578	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
Kojto	91:031413cf7a89	4579	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4580	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4581
Kojto	91:031413cf7a89	4582	/* Bit 2 : Include CH2 in channel group. */
Kojto	91:031413cf7a89	4583	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
Kojto	91:031413cf7a89	4584	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
Kojto	91:031413cf7a89	4585	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4586	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4587
Kojto	91:031413cf7a89	4588	/* Bit 1 : Include CH1 in channel group. */
Kojto	91:031413cf7a89	4589	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
Kojto	91:031413cf7a89	4590	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
Kojto	91:031413cf7a89	4591	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4592	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4593
Kojto	91:031413cf7a89	4594	/* Bit 0 : Include CH0 in channel group. */
Kojto	91:031413cf7a89	4595	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
Kojto	91:031413cf7a89	4596	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
Kojto	91:031413cf7a89	4597	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
Kojto	91:031413cf7a89	4598	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
Kojto	91:031413cf7a89	4599
Kojto	91:031413cf7a89	4600
Kojto	91:031413cf7a89	4601	/* Peripheral: QDEC */
Kojto	91:031413cf7a89	4602	/* Description: Rotary decoder. */
Kojto	91:031413cf7a89	4603
Kojto	91:031413cf7a89	4604	/* Register: QDEC_SHORTS */
Kojto	97:433970e64889	4605	/* Description: Shortcuts for the QDEC. */
Kojto	97:433970e64889	4606
Kojto	97:433970e64889	4607	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
Kojto	91:031413cf7a89	4608	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
Kojto	91:031413cf7a89	4609	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
Kojto	91:031413cf7a89	4610	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4611	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4612
Kojto	97:433970e64889	4613	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
Kojto	91:031413cf7a89	4614	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
Kojto	91:031413cf7a89	4615	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
Kojto	91:031413cf7a89	4616	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4617	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4618
Kojto	91:031413cf7a89	4619	/* Register: QDEC_INTENSET */
Kojto	91:031413cf7a89	4620	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	4621
Kojto	91:031413cf7a89	4622	/* Bit 2 : Enable interrupt on ACCOF event. */
Kojto	91:031413cf7a89	4623	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
Kojto	91:031413cf7a89	4624	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
Kojto	91:031413cf7a89	4625	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4626	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4627	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4628
Kojto	91:031413cf7a89	4629	/* Bit 1 : Enable interrupt on REPORTRDY event. */
Kojto	91:031413cf7a89	4630	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
Kojto	91:031413cf7a89	4631	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
Kojto	91:031413cf7a89	4632	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4633	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4634	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4635
Kojto	91:031413cf7a89	4636	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
Kojto	91:031413cf7a89	4637	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
Kojto	91:031413cf7a89	4638	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
Kojto	91:031413cf7a89	4639	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4640	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4641	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4642
Kojto	91:031413cf7a89	4643	/* Register: QDEC_INTENCLR */
Kojto	91:031413cf7a89	4644	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	4645
Kojto	91:031413cf7a89	4646	/* Bit 2 : Disable interrupt on ACCOF event. */
Kojto	91:031413cf7a89	4647	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
Kojto	91:031413cf7a89	4648	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
Kojto	91:031413cf7a89	4649	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4650	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4651	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4652
Kojto	91:031413cf7a89	4653	/* Bit 1 : Disable interrupt on REPORTRDY event. */
Kojto	91:031413cf7a89	4654	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
Kojto	91:031413cf7a89	4655	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
Kojto	91:031413cf7a89	4656	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4657	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4658	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4659
Kojto	91:031413cf7a89	4660	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
Kojto	91:031413cf7a89	4661	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
Kojto	91:031413cf7a89	4662	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
Kojto	91:031413cf7a89	4663	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4664	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4665	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4666
Kojto	91:031413cf7a89	4667	/* Register: QDEC_ENABLE */
Kojto	91:031413cf7a89	4668	/* Description: Enable the QDEC. */
Kojto	91:031413cf7a89	4669
Kojto	91:031413cf7a89	4670	/* Bit 0 : Enable or disable QDEC. */
Kojto	91:031413cf7a89	4671	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	4672	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	4673	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
Kojto	91:031413cf7a89	4674	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
Kojto	91:031413cf7a89	4675
Kojto	91:031413cf7a89	4676	/* Register: QDEC_LEDPOL */
Kojto	91:031413cf7a89	4677	/* Description: LED output pin polarity. */
Kojto	91:031413cf7a89	4678
Kojto	91:031413cf7a89	4679	/* Bit 0 : LED output pin polarity. */
Kojto	91:031413cf7a89	4680	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
Kojto	91:031413cf7a89	4681	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
Kojto	91:031413cf7a89	4682	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
Kojto	91:031413cf7a89	4683	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
Kojto	91:031413cf7a89	4684
Kojto	91:031413cf7a89	4685	/* Register: QDEC_SAMPLEPER */
Kojto	91:031413cf7a89	4686	/* Description: Sample period. */
Kojto	91:031413cf7a89	4687
Kojto	91:031413cf7a89	4688	/* Bits 2..0 : Sample period. */
Kojto	91:031413cf7a89	4689	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
Kojto	91:031413cf7a89	4690	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
Kojto	91:031413cf7a89	4691	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
Kojto	91:031413cf7a89	4692	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
Kojto	91:031413cf7a89	4693	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
Kojto	91:031413cf7a89	4694	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
Kojto	91:031413cf7a89	4695	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
Kojto	91:031413cf7a89	4696	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
Kojto	91:031413cf7a89	4697	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
Kojto	91:031413cf7a89	4698	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
Kojto	91:031413cf7a89	4699
Kojto	91:031413cf7a89	4700	/* Register: QDEC_SAMPLE */
Kojto	91:031413cf7a89	4701	/* Description: Motion sample value. */
Kojto	91:031413cf7a89	4702
Kojto	91:031413cf7a89	4703	/* Bits 31..0 : Last sample taken in compliment to 2. */
Kojto	91:031413cf7a89	4704	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
Kojto	91:031413cf7a89	4705	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
Kojto	91:031413cf7a89	4706
Kojto	91:031413cf7a89	4707	/* Register: QDEC_REPORTPER */
Kojto	91:031413cf7a89	4708	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
Kojto	91:031413cf7a89	4709
Kojto	91:031413cf7a89	4710	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
Kojto	91:031413cf7a89	4711	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
Kojto	91:031413cf7a89	4712	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
Kojto	91:031413cf7a89	4713	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
Kojto	91:031413cf7a89	4714	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
Kojto	91:031413cf7a89	4715	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
Kojto	91:031413cf7a89	4716	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
Kojto	91:031413cf7a89	4717	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
Kojto	91:031413cf7a89	4718	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
Kojto	91:031413cf7a89	4719	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
Kojto	91:031413cf7a89	4720	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
Kojto	91:031413cf7a89	4721
Kojto	91:031413cf7a89	4722	/* Register: QDEC_DBFEN */
Kojto	91:031413cf7a89	4723	/* Description: Enable debouncer input filters. */
Kojto	91:031413cf7a89	4724
Kojto	91:031413cf7a89	4725	/* Bit 0 : Enable debounce input filters. */
Kojto	91:031413cf7a89	4726	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
Kojto	91:031413cf7a89	4727	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
Kojto	91:031413cf7a89	4728	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
Kojto	91:031413cf7a89	4729	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
Kojto	91:031413cf7a89	4730
Kojto	91:031413cf7a89	4731	/* Register: QDEC_LEDPRE */
Kojto	91:031413cf7a89	4732	/* Description: Time LED is switched ON before the sample. */
Kojto	91:031413cf7a89	4733
Kojto	97:433970e64889	4734	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
Kojto	91:031413cf7a89	4735	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
Kojto	97:433970e64889	4736	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
Kojto	91:031413cf7a89	4737
Kojto	91:031413cf7a89	4738	/* Register: QDEC_ACCDBL */
Kojto	91:031413cf7a89	4739	/* Description: Accumulated double (error) transitions register. */
Kojto	91:031413cf7a89	4740
Kojto	91:031413cf7a89	4741	/* Bits 3..0 : Accumulated double (error) transitions. */
Kojto	91:031413cf7a89	4742	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
Kojto	91:031413cf7a89	4743	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
Kojto	91:031413cf7a89	4744
Kojto	91:031413cf7a89	4745	/* Register: QDEC_ACCDBLREAD */
Kojto	91:031413cf7a89	4746	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
Kojto	91:031413cf7a89	4747
Kojto	91:031413cf7a89	4748	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
Kojto	91:031413cf7a89	4749	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
Kojto	91:031413cf7a89	4750	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
Kojto	91:031413cf7a89	4751
Kojto	91:031413cf7a89	4752	/* Register: QDEC_POWER */
Kojto	91:031413cf7a89	4753	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	4754
Kojto	91:031413cf7a89	4755	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	4756	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	4757	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	4758	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	4759	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	4760
Kojto	91:031413cf7a89	4761
Kojto	91:031413cf7a89	4762	/* Peripheral: RADIO */
Kojto	91:031413cf7a89	4763	/* Description: The radio. */
Kojto	91:031413cf7a89	4764
Kojto	91:031413cf7a89	4765	/* Register: RADIO_SHORTS */
Kojto	97:433970e64889	4766	/* Description: Shortcuts for the radio. */
Kojto	91:031413cf7a89	4767
Kojto	91:031413cf7a89	4768	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
Kojto	91:031413cf7a89	4769	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
Kojto	91:031413cf7a89	4770	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
Kojto	91:031413cf7a89	4771	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4772	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4773
Kojto	91:031413cf7a89	4774	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
Kojto	91:031413cf7a89	4775	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
Kojto	91:031413cf7a89	4776	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
Kojto	91:031413cf7a89	4777	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4778	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4779
Kojto	91:031413cf7a89	4780	/* Bit 5 : Shortcut between END event and START task. */
Kojto	91:031413cf7a89	4781	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
Kojto	91:031413cf7a89	4782	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
Kojto	91:031413cf7a89	4783	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4784	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4785
Kojto	91:031413cf7a89	4786	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
Kojto	91:031413cf7a89	4787	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
Kojto	91:031413cf7a89	4788	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
Kojto	91:031413cf7a89	4789	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4790	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4791
Kojto	91:031413cf7a89	4792	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
Kojto	91:031413cf7a89	4793	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
Kojto	91:031413cf7a89	4794	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
Kojto	91:031413cf7a89	4795	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4796	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4797
Kojto	91:031413cf7a89	4798	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
Kojto	91:031413cf7a89	4799	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
Kojto	91:031413cf7a89	4800	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
Kojto	91:031413cf7a89	4801	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4802	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4803
Kojto	91:031413cf7a89	4804	/* Bit 1 : Shortcut between END event and DISABLE task. */
Kojto	91:031413cf7a89	4805	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
Kojto	91:031413cf7a89	4806	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
Kojto	91:031413cf7a89	4807	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4808	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4809
Kojto	91:031413cf7a89	4810	/* Bit 0 : Shortcut between READY event and START task. */
Kojto	91:031413cf7a89	4811	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
Kojto	91:031413cf7a89	4812	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
Kojto	91:031413cf7a89	4813	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	4814	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	4815
Kojto	91:031413cf7a89	4816	/* Register: RADIO_INTENSET */
Kojto	91:031413cf7a89	4817	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	4818
Kojto	91:031413cf7a89	4819	/* Bit 10 : Enable interrupt on BCMATCH event. */
Kojto	91:031413cf7a89	4820	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
Kojto	91:031413cf7a89	4821	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
Kojto	91:031413cf7a89	4822	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4823	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4824	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4825
Kojto	91:031413cf7a89	4826	/* Bit 7 : Enable interrupt on RSSIEND event. */
Kojto	91:031413cf7a89	4827	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
Kojto	91:031413cf7a89	4828	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
Kojto	91:031413cf7a89	4829	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4830	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4831	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4832
Kojto	91:031413cf7a89	4833	/* Bit 6 : Enable interrupt on DEVMISS event. */
Kojto	91:031413cf7a89	4834	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
Kojto	91:031413cf7a89	4835	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
Kojto	91:031413cf7a89	4836	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4837	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4838	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4839
Kojto	91:031413cf7a89	4840	/* Bit 5 : Enable interrupt on DEVMATCH event. */
Kojto	91:031413cf7a89	4841	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
Kojto	91:031413cf7a89	4842	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
Kojto	91:031413cf7a89	4843	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4844	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4845	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4846
Kojto	91:031413cf7a89	4847	/* Bit 4 : Enable interrupt on DISABLED event. */
Kojto	91:031413cf7a89	4848	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
Kojto	91:031413cf7a89	4849	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
Kojto	91:031413cf7a89	4850	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4851	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4852	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4853
Kojto	91:031413cf7a89	4854	/* Bit 3 : Enable interrupt on END event. */
Kojto	91:031413cf7a89	4855	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
Kojto	91:031413cf7a89	4856	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	91:031413cf7a89	4857	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4858	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4859	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4860
Kojto	91:031413cf7a89	4861	/* Bit 2 : Enable interrupt on PAYLOAD event. */
Kojto	91:031413cf7a89	4862	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
Kojto	91:031413cf7a89	4863	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
Kojto	91:031413cf7a89	4864	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4865	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4866	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4867
Kojto	91:031413cf7a89	4868	/* Bit 1 : Enable interrupt on ADDRESS event. */
Kojto	91:031413cf7a89	4869	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
Kojto	91:031413cf7a89	4870	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
Kojto	91:031413cf7a89	4871	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4872	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4873	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4874
Kojto	91:031413cf7a89	4875	/* Bit 0 : Enable interrupt on READY event. */
Kojto	91:031413cf7a89	4876	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
Kojto	91:031413cf7a89	4877	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
Kojto	91:031413cf7a89	4878	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4879	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4880	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	4881
Kojto	91:031413cf7a89	4882	/* Register: RADIO_INTENCLR */
Kojto	91:031413cf7a89	4883	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	4884
Kojto	91:031413cf7a89	4885	/* Bit 10 : Disable interrupt on BCMATCH event. */
Kojto	91:031413cf7a89	4886	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
Kojto	91:031413cf7a89	4887	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
Kojto	91:031413cf7a89	4888	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4889	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4890	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4891
Kojto	91:031413cf7a89	4892	/* Bit 7 : Disable interrupt on RSSIEND event. */
Kojto	91:031413cf7a89	4893	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
Kojto	91:031413cf7a89	4894	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
Kojto	91:031413cf7a89	4895	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4896	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4897	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4898
Kojto	91:031413cf7a89	4899	/* Bit 6 : Disable interrupt on DEVMISS event. */
Kojto	91:031413cf7a89	4900	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
Kojto	91:031413cf7a89	4901	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
Kojto	91:031413cf7a89	4902	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4903	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4904	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4905
Kojto	91:031413cf7a89	4906	/* Bit 5 : Disable interrupt on DEVMATCH event. */
Kojto	91:031413cf7a89	4907	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
Kojto	91:031413cf7a89	4908	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
Kojto	91:031413cf7a89	4909	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4910	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4911	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4912
Kojto	91:031413cf7a89	4913	/* Bit 4 : Disable interrupt on DISABLED event. */
Kojto	91:031413cf7a89	4914	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
Kojto	91:031413cf7a89	4915	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
Kojto	91:031413cf7a89	4916	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4917	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4918	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4919
Kojto	91:031413cf7a89	4920	/* Bit 3 : Disable interrupt on END event. */
Kojto	91:031413cf7a89	4921	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
Kojto	91:031413cf7a89	4922	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	91:031413cf7a89	4923	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4924	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4925	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4926
Kojto	91:031413cf7a89	4927	/* Bit 2 : Disable interrupt on PAYLOAD event. */
Kojto	91:031413cf7a89	4928	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
Kojto	91:031413cf7a89	4929	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
Kojto	91:031413cf7a89	4930	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4931	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4932	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4933
Kojto	91:031413cf7a89	4934	/* Bit 1 : Disable interrupt on ADDRESS event. */
Kojto	91:031413cf7a89	4935	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
Kojto	91:031413cf7a89	4936	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
Kojto	91:031413cf7a89	4937	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4938	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4939	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4940
Kojto	91:031413cf7a89	4941	/* Bit 0 : Disable interrupt on READY event. */
Kojto	91:031413cf7a89	4942	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
Kojto	91:031413cf7a89	4943	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
Kojto	91:031413cf7a89	4944	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	4945	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	4946	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	4947
Kojto	91:031413cf7a89	4948	/* Register: RADIO_CRCSTATUS */
Kojto	91:031413cf7a89	4949	/* Description: CRC status of received packet. */
Kojto	91:031413cf7a89	4950
Kojto	91:031413cf7a89	4951	/* Bit 0 : CRC status of received packet. */
Kojto	91:031413cf7a89	4952	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
Kojto	91:031413cf7a89	4953	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
Kojto	91:031413cf7a89	4954	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
Kojto	91:031413cf7a89	4955	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
Kojto	91:031413cf7a89	4956
Kojto	91:031413cf7a89	4957	/* Register: RADIO_RXMATCH */
Kojto	91:031413cf7a89	4958	/* Description: Received address. */
Kojto	91:031413cf7a89	4959
Kojto	91:031413cf7a89	4960	/* Bits 2..0 : Logical address in which previous packet was received. */
Kojto	91:031413cf7a89	4961	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
Kojto	91:031413cf7a89	4962	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
Kojto	91:031413cf7a89	4963
Kojto	91:031413cf7a89	4964	/* Register: RADIO_RXCRC */
Kojto	91:031413cf7a89	4965	/* Description: Received CRC. */
Kojto	91:031413cf7a89	4966
Kojto	91:031413cf7a89	4967	/* Bits 23..0 : CRC field of previously received packet. */
Kojto	91:031413cf7a89	4968	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
Kojto	91:031413cf7a89	4969	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
Kojto	91:031413cf7a89	4970
Kojto	91:031413cf7a89	4971	/* Register: RADIO_DAI */
Kojto	91:031413cf7a89	4972	/* Description: Device address match index. */
Kojto	91:031413cf7a89	4973
Kojto	97:433970e64889	4974	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
Kojto	91:031413cf7a89	4975	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
Kojto	91:031413cf7a89	4976	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
Kojto	91:031413cf7a89	4977
Kojto	91:031413cf7a89	4978	/* Register: RADIO_FREQUENCY */
Kojto	91:031413cf7a89	4979	/* Description: Frequency. */
Kojto	91:031413cf7a89	4980
Kojto	91:031413cf7a89	4981	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
Kojto	91:031413cf7a89	4982	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	91:031413cf7a89	4983	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	91:031413cf7a89	4984
Kojto	91:031413cf7a89	4985	/* Register: RADIO_TXPOWER */
Kojto	91:031413cf7a89	4986	/* Description: Output power. */
Kojto	91:031413cf7a89	4987
Kojto	91:031413cf7a89	4988	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
Kojto	91:031413cf7a89	4989	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
Kojto	91:031413cf7a89	4990	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
Kojto	122:f9eeca106725	4991	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
Kojto	91:031413cf7a89	4992	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
Kojto	122:f9eeca106725	4993	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
Kojto	122:f9eeca106725	4994	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
Kojto	122:f9eeca106725	4995	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
Kojto	122:f9eeca106725	4996	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
Kojto	91:031413cf7a89	4997	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
Kojto	122:f9eeca106725	4998	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
Kojto	91:031413cf7a89	4999
Kojto	91:031413cf7a89	5000	/* Register: RADIO_MODE */
Kojto	91:031413cf7a89	5001	/* Description: Data rate and modulation. */
Kojto	91:031413cf7a89	5002
Kojto	91:031413cf7a89	5003	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
Kojto	91:031413cf7a89	5004	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
Kojto	91:031413cf7a89	5005	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
Kojto	91:031413cf7a89	5006	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
Kojto	91:031413cf7a89	5007	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
Kojto	91:031413cf7a89	5008	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
Kojto	91:031413cf7a89	5009	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
Kojto	91:031413cf7a89	5010
Kojto	91:031413cf7a89	5011	/* Register: RADIO_PCNF0 */
Kojto	91:031413cf7a89	5012	/* Description: Packet configuration 0. */
Kojto	91:031413cf7a89	5013
Kojto	91:031413cf7a89	5014	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
Kojto	91:031413cf7a89	5015	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
Kojto	91:031413cf7a89	5016	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
Kojto	91:031413cf7a89	5017
Kojto	91:031413cf7a89	5018	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
Kojto	91:031413cf7a89	5019	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
Kojto	91:031413cf7a89	5020	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
Kojto	91:031413cf7a89	5021
Kojto	91:031413cf7a89	5022	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
Kojto	91:031413cf7a89	5023	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
Kojto	91:031413cf7a89	5024	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
Kojto	91:031413cf7a89	5025
Kojto	91:031413cf7a89	5026	/* Register: RADIO_PCNF1 */
Kojto	91:031413cf7a89	5027	/* Description: Packet configuration 1. */
Kojto	91:031413cf7a89	5028
Kojto	91:031413cf7a89	5029	/* Bit 25 : Packet whitening enable. */
Kojto	91:031413cf7a89	5030	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
Kojto	91:031413cf7a89	5031	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
Kojto	91:031413cf7a89	5032	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
Kojto	91:031413cf7a89	5033	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
Kojto	91:031413cf7a89	5034
Kojto	91:031413cf7a89	5035	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
Kojto	91:031413cf7a89	5036	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
Kojto	91:031413cf7a89	5037	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
Kojto	91:031413cf7a89	5038	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
Kojto	91:031413cf7a89	5039	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
Kojto	91:031413cf7a89	5040
Kojto	91:031413cf7a89	5041	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
Kojto	91:031413cf7a89	5042	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
Kojto	91:031413cf7a89	5043	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
Kojto	91:031413cf7a89	5044
Kojto	91:031413cf7a89	5045	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
Kojto	91:031413cf7a89	5046	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
Kojto	91:031413cf7a89	5047	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
Kojto	91:031413cf7a89	5048
Kojto	91:031413cf7a89	5049	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
Kojto	91:031413cf7a89	5050	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
Kojto	91:031413cf7a89	5051	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
Kojto	91:031413cf7a89	5052
Kojto	91:031413cf7a89	5053	/* Register: RADIO_PREFIX0 */
Kojto	91:031413cf7a89	5054	/* Description: Prefixes bytes for logical addresses 0 to 3. */
Kojto	91:031413cf7a89	5055
Kojto	91:031413cf7a89	5056	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
Kojto	91:031413cf7a89	5057	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
Kojto	91:031413cf7a89	5058	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
Kojto	91:031413cf7a89	5059
Kojto	91:031413cf7a89	5060	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
Kojto	91:031413cf7a89	5061	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
Kojto	91:031413cf7a89	5062	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
Kojto	91:031413cf7a89	5063
Kojto	91:031413cf7a89	5064	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
Kojto	91:031413cf7a89	5065	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
Kojto	91:031413cf7a89	5066	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
Kojto	91:031413cf7a89	5067
Kojto	91:031413cf7a89	5068	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
Kojto	91:031413cf7a89	5069	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
Kojto	91:031413cf7a89	5070	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
Kojto	91:031413cf7a89	5071
Kojto	91:031413cf7a89	5072	/* Register: RADIO_PREFIX1 */
Kojto	91:031413cf7a89	5073	/* Description: Prefixes bytes for logical addresses 4 to 7. */
Kojto	91:031413cf7a89	5074
Kojto	91:031413cf7a89	5075	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
Kojto	91:031413cf7a89	5076	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
Kojto	91:031413cf7a89	5077	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
Kojto	91:031413cf7a89	5078
Kojto	91:031413cf7a89	5079	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
Kojto	91:031413cf7a89	5080	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
Kojto	91:031413cf7a89	5081	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
Kojto	91:031413cf7a89	5082
Kojto	91:031413cf7a89	5083	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
Kojto	91:031413cf7a89	5084	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
Kojto	91:031413cf7a89	5085	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
Kojto	91:031413cf7a89	5086
Kojto	91:031413cf7a89	5087	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
Kojto	91:031413cf7a89	5088	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
Kojto	91:031413cf7a89	5089	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
Kojto	91:031413cf7a89	5090
Kojto	91:031413cf7a89	5091	/* Register: RADIO_TXADDRESS */
Kojto	91:031413cf7a89	5092	/* Description: Transmit address select. */
Kojto	91:031413cf7a89	5093
Kojto	91:031413cf7a89	5094	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
Kojto	91:031413cf7a89	5095	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
Kojto	91:031413cf7a89	5096	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
Kojto	91:031413cf7a89	5097
Kojto	91:031413cf7a89	5098	/* Register: RADIO_RXADDRESSES */
Kojto	91:031413cf7a89	5099	/* Description: Receive address select. */
Kojto	91:031413cf7a89	5100
Kojto	91:031413cf7a89	5101	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
Kojto	91:031413cf7a89	5102	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
Kojto	91:031413cf7a89	5103	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
Kojto	91:031413cf7a89	5104	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
Kojto	91:031413cf7a89	5105	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
Kojto	91:031413cf7a89	5106
Kojto	91:031413cf7a89	5107	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
Kojto	91:031413cf7a89	5108	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
Kojto	91:031413cf7a89	5109	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
Kojto	91:031413cf7a89	5110	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
Kojto	91:031413cf7a89	5111	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
Kojto	91:031413cf7a89	5112
Kojto	91:031413cf7a89	5113	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
Kojto	91:031413cf7a89	5114	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
Kojto	91:031413cf7a89	5115	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
Kojto	91:031413cf7a89	5116	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
Kojto	91:031413cf7a89	5117	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
Kojto	91:031413cf7a89	5118
Kojto	91:031413cf7a89	5119	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
Kojto	91:031413cf7a89	5120	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
Kojto	91:031413cf7a89	5121	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
Kojto	91:031413cf7a89	5122	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
Kojto	91:031413cf7a89	5123	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
Kojto	91:031413cf7a89	5124
Kojto	91:031413cf7a89	5125	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
Kojto	91:031413cf7a89	5126	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
Kojto	91:031413cf7a89	5127	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
Kojto	91:031413cf7a89	5128	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
Kojto	91:031413cf7a89	5129	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
Kojto	91:031413cf7a89	5130
Kojto	91:031413cf7a89	5131	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
Kojto	91:031413cf7a89	5132	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
Kojto	91:031413cf7a89	5133	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
Kojto	91:031413cf7a89	5134	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
Kojto	91:031413cf7a89	5135	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
Kojto	91:031413cf7a89	5136
Kojto	91:031413cf7a89	5137	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
Kojto	91:031413cf7a89	5138	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
Kojto	91:031413cf7a89	5139	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
Kojto	91:031413cf7a89	5140	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
Kojto	91:031413cf7a89	5141	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
Kojto	91:031413cf7a89	5142
Kojto	91:031413cf7a89	5143	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
Kojto	91:031413cf7a89	5144	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
Kojto	91:031413cf7a89	5145	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
Kojto	91:031413cf7a89	5146	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
Kojto	91:031413cf7a89	5147	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
Kojto	91:031413cf7a89	5148
Kojto	91:031413cf7a89	5149	/* Register: RADIO_CRCCNF */
Kojto	91:031413cf7a89	5150	/* Description: CRC configuration. */
Kojto	91:031413cf7a89	5151
Kojto	91:031413cf7a89	5152	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
Kojto	97:433970e64889	5153	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
Kojto	97:433970e64889	5154	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
Kojto	97:433970e64889	5155	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
Kojto	97:433970e64889	5156	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
Kojto	91:031413cf7a89	5157
Kojto	91:031413cf7a89	5158	/* Bits 1..0 : CRC length. Decision point: START task. */
Kojto	91:031413cf7a89	5159	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
Kojto	91:031413cf7a89	5160	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
Kojto	91:031413cf7a89	5161	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
Kojto	91:031413cf7a89	5162	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
Kojto	91:031413cf7a89	5163	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
Kojto	91:031413cf7a89	5164	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
Kojto	91:031413cf7a89	5165
Kojto	91:031413cf7a89	5166	/* Register: RADIO_CRCPOLY */
Kojto	91:031413cf7a89	5167	/* Description: CRC polynomial. */
Kojto	91:031413cf7a89	5168
Kojto	97:433970e64889	5169	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
Kojto	97:433970e64889	5170	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
Kojto	97:433970e64889	5171	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
Kojto	91:031413cf7a89	5172
Kojto	91:031413cf7a89	5173	/* Register: RADIO_CRCINIT */
Kojto	91:031413cf7a89	5174	/* Description: CRC initial value. */
Kojto	91:031413cf7a89	5175
Kojto	91:031413cf7a89	5176	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
Kojto	91:031413cf7a89	5177	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
Kojto	91:031413cf7a89	5178	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
Kojto	91:031413cf7a89	5179
Kojto	91:031413cf7a89	5180	/* Register: RADIO_TEST */
Kojto	91:031413cf7a89	5181	/* Description: Test features enable register. */
Kojto	91:031413cf7a89	5182
Kojto	91:031413cf7a89	5183	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
Kojto	97:433970e64889	5184	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
Kojto	97:433970e64889	5185	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
Kojto	97:433970e64889	5186	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
Kojto	97:433970e64889	5187	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
Kojto	91:031413cf7a89	5188
Kojto	91:031413cf7a89	5189	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
Kojto	97:433970e64889	5190	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
Kojto	97:433970e64889	5191	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
Kojto	97:433970e64889	5192	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
Kojto	97:433970e64889	5193	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
Kojto	91:031413cf7a89	5194
Kojto	91:031413cf7a89	5195	/* Register: RADIO_TIFS */
Kojto	91:031413cf7a89	5196	/* Description: Inter Frame Spacing in microseconds. */
Kojto	91:031413cf7a89	5197
Kojto	91:031413cf7a89	5198	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
Kojto	91:031413cf7a89	5199	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
Kojto	91:031413cf7a89	5200	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
Kojto	91:031413cf7a89	5201
Kojto	91:031413cf7a89	5202	/* Register: RADIO_RSSISAMPLE */
Kojto	91:031413cf7a89	5203	/* Description: RSSI sample. */
Kojto	91:031413cf7a89	5204
Kojto	91:031413cf7a89	5205	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
Kojto	91:031413cf7a89	5206	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
Kojto	91:031413cf7a89	5207	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
Kojto	91:031413cf7a89	5208
Kojto	91:031413cf7a89	5209	/* Register: RADIO_STATE */
Kojto	91:031413cf7a89	5210	/* Description: Current radio state. */
Kojto	91:031413cf7a89	5211
Kojto	91:031413cf7a89	5212	/* Bits 3..0 : Current radio state. */
Kojto	91:031413cf7a89	5213	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
Kojto	91:031413cf7a89	5214	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
Kojto	91:031413cf7a89	5215	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
Kojto	91:031413cf7a89	5216	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
Kojto	91:031413cf7a89	5217	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
Kojto	91:031413cf7a89	5218	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
Kojto	91:031413cf7a89	5219	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
Kojto	91:031413cf7a89	5220	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
Kojto	91:031413cf7a89	5221	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
Kojto	91:031413cf7a89	5222	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
Kojto	91:031413cf7a89	5223	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
Kojto	91:031413cf7a89	5224
Kojto	91:031413cf7a89	5225	/* Register: RADIO_DATAWHITEIV */
Kojto	91:031413cf7a89	5226	/* Description: Data whitening initial value. */
Kojto	91:031413cf7a89	5227
Kojto	97:433970e64889	5228	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
Kojto	91:031413cf7a89	5229	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
Kojto	97:433970e64889	5230	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
Kojto	91:031413cf7a89	5231
Kojto	91:031413cf7a89	5232	/* Register: RADIO_DAP */
Kojto	91:031413cf7a89	5233	/* Description: Device address prefix. */
Kojto	91:031413cf7a89	5234
Kojto	91:031413cf7a89	5235	/* Bits 15..0 : Device address prefix. */
Kojto	91:031413cf7a89	5236	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
Kojto	91:031413cf7a89	5237	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
Kojto	91:031413cf7a89	5238
Kojto	91:031413cf7a89	5239	/* Register: RADIO_DACNF */
Kojto	91:031413cf7a89	5240	/* Description: Device address match configuration. */
Kojto	91:031413cf7a89	5241
Kojto	91:031413cf7a89	5242	/* Bit 15 : TxAdd for device address 7. */
Kojto	91:031413cf7a89	5243	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
Kojto	91:031413cf7a89	5244	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
Kojto	91:031413cf7a89	5245
Kojto	91:031413cf7a89	5246	/* Bit 14 : TxAdd for device address 6. */
Kojto	91:031413cf7a89	5247	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
Kojto	91:031413cf7a89	5248	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
Kojto	91:031413cf7a89	5249
Kojto	91:031413cf7a89	5250	/* Bit 13 : TxAdd for device address 5. */
Kojto	91:031413cf7a89	5251	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
Kojto	91:031413cf7a89	5252	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
Kojto	91:031413cf7a89	5253
Kojto	91:031413cf7a89	5254	/* Bit 12 : TxAdd for device address 4. */
Kojto	91:031413cf7a89	5255	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
Kojto	91:031413cf7a89	5256	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
Kojto	91:031413cf7a89	5257
Kojto	91:031413cf7a89	5258	/* Bit 11 : TxAdd for device address 3. */
Kojto	91:031413cf7a89	5259	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
Kojto	91:031413cf7a89	5260	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
Kojto	91:031413cf7a89	5261
Kojto	91:031413cf7a89	5262	/* Bit 10 : TxAdd for device address 2. */
Kojto	91:031413cf7a89	5263	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
Kojto	91:031413cf7a89	5264	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
Kojto	91:031413cf7a89	5265
Kojto	91:031413cf7a89	5266	/* Bit 9 : TxAdd for device address 1. */
Kojto	91:031413cf7a89	5267	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
Kojto	91:031413cf7a89	5268	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
Kojto	91:031413cf7a89	5269
Kojto	91:031413cf7a89	5270	/* Bit 8 : TxAdd for device address 0. */
Kojto	91:031413cf7a89	5271	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
Kojto	91:031413cf7a89	5272	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
Kojto	91:031413cf7a89	5273
Kojto	91:031413cf7a89	5274	/* Bit 7 : Enable or disable device address matching using device address 7. */
Kojto	91:031413cf7a89	5275	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
Kojto	91:031413cf7a89	5276	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
Kojto	91:031413cf7a89	5277	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	5278	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	5279
Kojto	91:031413cf7a89	5280	/* Bit 6 : Enable or disable device address matching using device address 6. */
Kojto	91:031413cf7a89	5281	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
Kojto	91:031413cf7a89	5282	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
Kojto	91:031413cf7a89	5283	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	5284	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	5285
Kojto	91:031413cf7a89	5286	/* Bit 5 : Enable or disable device address matching using device address 5. */
Kojto	91:031413cf7a89	5287	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
Kojto	91:031413cf7a89	5288	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
Kojto	91:031413cf7a89	5289	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	5290	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	5291
Kojto	91:031413cf7a89	5292	/* Bit 4 : Enable or disable device address matching using device address 4. */
Kojto	91:031413cf7a89	5293	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
Kojto	91:031413cf7a89	5294	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
Kojto	91:031413cf7a89	5295	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	5296	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	5297
Kojto	91:031413cf7a89	5298	/* Bit 3 : Enable or disable device address matching using device address 3. */
Kojto	91:031413cf7a89	5299	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
Kojto	91:031413cf7a89	5300	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
Kojto	91:031413cf7a89	5301	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	5302	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	5303
Kojto	91:031413cf7a89	5304	/* Bit 2 : Enable or disable device address matching using device address 2. */
Kojto	91:031413cf7a89	5305	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
Kojto	91:031413cf7a89	5306	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
Kojto	91:031413cf7a89	5307	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	5308	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	5309
Kojto	91:031413cf7a89	5310	/* Bit 1 : Enable or disable device address matching using device address 1. */
Kojto	91:031413cf7a89	5311	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
Kojto	91:031413cf7a89	5312	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
Kojto	91:031413cf7a89	5313	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	5314	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	5315
Kojto	91:031413cf7a89	5316	/* Bit 0 : Enable or disable device address matching using device address 0. */
Kojto	91:031413cf7a89	5317	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
Kojto	91:031413cf7a89	5318	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
Kojto	91:031413cf7a89	5319	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
Kojto	91:031413cf7a89	5320	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
Kojto	91:031413cf7a89	5321
Kojto	91:031413cf7a89	5322	/* Register: RADIO_OVERRIDE0 */
Kojto	91:031413cf7a89	5323	/* Description: Trim value override register 0. */
Kojto	91:031413cf7a89	5324
Kojto	97:433970e64889	5325	/* Bits 31..0 : Trim value override 0. */
Kojto	91:031413cf7a89	5326	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
Kojto	91:031413cf7a89	5327	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
Kojto	91:031413cf7a89	5328
Kojto	91:031413cf7a89	5329	/* Register: RADIO_OVERRIDE1 */
Kojto	91:031413cf7a89	5330	/* Description: Trim value override register 1. */
Kojto	91:031413cf7a89	5331
Kojto	97:433970e64889	5332	/* Bits 31..0 : Trim value override 1. */
Kojto	91:031413cf7a89	5333	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
Kojto	91:031413cf7a89	5334	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
Kojto	91:031413cf7a89	5335
Kojto	91:031413cf7a89	5336	/* Register: RADIO_OVERRIDE2 */
Kojto	91:031413cf7a89	5337	/* Description: Trim value override register 2. */
Kojto	91:031413cf7a89	5338
Kojto	97:433970e64889	5339	/* Bits 31..0 : Trim value override 2. */
Kojto	91:031413cf7a89	5340	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
Kojto	91:031413cf7a89	5341	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
Kojto	91:031413cf7a89	5342
Kojto	91:031413cf7a89	5343	/* Register: RADIO_OVERRIDE3 */
Kojto	91:031413cf7a89	5344	/* Description: Trim value override register 3. */
Kojto	91:031413cf7a89	5345
Kojto	97:433970e64889	5346	/* Bits 31..0 : Trim value override 3. */
Kojto	91:031413cf7a89	5347	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
Kojto	91:031413cf7a89	5348	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
Kojto	91:031413cf7a89	5349
Kojto	91:031413cf7a89	5350	/* Register: RADIO_OVERRIDE4 */
Kojto	91:031413cf7a89	5351	/* Description: Trim value override register 4. */
Kojto	91:031413cf7a89	5352
Kojto	91:031413cf7a89	5353	/* Bit 31 : Enable or disable override of default trim values. */
Kojto	91:031413cf7a89	5354	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	5355	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	5356	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
Kojto	91:031413cf7a89	5357	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
Kojto	91:031413cf7a89	5358
Kojto	97:433970e64889	5359	/* Bits 27..0 : Trim value override 4. */
Kojto	91:031413cf7a89	5360	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
Kojto	91:031413cf7a89	5361	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
Kojto	91:031413cf7a89	5362
Kojto	91:031413cf7a89	5363	/* Register: RADIO_POWER */
Kojto	91:031413cf7a89	5364	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	5365
Kojto	91:031413cf7a89	5366	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	5367	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	5368	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	5369	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	5370	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	5371
Kojto	91:031413cf7a89	5372
Kojto	91:031413cf7a89	5373	/* Peripheral: RNG */
Kojto	91:031413cf7a89	5374	/* Description: Random Number Generator. */
Kojto	91:031413cf7a89	5375
Kojto	91:031413cf7a89	5376	/* Register: RNG_SHORTS */
Kojto	97:433970e64889	5377	/* Description: Shortcuts for the RNG. */
Kojto	97:433970e64889	5378
Kojto	97:433970e64889	5379	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
Kojto	91:031413cf7a89	5380	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
Kojto	91:031413cf7a89	5381	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
Kojto	91:031413cf7a89	5382	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	5383	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	5384
Kojto	91:031413cf7a89	5385	/* Register: RNG_INTENSET */
Kojto	91:031413cf7a89	5386	/* Description: Interrupt enable set register */
Kojto	91:031413cf7a89	5387
Kojto	91:031413cf7a89	5388	/* Bit 0 : Enable interrupt on VALRDY event. */
Kojto	91:031413cf7a89	5389	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
Kojto	91:031413cf7a89	5390	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
Kojto	91:031413cf7a89	5391	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5392	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5393	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5394
Kojto	91:031413cf7a89	5395	/* Register: RNG_INTENCLR */
Kojto	91:031413cf7a89	5396	/* Description: Interrupt enable clear register */
Kojto	91:031413cf7a89	5397
Kojto	91:031413cf7a89	5398	/* Bit 0 : Disable interrupt on VALRDY event. */
Kojto	91:031413cf7a89	5399	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
Kojto	91:031413cf7a89	5400	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
Kojto	91:031413cf7a89	5401	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5402	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5403	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5404
Kojto	91:031413cf7a89	5405	/* Register: RNG_CONFIG */
Kojto	91:031413cf7a89	5406	/* Description: Configuration register. */
Kojto	91:031413cf7a89	5407
Kojto	91:031413cf7a89	5408	/* Bit 0 : Digital error correction enable. */
Kojto	91:031413cf7a89	5409	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
Kojto	91:031413cf7a89	5410	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
Kojto	91:031413cf7a89	5411	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
Kojto	91:031413cf7a89	5412	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
Kojto	91:031413cf7a89	5413
Kojto	91:031413cf7a89	5414	/* Register: RNG_VALUE */
Kojto	91:031413cf7a89	5415	/* Description: RNG random number. */
Kojto	91:031413cf7a89	5416
Kojto	91:031413cf7a89	5417	/* Bits 7..0 : Generated random number. */
Kojto	91:031413cf7a89	5418	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
Kojto	91:031413cf7a89	5419	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
Kojto	91:031413cf7a89	5420
Kojto	91:031413cf7a89	5421	/* Register: RNG_POWER */
Kojto	91:031413cf7a89	5422	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	5423
Kojto	91:031413cf7a89	5424	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	5425	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	5426	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	5427	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	5428	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	5429
Kojto	91:031413cf7a89	5430
Kojto	91:031413cf7a89	5431	/* Peripheral: RTC */
Kojto	91:031413cf7a89	5432	/* Description: Real time counter 0. */
Kojto	91:031413cf7a89	5433
Kojto	91:031413cf7a89	5434	/* Register: RTC_INTENSET */
Kojto	91:031413cf7a89	5435	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	5436
Kojto	91:031413cf7a89	5437	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
Kojto	91:031413cf7a89	5438	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	91:031413cf7a89	5439	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	91:031413cf7a89	5440	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5441	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5442	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5443
Kojto	91:031413cf7a89	5444	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
Kojto	91:031413cf7a89	5445	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	91:031413cf7a89	5446	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	91:031413cf7a89	5447	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5448	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5449	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5450
Kojto	91:031413cf7a89	5451	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
Kojto	91:031413cf7a89	5452	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	91:031413cf7a89	5453	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	91:031413cf7a89	5454	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5455	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5456	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5457
Kojto	91:031413cf7a89	5458	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
Kojto	91:031413cf7a89	5459	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	91:031413cf7a89	5460	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	91:031413cf7a89	5461	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5462	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5463	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5464
Kojto	91:031413cf7a89	5465	/* Bit 1 : Enable interrupt on OVRFLW event. */
Kojto	91:031413cf7a89	5466	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	91:031413cf7a89	5467	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	91:031413cf7a89	5468	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5469	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5470	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5471
Kojto	91:031413cf7a89	5472	/* Bit 0 : Enable interrupt on TICK event. */
Kojto	91:031413cf7a89	5473	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	91:031413cf7a89	5474	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	91:031413cf7a89	5475	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5476	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5477	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5478
Kojto	91:031413cf7a89	5479	/* Register: RTC_INTENCLR */
Kojto	91:031413cf7a89	5480	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	5481
Kojto	91:031413cf7a89	5482	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
Kojto	91:031413cf7a89	5483	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	91:031413cf7a89	5484	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	91:031413cf7a89	5485	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5486	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5487	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5488
Kojto	91:031413cf7a89	5489	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
Kojto	91:031413cf7a89	5490	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	91:031413cf7a89	5491	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	91:031413cf7a89	5492	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5493	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5494	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5495
Kojto	91:031413cf7a89	5496	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
Kojto	91:031413cf7a89	5497	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	91:031413cf7a89	5498	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	91:031413cf7a89	5499	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5500	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5501	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5502
Kojto	91:031413cf7a89	5503	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
Kojto	91:031413cf7a89	5504	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	91:031413cf7a89	5505	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	91:031413cf7a89	5506	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5507	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5508	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5509
Kojto	91:031413cf7a89	5510	/* Bit 1 : Disable interrupt on OVRFLW event. */
Kojto	91:031413cf7a89	5511	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	91:031413cf7a89	5512	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	91:031413cf7a89	5513	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5514	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5515	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5516
Kojto	91:031413cf7a89	5517	/* Bit 0 : Disable interrupt on TICK event. */
Kojto	91:031413cf7a89	5518	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	91:031413cf7a89	5519	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	91:031413cf7a89	5520	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5521	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5522	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5523
Kojto	91:031413cf7a89	5524	/* Register: RTC_EVTEN */
Kojto	91:031413cf7a89	5525	/* Description: Configures event enable routing to PPI for each RTC event. */
Kojto	91:031413cf7a89	5526
Kojto	91:031413cf7a89	5527	/* Bit 19 : COMPARE[3] event enable. */
Kojto	91:031413cf7a89	5528	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	91:031413cf7a89	5529	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	91:031413cf7a89	5530	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5531	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5532
Kojto	91:031413cf7a89	5533	/* Bit 18 : COMPARE[2] event enable. */
Kojto	91:031413cf7a89	5534	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	91:031413cf7a89	5535	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	91:031413cf7a89	5536	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5537	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5538
Kojto	91:031413cf7a89	5539	/* Bit 17 : COMPARE[1] event enable. */
Kojto	91:031413cf7a89	5540	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	91:031413cf7a89	5541	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	91:031413cf7a89	5542	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5543	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5544
Kojto	91:031413cf7a89	5545	/* Bit 16 : COMPARE[0] event enable. */
Kojto	91:031413cf7a89	5546	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	91:031413cf7a89	5547	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	91:031413cf7a89	5548	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5549	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5550
Kojto	91:031413cf7a89	5551	/* Bit 1 : OVRFLW event enable. */
Kojto	91:031413cf7a89	5552	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	91:031413cf7a89	5553	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	91:031413cf7a89	5554	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5555	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5556
Kojto	91:031413cf7a89	5557	/* Bit 0 : TICK event enable. */
Kojto	91:031413cf7a89	5558	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	91:031413cf7a89	5559	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	91:031413cf7a89	5560	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5561	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5562
Kojto	91:031413cf7a89	5563	/* Register: RTC_EVTENSET */
Kojto	91:031413cf7a89	5564	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
Kojto	91:031413cf7a89	5565
Kojto	91:031413cf7a89	5566	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
Kojto	91:031413cf7a89	5567	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	91:031413cf7a89	5568	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	91:031413cf7a89	5569	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5570	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5571	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
Kojto	91:031413cf7a89	5572
Kojto	91:031413cf7a89	5573	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
Kojto	91:031413cf7a89	5574	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	91:031413cf7a89	5575	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	91:031413cf7a89	5576	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5577	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5578	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
Kojto	91:031413cf7a89	5579
Kojto	91:031413cf7a89	5580	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
Kojto	91:031413cf7a89	5581	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	91:031413cf7a89	5582	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	91:031413cf7a89	5583	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5584	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5585	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
Kojto	91:031413cf7a89	5586
Kojto	91:031413cf7a89	5587	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
Kojto	91:031413cf7a89	5588	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	91:031413cf7a89	5589	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	91:031413cf7a89	5590	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5591	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5592	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
Kojto	91:031413cf7a89	5593
Kojto	91:031413cf7a89	5594	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
Kojto	91:031413cf7a89	5595	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	91:031413cf7a89	5596	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	91:031413cf7a89	5597	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5598	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5599	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
Kojto	91:031413cf7a89	5600
Kojto	91:031413cf7a89	5601	/* Bit 0 : Enable routing to PPI of TICK event. */
Kojto	91:031413cf7a89	5602	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	91:031413cf7a89	5603	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	91:031413cf7a89	5604	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5605	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5606	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
Kojto	91:031413cf7a89	5607
Kojto	91:031413cf7a89	5608	/* Register: RTC_EVTENCLR */
Kojto	91:031413cf7a89	5609	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
Kojto	91:031413cf7a89	5610
Kojto	91:031413cf7a89	5611	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
Kojto	91:031413cf7a89	5612	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	91:031413cf7a89	5613	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	91:031413cf7a89	5614	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5615	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5616	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
Kojto	91:031413cf7a89	5617
Kojto	91:031413cf7a89	5618	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
Kojto	91:031413cf7a89	5619	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	91:031413cf7a89	5620	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	91:031413cf7a89	5621	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5622	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5623	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
Kojto	91:031413cf7a89	5624
Kojto	91:031413cf7a89	5625	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
Kojto	91:031413cf7a89	5626	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	91:031413cf7a89	5627	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	91:031413cf7a89	5628	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5629	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5630	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
Kojto	91:031413cf7a89	5631
Kojto	91:031413cf7a89	5632	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
Kojto	91:031413cf7a89	5633	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	91:031413cf7a89	5634	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	91:031413cf7a89	5635	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5636	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5637	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
Kojto	91:031413cf7a89	5638
Kojto	91:031413cf7a89	5639	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
Kojto	91:031413cf7a89	5640	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
Kojto	91:031413cf7a89	5641	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
Kojto	91:031413cf7a89	5642	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5643	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5644	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
Kojto	91:031413cf7a89	5645
Kojto	91:031413cf7a89	5646	/* Bit 0 : Disable routing to PPI of TICK event. */
Kojto	91:031413cf7a89	5647	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
Kojto	91:031413cf7a89	5648	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
Kojto	91:031413cf7a89	5649	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
Kojto	91:031413cf7a89	5650	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
Kojto	91:031413cf7a89	5651	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
Kojto	91:031413cf7a89	5652
Kojto	91:031413cf7a89	5653	/* Register: RTC_COUNTER */
Kojto	91:031413cf7a89	5654	/* Description: Current COUNTER value. */
Kojto	91:031413cf7a89	5655
Kojto	91:031413cf7a89	5656	/* Bits 23..0 : Counter value. */
Kojto	91:031413cf7a89	5657	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
Kojto	91:031413cf7a89	5658	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
Kojto	91:031413cf7a89	5659
Kojto	91:031413cf7a89	5660	/* Register: RTC_PRESCALER */
Kojto	91:031413cf7a89	5661	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
Kojto	91:031413cf7a89	5662
Kojto	91:031413cf7a89	5663	/* Bits 11..0 : RTC PRESCALER value. */
Kojto	91:031413cf7a89	5664	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
Kojto	91:031413cf7a89	5665	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
Kojto	91:031413cf7a89	5666
Kojto	91:031413cf7a89	5667	/* Register: RTC_CC */
Kojto	91:031413cf7a89	5668	/* Description: Capture/compare registers. */
Kojto	91:031413cf7a89	5669
Kojto	91:031413cf7a89	5670	/* Bits 23..0 : Compare value. */
Kojto	91:031413cf7a89	5671	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
Kojto	91:031413cf7a89	5672	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
Kojto	91:031413cf7a89	5673
Kojto	91:031413cf7a89	5674	/* Register: RTC_POWER */
Kojto	91:031413cf7a89	5675	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	5676
Kojto	91:031413cf7a89	5677	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	5678	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	5679	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	5680	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	5681	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	5682
Kojto	91:031413cf7a89	5683
Kojto	91:031413cf7a89	5684	/* Peripheral: SPI */
Kojto	91:031413cf7a89	5685	/* Description: SPI master 0. */
Kojto	91:031413cf7a89	5686
Kojto	91:031413cf7a89	5687	/* Register: SPI_INTENSET */
Kojto	91:031413cf7a89	5688	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	5689
Kojto	91:031413cf7a89	5690	/* Bit 2 : Enable interrupt on READY event. */
Kojto	91:031413cf7a89	5691	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
Kojto	91:031413cf7a89	5692	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
Kojto	91:031413cf7a89	5693	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5694	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5695	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5696
Kojto	91:031413cf7a89	5697	/* Register: SPI_INTENCLR */
Kojto	91:031413cf7a89	5698	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	5699
Kojto	91:031413cf7a89	5700	/* Bit 2 : Disable interrupt on READY event. */
Kojto	91:031413cf7a89	5701	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
Kojto	91:031413cf7a89	5702	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
Kojto	91:031413cf7a89	5703	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5704	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5705	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5706
Kojto	91:031413cf7a89	5707	/* Register: SPI_ENABLE */
Kojto	91:031413cf7a89	5708	/* Description: Enable SPI. */
Kojto	91:031413cf7a89	5709
Kojto	91:031413cf7a89	5710	/* Bits 2..0 : Enable or disable SPI. */
Kojto	91:031413cf7a89	5711	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	5712	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	5713	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
Kojto	91:031413cf7a89	5714	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
Kojto	91:031413cf7a89	5715
Kojto	91:031413cf7a89	5716	/* Register: SPI_RXD */
Kojto	91:031413cf7a89	5717	/* Description: RX data. */
Kojto	91:031413cf7a89	5718
Kojto	91:031413cf7a89	5719	/* Bits 7..0 : RX data from last transfer. */
Kojto	91:031413cf7a89	5720	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
Kojto	91:031413cf7a89	5721	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
Kojto	91:031413cf7a89	5722
Kojto	91:031413cf7a89	5723	/* Register: SPI_TXD */
Kojto	91:031413cf7a89	5724	/* Description: TX data. */
Kojto	91:031413cf7a89	5725
Kojto	91:031413cf7a89	5726	/* Bits 7..0 : TX data for next transfer. */
Kojto	91:031413cf7a89	5727	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
Kojto	91:031413cf7a89	5728	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
Kojto	91:031413cf7a89	5729
Kojto	91:031413cf7a89	5730	/* Register: SPI_FREQUENCY */
Kojto	91:031413cf7a89	5731	/* Description: SPI frequency */
Kojto	91:031413cf7a89	5732
Kojto	91:031413cf7a89	5733	/* Bits 31..0 : SPI data rate. */
Kojto	91:031413cf7a89	5734	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	91:031413cf7a89	5735	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	91:031413cf7a89	5736	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
Kojto	91:031413cf7a89	5737	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
Kojto	91:031413cf7a89	5738	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
Kojto	91:031413cf7a89	5739	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
Kojto	91:031413cf7a89	5740	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
Kojto	91:031413cf7a89	5741	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
Kojto	91:031413cf7a89	5742	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
Kojto	91:031413cf7a89	5743
Kojto	91:031413cf7a89	5744	/* Register: SPI_CONFIG */
Kojto	91:031413cf7a89	5745	/* Description: Configuration register. */
Kojto	91:031413cf7a89	5746
Kojto	91:031413cf7a89	5747	/* Bit 2 : Serial clock (SCK) polarity. */
Kojto	91:031413cf7a89	5748	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
Kojto	91:031413cf7a89	5749	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
Kojto	91:031413cf7a89	5750	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
Kojto	91:031413cf7a89	5751	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
Kojto	91:031413cf7a89	5752
Kojto	91:031413cf7a89	5753	/* Bit 1 : Serial clock (SCK) phase. */
Kojto	91:031413cf7a89	5754	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
Kojto	91:031413cf7a89	5755	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
Kojto	91:031413cf7a89	5756	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
Kojto	91:031413cf7a89	5757	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
Kojto	91:031413cf7a89	5758
Kojto	91:031413cf7a89	5759	/* Bit 0 : Bit order. */
Kojto	91:031413cf7a89	5760	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
Kojto	91:031413cf7a89	5761	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
Kojto	91:031413cf7a89	5762	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
Kojto	91:031413cf7a89	5763	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
Kojto	91:031413cf7a89	5764
Kojto	91:031413cf7a89	5765	/* Register: SPI_POWER */
Kojto	91:031413cf7a89	5766	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	5767
Kojto	91:031413cf7a89	5768	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	5769	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	5770	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	5771	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	5772	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	5773
Kojto	91:031413cf7a89	5774
Kojto	97:433970e64889	5775	/* Peripheral: SPIM */
Kojto	97:433970e64889	5776	/* Description: SPI master with easyDMA 1. */
Kojto	97:433970e64889	5777
Kojto	97:433970e64889	5778	/* Register: SPIM_INTENSET */
Kojto	97:433970e64889	5779	/* Description: Interrupt enable set register. */
Kojto	97:433970e64889	5780
Kojto	97:433970e64889	5781	/* Bit 19 : Enable interrupt on STARTED event. */
Kojto	97:433970e64889	5782	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
Kojto	97:433970e64889	5783	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
Kojto	97:433970e64889	5784	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5785	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5786	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	5787
Kojto	97:433970e64889	5788	/* Bit 8 : Enable interrupt on ENDTX event. */
Kojto	97:433970e64889	5789	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
Kojto	97:433970e64889	5790	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
Kojto	97:433970e64889	5791	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5792	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5793	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	5794
Kojto	97:433970e64889	5795	/* Bit 4 : Enable interrupt on ENDRX event. */
Kojto	97:433970e64889	5796	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	97:433970e64889	5797	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	97:433970e64889	5798	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5799	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5800	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	5801
Kojto	97:433970e64889	5802	/* Bit 1 : Enable interrupt on STOPPED event. */
Kojto	97:433970e64889	5803	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	97:433970e64889	5804	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	97:433970e64889	5805	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5806	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5807	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	5808
Kojto	97:433970e64889	5809	/* Register: SPIM_INTENCLR */
Kojto	97:433970e64889	5810	/* Description: Interrupt enable clear register. */
Kojto	97:433970e64889	5811
Kojto	97:433970e64889	5812	/* Bit 19 : Disable interrupt on STARTED event. */
Kojto	97:433970e64889	5813	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
Kojto	97:433970e64889	5814	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
Kojto	97:433970e64889	5815	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5816	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5817	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	5818
Kojto	97:433970e64889	5819	/* Bit 8 : Disable interrupt on ENDTX event. */
Kojto	97:433970e64889	5820	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
Kojto	97:433970e64889	5821	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
Kojto	97:433970e64889	5822	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5823	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5824	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	5825
Kojto	97:433970e64889	5826	/* Bit 4 : Disable interrupt on ENDRX event. */
Kojto	97:433970e64889	5827	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	97:433970e64889	5828	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	97:433970e64889	5829	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5830	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5831	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	5832
Kojto	97:433970e64889	5833	/* Bit 1 : Disable interrupt on STOPPED event. */
Kojto	97:433970e64889	5834	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	97:433970e64889	5835	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	97:433970e64889	5836	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5837	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5838	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	5839
Kojto	97:433970e64889	5840	/* Register: SPIM_ENABLE */
Kojto	97:433970e64889	5841	/* Description: Enable SPIM. */
Kojto	97:433970e64889	5842
Kojto	97:433970e64889	5843	/* Bits 3..0 : Enable or disable SPIM. */
Kojto	97:433970e64889	5844	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	97:433970e64889	5845	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	97:433970e64889	5846	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
Kojto	97:433970e64889	5847	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
Kojto	97:433970e64889	5848
Kojto	97:433970e64889	5849	/* Register: SPIM_FREQUENCY */
Kojto	97:433970e64889	5850	/* Description: SPI frequency. */
Kojto	97:433970e64889	5851
Kojto	97:433970e64889	5852	/* Bits 31..0 : SPI master data rate. */
Kojto	97:433970e64889	5853	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	97:433970e64889	5854	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	97:433970e64889	5855	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
Kojto	97:433970e64889	5856	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
Kojto	97:433970e64889	5857	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
Kojto	97:433970e64889	5858	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
Kojto	97:433970e64889	5859	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
Kojto	97:433970e64889	5860	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
Kojto	97:433970e64889	5861	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
Kojto	97:433970e64889	5862
Kojto	97:433970e64889	5863	/* Register: SPIM_RXD_PTR */
Kojto	97:433970e64889	5864	/* Description: Data pointer. */
Kojto	97:433970e64889	5865
Kojto	97:433970e64889	5866	/* Bits 31..0 : Data pointer. */
Kojto	97:433970e64889	5867	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
Kojto	97:433970e64889	5868	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
Kojto	97:433970e64889	5869
Kojto	97:433970e64889	5870	/* Register: SPIM_RXD_MAXCNT */
Kojto	97:433970e64889	5871	/* Description: Maximum number of buffer bytes to receive. */
Kojto	97:433970e64889	5872
Kojto	97:433970e64889	5873	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
Kojto	97:433970e64889	5874	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
Kojto	97:433970e64889	5875	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
Kojto	97:433970e64889	5876
Kojto	97:433970e64889	5877	/* Register: SPIM_RXD_AMOUNT */
Kojto	97:433970e64889	5878	/* Description: Number of bytes received in the last transaction. */
Kojto	97:433970e64889	5879
Kojto	97:433970e64889	5880	/* Bits 7..0 : Number of bytes received in the last transaction. */
Kojto	97:433970e64889	5881	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
Kojto	97:433970e64889	5882	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
Kojto	97:433970e64889	5883
Kojto	97:433970e64889	5884	/* Register: SPIM_TXD_PTR */
Kojto	97:433970e64889	5885	/* Description: Data pointer. */
Kojto	97:433970e64889	5886
Kojto	97:433970e64889	5887	/* Bits 31..0 : Data pointer. */
Kojto	97:433970e64889	5888	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
Kojto	97:433970e64889	5889	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
Kojto	97:433970e64889	5890
Kojto	97:433970e64889	5891	/* Register: SPIM_TXD_MAXCNT */
Kojto	97:433970e64889	5892	/* Description: Maximum number of buffer bytes to send. */
Kojto	97:433970e64889	5893
Kojto	97:433970e64889	5894	/* Bits 7..0 : Maximum number of buffer bytes to send. */
Kojto	97:433970e64889	5895	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
Kojto	97:433970e64889	5896	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
Kojto	97:433970e64889	5897
Kojto	97:433970e64889	5898	/* Register: SPIM_TXD_AMOUNT */
Kojto	97:433970e64889	5899	/* Description: Number of bytes sent in the last transaction. */
Kojto	97:433970e64889	5900
Kojto	97:433970e64889	5901	/* Bits 7..0 : Number of bytes sent in the last transaction. */
Kojto	97:433970e64889	5902	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
Kojto	97:433970e64889	5903	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
Kojto	97:433970e64889	5904
Kojto	122:f9eeca106725	5905	/* Register: SPIM_CONFIG */
Kojto	122:f9eeca106725	5906	/* Description: Configuration register. */
Kojto	122:f9eeca106725	5907
Kojto	122:f9eeca106725	5908	/* Bit 2 : Serial clock (SCK) polarity. */
Kojto	122:f9eeca106725	5909	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
Kojto	122:f9eeca106725	5910	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
Kojto	122:f9eeca106725	5911	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
Kojto	122:f9eeca106725	5912	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
Kojto	122:f9eeca106725	5913
Kojto	122:f9eeca106725	5914	/* Bit 1 : Serial clock (SCK) phase. */
Kojto	122:f9eeca106725	5915	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
Kojto	122:f9eeca106725	5916	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
Kojto	122:f9eeca106725	5917	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
Kojto	122:f9eeca106725	5918	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
Kojto	122:f9eeca106725	5919
Kojto	122:f9eeca106725	5920	/* Bit 0 : Bit order. */
Kojto	122:f9eeca106725	5921	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
Kojto	122:f9eeca106725	5922	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
Kojto	122:f9eeca106725	5923	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
Kojto	122:f9eeca106725	5924	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
Kojto	122:f9eeca106725	5925
Kojto	122:f9eeca106725	5926	/* Register: SPIM_ORC */
Kojto	122:f9eeca106725	5927	/* Description: Over-read character. */
Kojto	122:f9eeca106725	5928
Kojto	122:f9eeca106725	5929	/* Bits 7..0 : Over-read character. */
Kojto	122:f9eeca106725	5930	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
Kojto	122:f9eeca106725	5931	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
Kojto	122:f9eeca106725	5932
Kojto	122:f9eeca106725	5933	/* Register: SPIM_POWER */
Kojto	122:f9eeca106725	5934	/* Description: Peripheral power control. */
Kojto	122:f9eeca106725	5935
Kojto	122:f9eeca106725	5936	/* Bit 0 : Peripheral power control. */
Kojto	122:f9eeca106725	5937	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	122:f9eeca106725	5938	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	122:f9eeca106725	5939	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	122:f9eeca106725	5940	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	122:f9eeca106725	5941
Kojto	97:433970e64889	5942
Kojto	91:031413cf7a89	5943	/* Peripheral: SPIS */
Kojto	91:031413cf7a89	5944	/* Description: SPI slave 1. */
Kojto	91:031413cf7a89	5945
Kojto	91:031413cf7a89	5946	/* Register: SPIS_SHORTS */
Kojto	91:031413cf7a89	5947	/* Description: Shortcuts for SPIS. */
Kojto	91:031413cf7a89	5948
Kojto	91:031413cf7a89	5949	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
Kojto	91:031413cf7a89	5950	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
Kojto	91:031413cf7a89	5951	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
Kojto	91:031413cf7a89	5952	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	5953	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	5954
Kojto	91:031413cf7a89	5955	/* Register: SPIS_INTENSET */
Kojto	91:031413cf7a89	5956	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	5957
Kojto	91:031413cf7a89	5958	/* Bit 10 : Enable interrupt on ACQUIRED event. */
Kojto	91:031413cf7a89	5959	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
Kojto	91:031413cf7a89	5960	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
Kojto	91:031413cf7a89	5961	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5962	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5963	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5964
Kojto	122:f9eeca106725	5965	/* Bit 4 : enable interrupt on ENDRX event. */
Kojto	122:f9eeca106725	5966	#define SPIS_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	122:f9eeca106725	5967	#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	122:f9eeca106725	5968	#define SPIS_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	122:f9eeca106725	5969	#define SPIS_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	122:f9eeca106725	5970	#define SPIS_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
Kojto	122:f9eeca106725	5971
Kojto	91:031413cf7a89	5972	/* Bit 1 : Enable interrupt on END event. */
Kojto	91:031413cf7a89	5973	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
Kojto	91:031413cf7a89	5974	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	91:031413cf7a89	5975	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5976	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5977	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	5978
Kojto	91:031413cf7a89	5979	/* Register: SPIS_INTENCLR */
Kojto	91:031413cf7a89	5980	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	5981
Kojto	91:031413cf7a89	5982	/* Bit 10 : Disable interrupt on ACQUIRED event. */
Kojto	91:031413cf7a89	5983	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
Kojto	91:031413cf7a89	5984	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
Kojto	91:031413cf7a89	5985	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	5986	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	5987	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	5988
Kojto	122:f9eeca106725	5989	/* Bit 4 : Disable interrupt on ENDRX event. */
Kojto	122:f9eeca106725	5990	#define SPIS_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	122:f9eeca106725	5991	#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	122:f9eeca106725	5992	#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	122:f9eeca106725	5993	#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	122:f9eeca106725	5994	#define SPIS_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	122:f9eeca106725	5995
Kojto	91:031413cf7a89	5996	/* Bit 1 : Disable interrupt on END event. */
Kojto	91:031413cf7a89	5997	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
Kojto	91:031413cf7a89	5998	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	91:031413cf7a89	5999	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6000	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6001	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6002
Kojto	91:031413cf7a89	6003	/* Register: SPIS_SEMSTAT */
Kojto	91:031413cf7a89	6004	/* Description: Semaphore status. */
Kojto	91:031413cf7a89	6005
Kojto	91:031413cf7a89	6006	/* Bits 1..0 : Semaphore status. */
Kojto	91:031413cf7a89	6007	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
Kojto	91:031413cf7a89	6008	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
Kojto	91:031413cf7a89	6009	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
Kojto	91:031413cf7a89	6010	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
Kojto	91:031413cf7a89	6011	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
Kojto	91:031413cf7a89	6012	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
Kojto	91:031413cf7a89	6013
Kojto	91:031413cf7a89	6014	/* Register: SPIS_STATUS */
Kojto	91:031413cf7a89	6015	/* Description: Status from last transaction. */
Kojto	91:031413cf7a89	6016
Kojto	91:031413cf7a89	6017	/* Bit 1 : RX buffer overflow detected, and prevented. */
Kojto	91:031413cf7a89	6018	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
Kojto	91:031413cf7a89	6019	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
Kojto	91:031413cf7a89	6020	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
Kojto	91:031413cf7a89	6021	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
Kojto	91:031413cf7a89	6022	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
Kojto	91:031413cf7a89	6023
Kojto	91:031413cf7a89	6024	/* Bit 0 : TX buffer overread detected, and prevented. */
Kojto	91:031413cf7a89	6025	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
Kojto	91:031413cf7a89	6026	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
Kojto	91:031413cf7a89	6027	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
Kojto	91:031413cf7a89	6028	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
Kojto	91:031413cf7a89	6029	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
Kojto	91:031413cf7a89	6030
Kojto	91:031413cf7a89	6031	/* Register: SPIS_ENABLE */
Kojto	91:031413cf7a89	6032	/* Description: Enable SPIS. */
Kojto	91:031413cf7a89	6033
Kojto	91:031413cf7a89	6034	/* Bits 2..0 : Enable or disable SPIS. */
Kojto	91:031413cf7a89	6035	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	6036	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	6037	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
Kojto	91:031413cf7a89	6038	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
Kojto	91:031413cf7a89	6039
Kojto	91:031413cf7a89	6040	/* Register: SPIS_MAXRX */
Kojto	91:031413cf7a89	6041	/* Description: Maximum number of bytes in the receive buffer. */
Kojto	91:031413cf7a89	6042
Kojto	91:031413cf7a89	6043	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
Kojto	91:031413cf7a89	6044	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
Kojto	91:031413cf7a89	6045	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
Kojto	91:031413cf7a89	6046
Kojto	91:031413cf7a89	6047	/* Register: SPIS_AMOUNTRX */
Kojto	91:031413cf7a89	6048	/* Description: Number of bytes received in last granted transaction. */
Kojto	91:031413cf7a89	6049
Kojto	91:031413cf7a89	6050	/* Bits 7..0 : Number of bytes received in last granted transaction. */
Kojto	91:031413cf7a89	6051	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
Kojto	91:031413cf7a89	6052	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
Kojto	91:031413cf7a89	6053
Kojto	91:031413cf7a89	6054	/* Register: SPIS_MAXTX */
Kojto	91:031413cf7a89	6055	/* Description: Maximum number of bytes in the transmit buffer. */
Kojto	91:031413cf7a89	6056
Kojto	91:031413cf7a89	6057	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
Kojto	91:031413cf7a89	6058	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
Kojto	91:031413cf7a89	6059	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
Kojto	91:031413cf7a89	6060
Kojto	91:031413cf7a89	6061	/* Register: SPIS_AMOUNTTX */
Kojto	91:031413cf7a89	6062	/* Description: Number of bytes transmitted in last granted transaction. */
Kojto	91:031413cf7a89	6063
Kojto	91:031413cf7a89	6064	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
Kojto	91:031413cf7a89	6065	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
Kojto	91:031413cf7a89	6066	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
Kojto	91:031413cf7a89	6067
Kojto	91:031413cf7a89	6068	/* Register: SPIS_CONFIG */
Kojto	91:031413cf7a89	6069	/* Description: Configuration register. */
Kojto	91:031413cf7a89	6070
Kojto	91:031413cf7a89	6071	/* Bit 2 : Serial clock (SCK) polarity. */
Kojto	91:031413cf7a89	6072	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
Kojto	91:031413cf7a89	6073	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
Kojto	91:031413cf7a89	6074	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
Kojto	91:031413cf7a89	6075	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
Kojto	91:031413cf7a89	6076
Kojto	91:031413cf7a89	6077	/* Bit 1 : Serial clock (SCK) phase. */
Kojto	91:031413cf7a89	6078	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
Kojto	91:031413cf7a89	6079	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
Kojto	91:031413cf7a89	6080	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
Kojto	91:031413cf7a89	6081	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
Kojto	91:031413cf7a89	6082
Kojto	91:031413cf7a89	6083	/* Bit 0 : Bit order. */
Kojto	91:031413cf7a89	6084	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
Kojto	91:031413cf7a89	6085	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
Kojto	91:031413cf7a89	6086	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
Kojto	91:031413cf7a89	6087	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
Kojto	91:031413cf7a89	6088
Kojto	91:031413cf7a89	6089	/* Register: SPIS_DEF */
Kojto	91:031413cf7a89	6090	/* Description: Default character. */
Kojto	91:031413cf7a89	6091
Kojto	91:031413cf7a89	6092	/* Bits 7..0 : Default character. */
Kojto	91:031413cf7a89	6093	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
Kojto	91:031413cf7a89	6094	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
Kojto	91:031413cf7a89	6095
Kojto	91:031413cf7a89	6096	/* Register: SPIS_ORC */
Kojto	91:031413cf7a89	6097	/* Description: Over-read character. */
Kojto	91:031413cf7a89	6098
Kojto	91:031413cf7a89	6099	/* Bits 7..0 : Over-read character. */
Kojto	91:031413cf7a89	6100	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
Kojto	91:031413cf7a89	6101	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
Kojto	91:031413cf7a89	6102
Kojto	91:031413cf7a89	6103	/* Register: SPIS_POWER */
Kojto	91:031413cf7a89	6104	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	6105
Kojto	91:031413cf7a89	6106	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	6107	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	6108	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	6109	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	6110	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	6111
Kojto	91:031413cf7a89	6112
Kojto	91:031413cf7a89	6113	/* Peripheral: TEMP */
Kojto	91:031413cf7a89	6114	/* Description: Temperature Sensor. */
Kojto	91:031413cf7a89	6115
Kojto	91:031413cf7a89	6116	/* Register: TEMP_INTENSET */
Kojto	91:031413cf7a89	6117	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	6118
Kojto	91:031413cf7a89	6119	/* Bit 0 : Enable interrupt on DATARDY event. */
Kojto	91:031413cf7a89	6120	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
Kojto	91:031413cf7a89	6121	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
Kojto	91:031413cf7a89	6122	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6123	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6124	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6125
Kojto	91:031413cf7a89	6126	/* Register: TEMP_INTENCLR */
Kojto	91:031413cf7a89	6127	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	6128
Kojto	91:031413cf7a89	6129	/* Bit 0 : Disable interrupt on DATARDY event. */
Kojto	91:031413cf7a89	6130	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
Kojto	91:031413cf7a89	6131	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
Kojto	91:031413cf7a89	6132	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6133	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6134	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6135
Kojto	91:031413cf7a89	6136	/* Register: TEMP_POWER */
Kojto	91:031413cf7a89	6137	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	6138
Kojto	91:031413cf7a89	6139	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	6140	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	6141	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	6142	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	6143	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	6144
Kojto	91:031413cf7a89	6145
Kojto	91:031413cf7a89	6146	/* Peripheral: TIMER */
Kojto	91:031413cf7a89	6147	/* Description: Timer 0. */
Kojto	91:031413cf7a89	6148
Kojto	91:031413cf7a89	6149	/* Register: TIMER_SHORTS */
Kojto	91:031413cf7a89	6150	/* Description: Shortcuts for Timer. */
Kojto	91:031413cf7a89	6151
Kojto	91:031413cf7a89	6152	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
Kojto	91:031413cf7a89	6153	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
Kojto	91:031413cf7a89	6154	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
Kojto	91:031413cf7a89	6155	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6156	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6157
Kojto	91:031413cf7a89	6158	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
Kojto	91:031413cf7a89	6159	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
Kojto	91:031413cf7a89	6160	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
Kojto	91:031413cf7a89	6161	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6162	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6163
Kojto	91:031413cf7a89	6164	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
Kojto	91:031413cf7a89	6165	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
Kojto	91:031413cf7a89	6166	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
Kojto	91:031413cf7a89	6167	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6168	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6169
Kojto	91:031413cf7a89	6170	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
Kojto	91:031413cf7a89	6171	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
Kojto	91:031413cf7a89	6172	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
Kojto	91:031413cf7a89	6173	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6174	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6175
Kojto	91:031413cf7a89	6176	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
Kojto	91:031413cf7a89	6177	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
Kojto	91:031413cf7a89	6178	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
Kojto	91:031413cf7a89	6179	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6180	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6181
Kojto	91:031413cf7a89	6182	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
Kojto	91:031413cf7a89	6183	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
Kojto	91:031413cf7a89	6184	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
Kojto	91:031413cf7a89	6185	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6186	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6187
Kojto	91:031413cf7a89	6188	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
Kojto	91:031413cf7a89	6189	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
Kojto	91:031413cf7a89	6190	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
Kojto	91:031413cf7a89	6191	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6192	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6193
Kojto	91:031413cf7a89	6194	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
Kojto	91:031413cf7a89	6195	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
Kojto	91:031413cf7a89	6196	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
Kojto	91:031413cf7a89	6197	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6198	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6199
Kojto	91:031413cf7a89	6200	/* Register: TIMER_INTENSET */
Kojto	91:031413cf7a89	6201	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	6202
Kojto	91:031413cf7a89	6203	/* Bit 19 : Enable interrupt on COMPARE[3] */
Kojto	91:031413cf7a89	6204	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	91:031413cf7a89	6205	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	91:031413cf7a89	6206	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6207	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6208	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6209
Kojto	91:031413cf7a89	6210	/* Bit 18 : Enable interrupt on COMPARE[2] */
Kojto	91:031413cf7a89	6211	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	91:031413cf7a89	6212	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	91:031413cf7a89	6213	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6214	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6215	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6216
Kojto	91:031413cf7a89	6217	/* Bit 17 : Enable interrupt on COMPARE[1] */
Kojto	91:031413cf7a89	6218	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	91:031413cf7a89	6219	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	91:031413cf7a89	6220	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6221	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6222	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6223
Kojto	91:031413cf7a89	6224	/* Bit 16 : Enable interrupt on COMPARE[0] */
Kojto	91:031413cf7a89	6225	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	91:031413cf7a89	6226	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	91:031413cf7a89	6227	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6228	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6229	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6230
Kojto	91:031413cf7a89	6231	/* Register: TIMER_INTENCLR */
Kojto	91:031413cf7a89	6232	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	6233
Kojto	91:031413cf7a89	6234	/* Bit 19 : Disable interrupt on COMPARE[3] */
Kojto	91:031413cf7a89	6235	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
Kojto	91:031413cf7a89	6236	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
Kojto	91:031413cf7a89	6237	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6238	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6239	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6240
Kojto	91:031413cf7a89	6241	/* Bit 18 : Disable interrupt on COMPARE[2] */
Kojto	91:031413cf7a89	6242	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
Kojto	91:031413cf7a89	6243	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
Kojto	91:031413cf7a89	6244	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6245	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6246	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6247
Kojto	91:031413cf7a89	6248	/* Bit 17 : Disable interrupt on COMPARE[1] */
Kojto	91:031413cf7a89	6249	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
Kojto	91:031413cf7a89	6250	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
Kojto	91:031413cf7a89	6251	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6252	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6253	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6254
Kojto	91:031413cf7a89	6255	/* Bit 16 : Disable interrupt on COMPARE[0] */
Kojto	91:031413cf7a89	6256	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
Kojto	91:031413cf7a89	6257	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
Kojto	91:031413cf7a89	6258	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6259	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6260	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6261
Kojto	91:031413cf7a89	6262	/* Register: TIMER_MODE */
Kojto	91:031413cf7a89	6263	/* Description: Timer Mode selection. */
Kojto	91:031413cf7a89	6264
Kojto	91:031413cf7a89	6265	/* Bit 0 : Select Normal or Counter mode. */
Kojto	91:031413cf7a89	6266	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
Kojto	91:031413cf7a89	6267	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
Kojto	91:031413cf7a89	6268	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
Kojto	91:031413cf7a89	6269	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
Kojto	91:031413cf7a89	6270
Kojto	91:031413cf7a89	6271	/* Register: TIMER_BITMODE */
Kojto	91:031413cf7a89	6272	/* Description: Sets timer behaviour. */
Kojto	91:031413cf7a89	6273
Kojto	91:031413cf7a89	6274	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
Kojto	91:031413cf7a89	6275	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
Kojto	91:031413cf7a89	6276	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
Kojto	91:031413cf7a89	6277	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
Kojto	91:031413cf7a89	6278	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
Kojto	91:031413cf7a89	6279	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
Kojto	91:031413cf7a89	6280	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
Kojto	91:031413cf7a89	6281
Kojto	91:031413cf7a89	6282	/* Register: TIMER_PRESCALER */
Kojto	91:031413cf7a89	6283	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
Kojto	91:031413cf7a89	6284
Kojto	91:031413cf7a89	6285	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
Kojto	91:031413cf7a89	6286	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
Kojto	91:031413cf7a89	6287	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
Kojto	91:031413cf7a89	6288
Kojto	91:031413cf7a89	6289	/* Register: TIMER_POWER */
Kojto	91:031413cf7a89	6290	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	6291
Kojto	91:031413cf7a89	6292	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	6293	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	6294	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	6295	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	6296	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	6297
Kojto	91:031413cf7a89	6298
Kojto	91:031413cf7a89	6299	/* Peripheral: TWI */
Kojto	91:031413cf7a89	6300	/* Description: Two-wire interface master 0. */
Kojto	91:031413cf7a89	6301
Kojto	91:031413cf7a89	6302	/* Register: TWI_SHORTS */
Kojto	91:031413cf7a89	6303	/* Description: Shortcuts for TWI. */
Kojto	91:031413cf7a89	6304
Kojto	91:031413cf7a89	6305	/* Bit 1 : Shortcut between BB event and the STOP task. */
Kojto	91:031413cf7a89	6306	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
Kojto	91:031413cf7a89	6307	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
Kojto	91:031413cf7a89	6308	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6309	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6310
Kojto	91:031413cf7a89	6311	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
Kojto	91:031413cf7a89	6312	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
Kojto	91:031413cf7a89	6313	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
Kojto	91:031413cf7a89	6314	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6315	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6316
Kojto	91:031413cf7a89	6317	/* Register: TWI_INTENSET */
Kojto	91:031413cf7a89	6318	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	6319
Kojto	97:433970e64889	6320	/* Bit 18 : Enable interrupt on SUSPENDED event. */
Kojto	97:433970e64889	6321	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
Kojto	97:433970e64889	6322	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
Kojto	97:433970e64889	6323	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6324	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6325	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6326
Kojto	91:031413cf7a89	6327	/* Bit 14 : Enable interrupt on BB event. */
Kojto	91:031413cf7a89	6328	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
Kojto	91:031413cf7a89	6329	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
Kojto	91:031413cf7a89	6330	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6331	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6332	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6333
Kojto	91:031413cf7a89	6334	/* Bit 9 : Enable interrupt on ERROR event. */
Kojto	91:031413cf7a89	6335	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
Kojto	91:031413cf7a89	6336	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	91:031413cf7a89	6337	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6338	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6339	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6340
Kojto	91:031413cf7a89	6341	/* Bit 7 : Enable interrupt on TXDSENT event. */
Kojto	91:031413cf7a89	6342	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
Kojto	91:031413cf7a89	6343	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
Kojto	91:031413cf7a89	6344	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6345	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6346	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6347
Kojto	91:031413cf7a89	6348	/* Bit 2 : Enable interrupt on READY event. */
Kojto	91:031413cf7a89	6349	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
Kojto	91:031413cf7a89	6350	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
Kojto	91:031413cf7a89	6351	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6352	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6353	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6354
Kojto	91:031413cf7a89	6355	/* Bit 1 : Enable interrupt on STOPPED event. */
Kojto	91:031413cf7a89	6356	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	91:031413cf7a89	6357	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	91:031413cf7a89	6358	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6359	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6360	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6361
Kojto	91:031413cf7a89	6362	/* Register: TWI_INTENCLR */
Kojto	91:031413cf7a89	6363	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	6364
Kojto	97:433970e64889	6365	/* Bit 18 : Disable interrupt on SUSPENDED event. */
Kojto	97:433970e64889	6366	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
Kojto	97:433970e64889	6367	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
Kojto	97:433970e64889	6368	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6369	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6370	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6371
Kojto	91:031413cf7a89	6372	/* Bit 14 : Disable interrupt on BB event. */
Kojto	91:031413cf7a89	6373	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
Kojto	91:031413cf7a89	6374	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
Kojto	91:031413cf7a89	6375	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6376	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6377	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6378
Kojto	91:031413cf7a89	6379	/* Bit 9 : Disable interrupt on ERROR event. */
Kojto	91:031413cf7a89	6380	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
Kojto	91:031413cf7a89	6381	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	91:031413cf7a89	6382	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6383	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6384	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6385
Kojto	91:031413cf7a89	6386	/* Bit 7 : Disable interrupt on TXDSENT event. */
Kojto	91:031413cf7a89	6387	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
Kojto	91:031413cf7a89	6388	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
Kojto	91:031413cf7a89	6389	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6390	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6391	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6392
Kojto	91:031413cf7a89	6393	/* Bit 2 : Disable interrupt on RXDREADY event. */
Kojto	91:031413cf7a89	6394	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
Kojto	91:031413cf7a89	6395	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
Kojto	91:031413cf7a89	6396	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6397	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6398	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6399
Kojto	91:031413cf7a89	6400	/* Bit 1 : Disable interrupt on STOPPED event. */
Kojto	91:031413cf7a89	6401	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	91:031413cf7a89	6402	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	91:031413cf7a89	6403	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6404	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6405	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6406
Kojto	91:031413cf7a89	6407	/* Register: TWI_ERRORSRC */
Kojto	91:031413cf7a89	6408	/* Description: Two-wire error source. Write error field to 1 to clear error. */
Kojto	91:031413cf7a89	6409
Kojto	91:031413cf7a89	6410	/* Bit 2 : NACK received after sending a data byte. */
Kojto	91:031413cf7a89	6411	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
Kojto	91:031413cf7a89	6412	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
Kojto	91:031413cf7a89	6413	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
Kojto	91:031413cf7a89	6414	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
Kojto	91:031413cf7a89	6415	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
Kojto	91:031413cf7a89	6416
Kojto	91:031413cf7a89	6417	/* Bit 1 : NACK received after sending the address. */
Kojto	91:031413cf7a89	6418	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
Kojto	91:031413cf7a89	6419	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
Kojto	91:031413cf7a89	6420	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
Kojto	91:031413cf7a89	6421	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
Kojto	91:031413cf7a89	6422	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
Kojto	91:031413cf7a89	6423
Kojto	122:f9eeca106725	6424	/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
Kojto	122:f9eeca106725	6425	#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
Kojto	122:f9eeca106725	6426	#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
Kojto	122:f9eeca106725	6427	#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
Kojto	122:f9eeca106725	6428	#define TWI_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
Kojto	122:f9eeca106725	6429	#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
Kojto	122:f9eeca106725	6430
Kojto	91:031413cf7a89	6431	/* Register: TWI_ENABLE */
Kojto	91:031413cf7a89	6432	/* Description: Enable two-wire master. */
Kojto	91:031413cf7a89	6433
Kojto	91:031413cf7a89	6434	/* Bits 2..0 : Enable or disable W2M */
Kojto	91:031413cf7a89	6435	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	6436	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	6437	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
Kojto	91:031413cf7a89	6438	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
Kojto	91:031413cf7a89	6439
Kojto	91:031413cf7a89	6440	/* Register: TWI_RXD */
Kojto	91:031413cf7a89	6441	/* Description: RX data register. */
Kojto	91:031413cf7a89	6442
Kojto	91:031413cf7a89	6443	/* Bits 7..0 : RX data from last transfer. */
Kojto	91:031413cf7a89	6444	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
Kojto	91:031413cf7a89	6445	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
Kojto	91:031413cf7a89	6446
Kojto	91:031413cf7a89	6447	/* Register: TWI_TXD */
Kojto	91:031413cf7a89	6448	/* Description: TX data register. */
Kojto	91:031413cf7a89	6449
Kojto	91:031413cf7a89	6450	/* Bits 7..0 : TX data for next transfer. */
Kojto	91:031413cf7a89	6451	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
Kojto	91:031413cf7a89	6452	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
Kojto	91:031413cf7a89	6453
Kojto	91:031413cf7a89	6454	/* Register: TWI_FREQUENCY */
Kojto	91:031413cf7a89	6455	/* Description: Two-wire frequency. */
Kojto	91:031413cf7a89	6456
Kojto	91:031413cf7a89	6457	/* Bits 31..0 : Two-wire master clock frequency. */
Kojto	91:031413cf7a89	6458	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	91:031413cf7a89	6459	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	91:031413cf7a89	6460	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
Kojto	91:031413cf7a89	6461	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
Kojto	91:031413cf7a89	6462	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
Kojto	91:031413cf7a89	6463
Kojto	91:031413cf7a89	6464	/* Register: TWI_ADDRESS */
Kojto	91:031413cf7a89	6465	/* Description: Address used in the two-wire transfer. */
Kojto	91:031413cf7a89	6466
Kojto	91:031413cf7a89	6467	/* Bits 6..0 : Two-wire address. */
Kojto	91:031413cf7a89	6468	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
Kojto	91:031413cf7a89	6469	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
Kojto	91:031413cf7a89	6470
Kojto	91:031413cf7a89	6471	/* Register: TWI_POWER */
Kojto	91:031413cf7a89	6472	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	6473
Kojto	91:031413cf7a89	6474	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	6475	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	6476	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	6477	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	6478	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	6479
Kojto	91:031413cf7a89	6480
Kojto	91:031413cf7a89	6481	/* Peripheral: UART */
Kojto	91:031413cf7a89	6482	/* Description: Universal Asynchronous Receiver/Transmitter. */
Kojto	91:031413cf7a89	6483
Kojto	91:031413cf7a89	6484	/* Register: UART_SHORTS */
Kojto	97:433970e64889	6485	/* Description: Shortcuts for UART. */
Kojto	91:031413cf7a89	6486
Kojto	122:f9eeca106725	6487	/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
Kojto	91:031413cf7a89	6488	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
Kojto	91:031413cf7a89	6489	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
Kojto	91:031413cf7a89	6490	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6491	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6492
Kojto	122:f9eeca106725	6493	/* Bit 3 : Shortcut between CTS event and STARTRX task. */
Kojto	91:031413cf7a89	6494	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
Kojto	91:031413cf7a89	6495	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
Kojto	91:031413cf7a89	6496	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
Kojto	91:031413cf7a89	6497	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
Kojto	91:031413cf7a89	6498
Kojto	91:031413cf7a89	6499	/* Register: UART_INTENSET */
Kojto	91:031413cf7a89	6500	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	6501
Kojto	91:031413cf7a89	6502	/* Bit 17 : Enable interrupt on RXTO event. */
Kojto	91:031413cf7a89	6503	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
Kojto	91:031413cf7a89	6504	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
Kojto	91:031413cf7a89	6505	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6506	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6507	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6508
Kojto	91:031413cf7a89	6509	/* Bit 9 : Enable interrupt on ERROR event. */
Kojto	91:031413cf7a89	6510	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
Kojto	91:031413cf7a89	6511	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	91:031413cf7a89	6512	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6513	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6514	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6515
Kojto	91:031413cf7a89	6516	/* Bit 7 : Enable interrupt on TXRDY event. */
Kojto	91:031413cf7a89	6517	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
Kojto	91:031413cf7a89	6518	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
Kojto	91:031413cf7a89	6519	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6520	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6521	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6522
Kojto	91:031413cf7a89	6523	/* Bit 2 : Enable interrupt on RXRDY event. */
Kojto	91:031413cf7a89	6524	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
Kojto	91:031413cf7a89	6525	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
Kojto	91:031413cf7a89	6526	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6527	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6528	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6529
Kojto	91:031413cf7a89	6530	/* Bit 1 : Enable interrupt on NCTS event. */
Kojto	91:031413cf7a89	6531	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
Kojto	91:031413cf7a89	6532	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
Kojto	91:031413cf7a89	6533	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6534	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6535	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6536
Kojto	91:031413cf7a89	6537	/* Bit 0 : Enable interrupt on CTS event. */
Kojto	91:031413cf7a89	6538	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
Kojto	91:031413cf7a89	6539	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
Kojto	91:031413cf7a89	6540	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6541	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6542	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6543
Kojto	91:031413cf7a89	6544	/* Register: UART_INTENCLR */
Kojto	91:031413cf7a89	6545	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	6546
Kojto	91:031413cf7a89	6547	/* Bit 17 : Disable interrupt on RXTO event. */
Kojto	91:031413cf7a89	6548	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
Kojto	91:031413cf7a89	6549	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
Kojto	91:031413cf7a89	6550	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6551	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6552	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6553
Kojto	91:031413cf7a89	6554	/* Bit 9 : Disable interrupt on ERROR event. */
Kojto	91:031413cf7a89	6555	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
Kojto	91:031413cf7a89	6556	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
Kojto	91:031413cf7a89	6557	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6558	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6559	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6560
Kojto	91:031413cf7a89	6561	/* Bit 7 : Disable interrupt on TXRDY event. */
Kojto	91:031413cf7a89	6562	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
Kojto	91:031413cf7a89	6563	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
Kojto	91:031413cf7a89	6564	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6565	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6566	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6567
Kojto	91:031413cf7a89	6568	/* Bit 2 : Disable interrupt on RXRDY event. */
Kojto	91:031413cf7a89	6569	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
Kojto	91:031413cf7a89	6570	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
Kojto	91:031413cf7a89	6571	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6572	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6573	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6574
Kojto	91:031413cf7a89	6575	/* Bit 1 : Disable interrupt on NCTS event. */
Kojto	91:031413cf7a89	6576	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
Kojto	91:031413cf7a89	6577	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
Kojto	91:031413cf7a89	6578	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6579	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6580	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6581
Kojto	91:031413cf7a89	6582	/* Bit 0 : Disable interrupt on CTS event. */
Kojto	91:031413cf7a89	6583	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
Kojto	91:031413cf7a89	6584	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
Kojto	91:031413cf7a89	6585	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6586	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6587	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6588
Kojto	91:031413cf7a89	6589	/* Register: UART_ERRORSRC */
Kojto	91:031413cf7a89	6590	/* Description: Error source. Write error field to 1 to clear error. */
Kojto	91:031413cf7a89	6591
Kojto	91:031413cf7a89	6592	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
Kojto	91:031413cf7a89	6593	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
Kojto	91:031413cf7a89	6594	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
Kojto	91:031413cf7a89	6595	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
Kojto	91:031413cf7a89	6596	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
Kojto	91:031413cf7a89	6597	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
Kojto	91:031413cf7a89	6598
Kojto	91:031413cf7a89	6599	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
Kojto	91:031413cf7a89	6600	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
Kojto	91:031413cf7a89	6601	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
Kojto	91:031413cf7a89	6602	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
Kojto	91:031413cf7a89	6603	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
Kojto	91:031413cf7a89	6604	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
Kojto	91:031413cf7a89	6605
Kojto	91:031413cf7a89	6606	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
Kojto	91:031413cf7a89	6607	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
Kojto	91:031413cf7a89	6608	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
Kojto	91:031413cf7a89	6609	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
Kojto	91:031413cf7a89	6610	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
Kojto	91:031413cf7a89	6611	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
Kojto	91:031413cf7a89	6612
Kojto	91:031413cf7a89	6613	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
Kojto	91:031413cf7a89	6614	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
Kojto	91:031413cf7a89	6615	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
Kojto	91:031413cf7a89	6616	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
Kojto	91:031413cf7a89	6617	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
Kojto	91:031413cf7a89	6618	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
Kojto	91:031413cf7a89	6619
Kojto	91:031413cf7a89	6620	/* Register: UART_ENABLE */
Kojto	91:031413cf7a89	6621	/* Description: Enable UART and acquire IOs. */
Kojto	91:031413cf7a89	6622
Kojto	91:031413cf7a89	6623	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
Kojto	91:031413cf7a89	6624	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	91:031413cf7a89	6625	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	91:031413cf7a89	6626	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
Kojto	91:031413cf7a89	6627	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
Kojto	91:031413cf7a89	6628
Kojto	91:031413cf7a89	6629	/* Register: UART_RXD */
Kojto	97:433970e64889	6630	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
Kojto	91:031413cf7a89	6631
Kojto	91:031413cf7a89	6632	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
Kojto	91:031413cf7a89	6633	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
Kojto	91:031413cf7a89	6634	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
Kojto	91:031413cf7a89	6635
Kojto	91:031413cf7a89	6636	/* Register: UART_TXD */
Kojto	91:031413cf7a89	6637	/* Description: TXD register. */
Kojto	91:031413cf7a89	6638
Kojto	91:031413cf7a89	6639	/* Bits 7..0 : TX data for transfer. */
Kojto	91:031413cf7a89	6640	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
Kojto	91:031413cf7a89	6641	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
Kojto	91:031413cf7a89	6642
Kojto	91:031413cf7a89	6643	/* Register: UART_BAUDRATE */
Kojto	91:031413cf7a89	6644	/* Description: UART Baudrate. */
Kojto	91:031413cf7a89	6645
Kojto	91:031413cf7a89	6646	/* Bits 31..0 : UART baudrate. */
Kojto	91:031413cf7a89	6647	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
Kojto	91:031413cf7a89	6648	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
Kojto	91:031413cf7a89	6649	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
Kojto	91:031413cf7a89	6650	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
Kojto	91:031413cf7a89	6651	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
Kojto	91:031413cf7a89	6652	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
Kojto	91:031413cf7a89	6653	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
Kojto	91:031413cf7a89	6654	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
Kojto	91:031413cf7a89	6655	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
Kojto	91:031413cf7a89	6656	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
Kojto	91:031413cf7a89	6657	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
Kojto	91:031413cf7a89	6658	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
Kojto	91:031413cf7a89	6659	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
Kojto	91:031413cf7a89	6660	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
Kojto	91:031413cf7a89	6661	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
Kojto	91:031413cf7a89	6662	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
Kojto	122:f9eeca106725	6663	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /!< 921600 baud. /
Kojto	91:031413cf7a89	6664	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
Kojto	91:031413cf7a89	6665
Kojto	91:031413cf7a89	6666	/* Register: UART_CONFIG */
Kojto	91:031413cf7a89	6667	/* Description: Configuration of parity and hardware flow control register. */
Kojto	91:031413cf7a89	6668
Kojto	91:031413cf7a89	6669	/* Bits 3..1 : Include parity bit. */
Kojto	91:031413cf7a89	6670	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
Kojto	91:031413cf7a89	6671	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
Kojto	91:031413cf7a89	6672	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
Kojto	91:031413cf7a89	6673	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
Kojto	91:031413cf7a89	6674
Kojto	91:031413cf7a89	6675	/* Bit 0 : Hardware flow control. */
Kojto	91:031413cf7a89	6676	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
Kojto	91:031413cf7a89	6677	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
Kojto	91:031413cf7a89	6678	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
Kojto	91:031413cf7a89	6679	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
Kojto	91:031413cf7a89	6680
Kojto	91:031413cf7a89	6681	/* Register: UART_POWER */
Kojto	91:031413cf7a89	6682	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	6683
Kojto	91:031413cf7a89	6684	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	6685	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	6686	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	6687	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	6688	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	6689
Kojto	91:031413cf7a89	6690
Kojto	91:031413cf7a89	6691	/* Peripheral: UICR */
Kojto	91:031413cf7a89	6692	/* Description: User Information Configuration. */
Kojto	91:031413cf7a89	6693
Kojto	91:031413cf7a89	6694	/* Register: UICR_RBPCONF */
Kojto	91:031413cf7a89	6695	/* Description: Readback protection configuration. */
Kojto	91:031413cf7a89	6696
Kojto	91:031413cf7a89	6697	/* Bits 15..8 : Readback protect all code in the device. */
Kojto	91:031413cf7a89	6698	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
Kojto	91:031413cf7a89	6699	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
Kojto	122:f9eeca106725	6700	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
Kojto	91:031413cf7a89	6701	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
Kojto	91:031413cf7a89	6702
Kojto	91:031413cf7a89	6703	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
Kojto	91:031413cf7a89	6704	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
Kojto	91:031413cf7a89	6705	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
Kojto	122:f9eeca106725	6706	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
Kojto	91:031413cf7a89	6707	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
Kojto	91:031413cf7a89	6708
Kojto	91:031413cf7a89	6709	/* Register: UICR_XTALFREQ */
Kojto	91:031413cf7a89	6710	/* Description: Reset value for CLOCK XTALFREQ register. */
Kojto	91:031413cf7a89	6711
Kojto	91:031413cf7a89	6712	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
Kojto	91:031413cf7a89	6713	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
Kojto	91:031413cf7a89	6714	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
Kojto	122:f9eeca106725	6715	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
Kojto	91:031413cf7a89	6716	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
Kojto	91:031413cf7a89	6717
Kojto	91:031413cf7a89	6718	/* Register: UICR_FWID */
Kojto	91:031413cf7a89	6719	/* Description: Firmware ID. */
Kojto	91:031413cf7a89	6720
Kojto	91:031413cf7a89	6721	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
Kojto	91:031413cf7a89	6722	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
Kojto	91:031413cf7a89	6723	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
Kojto	91:031413cf7a89	6724
Kojto	91:031413cf7a89	6725
Kojto	91:031413cf7a89	6726	/* Peripheral: WDT */
Kojto	91:031413cf7a89	6727	/* Description: Watchdog Timer. */
Kojto	91:031413cf7a89	6728
Kojto	91:031413cf7a89	6729	/* Register: WDT_INTENSET */
Kojto	91:031413cf7a89	6730	/* Description: Interrupt enable set register. */
Kojto	91:031413cf7a89	6731
Kojto	91:031413cf7a89	6732	/* Bit 0 : Enable interrupt on TIMEOUT event. */
Kojto	91:031413cf7a89	6733	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
Kojto	91:031413cf7a89	6734	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
Kojto	91:031413cf7a89	6735	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6736	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6737	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
Kojto	91:031413cf7a89	6738
Kojto	91:031413cf7a89	6739	/* Register: WDT_INTENCLR */
Kojto	91:031413cf7a89	6740	/* Description: Interrupt enable clear register. */
Kojto	91:031413cf7a89	6741
Kojto	91:031413cf7a89	6742	/* Bit 0 : Disable interrupt on TIMEOUT event. */
Kojto	91:031413cf7a89	6743	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
Kojto	91:031413cf7a89	6744	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
Kojto	91:031413cf7a89	6745	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
Kojto	91:031413cf7a89	6746	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
Kojto	91:031413cf7a89	6747	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
Kojto	91:031413cf7a89	6748
Kojto	91:031413cf7a89	6749	/* Register: WDT_RUNSTATUS */
Kojto	91:031413cf7a89	6750	/* Description: Watchdog running status. */
Kojto	91:031413cf7a89	6751
Kojto	91:031413cf7a89	6752	/* Bit 0 : Watchdog running status. */
Kojto	91:031413cf7a89	6753	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
Kojto	91:031413cf7a89	6754	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
Kojto	91:031413cf7a89	6755	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
Kojto	91:031413cf7a89	6756	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
Kojto	91:031413cf7a89	6757
Kojto	91:031413cf7a89	6758	/* Register: WDT_REQSTATUS */
Kojto	91:031413cf7a89	6759	/* Description: Request status. */
Kojto	91:031413cf7a89	6760
Kojto	91:031413cf7a89	6761	/* Bit 7 : Request status for RR[7]. */
Kojto	91:031413cf7a89	6762	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
Kojto	91:031413cf7a89	6763	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
Kojto	91:031413cf7a89	6764	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
Kojto	91:031413cf7a89	6765	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
Kojto	91:031413cf7a89	6766
Kojto	91:031413cf7a89	6767	/* Bit 6 : Request status for RR[6]. */
Kojto	91:031413cf7a89	6768	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
Kojto	91:031413cf7a89	6769	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
Kojto	91:031413cf7a89	6770	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
Kojto	91:031413cf7a89	6771	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
Kojto	91:031413cf7a89	6772
Kojto	91:031413cf7a89	6773	/* Bit 5 : Request status for RR[5]. */
Kojto	91:031413cf7a89	6774	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
Kojto	91:031413cf7a89	6775	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
Kojto	91:031413cf7a89	6776	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
Kojto	91:031413cf7a89	6777	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
Kojto	91:031413cf7a89	6778
Kojto	91:031413cf7a89	6779	/* Bit 4 : Request status for RR[4]. */
Kojto	91:031413cf7a89	6780	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
Kojto	91:031413cf7a89	6781	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
Kojto	91:031413cf7a89	6782	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
Kojto	91:031413cf7a89	6783	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
Kojto	91:031413cf7a89	6784
Kojto	91:031413cf7a89	6785	/* Bit 3 : Request status for RR[3]. */
Kojto	91:031413cf7a89	6786	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
Kojto	91:031413cf7a89	6787	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
Kojto	91:031413cf7a89	6788	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
Kojto	91:031413cf7a89	6789	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
Kojto	91:031413cf7a89	6790
Kojto	91:031413cf7a89	6791	/* Bit 2 : Request status for RR[2]. */
Kojto	91:031413cf7a89	6792	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
Kojto	91:031413cf7a89	6793	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
Kojto	91:031413cf7a89	6794	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
Kojto	91:031413cf7a89	6795	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
Kojto	91:031413cf7a89	6796
Kojto	91:031413cf7a89	6797	/* Bit 1 : Request status for RR[1]. */
Kojto	91:031413cf7a89	6798	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
Kojto	91:031413cf7a89	6799	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
Kojto	91:031413cf7a89	6800	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
Kojto	91:031413cf7a89	6801	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
Kojto	91:031413cf7a89	6802
Kojto	91:031413cf7a89	6803	/* Bit 0 : Request status for RR[0]. */
Kojto	91:031413cf7a89	6804	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
Kojto	91:031413cf7a89	6805	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
Kojto	91:031413cf7a89	6806	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
Kojto	91:031413cf7a89	6807	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
Kojto	91:031413cf7a89	6808
Kojto	91:031413cf7a89	6809	/* Register: WDT_RREN */
Kojto	91:031413cf7a89	6810	/* Description: Reload request enable. */
Kojto	91:031413cf7a89	6811
Kojto	91:031413cf7a89	6812	/* Bit 7 : Enable or disable RR[7] register. */
Kojto	91:031413cf7a89	6813	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
Kojto	91:031413cf7a89	6814	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
Kojto	91:031413cf7a89	6815	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
Kojto	91:031413cf7a89	6816	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
Kojto	91:031413cf7a89	6817
Kojto	91:031413cf7a89	6818	/* Bit 6 : Enable or disable RR[6] register. */
Kojto	91:031413cf7a89	6819	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
Kojto	91:031413cf7a89	6820	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
Kojto	91:031413cf7a89	6821	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
Kojto	91:031413cf7a89	6822	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
Kojto	91:031413cf7a89	6823
Kojto	91:031413cf7a89	6824	/* Bit 5 : Enable or disable RR[5] register. */
Kojto	91:031413cf7a89	6825	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
Kojto	91:031413cf7a89	6826	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
Kojto	91:031413cf7a89	6827	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
Kojto	91:031413cf7a89	6828	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
Kojto	91:031413cf7a89	6829
Kojto	91:031413cf7a89	6830	/* Bit 4 : Enable or disable RR[4] register. */
Kojto	91:031413cf7a89	6831	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
Kojto	91:031413cf7a89	6832	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
Kojto	91:031413cf7a89	6833	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
Kojto	91:031413cf7a89	6834	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
Kojto	91:031413cf7a89	6835
Kojto	91:031413cf7a89	6836	/* Bit 3 : Enable or disable RR[3] register. */
Kojto	91:031413cf7a89	6837	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
Kojto	91:031413cf7a89	6838	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
Kojto	91:031413cf7a89	6839	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
Kojto	91:031413cf7a89	6840	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
Kojto	91:031413cf7a89	6841
Kojto	91:031413cf7a89	6842	/* Bit 2 : Enable or disable RR[2] register. */
Kojto	91:031413cf7a89	6843	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
Kojto	91:031413cf7a89	6844	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
Kojto	91:031413cf7a89	6845	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
Kojto	91:031413cf7a89	6846	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
Kojto	91:031413cf7a89	6847
Kojto	91:031413cf7a89	6848	/* Bit 1 : Enable or disable RR[1] register. */
Kojto	91:031413cf7a89	6849	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
Kojto	91:031413cf7a89	6850	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
Kojto	91:031413cf7a89	6851	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
Kojto	91:031413cf7a89	6852	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
Kojto	91:031413cf7a89	6853
Kojto	91:031413cf7a89	6854	/* Bit 0 : Enable or disable RR[0] register. */
Kojto	91:031413cf7a89	6855	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
Kojto	91:031413cf7a89	6856	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
Kojto	91:031413cf7a89	6857	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
Kojto	91:031413cf7a89	6858	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
Kojto	91:031413cf7a89	6859
Kojto	91:031413cf7a89	6860	/* Register: WDT_CONFIG */
Kojto	91:031413cf7a89	6861	/* Description: Configuration register. */
Kojto	91:031413cf7a89	6862
Kojto	91:031413cf7a89	6863	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
Kojto	91:031413cf7a89	6864	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
Kojto	91:031413cf7a89	6865	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
Kojto	91:031413cf7a89	6866	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
Kojto	91:031413cf7a89	6867	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
Kojto	91:031413cf7a89	6868
Kojto	91:031413cf7a89	6869	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
Kojto	91:031413cf7a89	6870	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
Kojto	91:031413cf7a89	6871	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
Kojto	91:031413cf7a89	6872	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
Kojto	91:031413cf7a89	6873	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
Kojto	91:031413cf7a89	6874
Kojto	91:031413cf7a89	6875	/* Register: WDT_RR */
Kojto	91:031413cf7a89	6876	/* Description: Reload requests registers. */
Kojto	91:031413cf7a89	6877
Kojto	91:031413cf7a89	6878	/* Bits 31..0 : Reload register. */
Kojto	91:031413cf7a89	6879	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
Kojto	91:031413cf7a89	6880	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
Kojto	91:031413cf7a89	6881	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
Kojto	91:031413cf7a89	6882
Kojto	91:031413cf7a89	6883	/* Register: WDT_POWER */
Kojto	91:031413cf7a89	6884	/* Description: Peripheral power control. */
Kojto	91:031413cf7a89	6885
Kojto	91:031413cf7a89	6886	/* Bit 0 : Peripheral power control. */
Kojto	91:031413cf7a89	6887	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	91:031413cf7a89	6888	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	91:031413cf7a89	6889	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	91:031413cf7a89	6890	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	91:031413cf7a89	6891
Kojto	91:031413cf7a89	6892
Kojto	91:031413cf7a89	6893	/lint --flb "Leave library region" /
Kojto	91:031413cf7a89	6894	#endif

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Created:	17 Jan 2017
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