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TARGET_HRM1017/nrf51_bitfields.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:: Kojto
Date:: Thu Jul 07 14:34:11 2016 +0100
Revision:: 122:f9eeca106725
Parent:: 97:433970e64889

Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	122:f9eeca106725	1	/*
Kojto	122:f9eeca106725	2	* Copyright (c) Nordic Semiconductor ASA
Kojto	97:433970e64889	3	* All rights reserved.
Kojto	97:433970e64889	4	*
Kojto	122:f9eeca106725	5	* Redistribution and use in source and binary forms, with or without modification,
Kojto	122:f9eeca106725	6	* are permitted provided that the following conditions are met:
Kojto	97:433970e64889	7	*
Kojto	122:f9eeca106725	8	* 1. Redistributions of source code must retain the above copyright notice, this
Kojto	122:f9eeca106725	9	* list of conditions and the following disclaimer.
Kojto	97:433970e64889	10	*
Kojto	122:f9eeca106725	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
Kojto	122:f9eeca106725	12	* list of conditions and the following disclaimer in the documentation and/or
Kojto	122:f9eeca106725	13	* other materials provided with the distribution.
bogdanm	87:6213f644d804	14	*
Kojto	122:f9eeca106725	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
Kojto	122:f9eeca106725	16	* contributors to this software may be used to endorse or promote products
Kojto	122:f9eeca106725	17	* derived from this software without specific prior written permission.
Kojto	122:f9eeca106725	18	*
bogdanm	87:6213f644d804	19	*
Kojto	122:f9eeca106725	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto	122:f9eeca106725	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto	122:f9eeca106725	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	122:f9eeca106725	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto	122:f9eeca106725	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto	122:f9eeca106725	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto	122:f9eeca106725	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto	122:f9eeca106725	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto	122:f9eeca106725	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto	122:f9eeca106725	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	87:6213f644d804	30	*
bogdanm	87:6213f644d804	31	*/
bogdanm	87:6213f644d804	32	#ifndef __NRF51_BITS_H
bogdanm	87:6213f644d804	33	#define __NRF51_BITS_H
bogdanm	87:6213f644d804	34
Kojto	122:f9eeca106725	35	/lint ++flb "Enter library region" /
bogdanm	87:6213f644d804	36
bogdanm	87:6213f644d804	37	/* Peripheral: AAR */
bogdanm	87:6213f644d804	38	/* Description: Accelerated Address Resolver. */
bogdanm	87:6213f644d804	39
bogdanm	87:6213f644d804	40	/* Register: AAR_INTENSET */
bogdanm	87:6213f644d804	41	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	42
bogdanm	87:6213f644d804	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
bogdanm	87:6213f644d804	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
bogdanm	87:6213f644d804	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
bogdanm	87:6213f644d804	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	49
bogdanm	87:6213f644d804	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
bogdanm	87:6213f644d804	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
bogdanm	87:6213f644d804	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
bogdanm	87:6213f644d804	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	56
bogdanm	87:6213f644d804	57	/* Bit 0 : Enable interrupt on END event. */
bogdanm	87:6213f644d804	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
bogdanm	87:6213f644d804	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	87:6213f644d804	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	63
bogdanm	87:6213f644d804	64	/* Register: AAR_INTENCLR */
bogdanm	87:6213f644d804	65	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	66
bogdanm	87:6213f644d804	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
bogdanm	87:6213f644d804	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
bogdanm	87:6213f644d804	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
bogdanm	87:6213f644d804	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	73
bogdanm	87:6213f644d804	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
bogdanm	87:6213f644d804	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
bogdanm	87:6213f644d804	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
bogdanm	87:6213f644d804	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	80
bogdanm	87:6213f644d804	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
bogdanm	87:6213f644d804	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
bogdanm	87:6213f644d804	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	87:6213f644d804	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	87
bogdanm	87:6213f644d804	88	/* Register: AAR_STATUS */
bogdanm	87:6213f644d804	89	/* Description: Resolution status. */
bogdanm	87:6213f644d804	90
bogdanm	87:6213f644d804	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
bogdanm	87:6213f644d804	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
bogdanm	87:6213f644d804	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
bogdanm	87:6213f644d804	94
bogdanm	87:6213f644d804	95	/* Register: AAR_ENABLE */
bogdanm	87:6213f644d804	96	/* Description: Enable AAR. */
bogdanm	87:6213f644d804	97
bogdanm	87:6213f644d804	98	/* Bits 1..0 : Enable AAR. */
bogdanm	87:6213f644d804	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
bogdanm	87:6213f644d804	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
bogdanm	87:6213f644d804	103
bogdanm	87:6213f644d804	104	/* Register: AAR_NIRK */
bogdanm	87:6213f644d804	105	/* Description: Number of Identity root Keys in the IRK data structure. */
bogdanm	87:6213f644d804	106
bogdanm	87:6213f644d804	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
bogdanm	87:6213f644d804	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
bogdanm	87:6213f644d804	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
bogdanm	87:6213f644d804	110
bogdanm	87:6213f644d804	111	/* Register: AAR_POWER */
bogdanm	87:6213f644d804	112	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	113
bogdanm	87:6213f644d804	114	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	119
bogdanm	87:6213f644d804	120
bogdanm	87:6213f644d804	121	/* Peripheral: ADC */
bogdanm	87:6213f644d804	122	/* Description: Analog to digital converter. */
bogdanm	87:6213f644d804	123
bogdanm	87:6213f644d804	124	/* Register: ADC_INTENSET */
bogdanm	87:6213f644d804	125	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	126
bogdanm	87:6213f644d804	127	/* Bit 0 : Enable interrupt on END event. */
bogdanm	87:6213f644d804	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
bogdanm	87:6213f644d804	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	87:6213f644d804	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	133
bogdanm	87:6213f644d804	134	/* Register: ADC_INTENCLR */
bogdanm	87:6213f644d804	135	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	136
bogdanm	87:6213f644d804	137	/* Bit 0 : Disable interrupt on END event. */
bogdanm	87:6213f644d804	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
bogdanm	87:6213f644d804	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	87:6213f644d804	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	143
bogdanm	87:6213f644d804	144	/* Register: ADC_BUSY */
bogdanm	87:6213f644d804	145	/* Description: ADC busy register. */
bogdanm	87:6213f644d804	146
bogdanm	87:6213f644d804	147	/* Bit 0 : ADC busy register. */
bogdanm	87:6213f644d804	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
bogdanm	87:6213f644d804	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
bogdanm	87:6213f644d804	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
bogdanm	87:6213f644d804	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
bogdanm	87:6213f644d804	152
bogdanm	87:6213f644d804	153	/* Register: ADC_ENABLE */
bogdanm	87:6213f644d804	154	/* Description: ADC enable. */
bogdanm	87:6213f644d804	155
bogdanm	87:6213f644d804	156	/* Bits 1..0 : ADC enable. */
bogdanm	87:6213f644d804	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
bogdanm	87:6213f644d804	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
bogdanm	87:6213f644d804	161
bogdanm	87:6213f644d804	162	/* Register: ADC_CONFIG */
bogdanm	87:6213f644d804	163	/* Description: ADC configuration register. */
bogdanm	87:6213f644d804	164
bogdanm	87:6213f644d804	165	/* Bits 17..16 : ADC external reference pin selection. */
bogdanm	87:6213f644d804	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
bogdanm	87:6213f644d804	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
bogdanm	87:6213f644d804	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
bogdanm	87:6213f644d804	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
bogdanm	87:6213f644d804	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
bogdanm	87:6213f644d804	171
bogdanm	87:6213f644d804	172	/* Bits 15..8 : ADC analog pin selection. */
bogdanm	87:6213f644d804	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
bogdanm	87:6213f644d804	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	87:6213f644d804	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
bogdanm	87:6213f644d804	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
bogdanm	87:6213f644d804	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
bogdanm	87:6213f644d804	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
bogdanm	87:6213f644d804	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
bogdanm	87:6213f644d804	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
bogdanm	87:6213f644d804	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
bogdanm	87:6213f644d804	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
bogdanm	87:6213f644d804	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
bogdanm	87:6213f644d804	184
bogdanm	87:6213f644d804	185	/* Bits 6..5 : ADC reference selection. */
bogdanm	87:6213f644d804	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
bogdanm	87:6213f644d804	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
bogdanm	87:6213f644d804	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
bogdanm	87:6213f644d804	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
bogdanm	87:6213f644d804	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
bogdanm	87:6213f644d804	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
bogdanm	87:6213f644d804	192
bogdanm	87:6213f644d804	193	/* Bits 4..2 : ADC input selection. */
bogdanm	87:6213f644d804	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
bogdanm	87:6213f644d804	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
bogdanm	87:6213f644d804	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
bogdanm	87:6213f644d804	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
bogdanm	87:6213f644d804	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
bogdanm	87:6213f644d804	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
bogdanm	87:6213f644d804	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
bogdanm	87:6213f644d804	201
bogdanm	87:6213f644d804	202	/* Bits 1..0 : ADC resolution. */
bogdanm	87:6213f644d804	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
bogdanm	87:6213f644d804	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
bogdanm	87:6213f644d804	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
bogdanm	87:6213f644d804	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
bogdanm	87:6213f644d804	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
bogdanm	87:6213f644d804	208
bogdanm	87:6213f644d804	209	/* Register: ADC_RESULT */
bogdanm	87:6213f644d804	210	/* Description: Result of ADC conversion. */
bogdanm	87:6213f644d804	211
bogdanm	87:6213f644d804	212	/* Bits 9..0 : Result of ADC conversion. */
bogdanm	87:6213f644d804	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
bogdanm	87:6213f644d804	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
bogdanm	87:6213f644d804	215
bogdanm	87:6213f644d804	216	/* Register: ADC_POWER */
bogdanm	87:6213f644d804	217	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	218
bogdanm	87:6213f644d804	219	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	224
bogdanm	87:6213f644d804	225
bogdanm	87:6213f644d804	226	/* Peripheral: AMLI */
bogdanm	87:6213f644d804	227	/* Description: AHB Multi-Layer Interface. */
bogdanm	87:6213f644d804	228
bogdanm	87:6213f644d804	229	/* Register: AMLI_RAMPRI_CPU0 */
bogdanm	87:6213f644d804	230	/* Description: Configurable priority configuration register for CPU0. */
bogdanm	87:6213f644d804	231
Kojto	97:433970e64889	232	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	243
Kojto	97:433970e64889	244	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	255
Kojto	97:433970e64889	256	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	267
Kojto	97:433970e64889	268	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	279
bogdanm	87:6213f644d804	280	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	87:6213f644d804	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	87:6213f644d804	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	291
bogdanm	87:6213f644d804	292	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	87:6213f644d804	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	87:6213f644d804	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	303
bogdanm	87:6213f644d804	304	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	87:6213f644d804	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	87:6213f644d804	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	315
bogdanm	87:6213f644d804	316	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	87:6213f644d804	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	87:6213f644d804	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	327
bogdanm	87:6213f644d804	328	/* Register: AMLI_RAMPRI_SPIS1 */
bogdanm	87:6213f644d804	329	/* Description: Configurable priority configuration register for SPIS1. */
bogdanm	87:6213f644d804	330
Kojto	97:433970e64889	331	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	342
Kojto	97:433970e64889	343	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	354
Kojto	97:433970e64889	355	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	366
Kojto	97:433970e64889	367	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	378
bogdanm	87:6213f644d804	379	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	87:6213f644d804	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	87:6213f644d804	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	390
bogdanm	87:6213f644d804	391	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	87:6213f644d804	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	87:6213f644d804	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	402
bogdanm	87:6213f644d804	403	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	87:6213f644d804	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	87:6213f644d804	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	414
bogdanm	87:6213f644d804	415	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	87:6213f644d804	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	87:6213f644d804	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	426
bogdanm	87:6213f644d804	427	/* Register: AMLI_RAMPRI_RADIO */
bogdanm	87:6213f644d804	428	/* Description: Configurable priority configuration register for RADIO. */
bogdanm	87:6213f644d804	429
Kojto	97:433970e64889	430	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	441
Kojto	97:433970e64889	442	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	453
Kojto	97:433970e64889	454	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	465
Kojto	97:433970e64889	466	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	477
bogdanm	87:6213f644d804	478	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	87:6213f644d804	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	87:6213f644d804	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	489
bogdanm	87:6213f644d804	490	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	87:6213f644d804	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	87:6213f644d804	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	501
bogdanm	87:6213f644d804	502	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	87:6213f644d804	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	87:6213f644d804	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	513
bogdanm	87:6213f644d804	514	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	87:6213f644d804	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	87:6213f644d804	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	525
bogdanm	87:6213f644d804	526	/* Register: AMLI_RAMPRI_ECB */
bogdanm	87:6213f644d804	527	/* Description: Configurable priority configuration register for ECB. */
bogdanm	87:6213f644d804	528
Kojto	97:433970e64889	529	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	540
Kojto	97:433970e64889	541	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	552
Kojto	97:433970e64889	553	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	564
Kojto	97:433970e64889	565	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	576
bogdanm	87:6213f644d804	577	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	87:6213f644d804	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	87:6213f644d804	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	588
bogdanm	87:6213f644d804	589	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	87:6213f644d804	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	87:6213f644d804	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	600
bogdanm	87:6213f644d804	601	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	87:6213f644d804	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	87:6213f644d804	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	612
bogdanm	87:6213f644d804	613	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	87:6213f644d804	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	87:6213f644d804	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	624
bogdanm	87:6213f644d804	625	/* Register: AMLI_RAMPRI_CCM */
bogdanm	87:6213f644d804	626	/* Description: Configurable priority configuration register for CCM. */
bogdanm	87:6213f644d804	627
Kojto	97:433970e64889	628	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	639
Kojto	97:433970e64889	640	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	651
Kojto	97:433970e64889	652	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	663
Kojto	97:433970e64889	664	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	675
bogdanm	87:6213f644d804	676	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	87:6213f644d804	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	87:6213f644d804	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	687
bogdanm	87:6213f644d804	688	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	87:6213f644d804	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	87:6213f644d804	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	699
bogdanm	87:6213f644d804	700	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	87:6213f644d804	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	87:6213f644d804	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	711
bogdanm	87:6213f644d804	712	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	87:6213f644d804	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	87:6213f644d804	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	723
bogdanm	87:6213f644d804	724	/* Register: AMLI_RAMPRI_AAR */
bogdanm	87:6213f644d804	725	/* Description: Configurable priority configuration register for AAR. */
bogdanm	87:6213f644d804	726
Kojto	97:433970e64889	727	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	738
Kojto	97:433970e64889	739	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	750
Kojto	97:433970e64889	751	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	762
Kojto	97:433970e64889	763	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	774
bogdanm	87:6213f644d804	775	/* Bits 15..12 : Configuration field for RAM block 3. */
bogdanm	87:6213f644d804	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
bogdanm	87:6213f644d804	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	786
bogdanm	87:6213f644d804	787	/* Bits 11..8 : Configuration field for RAM block 2. */
bogdanm	87:6213f644d804	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
bogdanm	87:6213f644d804	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	798
bogdanm	87:6213f644d804	799	/* Bits 7..4 : Configuration field for RAM block 1. */
bogdanm	87:6213f644d804	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
bogdanm	87:6213f644d804	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	810
bogdanm	87:6213f644d804	811	/* Bits 3..0 : Configuration field for RAM block 0. */
bogdanm	87:6213f644d804	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
bogdanm	87:6213f644d804	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
bogdanm	87:6213f644d804	822
Kojto	122:f9eeca106725	823
bogdanm	87:6213f644d804	824	/* Peripheral: CCM */
bogdanm	87:6213f644d804	825	/* Description: AES CCM Mode Encryption. */
bogdanm	87:6213f644d804	826
bogdanm	87:6213f644d804	827	/* Register: CCM_SHORTS */
Kojto	97:433970e64889	828	/* Description: Shortcuts for the CCM. */
Kojto	97:433970e64889	829
Kojto	97:433970e64889	830	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
bogdanm	87:6213f644d804	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
bogdanm	87:6213f644d804	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
bogdanm	87:6213f644d804	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	834	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	835
bogdanm	87:6213f644d804	836	/* Register: CCM_INTENSET */
bogdanm	87:6213f644d804	837	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	838
bogdanm	87:6213f644d804	839	/* Bit 2 : Enable interrupt on ERROR event. */
bogdanm	87:6213f644d804	840	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
bogdanm	87:6213f644d804	841	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	87:6213f644d804	842	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	843	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	844	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	845
bogdanm	87:6213f644d804	846	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
bogdanm	87:6213f644d804	847	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
bogdanm	87:6213f644d804	848	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
bogdanm	87:6213f644d804	849	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	850	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	851	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	852
bogdanm	87:6213f644d804	853	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
bogdanm	87:6213f644d804	854	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
bogdanm	87:6213f644d804	855	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
bogdanm	87:6213f644d804	856	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	857	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	858	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	859
bogdanm	87:6213f644d804	860	/* Register: CCM_INTENCLR */
bogdanm	87:6213f644d804	861	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	862
bogdanm	87:6213f644d804	863	/* Bit 2 : Disable interrupt on ERROR event. */
bogdanm	87:6213f644d804	864	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
bogdanm	87:6213f644d804	865	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	87:6213f644d804	866	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	867	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	868	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	869
bogdanm	87:6213f644d804	870	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
bogdanm	87:6213f644d804	871	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
bogdanm	87:6213f644d804	872	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
bogdanm	87:6213f644d804	873	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	874	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	875	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	876
bogdanm	87:6213f644d804	877	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
bogdanm	87:6213f644d804	878	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
bogdanm	87:6213f644d804	879	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
bogdanm	87:6213f644d804	880	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	881	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	882	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	883
bogdanm	87:6213f644d804	884	/* Register: CCM_MICSTATUS */
bogdanm	87:6213f644d804	885	/* Description: CCM RX MIC check result. */
bogdanm	87:6213f644d804	886
bogdanm	87:6213f644d804	887	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
bogdanm	87:6213f644d804	888	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
bogdanm	87:6213f644d804	889	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
bogdanm	87:6213f644d804	890	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
bogdanm	87:6213f644d804	891	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
bogdanm	87:6213f644d804	892
bogdanm	87:6213f644d804	893	/* Register: CCM_ENABLE */
bogdanm	87:6213f644d804	894	/* Description: CCM enable. */
bogdanm	87:6213f644d804	895
bogdanm	87:6213f644d804	896	/* Bits 1..0 : CCM enable. */
bogdanm	87:6213f644d804	897	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	898	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	899	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
bogdanm	87:6213f644d804	900	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
bogdanm	87:6213f644d804	901
bogdanm	87:6213f644d804	902	/* Register: CCM_MODE */
bogdanm	87:6213f644d804	903	/* Description: Operation mode. */
bogdanm	87:6213f644d804	904
bogdanm	87:6213f644d804	905	/* Bit 0 : CCM mode operation. */
bogdanm	87:6213f644d804	906	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	87:6213f644d804	907	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	87:6213f644d804	908	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
bogdanm	87:6213f644d804	909	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
bogdanm	87:6213f644d804	910
bogdanm	87:6213f644d804	911	/* Register: CCM_POWER */
bogdanm	87:6213f644d804	912	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	913
bogdanm	87:6213f644d804	914	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	915	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	916	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	917	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	918	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	919
bogdanm	87:6213f644d804	920
bogdanm	87:6213f644d804	921	/* Peripheral: CLOCK */
bogdanm	87:6213f644d804	922	/* Description: Clock control. */
bogdanm	87:6213f644d804	923
bogdanm	87:6213f644d804	924	/* Register: CLOCK_INTENSET */
bogdanm	87:6213f644d804	925	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	926
bogdanm	87:6213f644d804	927	/* Bit 4 : Enable interrupt on CTTO event. */
bogdanm	87:6213f644d804	928	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
bogdanm	87:6213f644d804	929	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
bogdanm	87:6213f644d804	930	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	931	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	932	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	933
bogdanm	87:6213f644d804	934	/* Bit 3 : Enable interrupt on DONE event. */
bogdanm	87:6213f644d804	935	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
bogdanm	87:6213f644d804	936	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
bogdanm	87:6213f644d804	937	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	938	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	939	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	940
bogdanm	87:6213f644d804	941	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
bogdanm	87:6213f644d804	942	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
bogdanm	87:6213f644d804	943	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
bogdanm	87:6213f644d804	944	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	945	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	946	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	947
bogdanm	87:6213f644d804	948	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
bogdanm	87:6213f644d804	949	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
bogdanm	87:6213f644d804	950	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
bogdanm	87:6213f644d804	951	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	952	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	953	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	954
bogdanm	87:6213f644d804	955	/* Register: CLOCK_INTENCLR */
bogdanm	87:6213f644d804	956	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	957
bogdanm	87:6213f644d804	958	/* Bit 4 : Disable interrupt on CTTO event. */
bogdanm	87:6213f644d804	959	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
bogdanm	87:6213f644d804	960	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
bogdanm	87:6213f644d804	961	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	962	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	963	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	964
bogdanm	87:6213f644d804	965	/* Bit 3 : Disable interrupt on DONE event. */
bogdanm	87:6213f644d804	966	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
bogdanm	87:6213f644d804	967	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
bogdanm	87:6213f644d804	968	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	969	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	970	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	971
bogdanm	87:6213f644d804	972	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
bogdanm	87:6213f644d804	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
bogdanm	87:6213f644d804	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
bogdanm	87:6213f644d804	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	977	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	978
bogdanm	87:6213f644d804	979	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
bogdanm	87:6213f644d804	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
bogdanm	87:6213f644d804	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
bogdanm	87:6213f644d804	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	984	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	985
Kojto	97:433970e64889	986	/* Register: CLOCK_HFCLKRUN */
Kojto	97:433970e64889	987	/* Description: Task HFCLKSTART trigger status. */
Kojto	97:433970e64889	988
Kojto	97:433970e64889	989	/* Bit 0 : Task HFCLKSTART trigger status. */
Kojto	97:433970e64889	990	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	97:433970e64889	991	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	97:433970e64889	992	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
Kojto	97:433970e64889	993	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
Kojto	97:433970e64889	994
bogdanm	87:6213f644d804	995	/* Register: CLOCK_HFCLKSTAT */
bogdanm	87:6213f644d804	996	/* Description: High frequency clock status. */
bogdanm	87:6213f644d804	997
bogdanm	87:6213f644d804	998	/* Bit 16 : State for the HFCLK. */
bogdanm	87:6213f644d804	999	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
bogdanm	87:6213f644d804	1000	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	87:6213f644d804	1001	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
bogdanm	87:6213f644d804	1002	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
bogdanm	87:6213f644d804	1003
bogdanm	87:6213f644d804	1004	/* Bit 0 : Active clock source for the HF clock. */
bogdanm	87:6213f644d804	1005	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	87:6213f644d804	1006	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	87:6213f644d804	1007	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
bogdanm	87:6213f644d804	1008	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
bogdanm	87:6213f644d804	1009
Kojto	97:433970e64889	1010	/* Register: CLOCK_LFCLKRUN */
Kojto	97:433970e64889	1011	/* Description: Task LFCLKSTART triggered status. */
Kojto	97:433970e64889	1012
Kojto	97:433970e64889	1013	/* Bit 0 : Task LFCLKSTART triggered status. */
Kojto	97:433970e64889	1014	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	97:433970e64889	1015	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	97:433970e64889	1016	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
Kojto	97:433970e64889	1017	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
Kojto	97:433970e64889	1018
bogdanm	87:6213f644d804	1019	/* Register: CLOCK_LFCLKSTAT */
bogdanm	87:6213f644d804	1020	/* Description: Low frequency clock status. */
bogdanm	87:6213f644d804	1021
bogdanm	87:6213f644d804	1022	/* Bit 16 : State for the LF clock. */
bogdanm	87:6213f644d804	1023	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
bogdanm	87:6213f644d804	1024	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	87:6213f644d804	1025	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
bogdanm	87:6213f644d804	1026	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
bogdanm	87:6213f644d804	1027
bogdanm	87:6213f644d804	1028	/* Bits 1..0 : Active clock source for the LF clock. */
bogdanm	87:6213f644d804	1029	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	87:6213f644d804	1030	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	87:6213f644d804	1031	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
bogdanm	87:6213f644d804	1032	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
bogdanm	87:6213f644d804	1033	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
bogdanm	87:6213f644d804	1034
Kojto	97:433970e64889	1035	/* Register: CLOCK_LFCLKSRCCOPY */
Kojto	97:433970e64889	1036	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto	97:433970e64889	1037
Kojto	97:433970e64889	1038	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto	97:433970e64889	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	97:433970e64889	1040	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	97:433970e64889	1041	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
Kojto	97:433970e64889	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
Kojto	97:433970e64889	1043	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
Kojto	97:433970e64889	1044
bogdanm	87:6213f644d804	1045	/* Register: CLOCK_LFCLKSRC */
bogdanm	87:6213f644d804	1046	/* Description: Clock source for the LFCLK clock. */
bogdanm	87:6213f644d804	1047
bogdanm	87:6213f644d804	1048	/* Bits 1..0 : Clock source. */
bogdanm	87:6213f644d804	1049	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
bogdanm	87:6213f644d804	1050	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
bogdanm	87:6213f644d804	1051	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
bogdanm	87:6213f644d804	1052	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
bogdanm	87:6213f644d804	1053	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
bogdanm	87:6213f644d804	1054
bogdanm	87:6213f644d804	1055	/* Register: CLOCK_CTIV */
bogdanm	87:6213f644d804	1056	/* Description: Calibration timer interval. */
bogdanm	87:6213f644d804	1057
bogdanm	87:6213f644d804	1058	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
bogdanm	87:6213f644d804	1059	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
bogdanm	87:6213f644d804	1060	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
bogdanm	87:6213f644d804	1061
bogdanm	87:6213f644d804	1062	/* Register: CLOCK_XTALFREQ */
bogdanm	87:6213f644d804	1063	/* Description: Crystal frequency. */
bogdanm	87:6213f644d804	1064
bogdanm	87:6213f644d804	1065	/* Bits 7..0 : External Xtal frequency selection. */
bogdanm	87:6213f644d804	1066	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
bogdanm	87:6213f644d804	1067	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
Kojto	122:f9eeca106725	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
Kojto	97:433970e64889	1069	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
bogdanm	87:6213f644d804	1070
bogdanm	87:6213f644d804	1071
bogdanm	87:6213f644d804	1072	/* Peripheral: ECB */
bogdanm	87:6213f644d804	1073	/* Description: AES ECB Mode Encryption. */
bogdanm	87:6213f644d804	1074
bogdanm	87:6213f644d804	1075	/* Register: ECB_INTENSET */
bogdanm	87:6213f644d804	1076	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	1077
bogdanm	87:6213f644d804	1078	/* Bit 1 : Enable interrupt on ERRORECB event. */
bogdanm	87:6213f644d804	1079	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
bogdanm	87:6213f644d804	1080	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
bogdanm	87:6213f644d804	1081	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	1082	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	1083	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	1084
bogdanm	87:6213f644d804	1085	/* Bit 0 : Enable interrupt on ENDECB event. */
bogdanm	87:6213f644d804	1086	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
bogdanm	87:6213f644d804	1087	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
bogdanm	87:6213f644d804	1088	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	1089	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	1090	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	1091
bogdanm	87:6213f644d804	1092	/* Register: ECB_INTENCLR */
bogdanm	87:6213f644d804	1093	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	1094
bogdanm	87:6213f644d804	1095	/* Bit 1 : Disable interrupt on ERRORECB event. */
bogdanm	87:6213f644d804	1096	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
bogdanm	87:6213f644d804	1097	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
bogdanm	87:6213f644d804	1098	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	1099	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	1100	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	1101
bogdanm	87:6213f644d804	1102	/* Bit 0 : Disable interrupt on ENDECB event. */
bogdanm	87:6213f644d804	1103	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
bogdanm	87:6213f644d804	1104	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
bogdanm	87:6213f644d804	1105	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	1106	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	1107	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	1108
bogdanm	87:6213f644d804	1109	/* Register: ECB_POWER */
bogdanm	87:6213f644d804	1110	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	1111
bogdanm	87:6213f644d804	1112	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	1113	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	1114	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	1115	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	1116	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	1117
bogdanm	87:6213f644d804	1118
bogdanm	87:6213f644d804	1119	/* Peripheral: FICR */
bogdanm	87:6213f644d804	1120	/* Description: Factory Information Configuration. */
bogdanm	87:6213f644d804	1121
bogdanm	87:6213f644d804	1122	/* Register: FICR_PPFC */
bogdanm	87:6213f644d804	1123	/* Description: Pre-programmed factory code present. */
bogdanm	87:6213f644d804	1124
bogdanm	87:6213f644d804	1125	/* Bits 7..0 : Pre-programmed factory code present. */
bogdanm	87:6213f644d804	1126	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
bogdanm	87:6213f644d804	1127	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
Kojto	122:f9eeca106725	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
bogdanm	87:6213f644d804	1129	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
bogdanm	87:6213f644d804	1130
bogdanm	87:6213f644d804	1131	/* Register: FICR_CONFIGID */
bogdanm	87:6213f644d804	1132	/* Description: Configuration identifier. */
bogdanm	87:6213f644d804	1133
bogdanm	87:6213f644d804	1134	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
bogdanm	87:6213f644d804	1135	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
bogdanm	87:6213f644d804	1136	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
bogdanm	87:6213f644d804	1137
bogdanm	87:6213f644d804	1138	/* Bits 15..0 : Hardware Identification Number. */
bogdanm	87:6213f644d804	1139	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
bogdanm	87:6213f644d804	1140	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
bogdanm	87:6213f644d804	1141
bogdanm	87:6213f644d804	1142	/* Register: FICR_DEVICEADDRTYPE */
bogdanm	87:6213f644d804	1143	/* Description: Device address type. */
bogdanm	87:6213f644d804	1144
bogdanm	87:6213f644d804	1145	/* Bit 0 : Device address type. */
bogdanm	87:6213f644d804	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
bogdanm	87:6213f644d804	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
bogdanm	87:6213f644d804	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
bogdanm	87:6213f644d804	1149	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
bogdanm	87:6213f644d804	1150
bogdanm	87:6213f644d804	1151	/* Register: FICR_OVERRIDEEN */
bogdanm	87:6213f644d804	1152	/* Description: Radio calibration override enable. */
bogdanm	87:6213f644d804	1153
bogdanm	87:6213f644d804	1154	/* Bit 3 : Override default values for BLE_1Mbit mode. */
bogdanm	87:6213f644d804	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
bogdanm	87:6213f644d804	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
bogdanm	87:6213f644d804	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
bogdanm	87:6213f644d804	1158	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
bogdanm	87:6213f644d804	1159
Kojto	97:433970e64889	1160	/* Bit 0 : Override default values for NRF_1Mbit mode. */
Kojto	97:433970e64889	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
Kojto	97:433970e64889	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
Kojto	97:433970e64889	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
Kojto	97:433970e64889	1164	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
Kojto	97:433970e64889	1165
bogdanm	87:6213f644d804	1166
bogdanm	87:6213f644d804	1167	/* Peripheral: GPIO */
bogdanm	87:6213f644d804	1168	/* Description: General purpose input and output. */
bogdanm	87:6213f644d804	1169
bogdanm	87:6213f644d804	1170	/* Register: GPIO_OUT */
bogdanm	87:6213f644d804	1171	/* Description: Write GPIO port. */
bogdanm	87:6213f644d804	1172
bogdanm	87:6213f644d804	1173	/* Bit 31 : Pin 31. */
bogdanm	87:6213f644d804	1174	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	87:6213f644d804	1175	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	87:6213f644d804	1176	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1177	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1178
bogdanm	87:6213f644d804	1179	/* Bit 30 : Pin 30. */
bogdanm	87:6213f644d804	1180	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	87:6213f644d804	1181	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	87:6213f644d804	1182	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1183	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1184
bogdanm	87:6213f644d804	1185	/* Bit 29 : Pin 29. */
bogdanm	87:6213f644d804	1186	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	87:6213f644d804	1187	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	87:6213f644d804	1188	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1189	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1190
bogdanm	87:6213f644d804	1191	/* Bit 28 : Pin 28. */
bogdanm	87:6213f644d804	1192	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	87:6213f644d804	1193	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	87:6213f644d804	1194	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1195	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1196
bogdanm	87:6213f644d804	1197	/* Bit 27 : Pin 27. */
bogdanm	87:6213f644d804	1198	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	87:6213f644d804	1199	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	87:6213f644d804	1200	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1201	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1202
bogdanm	87:6213f644d804	1203	/* Bit 26 : Pin 26. */
bogdanm	87:6213f644d804	1204	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	87:6213f644d804	1205	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	87:6213f644d804	1206	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1207	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1208
bogdanm	87:6213f644d804	1209	/* Bit 25 : Pin 25. */
bogdanm	87:6213f644d804	1210	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	87:6213f644d804	1211	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	87:6213f644d804	1212	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1213	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1214
bogdanm	87:6213f644d804	1215	/* Bit 24 : Pin 24. */
bogdanm	87:6213f644d804	1216	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	87:6213f644d804	1217	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	87:6213f644d804	1218	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1219	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1220
bogdanm	87:6213f644d804	1221	/* Bit 23 : Pin 23. */
bogdanm	87:6213f644d804	1222	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	87:6213f644d804	1223	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	87:6213f644d804	1224	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1225	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1226
bogdanm	87:6213f644d804	1227	/* Bit 22 : Pin 22. */
bogdanm	87:6213f644d804	1228	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	87:6213f644d804	1229	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	87:6213f644d804	1230	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1231	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1232
bogdanm	87:6213f644d804	1233	/* Bit 21 : Pin 21. */
bogdanm	87:6213f644d804	1234	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	87:6213f644d804	1235	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	87:6213f644d804	1236	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1237	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1238
bogdanm	87:6213f644d804	1239	/* Bit 20 : Pin 20. */
bogdanm	87:6213f644d804	1240	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	87:6213f644d804	1241	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	87:6213f644d804	1242	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1243	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1244
bogdanm	87:6213f644d804	1245	/* Bit 19 : Pin 19. */
bogdanm	87:6213f644d804	1246	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	87:6213f644d804	1247	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	87:6213f644d804	1248	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1249	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1250
bogdanm	87:6213f644d804	1251	/* Bit 18 : Pin 18. */
bogdanm	87:6213f644d804	1252	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	87:6213f644d804	1253	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	87:6213f644d804	1254	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1255	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1256
bogdanm	87:6213f644d804	1257	/* Bit 17 : Pin 17. */
bogdanm	87:6213f644d804	1258	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	87:6213f644d804	1259	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	87:6213f644d804	1260	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1261	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1262
bogdanm	87:6213f644d804	1263	/* Bit 16 : Pin 16. */
bogdanm	87:6213f644d804	1264	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	87:6213f644d804	1265	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	87:6213f644d804	1266	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1267	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1268
bogdanm	87:6213f644d804	1269	/* Bit 15 : Pin 15. */
bogdanm	87:6213f644d804	1270	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	87:6213f644d804	1271	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	87:6213f644d804	1272	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1273	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1274
bogdanm	87:6213f644d804	1275	/* Bit 14 : Pin 14. */
bogdanm	87:6213f644d804	1276	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	87:6213f644d804	1277	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	87:6213f644d804	1278	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1279	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1280
bogdanm	87:6213f644d804	1281	/* Bit 13 : Pin 13. */
bogdanm	87:6213f644d804	1282	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	87:6213f644d804	1283	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	87:6213f644d804	1284	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1285	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1286
bogdanm	87:6213f644d804	1287	/* Bit 12 : Pin 12. */
bogdanm	87:6213f644d804	1288	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	87:6213f644d804	1289	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	87:6213f644d804	1290	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1291	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1292
bogdanm	87:6213f644d804	1293	/* Bit 11 : Pin 11. */
bogdanm	87:6213f644d804	1294	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	87:6213f644d804	1295	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	87:6213f644d804	1296	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1297	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1298
bogdanm	87:6213f644d804	1299	/* Bit 10 : Pin 10. */
bogdanm	87:6213f644d804	1300	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	87:6213f644d804	1301	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	87:6213f644d804	1302	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1303	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1304
bogdanm	87:6213f644d804	1305	/* Bit 9 : Pin 9. */
bogdanm	87:6213f644d804	1306	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	87:6213f644d804	1307	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	87:6213f644d804	1308	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1309	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1310
bogdanm	87:6213f644d804	1311	/* Bit 8 : Pin 8. */
bogdanm	87:6213f644d804	1312	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	87:6213f644d804	1313	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	87:6213f644d804	1314	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1315	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1316
bogdanm	87:6213f644d804	1317	/* Bit 7 : Pin 7. */
bogdanm	87:6213f644d804	1318	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	87:6213f644d804	1319	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	87:6213f644d804	1320	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1321	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1322
bogdanm	87:6213f644d804	1323	/* Bit 6 : Pin 6. */
bogdanm	87:6213f644d804	1324	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	87:6213f644d804	1325	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	87:6213f644d804	1326	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1327	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1328
bogdanm	87:6213f644d804	1329	/* Bit 5 : Pin 5. */
bogdanm	87:6213f644d804	1330	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	87:6213f644d804	1331	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	87:6213f644d804	1332	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1333	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1334
bogdanm	87:6213f644d804	1335	/* Bit 4 : Pin 4. */
bogdanm	87:6213f644d804	1336	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	87:6213f644d804	1337	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	87:6213f644d804	1338	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1339	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1340
bogdanm	87:6213f644d804	1341	/* Bit 3 : Pin 3. */
bogdanm	87:6213f644d804	1342	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	87:6213f644d804	1343	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	87:6213f644d804	1344	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1345	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1346
bogdanm	87:6213f644d804	1347	/* Bit 2 : Pin 2. */
bogdanm	87:6213f644d804	1348	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	87:6213f644d804	1349	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	87:6213f644d804	1350	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1351	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1352
bogdanm	87:6213f644d804	1353	/* Bit 1 : Pin 1. */
bogdanm	87:6213f644d804	1354	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	87:6213f644d804	1355	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	87:6213f644d804	1356	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1357	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1358
bogdanm	87:6213f644d804	1359	/* Bit 0 : Pin 0. */
bogdanm	87:6213f644d804	1360	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	87:6213f644d804	1361	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	87:6213f644d804	1362	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1363	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1364
bogdanm	87:6213f644d804	1365	/* Register: GPIO_OUTSET */
bogdanm	87:6213f644d804	1366	/* Description: Set individual bits in GPIO port. */
bogdanm	87:6213f644d804	1367
bogdanm	87:6213f644d804	1368	/* Bit 31 : Pin 31. */
bogdanm	87:6213f644d804	1369	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	87:6213f644d804	1370	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	87:6213f644d804	1371	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1372	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1373	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1374
bogdanm	87:6213f644d804	1375	/* Bit 30 : Pin 30. */
bogdanm	87:6213f644d804	1376	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	87:6213f644d804	1377	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	87:6213f644d804	1378	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1379	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1380	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1381
bogdanm	87:6213f644d804	1382	/* Bit 29 : Pin 29. */
bogdanm	87:6213f644d804	1383	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	87:6213f644d804	1384	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	87:6213f644d804	1385	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1386	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1387	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1388
bogdanm	87:6213f644d804	1389	/* Bit 28 : Pin 28. */
bogdanm	87:6213f644d804	1390	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	87:6213f644d804	1391	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	87:6213f644d804	1392	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1393	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1394	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1395
bogdanm	87:6213f644d804	1396	/* Bit 27 : Pin 27. */
bogdanm	87:6213f644d804	1397	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	87:6213f644d804	1398	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	87:6213f644d804	1399	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1400	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1401	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1402
bogdanm	87:6213f644d804	1403	/* Bit 26 : Pin 26. */
bogdanm	87:6213f644d804	1404	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	87:6213f644d804	1405	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	87:6213f644d804	1406	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1407	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1408	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1409
bogdanm	87:6213f644d804	1410	/* Bit 25 : Pin 25. */
bogdanm	87:6213f644d804	1411	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	87:6213f644d804	1412	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	87:6213f644d804	1413	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1414	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1415	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1416
bogdanm	87:6213f644d804	1417	/* Bit 24 : Pin 24. */
bogdanm	87:6213f644d804	1418	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	87:6213f644d804	1419	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	87:6213f644d804	1420	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1421	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1422	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1423
bogdanm	87:6213f644d804	1424	/* Bit 23 : Pin 23. */
bogdanm	87:6213f644d804	1425	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	87:6213f644d804	1426	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	87:6213f644d804	1427	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1428	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1429	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1430
bogdanm	87:6213f644d804	1431	/* Bit 22 : Pin 22. */
bogdanm	87:6213f644d804	1432	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	87:6213f644d804	1433	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	87:6213f644d804	1434	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1435	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1436	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1437
bogdanm	87:6213f644d804	1438	/* Bit 21 : Pin 21. */
bogdanm	87:6213f644d804	1439	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	87:6213f644d804	1440	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	87:6213f644d804	1441	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1442	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1443	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1444
bogdanm	87:6213f644d804	1445	/* Bit 20 : Pin 20. */
bogdanm	87:6213f644d804	1446	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	87:6213f644d804	1447	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	87:6213f644d804	1448	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1449	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1450	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1451
bogdanm	87:6213f644d804	1452	/* Bit 19 : Pin 19. */
bogdanm	87:6213f644d804	1453	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	87:6213f644d804	1454	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	87:6213f644d804	1455	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1456	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1457	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1458
bogdanm	87:6213f644d804	1459	/* Bit 18 : Pin 18. */
bogdanm	87:6213f644d804	1460	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	87:6213f644d804	1461	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	87:6213f644d804	1462	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1463	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1464	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1465
bogdanm	87:6213f644d804	1466	/* Bit 17 : Pin 17. */
bogdanm	87:6213f644d804	1467	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	87:6213f644d804	1468	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	87:6213f644d804	1469	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1470	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1471	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1472
bogdanm	87:6213f644d804	1473	/* Bit 16 : Pin 16. */
bogdanm	87:6213f644d804	1474	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	87:6213f644d804	1475	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	87:6213f644d804	1476	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1477	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1478	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1479
bogdanm	87:6213f644d804	1480	/* Bit 15 : Pin 15. */
bogdanm	87:6213f644d804	1481	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	87:6213f644d804	1482	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	87:6213f644d804	1483	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1484	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1485	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1486
bogdanm	87:6213f644d804	1487	/* Bit 14 : Pin 14. */
bogdanm	87:6213f644d804	1488	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	87:6213f644d804	1489	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	87:6213f644d804	1490	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1491	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1492	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1493
bogdanm	87:6213f644d804	1494	/* Bit 13 : Pin 13. */
bogdanm	87:6213f644d804	1495	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	87:6213f644d804	1496	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	87:6213f644d804	1497	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1498	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1499	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1500
bogdanm	87:6213f644d804	1501	/* Bit 12 : Pin 12. */
bogdanm	87:6213f644d804	1502	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	87:6213f644d804	1503	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	87:6213f644d804	1504	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1505	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1506	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1507
bogdanm	87:6213f644d804	1508	/* Bit 11 : Pin 11. */
bogdanm	87:6213f644d804	1509	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	87:6213f644d804	1510	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	87:6213f644d804	1511	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1512	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1513	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1514
bogdanm	87:6213f644d804	1515	/* Bit 10 : Pin 10. */
bogdanm	87:6213f644d804	1516	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	87:6213f644d804	1517	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	87:6213f644d804	1518	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1519	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1520	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1521
bogdanm	87:6213f644d804	1522	/* Bit 9 : Pin 9. */
bogdanm	87:6213f644d804	1523	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	87:6213f644d804	1524	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	87:6213f644d804	1525	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1526	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1527	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1528
bogdanm	87:6213f644d804	1529	/* Bit 8 : Pin 8. */
bogdanm	87:6213f644d804	1530	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	87:6213f644d804	1531	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	87:6213f644d804	1532	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1533	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1534	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1535
bogdanm	87:6213f644d804	1536	/* Bit 7 : Pin 7. */
bogdanm	87:6213f644d804	1537	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	87:6213f644d804	1538	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	87:6213f644d804	1539	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1540	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1541	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1542
bogdanm	87:6213f644d804	1543	/* Bit 6 : Pin 6. */
bogdanm	87:6213f644d804	1544	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	87:6213f644d804	1545	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	87:6213f644d804	1546	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1547	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1548	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1549
bogdanm	87:6213f644d804	1550	/* Bit 5 : Pin 5. */
bogdanm	87:6213f644d804	1551	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	87:6213f644d804	1552	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	87:6213f644d804	1553	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1554	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1555	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1556
bogdanm	87:6213f644d804	1557	/* Bit 4 : Pin 4. */
bogdanm	87:6213f644d804	1558	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	87:6213f644d804	1559	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	87:6213f644d804	1560	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1561	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1562	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1563
bogdanm	87:6213f644d804	1564	/* Bit 3 : Pin 3. */
bogdanm	87:6213f644d804	1565	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	87:6213f644d804	1566	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	87:6213f644d804	1567	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1568	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1569	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1570
bogdanm	87:6213f644d804	1571	/* Bit 2 : Pin 2. */
bogdanm	87:6213f644d804	1572	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	87:6213f644d804	1573	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	87:6213f644d804	1574	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1575	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1576	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1577
bogdanm	87:6213f644d804	1578	/* Bit 1 : Pin 1. */
bogdanm	87:6213f644d804	1579	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	87:6213f644d804	1580	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	87:6213f644d804	1581	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1582	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1583	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1584
bogdanm	87:6213f644d804	1585	/* Bit 0 : Pin 0. */
bogdanm	87:6213f644d804	1586	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	87:6213f644d804	1587	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	87:6213f644d804	1588	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1589	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1590	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
bogdanm	87:6213f644d804	1591
bogdanm	87:6213f644d804	1592	/* Register: GPIO_OUTCLR */
bogdanm	87:6213f644d804	1593	/* Description: Clear individual bits in GPIO port. */
bogdanm	87:6213f644d804	1594
bogdanm	87:6213f644d804	1595	/* Bit 31 : Pin 31. */
bogdanm	87:6213f644d804	1596	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	87:6213f644d804	1597	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	87:6213f644d804	1598	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1599	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1600	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1601
bogdanm	87:6213f644d804	1602	/* Bit 30 : Pin 30. */
bogdanm	87:6213f644d804	1603	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	87:6213f644d804	1604	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	87:6213f644d804	1605	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1606	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1607	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1608
bogdanm	87:6213f644d804	1609	/* Bit 29 : Pin 29. */
bogdanm	87:6213f644d804	1610	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	87:6213f644d804	1611	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	87:6213f644d804	1612	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1613	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1614	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1615
bogdanm	87:6213f644d804	1616	/* Bit 28 : Pin 28. */
bogdanm	87:6213f644d804	1617	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	87:6213f644d804	1618	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	87:6213f644d804	1619	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1620	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1621	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1622
bogdanm	87:6213f644d804	1623	/* Bit 27 : Pin 27. */
bogdanm	87:6213f644d804	1624	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	87:6213f644d804	1625	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	87:6213f644d804	1626	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1627	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1628	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1629
bogdanm	87:6213f644d804	1630	/* Bit 26 : Pin 26. */
bogdanm	87:6213f644d804	1631	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	87:6213f644d804	1632	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	87:6213f644d804	1633	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1634	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1635	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1636
bogdanm	87:6213f644d804	1637	/* Bit 25 : Pin 25. */
bogdanm	87:6213f644d804	1638	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	87:6213f644d804	1639	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	87:6213f644d804	1640	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1641	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1642	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1643
bogdanm	87:6213f644d804	1644	/* Bit 24 : Pin 24. */
bogdanm	87:6213f644d804	1645	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	87:6213f644d804	1646	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	87:6213f644d804	1647	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1648	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1649	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1650
bogdanm	87:6213f644d804	1651	/* Bit 23 : Pin 23. */
bogdanm	87:6213f644d804	1652	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	87:6213f644d804	1653	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	87:6213f644d804	1654	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1655	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1656	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1657
bogdanm	87:6213f644d804	1658	/* Bit 22 : Pin 22. */
bogdanm	87:6213f644d804	1659	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	87:6213f644d804	1660	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	87:6213f644d804	1661	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1662	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1663	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1664
bogdanm	87:6213f644d804	1665	/* Bit 21 : Pin 21. */
bogdanm	87:6213f644d804	1666	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	87:6213f644d804	1667	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	87:6213f644d804	1668	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1669	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1670	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1671
bogdanm	87:6213f644d804	1672	/* Bit 20 : Pin 20. */
bogdanm	87:6213f644d804	1673	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	87:6213f644d804	1674	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	87:6213f644d804	1675	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1676	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1677	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1678
bogdanm	87:6213f644d804	1679	/* Bit 19 : Pin 19. */
bogdanm	87:6213f644d804	1680	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	87:6213f644d804	1681	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	87:6213f644d804	1682	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1683	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1684	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1685
bogdanm	87:6213f644d804	1686	/* Bit 18 : Pin 18. */
bogdanm	87:6213f644d804	1687	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	87:6213f644d804	1688	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	87:6213f644d804	1689	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1690	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1691	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1692
bogdanm	87:6213f644d804	1693	/* Bit 17 : Pin 17. */
bogdanm	87:6213f644d804	1694	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	87:6213f644d804	1695	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	87:6213f644d804	1696	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1697	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1698	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1699
bogdanm	87:6213f644d804	1700	/* Bit 16 : Pin 16. */
bogdanm	87:6213f644d804	1701	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	87:6213f644d804	1702	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	87:6213f644d804	1703	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1704	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1705	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1706
bogdanm	87:6213f644d804	1707	/* Bit 15 : Pin 15. */
bogdanm	87:6213f644d804	1708	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	87:6213f644d804	1709	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	87:6213f644d804	1710	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1711	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1712	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1713
bogdanm	87:6213f644d804	1714	/* Bit 14 : Pin 14. */
bogdanm	87:6213f644d804	1715	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	87:6213f644d804	1716	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	87:6213f644d804	1717	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1718	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1719	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1720
bogdanm	87:6213f644d804	1721	/* Bit 13 : Pin 13. */
bogdanm	87:6213f644d804	1722	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	87:6213f644d804	1723	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	87:6213f644d804	1724	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1725	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1726	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1727
bogdanm	87:6213f644d804	1728	/* Bit 12 : Pin 12. */
bogdanm	87:6213f644d804	1729	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	87:6213f644d804	1730	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	87:6213f644d804	1731	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1732	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1733	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1734
bogdanm	87:6213f644d804	1735	/* Bit 11 : Pin 11. */
bogdanm	87:6213f644d804	1736	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	87:6213f644d804	1737	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	87:6213f644d804	1738	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1739	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1740	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1741
bogdanm	87:6213f644d804	1742	/* Bit 10 : Pin 10. */
bogdanm	87:6213f644d804	1743	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	87:6213f644d804	1744	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	87:6213f644d804	1745	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1746	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1747	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1748
bogdanm	87:6213f644d804	1749	/* Bit 9 : Pin 9. */
bogdanm	87:6213f644d804	1750	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	87:6213f644d804	1751	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	87:6213f644d804	1752	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1753	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1754	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1755
bogdanm	87:6213f644d804	1756	/* Bit 8 : Pin 8. */
bogdanm	87:6213f644d804	1757	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	87:6213f644d804	1758	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	87:6213f644d804	1759	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1760	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1761	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1762
bogdanm	87:6213f644d804	1763	/* Bit 7 : Pin 7. */
bogdanm	87:6213f644d804	1764	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	87:6213f644d804	1765	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	87:6213f644d804	1766	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1767	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1768	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1769
bogdanm	87:6213f644d804	1770	/* Bit 6 : Pin 6. */
bogdanm	87:6213f644d804	1771	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	87:6213f644d804	1772	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	87:6213f644d804	1773	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1774	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1775	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1776
bogdanm	87:6213f644d804	1777	/* Bit 5 : Pin 5. */
bogdanm	87:6213f644d804	1778	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	87:6213f644d804	1779	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	87:6213f644d804	1780	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1781	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1782	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1783
bogdanm	87:6213f644d804	1784	/* Bit 4 : Pin 4. */
bogdanm	87:6213f644d804	1785	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	87:6213f644d804	1786	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	87:6213f644d804	1787	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1788	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1789	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1790
bogdanm	87:6213f644d804	1791	/* Bit 3 : Pin 3. */
bogdanm	87:6213f644d804	1792	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	87:6213f644d804	1793	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	87:6213f644d804	1794	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1795	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1796	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1797
bogdanm	87:6213f644d804	1798	/* Bit 2 : Pin 2. */
bogdanm	87:6213f644d804	1799	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	87:6213f644d804	1800	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	87:6213f644d804	1801	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1802	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1803	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1804
bogdanm	87:6213f644d804	1805	/* Bit 1 : Pin 1. */
bogdanm	87:6213f644d804	1806	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	87:6213f644d804	1807	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	87:6213f644d804	1808	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1809	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1810	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1811
bogdanm	87:6213f644d804	1812	/* Bit 0 : Pin 0. */
bogdanm	87:6213f644d804	1813	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	87:6213f644d804	1814	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	87:6213f644d804	1815	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
bogdanm	87:6213f644d804	1816	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
bogdanm	87:6213f644d804	1817	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
bogdanm	87:6213f644d804	1818
bogdanm	87:6213f644d804	1819	/* Register: GPIO_IN */
bogdanm	87:6213f644d804	1820	/* Description: Read GPIO port. */
bogdanm	87:6213f644d804	1821
bogdanm	87:6213f644d804	1822	/* Bit 31 : Pin 31. */
bogdanm	87:6213f644d804	1823	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	87:6213f644d804	1824	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	87:6213f644d804	1825	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1826	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1827
bogdanm	87:6213f644d804	1828	/* Bit 30 : Pin 30. */
bogdanm	87:6213f644d804	1829	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	87:6213f644d804	1830	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	87:6213f644d804	1831	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1832	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1833
bogdanm	87:6213f644d804	1834	/* Bit 29 : Pin 29. */
bogdanm	87:6213f644d804	1835	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	87:6213f644d804	1836	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	87:6213f644d804	1837	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1838	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1839
bogdanm	87:6213f644d804	1840	/* Bit 28 : Pin 28. */
bogdanm	87:6213f644d804	1841	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	87:6213f644d804	1842	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	87:6213f644d804	1843	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1844	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1845
bogdanm	87:6213f644d804	1846	/* Bit 27 : Pin 27. */
bogdanm	87:6213f644d804	1847	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	87:6213f644d804	1848	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	87:6213f644d804	1849	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1850	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1851
bogdanm	87:6213f644d804	1852	/* Bit 26 : Pin 26. */
bogdanm	87:6213f644d804	1853	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	87:6213f644d804	1854	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	87:6213f644d804	1855	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1856	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1857
bogdanm	87:6213f644d804	1858	/* Bit 25 : Pin 25. */
bogdanm	87:6213f644d804	1859	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	87:6213f644d804	1860	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	87:6213f644d804	1861	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1862	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1863
bogdanm	87:6213f644d804	1864	/* Bit 24 : Pin 24. */
bogdanm	87:6213f644d804	1865	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	87:6213f644d804	1866	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	87:6213f644d804	1867	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1868	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1869
bogdanm	87:6213f644d804	1870	/* Bit 23 : Pin 23. */
bogdanm	87:6213f644d804	1871	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	87:6213f644d804	1872	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	87:6213f644d804	1873	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1874	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1875
bogdanm	87:6213f644d804	1876	/* Bit 22 : Pin 22. */
bogdanm	87:6213f644d804	1877	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	87:6213f644d804	1878	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	87:6213f644d804	1879	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1880	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1881
bogdanm	87:6213f644d804	1882	/* Bit 21 : Pin 21. */
bogdanm	87:6213f644d804	1883	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	87:6213f644d804	1884	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	87:6213f644d804	1885	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1886	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1887
bogdanm	87:6213f644d804	1888	/* Bit 20 : Pin 20. */
bogdanm	87:6213f644d804	1889	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	87:6213f644d804	1890	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	87:6213f644d804	1891	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1892	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1893
bogdanm	87:6213f644d804	1894	/* Bit 19 : Pin 19. */
bogdanm	87:6213f644d804	1895	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	87:6213f644d804	1896	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	87:6213f644d804	1897	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1898	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1899
bogdanm	87:6213f644d804	1900	/* Bit 18 : Pin 18. */
bogdanm	87:6213f644d804	1901	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	87:6213f644d804	1902	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	87:6213f644d804	1903	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1904	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1905
bogdanm	87:6213f644d804	1906	/* Bit 17 : Pin 17. */
bogdanm	87:6213f644d804	1907	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	87:6213f644d804	1908	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	87:6213f644d804	1909	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1910	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1911
bogdanm	87:6213f644d804	1912	/* Bit 16 : Pin 16. */
bogdanm	87:6213f644d804	1913	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	87:6213f644d804	1914	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	87:6213f644d804	1915	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1916	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1917
bogdanm	87:6213f644d804	1918	/* Bit 15 : Pin 15. */
bogdanm	87:6213f644d804	1919	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	87:6213f644d804	1920	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	87:6213f644d804	1921	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1922	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1923
bogdanm	87:6213f644d804	1924	/* Bit 14 : Pin 14. */
bogdanm	87:6213f644d804	1925	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	87:6213f644d804	1926	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	87:6213f644d804	1927	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1928	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1929
bogdanm	87:6213f644d804	1930	/* Bit 13 : Pin 13. */
bogdanm	87:6213f644d804	1931	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	87:6213f644d804	1932	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	87:6213f644d804	1933	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1934	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1935
bogdanm	87:6213f644d804	1936	/* Bit 12 : Pin 12. */
bogdanm	87:6213f644d804	1937	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	87:6213f644d804	1938	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	87:6213f644d804	1939	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1940	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1941
bogdanm	87:6213f644d804	1942	/* Bit 11 : Pin 11. */
bogdanm	87:6213f644d804	1943	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	87:6213f644d804	1944	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	87:6213f644d804	1945	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1946	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1947
bogdanm	87:6213f644d804	1948	/* Bit 10 : Pin 10. */
bogdanm	87:6213f644d804	1949	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	87:6213f644d804	1950	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	87:6213f644d804	1951	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1952	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1953
bogdanm	87:6213f644d804	1954	/* Bit 9 : Pin 9. */
bogdanm	87:6213f644d804	1955	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	87:6213f644d804	1956	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	87:6213f644d804	1957	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1958	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1959
bogdanm	87:6213f644d804	1960	/* Bit 8 : Pin 8. */
bogdanm	87:6213f644d804	1961	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	87:6213f644d804	1962	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	87:6213f644d804	1963	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1964	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1965
bogdanm	87:6213f644d804	1966	/* Bit 7 : Pin 7. */
bogdanm	87:6213f644d804	1967	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	87:6213f644d804	1968	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	87:6213f644d804	1969	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1970	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1971
bogdanm	87:6213f644d804	1972	/* Bit 6 : Pin 6. */
bogdanm	87:6213f644d804	1973	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	87:6213f644d804	1974	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	87:6213f644d804	1975	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1976	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1977
bogdanm	87:6213f644d804	1978	/* Bit 5 : Pin 5. */
bogdanm	87:6213f644d804	1979	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	87:6213f644d804	1980	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	87:6213f644d804	1981	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1982	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1983
bogdanm	87:6213f644d804	1984	/* Bit 4 : Pin 4. */
bogdanm	87:6213f644d804	1985	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	87:6213f644d804	1986	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	87:6213f644d804	1987	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1988	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1989
bogdanm	87:6213f644d804	1990	/* Bit 3 : Pin 3. */
bogdanm	87:6213f644d804	1991	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	87:6213f644d804	1992	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	87:6213f644d804	1993	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	1994	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	1995
bogdanm	87:6213f644d804	1996	/* Bit 2 : Pin 2. */
bogdanm	87:6213f644d804	1997	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	87:6213f644d804	1998	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	87:6213f644d804	1999	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	2000	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	2001
bogdanm	87:6213f644d804	2002	/* Bit 1 : Pin 1. */
bogdanm	87:6213f644d804	2003	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	87:6213f644d804	2004	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	87:6213f644d804	2005	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	2006	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	2007
bogdanm	87:6213f644d804	2008	/* Bit 0 : Pin 0. */
bogdanm	87:6213f644d804	2009	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	87:6213f644d804	2010	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	87:6213f644d804	2011	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
bogdanm	87:6213f644d804	2012	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
bogdanm	87:6213f644d804	2013
bogdanm	87:6213f644d804	2014	/* Register: GPIO_DIR */
bogdanm	87:6213f644d804	2015	/* Description: Direction of GPIO pins. */
bogdanm	87:6213f644d804	2016
bogdanm	87:6213f644d804	2017	/* Bit 31 : Pin 31. */
bogdanm	87:6213f644d804	2018	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	87:6213f644d804	2019	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	87:6213f644d804	2020	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2021	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2022
bogdanm	87:6213f644d804	2023	/* Bit 30 : Pin 30. */
bogdanm	87:6213f644d804	2024	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	87:6213f644d804	2025	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	87:6213f644d804	2026	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2027	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2028
bogdanm	87:6213f644d804	2029	/* Bit 29 : Pin 29. */
bogdanm	87:6213f644d804	2030	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	87:6213f644d804	2031	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	87:6213f644d804	2032	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2033	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2034
bogdanm	87:6213f644d804	2035	/* Bit 28 : Pin 28. */
bogdanm	87:6213f644d804	2036	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	87:6213f644d804	2037	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	87:6213f644d804	2038	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2039	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2040
bogdanm	87:6213f644d804	2041	/* Bit 27 : Pin 27. */
bogdanm	87:6213f644d804	2042	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	87:6213f644d804	2043	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	87:6213f644d804	2044	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2045	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2046
bogdanm	87:6213f644d804	2047	/* Bit 26 : Pin 26. */
bogdanm	87:6213f644d804	2048	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	87:6213f644d804	2049	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	87:6213f644d804	2050	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2051	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2052
bogdanm	87:6213f644d804	2053	/* Bit 25 : Pin 25. */
bogdanm	87:6213f644d804	2054	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	87:6213f644d804	2055	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	87:6213f644d804	2056	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2057	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2058
bogdanm	87:6213f644d804	2059	/* Bit 24 : Pin 24. */
bogdanm	87:6213f644d804	2060	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	87:6213f644d804	2061	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	87:6213f644d804	2062	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2063	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2064
bogdanm	87:6213f644d804	2065	/* Bit 23 : Pin 23. */
bogdanm	87:6213f644d804	2066	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	87:6213f644d804	2067	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	87:6213f644d804	2068	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2069	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2070
bogdanm	87:6213f644d804	2071	/* Bit 22 : Pin 22. */
bogdanm	87:6213f644d804	2072	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	87:6213f644d804	2073	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	87:6213f644d804	2074	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2075	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2076
bogdanm	87:6213f644d804	2077	/* Bit 21 : Pin 21. */
bogdanm	87:6213f644d804	2078	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	87:6213f644d804	2079	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	87:6213f644d804	2080	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2081	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2082
bogdanm	87:6213f644d804	2083	/* Bit 20 : Pin 20. */
bogdanm	87:6213f644d804	2084	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	87:6213f644d804	2085	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	87:6213f644d804	2086	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2087	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2088
bogdanm	87:6213f644d804	2089	/* Bit 19 : Pin 19. */
bogdanm	87:6213f644d804	2090	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	87:6213f644d804	2091	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	87:6213f644d804	2092	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2093	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2094
bogdanm	87:6213f644d804	2095	/* Bit 18 : Pin 18. */
bogdanm	87:6213f644d804	2096	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	87:6213f644d804	2097	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	87:6213f644d804	2098	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2099	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2100
bogdanm	87:6213f644d804	2101	/* Bit 17 : Pin 17. */
bogdanm	87:6213f644d804	2102	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	87:6213f644d804	2103	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	87:6213f644d804	2104	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2105	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2106
bogdanm	87:6213f644d804	2107	/* Bit 16 : Pin 16. */
bogdanm	87:6213f644d804	2108	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	87:6213f644d804	2109	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	87:6213f644d804	2110	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2111	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2112
bogdanm	87:6213f644d804	2113	/* Bit 15 : Pin 15. */
bogdanm	87:6213f644d804	2114	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	87:6213f644d804	2115	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	87:6213f644d804	2116	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2117	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2118
bogdanm	87:6213f644d804	2119	/* Bit 14 : Pin 14. */
bogdanm	87:6213f644d804	2120	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	87:6213f644d804	2121	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	87:6213f644d804	2122	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2123	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2124
bogdanm	87:6213f644d804	2125	/* Bit 13 : Pin 13. */
bogdanm	87:6213f644d804	2126	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	87:6213f644d804	2127	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	87:6213f644d804	2128	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2129	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2130
bogdanm	87:6213f644d804	2131	/* Bit 12 : Pin 12. */
bogdanm	87:6213f644d804	2132	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	87:6213f644d804	2133	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	87:6213f644d804	2134	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2135	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2136
bogdanm	87:6213f644d804	2137	/* Bit 11 : Pin 11. */
bogdanm	87:6213f644d804	2138	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	87:6213f644d804	2139	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	87:6213f644d804	2140	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2141	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2142
bogdanm	87:6213f644d804	2143	/* Bit 10 : Pin 10. */
bogdanm	87:6213f644d804	2144	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	87:6213f644d804	2145	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	87:6213f644d804	2146	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2147	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2148
bogdanm	87:6213f644d804	2149	/* Bit 9 : Pin 9. */
bogdanm	87:6213f644d804	2150	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	87:6213f644d804	2151	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	87:6213f644d804	2152	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2153	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2154
bogdanm	87:6213f644d804	2155	/* Bit 8 : Pin 8. */
bogdanm	87:6213f644d804	2156	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	87:6213f644d804	2157	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	87:6213f644d804	2158	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2159	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2160
bogdanm	87:6213f644d804	2161	/* Bit 7 : Pin 7. */
bogdanm	87:6213f644d804	2162	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	87:6213f644d804	2163	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	87:6213f644d804	2164	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2165	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2166
bogdanm	87:6213f644d804	2167	/* Bit 6 : Pin 6. */
bogdanm	87:6213f644d804	2168	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	87:6213f644d804	2169	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	87:6213f644d804	2170	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2171	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2172
bogdanm	87:6213f644d804	2173	/* Bit 5 : Pin 5. */
bogdanm	87:6213f644d804	2174	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	87:6213f644d804	2175	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	87:6213f644d804	2176	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2177	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2178
bogdanm	87:6213f644d804	2179	/* Bit 4 : Pin 4. */
bogdanm	87:6213f644d804	2180	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	87:6213f644d804	2181	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	87:6213f644d804	2182	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2183	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2184
bogdanm	87:6213f644d804	2185	/* Bit 3 : Pin 3. */
bogdanm	87:6213f644d804	2186	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	87:6213f644d804	2187	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	87:6213f644d804	2188	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2189	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2190
bogdanm	87:6213f644d804	2191	/* Bit 2 : Pin 2. */
bogdanm	87:6213f644d804	2192	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	87:6213f644d804	2193	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	87:6213f644d804	2194	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2195	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2196
bogdanm	87:6213f644d804	2197	/* Bit 1 : Pin 1. */
bogdanm	87:6213f644d804	2198	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	87:6213f644d804	2199	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	87:6213f644d804	2200	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2201	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2202
bogdanm	87:6213f644d804	2203	/* Bit 0 : Pin 0. */
bogdanm	87:6213f644d804	2204	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	87:6213f644d804	2205	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	87:6213f644d804	2206	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2207	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2208
bogdanm	87:6213f644d804	2209	/* Register: GPIO_DIRSET */
bogdanm	87:6213f644d804	2210	/* Description: DIR set register. */
bogdanm	87:6213f644d804	2211
bogdanm	87:6213f644d804	2212	/* Bit 31 : Set as output pin 31. */
bogdanm	87:6213f644d804	2213	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	87:6213f644d804	2214	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	87:6213f644d804	2215	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2216	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2217	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2218
bogdanm	87:6213f644d804	2219	/* Bit 30 : Set as output pin 30. */
bogdanm	87:6213f644d804	2220	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	87:6213f644d804	2221	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	87:6213f644d804	2222	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2223	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2224	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2225
bogdanm	87:6213f644d804	2226	/* Bit 29 : Set as output pin 29. */
bogdanm	87:6213f644d804	2227	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	87:6213f644d804	2228	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	87:6213f644d804	2229	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2230	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2231	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2232
bogdanm	87:6213f644d804	2233	/* Bit 28 : Set as output pin 28. */
bogdanm	87:6213f644d804	2234	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	87:6213f644d804	2235	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	87:6213f644d804	2236	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2237	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2238	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2239
bogdanm	87:6213f644d804	2240	/* Bit 27 : Set as output pin 27. */
bogdanm	87:6213f644d804	2241	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	87:6213f644d804	2242	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	87:6213f644d804	2243	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2244	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2245	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2246
bogdanm	87:6213f644d804	2247	/* Bit 26 : Set as output pin 26. */
bogdanm	87:6213f644d804	2248	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	87:6213f644d804	2249	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	87:6213f644d804	2250	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2251	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2252	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2253
bogdanm	87:6213f644d804	2254	/* Bit 25 : Set as output pin 25. */
bogdanm	87:6213f644d804	2255	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	87:6213f644d804	2256	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	87:6213f644d804	2257	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2258	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2259	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2260
bogdanm	87:6213f644d804	2261	/* Bit 24 : Set as output pin 24. */
bogdanm	87:6213f644d804	2262	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	87:6213f644d804	2263	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	87:6213f644d804	2264	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2265	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2266	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2267
bogdanm	87:6213f644d804	2268	/* Bit 23 : Set as output pin 23. */
bogdanm	87:6213f644d804	2269	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	87:6213f644d804	2270	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	87:6213f644d804	2271	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2272	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2273	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2274
bogdanm	87:6213f644d804	2275	/* Bit 22 : Set as output pin 22. */
bogdanm	87:6213f644d804	2276	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	87:6213f644d804	2277	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	87:6213f644d804	2278	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2279	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2280	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2281
bogdanm	87:6213f644d804	2282	/* Bit 21 : Set as output pin 21. */
bogdanm	87:6213f644d804	2283	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	87:6213f644d804	2284	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	87:6213f644d804	2285	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2286	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2287	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2288
bogdanm	87:6213f644d804	2289	/* Bit 20 : Set as output pin 20. */
bogdanm	87:6213f644d804	2290	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	87:6213f644d804	2291	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	87:6213f644d804	2292	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2293	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2294	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2295
bogdanm	87:6213f644d804	2296	/* Bit 19 : Set as output pin 19. */
bogdanm	87:6213f644d804	2297	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	87:6213f644d804	2298	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	87:6213f644d804	2299	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2300	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2301	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2302
bogdanm	87:6213f644d804	2303	/* Bit 18 : Set as output pin 18. */
bogdanm	87:6213f644d804	2304	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	87:6213f644d804	2305	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	87:6213f644d804	2306	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2307	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2308	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2309
bogdanm	87:6213f644d804	2310	/* Bit 17 : Set as output pin 17. */
bogdanm	87:6213f644d804	2311	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	87:6213f644d804	2312	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	87:6213f644d804	2313	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2314	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2315	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2316
bogdanm	87:6213f644d804	2317	/* Bit 16 : Set as output pin 16. */
bogdanm	87:6213f644d804	2318	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	87:6213f644d804	2319	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	87:6213f644d804	2320	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2321	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2322	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2323
bogdanm	87:6213f644d804	2324	/* Bit 15 : Set as output pin 15. */
bogdanm	87:6213f644d804	2325	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	87:6213f644d804	2326	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	87:6213f644d804	2327	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2328	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2329	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2330
bogdanm	87:6213f644d804	2331	/* Bit 14 : Set as output pin 14. */
bogdanm	87:6213f644d804	2332	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	87:6213f644d804	2333	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	87:6213f644d804	2334	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2335	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2336	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2337
bogdanm	87:6213f644d804	2338	/* Bit 13 : Set as output pin 13. */
bogdanm	87:6213f644d804	2339	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	87:6213f644d804	2340	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	87:6213f644d804	2341	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2342	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2343	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2344
bogdanm	87:6213f644d804	2345	/* Bit 12 : Set as output pin 12. */
bogdanm	87:6213f644d804	2346	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	87:6213f644d804	2347	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	87:6213f644d804	2348	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2349	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2350	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2351
bogdanm	87:6213f644d804	2352	/* Bit 11 : Set as output pin 11. */
bogdanm	87:6213f644d804	2353	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	87:6213f644d804	2354	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	87:6213f644d804	2355	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2356	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2357	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2358
bogdanm	87:6213f644d804	2359	/* Bit 10 : Set as output pin 10. */
bogdanm	87:6213f644d804	2360	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	87:6213f644d804	2361	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	87:6213f644d804	2362	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2363	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2364	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2365
bogdanm	87:6213f644d804	2366	/* Bit 9 : Set as output pin 9. */
bogdanm	87:6213f644d804	2367	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	87:6213f644d804	2368	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	87:6213f644d804	2369	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2370	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2371	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2372
bogdanm	87:6213f644d804	2373	/* Bit 8 : Set as output pin 8. */
bogdanm	87:6213f644d804	2374	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	87:6213f644d804	2375	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	87:6213f644d804	2376	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2377	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2378	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2379
bogdanm	87:6213f644d804	2380	/* Bit 7 : Set as output pin 7. */
bogdanm	87:6213f644d804	2381	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	87:6213f644d804	2382	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	87:6213f644d804	2383	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2384	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2385	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2386
bogdanm	87:6213f644d804	2387	/* Bit 6 : Set as output pin 6. */
bogdanm	87:6213f644d804	2388	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	87:6213f644d804	2389	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	87:6213f644d804	2390	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2391	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2392	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2393
bogdanm	87:6213f644d804	2394	/* Bit 5 : Set as output pin 5. */
bogdanm	87:6213f644d804	2395	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	87:6213f644d804	2396	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	87:6213f644d804	2397	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2398	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2399	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2400
bogdanm	87:6213f644d804	2401	/* Bit 4 : Set as output pin 4. */
bogdanm	87:6213f644d804	2402	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	87:6213f644d804	2403	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	87:6213f644d804	2404	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2405	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2406	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2407
bogdanm	87:6213f644d804	2408	/* Bit 3 : Set as output pin 3. */
bogdanm	87:6213f644d804	2409	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	87:6213f644d804	2410	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	87:6213f644d804	2411	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2412	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2413	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2414
bogdanm	87:6213f644d804	2415	/* Bit 2 : Set as output pin 2. */
bogdanm	87:6213f644d804	2416	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	87:6213f644d804	2417	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	87:6213f644d804	2418	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2419	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2420	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2421
bogdanm	87:6213f644d804	2422	/* Bit 1 : Set as output pin 1. */
bogdanm	87:6213f644d804	2423	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	87:6213f644d804	2424	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	87:6213f644d804	2425	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2426	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2427	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2428
bogdanm	87:6213f644d804	2429	/* Bit 0 : Set as output pin 0. */
bogdanm	87:6213f644d804	2430	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	87:6213f644d804	2431	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	87:6213f644d804	2432	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2433	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2434	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
bogdanm	87:6213f644d804	2435
bogdanm	87:6213f644d804	2436	/* Register: GPIO_DIRCLR */
bogdanm	87:6213f644d804	2437	/* Description: DIR clear register. */
bogdanm	87:6213f644d804	2438
bogdanm	87:6213f644d804	2439	/* Bit 31 : Set as input pin 31. */
bogdanm	87:6213f644d804	2440	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
bogdanm	87:6213f644d804	2441	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
bogdanm	87:6213f644d804	2442	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2443	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2444	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2445
bogdanm	87:6213f644d804	2446	/* Bit 30 : Set as input pin 30. */
bogdanm	87:6213f644d804	2447	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
bogdanm	87:6213f644d804	2448	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
bogdanm	87:6213f644d804	2449	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2450	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2451	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2452
bogdanm	87:6213f644d804	2453	/* Bit 29 : Set as input pin 29. */
bogdanm	87:6213f644d804	2454	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
bogdanm	87:6213f644d804	2455	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
bogdanm	87:6213f644d804	2456	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2457	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2458	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2459
bogdanm	87:6213f644d804	2460	/* Bit 28 : Set as input pin 28. */
bogdanm	87:6213f644d804	2461	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
bogdanm	87:6213f644d804	2462	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
bogdanm	87:6213f644d804	2463	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2464	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2465	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2466
bogdanm	87:6213f644d804	2467	/* Bit 27 : Set as input pin 27. */
bogdanm	87:6213f644d804	2468	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
bogdanm	87:6213f644d804	2469	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
bogdanm	87:6213f644d804	2470	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2471	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2472	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2473
bogdanm	87:6213f644d804	2474	/* Bit 26 : Set as input pin 26. */
bogdanm	87:6213f644d804	2475	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
bogdanm	87:6213f644d804	2476	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
bogdanm	87:6213f644d804	2477	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2478	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2479	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2480
bogdanm	87:6213f644d804	2481	/* Bit 25 : Set as input pin 25. */
bogdanm	87:6213f644d804	2482	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
bogdanm	87:6213f644d804	2483	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
bogdanm	87:6213f644d804	2484	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2485	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2486	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2487
bogdanm	87:6213f644d804	2488	/* Bit 24 : Set as input pin 24. */
bogdanm	87:6213f644d804	2489	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
bogdanm	87:6213f644d804	2490	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
bogdanm	87:6213f644d804	2491	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2492	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2493	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2494
bogdanm	87:6213f644d804	2495	/* Bit 23 : Set as input pin 23. */
bogdanm	87:6213f644d804	2496	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
bogdanm	87:6213f644d804	2497	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
bogdanm	87:6213f644d804	2498	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2499	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2500	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2501
bogdanm	87:6213f644d804	2502	/* Bit 22 : Set as input pin 22. */
bogdanm	87:6213f644d804	2503	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
bogdanm	87:6213f644d804	2504	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
bogdanm	87:6213f644d804	2505	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2506	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2507	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2508
bogdanm	87:6213f644d804	2509	/* Bit 21 : Set as input pin 21. */
bogdanm	87:6213f644d804	2510	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
bogdanm	87:6213f644d804	2511	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
bogdanm	87:6213f644d804	2512	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2513	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2514	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2515
bogdanm	87:6213f644d804	2516	/* Bit 20 : Set as input pin 20. */
bogdanm	87:6213f644d804	2517	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
bogdanm	87:6213f644d804	2518	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
bogdanm	87:6213f644d804	2519	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2520	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2521	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2522
bogdanm	87:6213f644d804	2523	/* Bit 19 : Set as input pin 19. */
bogdanm	87:6213f644d804	2524	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
bogdanm	87:6213f644d804	2525	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
bogdanm	87:6213f644d804	2526	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2527	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2528	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2529
bogdanm	87:6213f644d804	2530	/* Bit 18 : Set as input pin 18. */
bogdanm	87:6213f644d804	2531	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
bogdanm	87:6213f644d804	2532	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
bogdanm	87:6213f644d804	2533	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2534	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2535	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2536
bogdanm	87:6213f644d804	2537	/* Bit 17 : Set as input pin 17. */
bogdanm	87:6213f644d804	2538	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
bogdanm	87:6213f644d804	2539	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
bogdanm	87:6213f644d804	2540	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2541	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2542	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2543
bogdanm	87:6213f644d804	2544	/* Bit 16 : Set as input pin 16. */
bogdanm	87:6213f644d804	2545	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
bogdanm	87:6213f644d804	2546	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
bogdanm	87:6213f644d804	2547	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2548	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2549	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2550
bogdanm	87:6213f644d804	2551	/* Bit 15 : Set as input pin 15. */
bogdanm	87:6213f644d804	2552	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
bogdanm	87:6213f644d804	2553	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
bogdanm	87:6213f644d804	2554	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2555	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2556	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2557
bogdanm	87:6213f644d804	2558	/* Bit 14 : Set as input pin 14. */
bogdanm	87:6213f644d804	2559	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
bogdanm	87:6213f644d804	2560	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
bogdanm	87:6213f644d804	2561	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2562	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2563	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2564
bogdanm	87:6213f644d804	2565	/* Bit 13 : Set as input pin 13. */
bogdanm	87:6213f644d804	2566	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
bogdanm	87:6213f644d804	2567	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
bogdanm	87:6213f644d804	2568	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2569	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2570	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2571
bogdanm	87:6213f644d804	2572	/* Bit 12 : Set as input pin 12. */
bogdanm	87:6213f644d804	2573	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
bogdanm	87:6213f644d804	2574	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
bogdanm	87:6213f644d804	2575	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2576	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2577	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2578
bogdanm	87:6213f644d804	2579	/* Bit 11 : Set as input pin 11. */
bogdanm	87:6213f644d804	2580	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
bogdanm	87:6213f644d804	2581	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
bogdanm	87:6213f644d804	2582	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2583	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2584	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2585
bogdanm	87:6213f644d804	2586	/* Bit 10 : Set as input pin 10. */
bogdanm	87:6213f644d804	2587	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
bogdanm	87:6213f644d804	2588	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
bogdanm	87:6213f644d804	2589	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2590	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2591	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2592
bogdanm	87:6213f644d804	2593	/* Bit 9 : Set as input pin 9. */
bogdanm	87:6213f644d804	2594	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
bogdanm	87:6213f644d804	2595	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
bogdanm	87:6213f644d804	2596	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2597	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2598	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2599
bogdanm	87:6213f644d804	2600	/* Bit 8 : Set as input pin 8. */
bogdanm	87:6213f644d804	2601	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
bogdanm	87:6213f644d804	2602	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
bogdanm	87:6213f644d804	2603	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2604	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2605	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2606
bogdanm	87:6213f644d804	2607	/* Bit 7 : Set as input pin 7. */
bogdanm	87:6213f644d804	2608	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
bogdanm	87:6213f644d804	2609	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
bogdanm	87:6213f644d804	2610	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2611	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2612	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2613
bogdanm	87:6213f644d804	2614	/* Bit 6 : Set as input pin 6. */
bogdanm	87:6213f644d804	2615	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
bogdanm	87:6213f644d804	2616	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
bogdanm	87:6213f644d804	2617	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2618	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2619	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2620
bogdanm	87:6213f644d804	2621	/* Bit 5 : Set as input pin 5. */
bogdanm	87:6213f644d804	2622	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
bogdanm	87:6213f644d804	2623	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
bogdanm	87:6213f644d804	2624	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2625	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2626	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2627
bogdanm	87:6213f644d804	2628	/* Bit 4 : Set as input pin 4. */
bogdanm	87:6213f644d804	2629	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
bogdanm	87:6213f644d804	2630	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
bogdanm	87:6213f644d804	2631	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2632	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2633	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2634
bogdanm	87:6213f644d804	2635	/* Bit 3 : Set as input pin 3. */
bogdanm	87:6213f644d804	2636	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
bogdanm	87:6213f644d804	2637	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
bogdanm	87:6213f644d804	2638	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2639	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2640	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2641
bogdanm	87:6213f644d804	2642	/* Bit 2 : Set as input pin 2. */
bogdanm	87:6213f644d804	2643	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
bogdanm	87:6213f644d804	2644	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
bogdanm	87:6213f644d804	2645	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2646	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2647	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2648
bogdanm	87:6213f644d804	2649	/* Bit 1 : Set as input pin 1. */
bogdanm	87:6213f644d804	2650	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
bogdanm	87:6213f644d804	2651	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
bogdanm	87:6213f644d804	2652	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2653	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2654	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2655
bogdanm	87:6213f644d804	2656	/* Bit 0 : Set as input pin 0. */
bogdanm	87:6213f644d804	2657	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
bogdanm	87:6213f644d804	2658	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
bogdanm	87:6213f644d804	2659	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
bogdanm	87:6213f644d804	2660	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
bogdanm	87:6213f644d804	2661	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
bogdanm	87:6213f644d804	2662
bogdanm	87:6213f644d804	2663	/* Register: GPIO_PIN_CNF */
bogdanm	87:6213f644d804	2664	/* Description: Configuration of GPIO pins. */
bogdanm	87:6213f644d804	2665
bogdanm	87:6213f644d804	2666	/* Bits 17..16 : Pin sensing mechanism. */
bogdanm	87:6213f644d804	2667	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
bogdanm	87:6213f644d804	2668	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
bogdanm	87:6213f644d804	2669	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
bogdanm	87:6213f644d804	2670	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
bogdanm	87:6213f644d804	2671	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
bogdanm	87:6213f644d804	2672
bogdanm	87:6213f644d804	2673	/* Bits 10..8 : Drive configuration. */
bogdanm	87:6213f644d804	2674	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
bogdanm	87:6213f644d804	2675	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
bogdanm	87:6213f644d804	2676	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
bogdanm	87:6213f644d804	2677	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
bogdanm	87:6213f644d804	2678	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
bogdanm	87:6213f644d804	2679	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
bogdanm	87:6213f644d804	2680	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
bogdanm	87:6213f644d804	2681	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
bogdanm	87:6213f644d804	2682	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
bogdanm	87:6213f644d804	2683	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
bogdanm	87:6213f644d804	2684
bogdanm	87:6213f644d804	2685	/* Bits 3..2 : Pull-up or -down configuration. */
bogdanm	87:6213f644d804	2686	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
bogdanm	87:6213f644d804	2687	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
bogdanm	87:6213f644d804	2688	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
bogdanm	87:6213f644d804	2689	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
bogdanm	87:6213f644d804	2690	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
bogdanm	87:6213f644d804	2691
bogdanm	87:6213f644d804	2692	/* Bit 1 : Connect or disconnect input path. */
bogdanm	87:6213f644d804	2693	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
bogdanm	87:6213f644d804	2694	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
bogdanm	87:6213f644d804	2695	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
bogdanm	87:6213f644d804	2696	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
bogdanm	87:6213f644d804	2697
bogdanm	87:6213f644d804	2698	/* Bit 0 : Pin direction. */
bogdanm	87:6213f644d804	2699	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
bogdanm	87:6213f644d804	2700	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
bogdanm	87:6213f644d804	2701	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
bogdanm	87:6213f644d804	2702	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
bogdanm	87:6213f644d804	2703
bogdanm	87:6213f644d804	2704
bogdanm	87:6213f644d804	2705	/* Peripheral: GPIOTE */
bogdanm	87:6213f644d804	2706	/* Description: GPIO tasks and events. */
bogdanm	87:6213f644d804	2707
bogdanm	87:6213f644d804	2708	/* Register: GPIOTE_INTENSET */
bogdanm	87:6213f644d804	2709	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	2710
bogdanm	87:6213f644d804	2711	/* Bit 31 : Enable interrupt on PORT event. */
bogdanm	87:6213f644d804	2712	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
bogdanm	87:6213f644d804	2713	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
bogdanm	87:6213f644d804	2714	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2715	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2716	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2717
bogdanm	87:6213f644d804	2718	/* Bit 3 : Enable interrupt on IN[3] event. */
bogdanm	87:6213f644d804	2719	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
bogdanm	87:6213f644d804	2720	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
bogdanm	87:6213f644d804	2721	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2722	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2723	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2724
bogdanm	87:6213f644d804	2725	/* Bit 2 : Enable interrupt on IN[2] event. */
bogdanm	87:6213f644d804	2726	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
bogdanm	87:6213f644d804	2727	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
bogdanm	87:6213f644d804	2728	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2729	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2730	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2731
bogdanm	87:6213f644d804	2732	/* Bit 1 : Enable interrupt on IN[1] event. */
bogdanm	87:6213f644d804	2733	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
bogdanm	87:6213f644d804	2734	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
bogdanm	87:6213f644d804	2735	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2736	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2737	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2738
bogdanm	87:6213f644d804	2739	/* Bit 0 : Enable interrupt on IN[0] event. */
bogdanm	87:6213f644d804	2740	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
bogdanm	87:6213f644d804	2741	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
bogdanm	87:6213f644d804	2742	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2743	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2744	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2745
bogdanm	87:6213f644d804	2746	/* Register: GPIOTE_INTENCLR */
bogdanm	87:6213f644d804	2747	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	2748
bogdanm	87:6213f644d804	2749	/* Bit 31 : Disable interrupt on PORT event. */
bogdanm	87:6213f644d804	2750	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
bogdanm	87:6213f644d804	2751	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
bogdanm	87:6213f644d804	2752	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2753	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2754	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2755
bogdanm	87:6213f644d804	2756	/* Bit 3 : Disable interrupt on IN[3] event. */
bogdanm	87:6213f644d804	2757	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
bogdanm	87:6213f644d804	2758	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
bogdanm	87:6213f644d804	2759	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2760	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2761	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2762
bogdanm	87:6213f644d804	2763	/* Bit 2 : Disable interrupt on IN[2] event. */
bogdanm	87:6213f644d804	2764	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
bogdanm	87:6213f644d804	2765	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
bogdanm	87:6213f644d804	2766	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2767	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2768	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2769
bogdanm	87:6213f644d804	2770	/* Bit 1 : Disable interrupt on IN[1] event. */
bogdanm	87:6213f644d804	2771	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
bogdanm	87:6213f644d804	2772	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
bogdanm	87:6213f644d804	2773	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2774	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2775	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2776
bogdanm	87:6213f644d804	2777	/* Bit 0 : Disable interrupt on IN[0] event. */
bogdanm	87:6213f644d804	2778	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
bogdanm	87:6213f644d804	2779	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
bogdanm	87:6213f644d804	2780	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2781	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2782	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2783
bogdanm	87:6213f644d804	2784	/* Register: GPIOTE_CONFIG */
bogdanm	87:6213f644d804	2785	/* Description: Channel configuration registers. */
bogdanm	87:6213f644d804	2786
bogdanm	87:6213f644d804	2787	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
bogdanm	87:6213f644d804	2788	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
bogdanm	87:6213f644d804	2789	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
bogdanm	87:6213f644d804	2790	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
bogdanm	87:6213f644d804	2791	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
bogdanm	87:6213f644d804	2792
bogdanm	87:6213f644d804	2793	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
bogdanm	87:6213f644d804	2794	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
bogdanm	87:6213f644d804	2795	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
Kojto	122:f9eeca106725	2796	#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /!< No task or event. /
bogdanm	87:6213f644d804	2797	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
bogdanm	87:6213f644d804	2798	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
bogdanm	87:6213f644d804	2799	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
bogdanm	87:6213f644d804	2800
bogdanm	87:6213f644d804	2801	/* Bits 12..8 : Pin select. */
bogdanm	87:6213f644d804	2802	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
bogdanm	87:6213f644d804	2803	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	87:6213f644d804	2804
bogdanm	87:6213f644d804	2805	/* Bits 1..0 : Mode */
bogdanm	87:6213f644d804	2806	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	87:6213f644d804	2807	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	87:6213f644d804	2808	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
bogdanm	87:6213f644d804	2809	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
bogdanm	87:6213f644d804	2810	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
bogdanm	87:6213f644d804	2811
bogdanm	87:6213f644d804	2812	/* Register: GPIOTE_POWER */
bogdanm	87:6213f644d804	2813	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	2814
bogdanm	87:6213f644d804	2815	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	2816	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	2817	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	2818	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	2819	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	2820
bogdanm	87:6213f644d804	2821
bogdanm	87:6213f644d804	2822	/* Peripheral: LPCOMP */
Kojto	97:433970e64889	2823	/* Description: Low power comparator. */
bogdanm	87:6213f644d804	2824
bogdanm	87:6213f644d804	2825	/* Register: LPCOMP_SHORTS */
Kojto	97:433970e64889	2826	/* Description: Shortcuts for the LPCOMP. */
Kojto	97:433970e64889	2827
Kojto	97:433970e64889	2828	/* Bit 4 : Shortcut between CROSS event and STOP task. */
bogdanm	87:6213f644d804	2829	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
bogdanm	87:6213f644d804	2830	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
bogdanm	87:6213f644d804	2831	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	2832	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	2833
Kojto	97:433970e64889	2834	/* Bit 3 : Shortcut between UP event and STOP task. */
bogdanm	87:6213f644d804	2835	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
bogdanm	87:6213f644d804	2836	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
bogdanm	87:6213f644d804	2837	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	2838	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	2839
Kojto	97:433970e64889	2840	/* Bit 2 : Shortcut between DOWN event and STOP task. */
bogdanm	87:6213f644d804	2841	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
bogdanm	87:6213f644d804	2842	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
bogdanm	87:6213f644d804	2843	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	2844	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	2845
Kojto	97:433970e64889	2846	/* Bit 1 : Shortcut between RADY event and STOP task. */
bogdanm	87:6213f644d804	2847	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
bogdanm	87:6213f644d804	2848	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
bogdanm	87:6213f644d804	2849	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	2850	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	2851
Kojto	97:433970e64889	2852	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
bogdanm	87:6213f644d804	2853	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
bogdanm	87:6213f644d804	2854	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
bogdanm	87:6213f644d804	2855	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	2856	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	2857
bogdanm	87:6213f644d804	2858	/* Register: LPCOMP_INTENSET */
bogdanm	87:6213f644d804	2859	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	2860
bogdanm	87:6213f644d804	2861	/* Bit 3 : Enable interrupt on CROSS event. */
bogdanm	87:6213f644d804	2862	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
bogdanm	87:6213f644d804	2863	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
bogdanm	87:6213f644d804	2864	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2865	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2866	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2867
bogdanm	87:6213f644d804	2868	/* Bit 2 : Enable interrupt on UP event. */
bogdanm	87:6213f644d804	2869	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
bogdanm	87:6213f644d804	2870	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
bogdanm	87:6213f644d804	2871	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2872	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2873	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2874
bogdanm	87:6213f644d804	2875	/* Bit 1 : Enable interrupt on DOWN event. */
bogdanm	87:6213f644d804	2876	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
bogdanm	87:6213f644d804	2877	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
bogdanm	87:6213f644d804	2878	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2879	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2880	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2881
bogdanm	87:6213f644d804	2882	/* Bit 0 : Enable interrupt on READY event. */
bogdanm	87:6213f644d804	2883	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	87:6213f644d804	2884	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	87:6213f644d804	2885	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2886	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2887	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	2888
bogdanm	87:6213f644d804	2889	/* Register: LPCOMP_INTENCLR */
bogdanm	87:6213f644d804	2890	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	2891
bogdanm	87:6213f644d804	2892	/* Bit 3 : Disable interrupt on CROSS event. */
bogdanm	87:6213f644d804	2893	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
bogdanm	87:6213f644d804	2894	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
bogdanm	87:6213f644d804	2895	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2896	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2897	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2898
bogdanm	87:6213f644d804	2899	/* Bit 2 : Disable interrupt on UP event. */
bogdanm	87:6213f644d804	2900	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
bogdanm	87:6213f644d804	2901	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
bogdanm	87:6213f644d804	2902	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2903	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2904	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2905
bogdanm	87:6213f644d804	2906	/* Bit 1 : Disable interrupt on DOWN event. */
bogdanm	87:6213f644d804	2907	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
bogdanm	87:6213f644d804	2908	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
bogdanm	87:6213f644d804	2909	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2910	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2911	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2912
bogdanm	87:6213f644d804	2913	/* Bit 0 : Disable interrupt on READY event. */
bogdanm	87:6213f644d804	2914	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	87:6213f644d804	2915	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	87:6213f644d804	2916	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	2917	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	2918	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	2919
bogdanm	87:6213f644d804	2920	/* Register: LPCOMP_RESULT */
bogdanm	87:6213f644d804	2921	/* Description: Result of last compare. */
bogdanm	87:6213f644d804	2922
bogdanm	87:6213f644d804	2923	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
bogdanm	87:6213f644d804	2924	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
bogdanm	87:6213f644d804	2925	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
bogdanm	87:6213f644d804	2926	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
bogdanm	87:6213f644d804	2927	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
bogdanm	87:6213f644d804	2928
bogdanm	87:6213f644d804	2929	/* Register: LPCOMP_ENABLE */
bogdanm	87:6213f644d804	2930	/* Description: Enable the LPCOMP. */
bogdanm	87:6213f644d804	2931
bogdanm	87:6213f644d804	2932	/* Bits 1..0 : Enable or disable LPCOMP. */
bogdanm	87:6213f644d804	2933	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	2934	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	2935	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
bogdanm	87:6213f644d804	2936	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
bogdanm	87:6213f644d804	2937
bogdanm	87:6213f644d804	2938	/* Register: LPCOMP_PSEL */
bogdanm	87:6213f644d804	2939	/* Description: Input pin select. */
bogdanm	87:6213f644d804	2940
bogdanm	87:6213f644d804	2941	/* Bits 2..0 : Analog input pin select. */
bogdanm	87:6213f644d804	2942	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
bogdanm	87:6213f644d804	2943	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
bogdanm	87:6213f644d804	2944	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
bogdanm	87:6213f644d804	2945	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
bogdanm	87:6213f644d804	2946	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
bogdanm	87:6213f644d804	2947	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
bogdanm	87:6213f644d804	2948	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
bogdanm	87:6213f644d804	2949	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
bogdanm	87:6213f644d804	2950	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
bogdanm	87:6213f644d804	2951	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
bogdanm	87:6213f644d804	2952
bogdanm	87:6213f644d804	2953	/* Register: LPCOMP_REFSEL */
bogdanm	87:6213f644d804	2954	/* Description: Reference select. */
bogdanm	87:6213f644d804	2955
bogdanm	87:6213f644d804	2956	/* Bits 2..0 : Reference select. */
bogdanm	87:6213f644d804	2957	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
bogdanm	87:6213f644d804	2958	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
Kojto	97:433970e64889	2959	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
Kojto	97:433970e64889	2960	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
Kojto	97:433970e64889	2961	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
Kojto	97:433970e64889	2962	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
Kojto	97:433970e64889	2963	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
Kojto	97:433970e64889	2964	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
Kojto	97:433970e64889	2965	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
bogdanm	87:6213f644d804	2966	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
bogdanm	87:6213f644d804	2967
bogdanm	87:6213f644d804	2968	/* Register: LPCOMP_EXTREFSEL */
bogdanm	87:6213f644d804	2969	/* Description: External reference select. */
bogdanm	87:6213f644d804	2970
bogdanm	87:6213f644d804	2971	/* Bit 0 : External analog reference pin selection. */
bogdanm	87:6213f644d804	2972	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
bogdanm	87:6213f644d804	2973	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
bogdanm	87:6213f644d804	2974	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
bogdanm	87:6213f644d804	2975	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
bogdanm	87:6213f644d804	2976
bogdanm	87:6213f644d804	2977	/* Register: LPCOMP_ANADETECT */
bogdanm	87:6213f644d804	2978	/* Description: Analog detect configuration. */
bogdanm	87:6213f644d804	2979
bogdanm	87:6213f644d804	2980	/* Bits 1..0 : Analog detect configuration. */
bogdanm	87:6213f644d804	2981	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
bogdanm	87:6213f644d804	2982	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
bogdanm	87:6213f644d804	2983	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
bogdanm	87:6213f644d804	2984	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
bogdanm	87:6213f644d804	2985	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
bogdanm	87:6213f644d804	2986
bogdanm	87:6213f644d804	2987	/* Register: LPCOMP_POWER */
bogdanm	87:6213f644d804	2988	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	2989
bogdanm	87:6213f644d804	2990	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	2991	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	2992	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	2993	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	2994	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	2995
bogdanm	87:6213f644d804	2996
bogdanm	87:6213f644d804	2997	/* Peripheral: MPU */
bogdanm	87:6213f644d804	2998	/* Description: Memory Protection Unit. */
bogdanm	87:6213f644d804	2999
bogdanm	87:6213f644d804	3000	/* Register: MPU_PERR0 */
bogdanm	87:6213f644d804	3001	/* Description: Configuration of peripherals in mpu regions. */
bogdanm	87:6213f644d804	3002
bogdanm	87:6213f644d804	3003	/* Bit 31 : PPI region configuration. */
bogdanm	87:6213f644d804	3004	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
bogdanm	87:6213f644d804	3005	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
bogdanm	87:6213f644d804	3006	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3007	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3008
bogdanm	87:6213f644d804	3009	/* Bit 30 : NVMC region configuration. */
bogdanm	87:6213f644d804	3010	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
bogdanm	87:6213f644d804	3011	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
bogdanm	87:6213f644d804	3012	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3013	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3014
Kojto	97:433970e64889	3015	/* Bit 19 : LPCOMP region configuration. */
Kojto	97:433970e64889	3016	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
Kojto	97:433970e64889	3017	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
Kojto	97:433970e64889	3018	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	97:433970e64889	3019	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3020
bogdanm	87:6213f644d804	3021	/* Bit 18 : QDEC region configuration. */
bogdanm	87:6213f644d804	3022	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
bogdanm	87:6213f644d804	3023	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
bogdanm	87:6213f644d804	3024	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3025	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3026
bogdanm	87:6213f644d804	3027	/* Bit 17 : RTC1 region configuration. */
bogdanm	87:6213f644d804	3028	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
bogdanm	87:6213f644d804	3029	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
bogdanm	87:6213f644d804	3030	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3031	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3032
bogdanm	87:6213f644d804	3033	/* Bit 16 : WDT region configuration. */
bogdanm	87:6213f644d804	3034	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
bogdanm	87:6213f644d804	3035	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
bogdanm	87:6213f644d804	3036	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3037	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3038
bogdanm	87:6213f644d804	3039	/* Bit 15 : CCM and AAR region configuration. */
bogdanm	87:6213f644d804	3040	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
bogdanm	87:6213f644d804	3041	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
bogdanm	87:6213f644d804	3042	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3043	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3044
bogdanm	87:6213f644d804	3045	/* Bit 14 : ECB region configuration. */
bogdanm	87:6213f644d804	3046	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
bogdanm	87:6213f644d804	3047	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
bogdanm	87:6213f644d804	3048	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3049	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3050
bogdanm	87:6213f644d804	3051	/* Bit 13 : RNG region configuration. */
bogdanm	87:6213f644d804	3052	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
bogdanm	87:6213f644d804	3053	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
bogdanm	87:6213f644d804	3054	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3055	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3056
bogdanm	87:6213f644d804	3057	/* Bit 12 : TEMP region configuration. */
bogdanm	87:6213f644d804	3058	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
bogdanm	87:6213f644d804	3059	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
bogdanm	87:6213f644d804	3060	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3061	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3062
bogdanm	87:6213f644d804	3063	/* Bit 11 : RTC0 region configuration. */
bogdanm	87:6213f644d804	3064	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
bogdanm	87:6213f644d804	3065	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
bogdanm	87:6213f644d804	3066	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3067	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3068
bogdanm	87:6213f644d804	3069	/* Bit 10 : TIMER2 region configuration. */
bogdanm	87:6213f644d804	3070	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
bogdanm	87:6213f644d804	3071	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
bogdanm	87:6213f644d804	3072	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3073	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3074
bogdanm	87:6213f644d804	3075	/* Bit 9 : TIMER1 region configuration. */
bogdanm	87:6213f644d804	3076	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
bogdanm	87:6213f644d804	3077	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
bogdanm	87:6213f644d804	3078	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3079	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3080
bogdanm	87:6213f644d804	3081	/* Bit 8 : TIMER0 region configuration. */
bogdanm	87:6213f644d804	3082	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
bogdanm	87:6213f644d804	3083	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
bogdanm	87:6213f644d804	3084	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3085	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3086
bogdanm	87:6213f644d804	3087	/* Bit 7 : ADC region configuration. */
bogdanm	87:6213f644d804	3088	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
bogdanm	87:6213f644d804	3089	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
bogdanm	87:6213f644d804	3090	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3091	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3092
bogdanm	87:6213f644d804	3093	/* Bit 6 : GPIOTE region configuration. */
bogdanm	87:6213f644d804	3094	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
bogdanm	87:6213f644d804	3095	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
bogdanm	87:6213f644d804	3096	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3097	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3098
bogdanm	87:6213f644d804	3099	/* Bit 4 : SPI1 and TWI1 region configuration. */
bogdanm	87:6213f644d804	3100	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
bogdanm	87:6213f644d804	3101	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
bogdanm	87:6213f644d804	3102	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3103	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3104
bogdanm	87:6213f644d804	3105	/* Bit 3 : SPI0 and TWI0 region configuration. */
bogdanm	87:6213f644d804	3106	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
bogdanm	87:6213f644d804	3107	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
bogdanm	87:6213f644d804	3108	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3109	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3110
bogdanm	87:6213f644d804	3111	/* Bit 2 : UART0 region configuration. */
bogdanm	87:6213f644d804	3112	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
bogdanm	87:6213f644d804	3113	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
bogdanm	87:6213f644d804	3114	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3115	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3116
bogdanm	87:6213f644d804	3117	/* Bit 1 : RADIO region configuration. */
bogdanm	87:6213f644d804	3118	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
bogdanm	87:6213f644d804	3119	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
bogdanm	87:6213f644d804	3120	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3121	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3122
bogdanm	87:6213f644d804	3123	/* Bit 0 : POWER_CLOCK region configuration. */
bogdanm	87:6213f644d804	3124	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
bogdanm	87:6213f644d804	3125	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
bogdanm	87:6213f644d804	3126	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
bogdanm	87:6213f644d804	3127	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
bogdanm	87:6213f644d804	3128
bogdanm	87:6213f644d804	3129	/* Register: MPU_PROTENSET0 */
Kojto	97:433970e64889	3130	/* Description: Erase and write protection bit enable set register. */
bogdanm	87:6213f644d804	3131
bogdanm	87:6213f644d804	3132	/* Bit 31 : Protection enable for region 31. */
bogdanm	87:6213f644d804	3133	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
bogdanm	87:6213f644d804	3134	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
bogdanm	87:6213f644d804	3135	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3136	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3137	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3138
bogdanm	87:6213f644d804	3139	/* Bit 30 : Protection enable for region 30. */
bogdanm	87:6213f644d804	3140	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
bogdanm	87:6213f644d804	3141	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
bogdanm	87:6213f644d804	3142	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3143	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3144	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3145
bogdanm	87:6213f644d804	3146	/* Bit 29 : Protection enable for region 29. */
bogdanm	87:6213f644d804	3147	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
bogdanm	87:6213f644d804	3148	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
bogdanm	87:6213f644d804	3149	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3150	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3151	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3152
bogdanm	87:6213f644d804	3153	/* Bit 28 : Protection enable for region 28. */
bogdanm	87:6213f644d804	3154	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
bogdanm	87:6213f644d804	3155	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
bogdanm	87:6213f644d804	3156	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3157	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3158	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3159
bogdanm	87:6213f644d804	3160	/* Bit 27 : Protection enable for region 27. */
bogdanm	87:6213f644d804	3161	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
bogdanm	87:6213f644d804	3162	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
bogdanm	87:6213f644d804	3163	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3164	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3165	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3166
bogdanm	87:6213f644d804	3167	/* Bit 26 : Protection enable for region 26. */
bogdanm	87:6213f644d804	3168	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
bogdanm	87:6213f644d804	3169	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
bogdanm	87:6213f644d804	3170	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3171	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3172	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3173
bogdanm	87:6213f644d804	3174	/* Bit 25 : Protection enable for region 25. */
bogdanm	87:6213f644d804	3175	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
bogdanm	87:6213f644d804	3176	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
bogdanm	87:6213f644d804	3177	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3178	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3179	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3180
bogdanm	87:6213f644d804	3181	/* Bit 24 : Protection enable for region 24. */
bogdanm	87:6213f644d804	3182	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
bogdanm	87:6213f644d804	3183	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
bogdanm	87:6213f644d804	3184	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3185	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3186	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3187
bogdanm	87:6213f644d804	3188	/* Bit 23 : Protection enable for region 23. */
bogdanm	87:6213f644d804	3189	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
bogdanm	87:6213f644d804	3190	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
bogdanm	87:6213f644d804	3191	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3192	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3193	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3194
bogdanm	87:6213f644d804	3195	/* Bit 22 : Protection enable for region 22. */
bogdanm	87:6213f644d804	3196	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
bogdanm	87:6213f644d804	3197	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
bogdanm	87:6213f644d804	3198	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3199	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3200	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3201
bogdanm	87:6213f644d804	3202	/* Bit 21 : Protection enable for region 21. */
bogdanm	87:6213f644d804	3203	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
bogdanm	87:6213f644d804	3204	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
bogdanm	87:6213f644d804	3205	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3206	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3207	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3208
bogdanm	87:6213f644d804	3209	/* Bit 20 : Protection enable for region 20. */
bogdanm	87:6213f644d804	3210	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
bogdanm	87:6213f644d804	3211	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
bogdanm	87:6213f644d804	3212	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3213	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3214	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3215
bogdanm	87:6213f644d804	3216	/* Bit 19 : Protection enable for region 19. */
bogdanm	87:6213f644d804	3217	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
bogdanm	87:6213f644d804	3218	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
bogdanm	87:6213f644d804	3219	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3220	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3221	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3222
bogdanm	87:6213f644d804	3223	/* Bit 18 : Protection enable for region 18. */
bogdanm	87:6213f644d804	3224	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
bogdanm	87:6213f644d804	3225	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
bogdanm	87:6213f644d804	3226	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3227	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3228	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3229
bogdanm	87:6213f644d804	3230	/* Bit 17 : Protection enable for region 17. */
bogdanm	87:6213f644d804	3231	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
bogdanm	87:6213f644d804	3232	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
bogdanm	87:6213f644d804	3233	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3234	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3235	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3236
bogdanm	87:6213f644d804	3237	/* Bit 16 : Protection enable for region 16. */
bogdanm	87:6213f644d804	3238	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
bogdanm	87:6213f644d804	3239	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
bogdanm	87:6213f644d804	3240	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3241	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3242	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3243
bogdanm	87:6213f644d804	3244	/* Bit 15 : Protection enable for region 15. */
bogdanm	87:6213f644d804	3245	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
bogdanm	87:6213f644d804	3246	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
bogdanm	87:6213f644d804	3247	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3248	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3249	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3250
bogdanm	87:6213f644d804	3251	/* Bit 14 : Protection enable for region 14. */
bogdanm	87:6213f644d804	3252	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
bogdanm	87:6213f644d804	3253	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
bogdanm	87:6213f644d804	3254	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3255	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3256	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3257
bogdanm	87:6213f644d804	3258	/* Bit 13 : Protection enable for region 13. */
bogdanm	87:6213f644d804	3259	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
bogdanm	87:6213f644d804	3260	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
bogdanm	87:6213f644d804	3261	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3262	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3263	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3264
bogdanm	87:6213f644d804	3265	/* Bit 12 : Protection enable for region 12. */
bogdanm	87:6213f644d804	3266	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
bogdanm	87:6213f644d804	3267	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
bogdanm	87:6213f644d804	3268	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3269	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3270	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3271
bogdanm	87:6213f644d804	3272	/* Bit 11 : Protection enable for region 11. */
bogdanm	87:6213f644d804	3273	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
bogdanm	87:6213f644d804	3274	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
bogdanm	87:6213f644d804	3275	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3276	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3277	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3278
bogdanm	87:6213f644d804	3279	/* Bit 10 : Protection enable for region 10. */
bogdanm	87:6213f644d804	3280	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
bogdanm	87:6213f644d804	3281	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
bogdanm	87:6213f644d804	3282	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3283	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3284	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3285
bogdanm	87:6213f644d804	3286	/* Bit 9 : Protection enable for region 9. */
bogdanm	87:6213f644d804	3287	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
bogdanm	87:6213f644d804	3288	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
bogdanm	87:6213f644d804	3289	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3290	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3291	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3292
bogdanm	87:6213f644d804	3293	/* Bit 8 : Protection enable for region 8. */
bogdanm	87:6213f644d804	3294	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
bogdanm	87:6213f644d804	3295	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
bogdanm	87:6213f644d804	3296	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3297	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3298	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3299
bogdanm	87:6213f644d804	3300	/* Bit 7 : Protection enable for region 7. */
bogdanm	87:6213f644d804	3301	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
bogdanm	87:6213f644d804	3302	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
bogdanm	87:6213f644d804	3303	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3304	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3305	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3306
bogdanm	87:6213f644d804	3307	/* Bit 6 : Protection enable for region 6. */
bogdanm	87:6213f644d804	3308	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
bogdanm	87:6213f644d804	3309	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
bogdanm	87:6213f644d804	3310	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3311	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3312	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3313
bogdanm	87:6213f644d804	3314	/* Bit 5 : Protection enable for region 5. */
bogdanm	87:6213f644d804	3315	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
bogdanm	87:6213f644d804	3316	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
bogdanm	87:6213f644d804	3317	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3318	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3319	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3320
bogdanm	87:6213f644d804	3321	/* Bit 4 : Protection enable for region 4. */
bogdanm	87:6213f644d804	3322	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
bogdanm	87:6213f644d804	3323	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
bogdanm	87:6213f644d804	3324	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3325	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3326	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3327
bogdanm	87:6213f644d804	3328	/* Bit 3 : Protection enable for region 3. */
bogdanm	87:6213f644d804	3329	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
bogdanm	87:6213f644d804	3330	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
bogdanm	87:6213f644d804	3331	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3332	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3333	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3334
bogdanm	87:6213f644d804	3335	/* Bit 2 : Protection enable for region 2. */
bogdanm	87:6213f644d804	3336	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
bogdanm	87:6213f644d804	3337	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
bogdanm	87:6213f644d804	3338	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3339	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3340	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3341
bogdanm	87:6213f644d804	3342	/* Bit 1 : Protection enable for region 1. */
bogdanm	87:6213f644d804	3343	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
bogdanm	87:6213f644d804	3344	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
bogdanm	87:6213f644d804	3345	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3346	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3347	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3348
bogdanm	87:6213f644d804	3349	/* Bit 0 : Protection enable for region 0. */
bogdanm	87:6213f644d804	3350	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
bogdanm	87:6213f644d804	3351	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
bogdanm	87:6213f644d804	3352	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3353	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3354	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3355
bogdanm	87:6213f644d804	3356	/* Register: MPU_PROTENSET1 */
Kojto	97:433970e64889	3357	/* Description: Erase and write protection bit enable set register. */
bogdanm	87:6213f644d804	3358
bogdanm	87:6213f644d804	3359	/* Bit 31 : Protection enable for region 63. */
bogdanm	87:6213f644d804	3360	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
bogdanm	87:6213f644d804	3361	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
bogdanm	87:6213f644d804	3362	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3363	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3364	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3365
bogdanm	87:6213f644d804	3366	/* Bit 30 : Protection enable for region 62. */
bogdanm	87:6213f644d804	3367	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
bogdanm	87:6213f644d804	3368	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
bogdanm	87:6213f644d804	3369	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3370	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3371	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3372
bogdanm	87:6213f644d804	3373	/* Bit 29 : Protection enable for region 61. */
bogdanm	87:6213f644d804	3374	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
bogdanm	87:6213f644d804	3375	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
bogdanm	87:6213f644d804	3376	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3377	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3378	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3379
bogdanm	87:6213f644d804	3380	/* Bit 28 : Protection enable for region 60. */
bogdanm	87:6213f644d804	3381	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
bogdanm	87:6213f644d804	3382	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
bogdanm	87:6213f644d804	3383	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3384	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3385	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3386
bogdanm	87:6213f644d804	3387	/* Bit 27 : Protection enable for region 59. */
bogdanm	87:6213f644d804	3388	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
bogdanm	87:6213f644d804	3389	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
bogdanm	87:6213f644d804	3390	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3391	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3392	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3393
bogdanm	87:6213f644d804	3394	/* Bit 26 : Protection enable for region 58. */
bogdanm	87:6213f644d804	3395	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
bogdanm	87:6213f644d804	3396	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
bogdanm	87:6213f644d804	3397	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3398	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3399	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3400
bogdanm	87:6213f644d804	3401	/* Bit 25 : Protection enable for region 57. */
bogdanm	87:6213f644d804	3402	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
bogdanm	87:6213f644d804	3403	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
bogdanm	87:6213f644d804	3404	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3405	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3406	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3407
bogdanm	87:6213f644d804	3408	/* Bit 24 : Protection enable for region 56. */
bogdanm	87:6213f644d804	3409	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
bogdanm	87:6213f644d804	3410	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
bogdanm	87:6213f644d804	3411	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3412	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3413	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3414
bogdanm	87:6213f644d804	3415	/* Bit 23 : Protection enable for region 55. */
bogdanm	87:6213f644d804	3416	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
bogdanm	87:6213f644d804	3417	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
bogdanm	87:6213f644d804	3418	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3419	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3420	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3421
bogdanm	87:6213f644d804	3422	/* Bit 22 : Protection enable for region 54. */
bogdanm	87:6213f644d804	3423	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
bogdanm	87:6213f644d804	3424	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
bogdanm	87:6213f644d804	3425	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3426	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3427	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3428
bogdanm	87:6213f644d804	3429	/* Bit 21 : Protection enable for region 53. */
bogdanm	87:6213f644d804	3430	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
bogdanm	87:6213f644d804	3431	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
bogdanm	87:6213f644d804	3432	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3433	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3434	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3435
bogdanm	87:6213f644d804	3436	/* Bit 20 : Protection enable for region 52. */
bogdanm	87:6213f644d804	3437	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
bogdanm	87:6213f644d804	3438	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
bogdanm	87:6213f644d804	3439	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3440	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3441	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3442
bogdanm	87:6213f644d804	3443	/* Bit 19 : Protection enable for region 51. */
bogdanm	87:6213f644d804	3444	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
bogdanm	87:6213f644d804	3445	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
bogdanm	87:6213f644d804	3446	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3447	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3448	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3449
bogdanm	87:6213f644d804	3450	/* Bit 18 : Protection enable for region 50. */
bogdanm	87:6213f644d804	3451	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
bogdanm	87:6213f644d804	3452	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
bogdanm	87:6213f644d804	3453	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3454	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3455	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3456
bogdanm	87:6213f644d804	3457	/* Bit 17 : Protection enable for region 49. */
bogdanm	87:6213f644d804	3458	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
bogdanm	87:6213f644d804	3459	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
bogdanm	87:6213f644d804	3460	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3461	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3462	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3463
bogdanm	87:6213f644d804	3464	/* Bit 16 : Protection enable for region 48. */
bogdanm	87:6213f644d804	3465	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
bogdanm	87:6213f644d804	3466	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
bogdanm	87:6213f644d804	3467	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3468	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3469	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3470
bogdanm	87:6213f644d804	3471	/* Bit 15 : Protection enable for region 47. */
bogdanm	87:6213f644d804	3472	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
bogdanm	87:6213f644d804	3473	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
bogdanm	87:6213f644d804	3474	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3475	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3476	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3477
bogdanm	87:6213f644d804	3478	/* Bit 14 : Protection enable for region 46. */
bogdanm	87:6213f644d804	3479	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
bogdanm	87:6213f644d804	3480	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
bogdanm	87:6213f644d804	3481	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3482	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3483	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3484
bogdanm	87:6213f644d804	3485	/* Bit 13 : Protection enable for region 45. */
bogdanm	87:6213f644d804	3486	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
bogdanm	87:6213f644d804	3487	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
bogdanm	87:6213f644d804	3488	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3489	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3490	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3491
bogdanm	87:6213f644d804	3492	/* Bit 12 : Protection enable for region 44. */
bogdanm	87:6213f644d804	3493	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
bogdanm	87:6213f644d804	3494	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
bogdanm	87:6213f644d804	3495	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3496	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3497	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3498
bogdanm	87:6213f644d804	3499	/* Bit 11 : Protection enable for region 43. */
bogdanm	87:6213f644d804	3500	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
bogdanm	87:6213f644d804	3501	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
bogdanm	87:6213f644d804	3502	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3503	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3504	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3505
bogdanm	87:6213f644d804	3506	/* Bit 10 : Protection enable for region 42. */
bogdanm	87:6213f644d804	3507	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
bogdanm	87:6213f644d804	3508	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
bogdanm	87:6213f644d804	3509	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3510	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3511	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3512
bogdanm	87:6213f644d804	3513	/* Bit 9 : Protection enable for region 41. */
bogdanm	87:6213f644d804	3514	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
bogdanm	87:6213f644d804	3515	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
bogdanm	87:6213f644d804	3516	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3517	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3518	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3519
bogdanm	87:6213f644d804	3520	/* Bit 8 : Protection enable for region 40. */
bogdanm	87:6213f644d804	3521	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
bogdanm	87:6213f644d804	3522	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
bogdanm	87:6213f644d804	3523	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3524	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3525	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3526
bogdanm	87:6213f644d804	3527	/* Bit 7 : Protection enable for region 39. */
bogdanm	87:6213f644d804	3528	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
bogdanm	87:6213f644d804	3529	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
bogdanm	87:6213f644d804	3530	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3531	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3532	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3533
bogdanm	87:6213f644d804	3534	/* Bit 6 : Protection enable for region 38. */
bogdanm	87:6213f644d804	3535	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
bogdanm	87:6213f644d804	3536	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
bogdanm	87:6213f644d804	3537	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3538	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3539	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3540
bogdanm	87:6213f644d804	3541	/* Bit 5 : Protection enable for region 37. */
bogdanm	87:6213f644d804	3542	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
bogdanm	87:6213f644d804	3543	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
bogdanm	87:6213f644d804	3544	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3545	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3546	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3547
bogdanm	87:6213f644d804	3548	/* Bit 4 : Protection enable for region 36. */
bogdanm	87:6213f644d804	3549	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
bogdanm	87:6213f644d804	3550	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
bogdanm	87:6213f644d804	3551	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3552	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3553	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3554
bogdanm	87:6213f644d804	3555	/* Bit 3 : Protection enable for region 35. */
bogdanm	87:6213f644d804	3556	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
bogdanm	87:6213f644d804	3557	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
bogdanm	87:6213f644d804	3558	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3559	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3560	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3561
bogdanm	87:6213f644d804	3562	/* Bit 2 : Protection enable for region 34. */
bogdanm	87:6213f644d804	3563	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
bogdanm	87:6213f644d804	3564	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
bogdanm	87:6213f644d804	3565	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3566	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3567	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3568
bogdanm	87:6213f644d804	3569	/* Bit 1 : Protection enable for region 33. */
bogdanm	87:6213f644d804	3570	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
bogdanm	87:6213f644d804	3571	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
bogdanm	87:6213f644d804	3572	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3573	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3574	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3575
bogdanm	87:6213f644d804	3576	/* Bit 0 : Protection enable for region 32. */
bogdanm	87:6213f644d804	3577	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
bogdanm	87:6213f644d804	3578	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
bogdanm	87:6213f644d804	3579	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3580	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3581	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
bogdanm	87:6213f644d804	3582
bogdanm	87:6213f644d804	3583	/* Register: MPU_DISABLEINDEBUG */
Kojto	97:433970e64889	3584	/* Description: Disable erase and write protection mechanism in debug mode. */
bogdanm	87:6213f644d804	3585
bogdanm	87:6213f644d804	3586	/* Bit 0 : Disable protection mechanism in debug mode. */
bogdanm	87:6213f644d804	3587	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
bogdanm	87:6213f644d804	3588	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
bogdanm	87:6213f644d804	3589	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
bogdanm	87:6213f644d804	3590	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
bogdanm	87:6213f644d804	3591
Kojto	97:433970e64889	3592	/* Register: MPU_PROTBLOCKSIZE */
Kojto	97:433970e64889	3593	/* Description: Erase and write protection block size. */
Kojto	97:433970e64889	3594
Kojto	97:433970e64889	3595	/* Bits 1..0 : Erase and write protection block size. */
Kojto	97:433970e64889	3596	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
Kojto	97:433970e64889	3597	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
Kojto	97:433970e64889	3598	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
Kojto	97:433970e64889	3599
bogdanm	87:6213f644d804	3600
bogdanm	87:6213f644d804	3601	/* Peripheral: NVMC */
bogdanm	87:6213f644d804	3602	/* Description: Non Volatile Memory Controller. */
bogdanm	87:6213f644d804	3603
bogdanm	87:6213f644d804	3604	/* Register: NVMC_READY */
bogdanm	87:6213f644d804	3605	/* Description: Ready flag. */
bogdanm	87:6213f644d804	3606
bogdanm	87:6213f644d804	3607	/* Bit 0 : NVMC ready. */
bogdanm	87:6213f644d804	3608	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	87:6213f644d804	3609	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
bogdanm	87:6213f644d804	3610	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
bogdanm	87:6213f644d804	3611	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
bogdanm	87:6213f644d804	3612
bogdanm	87:6213f644d804	3613	/* Register: NVMC_CONFIG */
bogdanm	87:6213f644d804	3614	/* Description: Configuration register. */
bogdanm	87:6213f644d804	3615
bogdanm	87:6213f644d804	3616	/* Bits 1..0 : Program write enable. */
bogdanm	87:6213f644d804	3617	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
bogdanm	87:6213f644d804	3618	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
bogdanm	87:6213f644d804	3619	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
bogdanm	87:6213f644d804	3620	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
bogdanm	87:6213f644d804	3621	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
bogdanm	87:6213f644d804	3622
bogdanm	87:6213f644d804	3623	/* Register: NVMC_ERASEALL */
bogdanm	87:6213f644d804	3624	/* Description: Register for erasing all non-volatile user memory. */
bogdanm	87:6213f644d804	3625
bogdanm	87:6213f644d804	3626	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
bogdanm	87:6213f644d804	3627	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
bogdanm	87:6213f644d804	3628	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
bogdanm	87:6213f644d804	3629	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
bogdanm	87:6213f644d804	3630	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
bogdanm	87:6213f644d804	3631
bogdanm	87:6213f644d804	3632	/* Register: NVMC_ERASEUICR */
bogdanm	87:6213f644d804	3633	/* Description: Register for start erasing User Information Congfiguration Registers. */
bogdanm	87:6213f644d804	3634
bogdanm	87:6213f644d804	3635	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
bogdanm	87:6213f644d804	3636	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
bogdanm	87:6213f644d804	3637	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
bogdanm	87:6213f644d804	3638	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
bogdanm	87:6213f644d804	3639	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
bogdanm	87:6213f644d804	3640
bogdanm	87:6213f644d804	3641
bogdanm	87:6213f644d804	3642	/* Peripheral: POWER */
bogdanm	87:6213f644d804	3643	/* Description: Power Control. */
bogdanm	87:6213f644d804	3644
bogdanm	87:6213f644d804	3645	/* Register: POWER_INTENSET */
bogdanm	87:6213f644d804	3646	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	3647
bogdanm	87:6213f644d804	3648	/* Bit 2 : Enable interrupt on POFWARN event. */
bogdanm	87:6213f644d804	3649	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
bogdanm	87:6213f644d804	3650	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
bogdanm	87:6213f644d804	3651	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	3652	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	3653	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	3654
bogdanm	87:6213f644d804	3655	/* Register: POWER_INTENCLR */
bogdanm	87:6213f644d804	3656	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	3657
bogdanm	87:6213f644d804	3658	/* Bit 2 : Disable interrupt on POFWARN event. */
bogdanm	87:6213f644d804	3659	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
bogdanm	87:6213f644d804	3660	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
bogdanm	87:6213f644d804	3661	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	3662	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	3663	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	3664
bogdanm	87:6213f644d804	3665	/* Register: POWER_RESETREAS */
bogdanm	87:6213f644d804	3666	/* Description: Reset reason. */
bogdanm	87:6213f644d804	3667
bogdanm	87:6213f644d804	3668	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
bogdanm	87:6213f644d804	3669	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
bogdanm	87:6213f644d804	3670	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
Kojto	122:f9eeca106725	3671	#define POWER_RESETREAS_DIF_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3672	#define POWER_RESETREAS_DIF_Detected (1UL) /!< Reset detected. /
bogdanm	87:6213f644d804	3673
bogdanm	87:6213f644d804	3674	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
bogdanm	87:6213f644d804	3675	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
bogdanm	87:6213f644d804	3676	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
Kojto	122:f9eeca106725	3677	#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3678	#define POWER_RESETREAS_LPCOMP_Detected (1UL) /!< Reset detected. /
bogdanm	87:6213f644d804	3679
bogdanm	87:6213f644d804	3680	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
bogdanm	87:6213f644d804	3681	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
bogdanm	87:6213f644d804	3682	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
Kojto	122:f9eeca106725	3683	#define POWER_RESETREAS_OFF_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3684	#define POWER_RESETREAS_OFF_Detected (1UL) /!< Reset detected. /
bogdanm	87:6213f644d804	3685
bogdanm	87:6213f644d804	3686	/* Bit 3 : Reset from CPU lock-up detected. */
bogdanm	87:6213f644d804	3687	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
bogdanm	87:6213f644d804	3688	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
Kojto	122:f9eeca106725	3689	#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3690	#define POWER_RESETREAS_LOCKUP_Detected (1UL) /!< Reset detected. /
bogdanm	87:6213f644d804	3691
bogdanm	87:6213f644d804	3692	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
bogdanm	87:6213f644d804	3693	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
bogdanm	87:6213f644d804	3694	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
Kojto	122:f9eeca106725	3695	#define POWER_RESETREAS_SREQ_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3696	#define POWER_RESETREAS_SREQ_Detected (1UL) /!< Reset detected. /
bogdanm	87:6213f644d804	3697
bogdanm	87:6213f644d804	3698	/* Bit 1 : Reset from watchdog detected. */
bogdanm	87:6213f644d804	3699	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
bogdanm	87:6213f644d804	3700	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
Kojto	122:f9eeca106725	3701	#define POWER_RESETREAS_DOG_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3702	#define POWER_RESETREAS_DOG_Detected (1UL) /!< Reset detected. /
bogdanm	87:6213f644d804	3703
bogdanm	87:6213f644d804	3704	/* Bit 0 : Reset from pin-reset detected. */
bogdanm	87:6213f644d804	3705	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
bogdanm	87:6213f644d804	3706	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
Kojto	122:f9eeca106725	3707	#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /!< Reset not detected. /
Kojto	122:f9eeca106725	3708	#define POWER_RESETREAS_RESETPIN_Detected (1UL) /!< Reset detected. /
bogdanm	87:6213f644d804	3709
Kojto	97:433970e64889	3710	/* Register: POWER_RAMSTATUS */
Kojto	97:433970e64889	3711	/* Description: Ram status register. */
Kojto	97:433970e64889	3712
Kojto	97:433970e64889	3713	/* Bit 3 : RAM block 3 status. */
Kojto	97:433970e64889	3714	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
Kojto	97:433970e64889	3715	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
Kojto	97:433970e64889	3716	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
Kojto	97:433970e64889	3717	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
Kojto	97:433970e64889	3718
Kojto	97:433970e64889	3719	/* Bit 2 : RAM block 2 status. */
Kojto	97:433970e64889	3720	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
Kojto	97:433970e64889	3721	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
Kojto	97:433970e64889	3722	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
Kojto	97:433970e64889	3723	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
Kojto	97:433970e64889	3724
Kojto	97:433970e64889	3725	/* Bit 1 : RAM block 1 status. */
Kojto	97:433970e64889	3726	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
Kojto	97:433970e64889	3727	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
Kojto	97:433970e64889	3728	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
Kojto	97:433970e64889	3729	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
Kojto	97:433970e64889	3730
Kojto	97:433970e64889	3731	/* Bit 0 : RAM block 0 status. */
Kojto	97:433970e64889	3732	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
Kojto	97:433970e64889	3733	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
Kojto	97:433970e64889	3734	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
Kojto	97:433970e64889	3735	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
Kojto	97:433970e64889	3736
bogdanm	87:6213f644d804	3737	/* Register: POWER_SYSTEMOFF */
bogdanm	87:6213f644d804	3738	/* Description: System off register. */
bogdanm	87:6213f644d804	3739
bogdanm	87:6213f644d804	3740	/* Bit 0 : Enter system off mode. */
bogdanm	87:6213f644d804	3741	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
bogdanm	87:6213f644d804	3742	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
bogdanm	87:6213f644d804	3743	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
bogdanm	87:6213f644d804	3744
bogdanm	87:6213f644d804	3745	/* Register: POWER_POFCON */
bogdanm	87:6213f644d804	3746	/* Description: Power failure configuration. */
bogdanm	87:6213f644d804	3747
bogdanm	87:6213f644d804	3748	/* Bits 2..1 : Set threshold level. */
bogdanm	87:6213f644d804	3749	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
bogdanm	87:6213f644d804	3750	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
bogdanm	87:6213f644d804	3751	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
bogdanm	87:6213f644d804	3752	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
bogdanm	87:6213f644d804	3753	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
bogdanm	87:6213f644d804	3754	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
bogdanm	87:6213f644d804	3755
bogdanm	87:6213f644d804	3756	/* Bit 0 : Power failure comparator enable. */
bogdanm	87:6213f644d804	3757	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
bogdanm	87:6213f644d804	3758	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
bogdanm	87:6213f644d804	3759	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	3760	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	3761
bogdanm	87:6213f644d804	3762	/* Register: POWER_GPREGRET */
bogdanm	87:6213f644d804	3763	/* Description: General purpose retention register. This register is a retained register. */
bogdanm	87:6213f644d804	3764
bogdanm	87:6213f644d804	3765	/* Bits 7..0 : General purpose retention register. */
bogdanm	87:6213f644d804	3766	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
bogdanm	87:6213f644d804	3767	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
bogdanm	87:6213f644d804	3768
bogdanm	87:6213f644d804	3769	/* Register: POWER_RAMON */
bogdanm	87:6213f644d804	3770	/* Description: Ram on/off. */
bogdanm	87:6213f644d804	3771
bogdanm	87:6213f644d804	3772	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
bogdanm	87:6213f644d804	3773	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
bogdanm	87:6213f644d804	3774	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
bogdanm	87:6213f644d804	3775	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
bogdanm	87:6213f644d804	3776	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
bogdanm	87:6213f644d804	3777
bogdanm	87:6213f644d804	3778	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
bogdanm	87:6213f644d804	3779	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
bogdanm	87:6213f644d804	3780	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
bogdanm	87:6213f644d804	3781	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
bogdanm	87:6213f644d804	3782	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
bogdanm	87:6213f644d804	3783
bogdanm	87:6213f644d804	3784	/* Bit 1 : RAM block 1 behaviour in ON mode. */
bogdanm	87:6213f644d804	3785	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
bogdanm	87:6213f644d804	3786	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
bogdanm	87:6213f644d804	3787	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
bogdanm	87:6213f644d804	3788	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
bogdanm	87:6213f644d804	3789
bogdanm	87:6213f644d804	3790	/* Bit 0 : RAM block 0 behaviour in ON mode. */
bogdanm	87:6213f644d804	3791	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
bogdanm	87:6213f644d804	3792	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
bogdanm	87:6213f644d804	3793	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
bogdanm	87:6213f644d804	3794	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
bogdanm	87:6213f644d804	3795
bogdanm	87:6213f644d804	3796	/* Register: POWER_RESET */
bogdanm	87:6213f644d804	3797	/* Description: Pin reset functionality configuration register. This register is a retained register. */
bogdanm	87:6213f644d804	3798
Kojto	97:433970e64889	3799	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
bogdanm	87:6213f644d804	3800	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
bogdanm	87:6213f644d804	3801	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
bogdanm	87:6213f644d804	3802	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
bogdanm	87:6213f644d804	3803	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
bogdanm	87:6213f644d804	3804
Kojto	97:433970e64889	3805	/* Register: POWER_RAMONB */
Kojto	97:433970e64889	3806	/* Description: Ram on/off. */
Kojto	97:433970e64889	3807
Kojto	97:433970e64889	3808	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
Kojto	97:433970e64889	3809	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
Kojto	97:433970e64889	3810	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
Kojto	97:433970e64889	3811	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
Kojto	97:433970e64889	3812	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
Kojto	97:433970e64889	3813
Kojto	97:433970e64889	3814	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
Kojto	97:433970e64889	3815	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
Kojto	97:433970e64889	3816	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
Kojto	97:433970e64889	3817	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
Kojto	97:433970e64889	3818	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
Kojto	97:433970e64889	3819
Kojto	97:433970e64889	3820	/* Bit 1 : RAM block 3 behaviour in ON mode. */
Kojto	97:433970e64889	3821	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
Kojto	97:433970e64889	3822	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
Kojto	97:433970e64889	3823	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
Kojto	97:433970e64889	3824	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
Kojto	97:433970e64889	3825
Kojto	97:433970e64889	3826	/* Bit 0 : RAM block 2 behaviour in ON mode. */
Kojto	97:433970e64889	3827	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
Kojto	97:433970e64889	3828	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
Kojto	97:433970e64889	3829	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
Kojto	97:433970e64889	3830	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
Kojto	97:433970e64889	3831
bogdanm	87:6213f644d804	3832	/* Register: POWER_DCDCEN */
bogdanm	87:6213f644d804	3833	/* Description: DCDC converter enable configuration register. */
bogdanm	87:6213f644d804	3834
bogdanm	87:6213f644d804	3835	/* Bit 0 : Enable DCDC converter. */
bogdanm	87:6213f644d804	3836	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
bogdanm	87:6213f644d804	3837	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
bogdanm	87:6213f644d804	3838	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
bogdanm	87:6213f644d804	3839	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
bogdanm	87:6213f644d804	3840
Kojto	97:433970e64889	3841	/* Register: POWER_DCDCFORCE */
Kojto	97:433970e64889	3842	/* Description: DCDC power-up force register. */
Kojto	97:433970e64889	3843
Kojto	97:433970e64889	3844	/* Bit 1 : DCDC power-up force on. */
Kojto	97:433970e64889	3845	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
Kojto	97:433970e64889	3846	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
Kojto	97:433970e64889	3847	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
Kojto	97:433970e64889	3848	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
Kojto	97:433970e64889	3849
Kojto	97:433970e64889	3850	/* Bit 0 : DCDC power-up force off. */
Kojto	97:433970e64889	3851	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
Kojto	97:433970e64889	3852	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
Kojto	97:433970e64889	3853	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
Kojto	97:433970e64889	3854	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
Kojto	97:433970e64889	3855
bogdanm	87:6213f644d804	3856
bogdanm	87:6213f644d804	3857	/* Peripheral: PPI */
bogdanm	87:6213f644d804	3858	/* Description: PPI controller. */
bogdanm	87:6213f644d804	3859
bogdanm	87:6213f644d804	3860	/* Register: PPI_CHEN */
bogdanm	87:6213f644d804	3861	/* Description: Channel enable. */
bogdanm	87:6213f644d804	3862
bogdanm	87:6213f644d804	3863	/* Bit 31 : Enable PPI channel 31. */
bogdanm	87:6213f644d804	3864	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	87:6213f644d804	3865	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	87:6213f644d804	3866	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3867	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3868
bogdanm	87:6213f644d804	3869	/* Bit 30 : Enable PPI channel 30. */
bogdanm	87:6213f644d804	3870	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	87:6213f644d804	3871	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	87:6213f644d804	3872	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3873	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3874
bogdanm	87:6213f644d804	3875	/* Bit 29 : Enable PPI channel 29. */
bogdanm	87:6213f644d804	3876	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	87:6213f644d804	3877	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	87:6213f644d804	3878	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3879	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3880
bogdanm	87:6213f644d804	3881	/* Bit 28 : Enable PPI channel 28. */
bogdanm	87:6213f644d804	3882	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	87:6213f644d804	3883	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	87:6213f644d804	3884	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3885	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3886
bogdanm	87:6213f644d804	3887	/* Bit 27 : Enable PPI channel 27. */
bogdanm	87:6213f644d804	3888	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	87:6213f644d804	3889	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	87:6213f644d804	3890	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3891	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3892
bogdanm	87:6213f644d804	3893	/* Bit 26 : Enable PPI channel 26. */
bogdanm	87:6213f644d804	3894	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	87:6213f644d804	3895	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	87:6213f644d804	3896	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3897	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3898
bogdanm	87:6213f644d804	3899	/* Bit 25 : Enable PPI channel 25. */
bogdanm	87:6213f644d804	3900	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	87:6213f644d804	3901	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	87:6213f644d804	3902	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3903	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3904
bogdanm	87:6213f644d804	3905	/* Bit 24 : Enable PPI channel 24. */
bogdanm	87:6213f644d804	3906	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	87:6213f644d804	3907	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	87:6213f644d804	3908	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3909	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3910
bogdanm	87:6213f644d804	3911	/* Bit 23 : Enable PPI channel 23. */
bogdanm	87:6213f644d804	3912	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	87:6213f644d804	3913	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	87:6213f644d804	3914	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3915	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3916
bogdanm	87:6213f644d804	3917	/* Bit 22 : Enable PPI channel 22. */
bogdanm	87:6213f644d804	3918	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	87:6213f644d804	3919	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	87:6213f644d804	3920	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3921	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3922
bogdanm	87:6213f644d804	3923	/* Bit 21 : Enable PPI channel 21. */
bogdanm	87:6213f644d804	3924	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	87:6213f644d804	3925	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	87:6213f644d804	3926	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3927	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3928
bogdanm	87:6213f644d804	3929	/* Bit 20 : Enable PPI channel 20. */
bogdanm	87:6213f644d804	3930	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	87:6213f644d804	3931	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	87:6213f644d804	3932	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3933	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3934
bogdanm	87:6213f644d804	3935	/* Bit 15 : Enable PPI channel 15. */
bogdanm	87:6213f644d804	3936	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	87:6213f644d804	3937	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	87:6213f644d804	3938	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3939	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3940
bogdanm	87:6213f644d804	3941	/* Bit 14 : Enable PPI channel 14. */
bogdanm	87:6213f644d804	3942	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	87:6213f644d804	3943	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	87:6213f644d804	3944	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3945	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3946
bogdanm	87:6213f644d804	3947	/* Bit 13 : Enable PPI channel 13. */
bogdanm	87:6213f644d804	3948	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	87:6213f644d804	3949	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	87:6213f644d804	3950	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3951	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3952
bogdanm	87:6213f644d804	3953	/* Bit 12 : Enable PPI channel 12. */
bogdanm	87:6213f644d804	3954	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	87:6213f644d804	3955	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	87:6213f644d804	3956	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3957	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3958
bogdanm	87:6213f644d804	3959	/* Bit 11 : Enable PPI channel 11. */
bogdanm	87:6213f644d804	3960	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	87:6213f644d804	3961	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	87:6213f644d804	3962	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3963	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3964
bogdanm	87:6213f644d804	3965	/* Bit 10 : Enable PPI channel 10. */
bogdanm	87:6213f644d804	3966	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	87:6213f644d804	3967	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	87:6213f644d804	3968	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3969	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3970
bogdanm	87:6213f644d804	3971	/* Bit 9 : Enable PPI channel 9. */
bogdanm	87:6213f644d804	3972	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	87:6213f644d804	3973	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	87:6213f644d804	3974	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3975	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3976
bogdanm	87:6213f644d804	3977	/* Bit 8 : Enable PPI channel 8. */
bogdanm	87:6213f644d804	3978	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	87:6213f644d804	3979	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	87:6213f644d804	3980	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3981	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3982
bogdanm	87:6213f644d804	3983	/* Bit 7 : Enable PPI channel 7. */
bogdanm	87:6213f644d804	3984	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	87:6213f644d804	3985	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	87:6213f644d804	3986	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3987	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3988
bogdanm	87:6213f644d804	3989	/* Bit 6 : Enable PPI channel 6. */
bogdanm	87:6213f644d804	3990	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	87:6213f644d804	3991	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	87:6213f644d804	3992	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3993	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	3994
bogdanm	87:6213f644d804	3995	/* Bit 5 : Enable PPI channel 5. */
bogdanm	87:6213f644d804	3996	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	87:6213f644d804	3997	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	87:6213f644d804	3998	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	3999	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4000
bogdanm	87:6213f644d804	4001	/* Bit 4 : Enable PPI channel 4. */
bogdanm	87:6213f644d804	4002	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	87:6213f644d804	4003	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	87:6213f644d804	4004	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4005	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4006
bogdanm	87:6213f644d804	4007	/* Bit 3 : Enable PPI channel 3. */
bogdanm	87:6213f644d804	4008	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	87:6213f644d804	4009	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	87:6213f644d804	4010	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
bogdanm	87:6213f644d804	4011	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
bogdanm	87:6213f644d804	4012
bogdanm	87:6213f644d804	4013	/* Bit 2 : Enable PPI channel 2. */
bogdanm	87:6213f644d804	4014	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	87:6213f644d804	4015	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	87:6213f644d804	4016	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4017	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4018
bogdanm	87:6213f644d804	4019	/* Bit 1 : Enable PPI channel 1. */
bogdanm	87:6213f644d804	4020	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	87:6213f644d804	4021	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	87:6213f644d804	4022	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4023	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4024
bogdanm	87:6213f644d804	4025	/* Bit 0 : Enable PPI channel 0. */
bogdanm	87:6213f644d804	4026	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	87:6213f644d804	4027	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	87:6213f644d804	4028	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4029	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4030
bogdanm	87:6213f644d804	4031	/* Register: PPI_CHENSET */
bogdanm	87:6213f644d804	4032	/* Description: Channel enable set. */
bogdanm	87:6213f644d804	4033
bogdanm	87:6213f644d804	4034	/* Bit 31 : Enable PPI channel 31. */
bogdanm	87:6213f644d804	4035	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	87:6213f644d804	4036	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	87:6213f644d804	4037	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4038	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4039	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4040
bogdanm	87:6213f644d804	4041	/* Bit 30 : Enable PPI channel 30. */
bogdanm	87:6213f644d804	4042	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	87:6213f644d804	4043	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	87:6213f644d804	4044	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4045	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4046	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4047
bogdanm	87:6213f644d804	4048	/* Bit 29 : Enable PPI channel 29. */
bogdanm	87:6213f644d804	4049	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	87:6213f644d804	4050	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	87:6213f644d804	4051	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4052	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4053	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4054
bogdanm	87:6213f644d804	4055	/* Bit 28 : Enable PPI channel 28. */
bogdanm	87:6213f644d804	4056	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	87:6213f644d804	4057	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	87:6213f644d804	4058	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4059	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4060	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4061
bogdanm	87:6213f644d804	4062	/* Bit 27 : Enable PPI channel 27. */
bogdanm	87:6213f644d804	4063	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	87:6213f644d804	4064	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	87:6213f644d804	4065	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4066	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4067	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4068
bogdanm	87:6213f644d804	4069	/* Bit 26 : Enable PPI channel 26. */
bogdanm	87:6213f644d804	4070	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	87:6213f644d804	4071	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	87:6213f644d804	4072	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4073	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4074	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4075
bogdanm	87:6213f644d804	4076	/* Bit 25 : Enable PPI channel 25. */
bogdanm	87:6213f644d804	4077	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	87:6213f644d804	4078	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	87:6213f644d804	4079	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4080	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4081	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4082
bogdanm	87:6213f644d804	4083	/* Bit 24 : Enable PPI channel 24. */
bogdanm	87:6213f644d804	4084	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	87:6213f644d804	4085	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	87:6213f644d804	4086	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4087	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4088	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4089
bogdanm	87:6213f644d804	4090	/* Bit 23 : Enable PPI channel 23. */
bogdanm	87:6213f644d804	4091	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	87:6213f644d804	4092	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	87:6213f644d804	4093	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4094	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4095	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4096
bogdanm	87:6213f644d804	4097	/* Bit 22 : Enable PPI channel 22. */
bogdanm	87:6213f644d804	4098	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	87:6213f644d804	4099	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	87:6213f644d804	4100	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4101	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4102	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4103
bogdanm	87:6213f644d804	4104	/* Bit 21 : Enable PPI channel 21. */
bogdanm	87:6213f644d804	4105	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	87:6213f644d804	4106	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	87:6213f644d804	4107	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4108	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4109	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4110
bogdanm	87:6213f644d804	4111	/* Bit 20 : Enable PPI channel 20. */
bogdanm	87:6213f644d804	4112	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	87:6213f644d804	4113	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	87:6213f644d804	4114	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4115	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4116	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4117
bogdanm	87:6213f644d804	4118	/* Bit 15 : Enable PPI channel 15. */
bogdanm	87:6213f644d804	4119	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	87:6213f644d804	4120	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	87:6213f644d804	4121	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4122	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4123	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4124
bogdanm	87:6213f644d804	4125	/* Bit 14 : Enable PPI channel 14. */
bogdanm	87:6213f644d804	4126	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	87:6213f644d804	4127	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	87:6213f644d804	4128	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4129	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4130	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4131
bogdanm	87:6213f644d804	4132	/* Bit 13 : Enable PPI channel 13. */
bogdanm	87:6213f644d804	4133	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	87:6213f644d804	4134	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	87:6213f644d804	4135	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4136	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4137	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4138
bogdanm	87:6213f644d804	4139	/* Bit 12 : Enable PPI channel 12. */
bogdanm	87:6213f644d804	4140	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	87:6213f644d804	4141	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	87:6213f644d804	4142	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4143	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4144	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4145
bogdanm	87:6213f644d804	4146	/* Bit 11 : Enable PPI channel 11. */
bogdanm	87:6213f644d804	4147	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	87:6213f644d804	4148	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	87:6213f644d804	4149	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4150	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4151	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4152
bogdanm	87:6213f644d804	4153	/* Bit 10 : Enable PPI channel 10. */
bogdanm	87:6213f644d804	4154	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	87:6213f644d804	4155	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	87:6213f644d804	4156	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4157	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4158	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4159
bogdanm	87:6213f644d804	4160	/* Bit 9 : Enable PPI channel 9. */
bogdanm	87:6213f644d804	4161	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	87:6213f644d804	4162	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	87:6213f644d804	4163	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4164	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4165	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4166
bogdanm	87:6213f644d804	4167	/* Bit 8 : Enable PPI channel 8. */
bogdanm	87:6213f644d804	4168	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	87:6213f644d804	4169	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	87:6213f644d804	4170	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4171	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4172	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4173
bogdanm	87:6213f644d804	4174	/* Bit 7 : Enable PPI channel 7. */
bogdanm	87:6213f644d804	4175	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	87:6213f644d804	4176	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	87:6213f644d804	4177	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4178	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4179	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4180
bogdanm	87:6213f644d804	4181	/* Bit 6 : Enable PPI channel 6. */
bogdanm	87:6213f644d804	4182	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	87:6213f644d804	4183	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	87:6213f644d804	4184	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4185	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4186	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4187
bogdanm	87:6213f644d804	4188	/* Bit 5 : Enable PPI channel 5. */
bogdanm	87:6213f644d804	4189	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	87:6213f644d804	4190	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	87:6213f644d804	4191	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4192	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4193	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4194
bogdanm	87:6213f644d804	4195	/* Bit 4 : Enable PPI channel 4. */
bogdanm	87:6213f644d804	4196	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	87:6213f644d804	4197	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	87:6213f644d804	4198	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4199	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4200	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4201
bogdanm	87:6213f644d804	4202	/* Bit 3 : Enable PPI channel 3. */
bogdanm	87:6213f644d804	4203	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	87:6213f644d804	4204	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	87:6213f644d804	4205	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4206	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4207	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4208
bogdanm	87:6213f644d804	4209	/* Bit 2 : Enable PPI channel 2. */
bogdanm	87:6213f644d804	4210	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	87:6213f644d804	4211	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	87:6213f644d804	4212	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4213	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4214	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4215
bogdanm	87:6213f644d804	4216	/* Bit 1 : Enable PPI channel 1. */
bogdanm	87:6213f644d804	4217	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	87:6213f644d804	4218	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	87:6213f644d804	4219	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4220	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4221	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4222
bogdanm	87:6213f644d804	4223	/* Bit 0 : Enable PPI channel 0. */
bogdanm	87:6213f644d804	4224	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	87:6213f644d804	4225	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	87:6213f644d804	4226	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4227	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4228	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
bogdanm	87:6213f644d804	4229
bogdanm	87:6213f644d804	4230	/* Register: PPI_CHENCLR */
bogdanm	87:6213f644d804	4231	/* Description: Channel enable clear. */
bogdanm	87:6213f644d804	4232
bogdanm	87:6213f644d804	4233	/* Bit 31 : Disable PPI channel 31. */
bogdanm	87:6213f644d804	4234	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	87:6213f644d804	4235	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	87:6213f644d804	4236	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4237	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4238	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4239
bogdanm	87:6213f644d804	4240	/* Bit 30 : Disable PPI channel 30. */
bogdanm	87:6213f644d804	4241	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	87:6213f644d804	4242	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	87:6213f644d804	4243	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4244	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4245	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4246
bogdanm	87:6213f644d804	4247	/* Bit 29 : Disable PPI channel 29. */
bogdanm	87:6213f644d804	4248	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	87:6213f644d804	4249	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	87:6213f644d804	4250	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4251	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4252	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4253
bogdanm	87:6213f644d804	4254	/* Bit 28 : Disable PPI channel 28. */
bogdanm	87:6213f644d804	4255	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	87:6213f644d804	4256	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	87:6213f644d804	4257	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4258	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4259	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4260
bogdanm	87:6213f644d804	4261	/* Bit 27 : Disable PPI channel 27. */
bogdanm	87:6213f644d804	4262	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	87:6213f644d804	4263	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	87:6213f644d804	4264	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4265	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4266	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4267
bogdanm	87:6213f644d804	4268	/* Bit 26 : Disable PPI channel 26. */
bogdanm	87:6213f644d804	4269	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	87:6213f644d804	4270	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	87:6213f644d804	4271	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4272	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4273	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4274
bogdanm	87:6213f644d804	4275	/* Bit 25 : Disable PPI channel 25. */
bogdanm	87:6213f644d804	4276	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	87:6213f644d804	4277	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	87:6213f644d804	4278	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4279	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4280	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4281
bogdanm	87:6213f644d804	4282	/* Bit 24 : Disable PPI channel 24. */
bogdanm	87:6213f644d804	4283	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	87:6213f644d804	4284	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	87:6213f644d804	4285	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4286	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4287	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4288
bogdanm	87:6213f644d804	4289	/* Bit 23 : Disable PPI channel 23. */
bogdanm	87:6213f644d804	4290	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	87:6213f644d804	4291	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	87:6213f644d804	4292	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4293	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4294	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4295
bogdanm	87:6213f644d804	4296	/* Bit 22 : Disable PPI channel 22. */
bogdanm	87:6213f644d804	4297	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	87:6213f644d804	4298	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	87:6213f644d804	4299	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4300	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4301	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4302
bogdanm	87:6213f644d804	4303	/* Bit 21 : Disable PPI channel 21. */
bogdanm	87:6213f644d804	4304	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	87:6213f644d804	4305	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	87:6213f644d804	4306	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4307	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4308	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4309
bogdanm	87:6213f644d804	4310	/* Bit 20 : Disable PPI channel 20. */
bogdanm	87:6213f644d804	4311	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	87:6213f644d804	4312	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	87:6213f644d804	4313	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4314	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4315	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4316
bogdanm	87:6213f644d804	4317	/* Bit 15 : Disable PPI channel 15. */
bogdanm	87:6213f644d804	4318	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	87:6213f644d804	4319	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	87:6213f644d804	4320	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4321	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4322	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4323
bogdanm	87:6213f644d804	4324	/* Bit 14 : Disable PPI channel 14. */
bogdanm	87:6213f644d804	4325	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	87:6213f644d804	4326	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	87:6213f644d804	4327	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4328	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4329	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4330
bogdanm	87:6213f644d804	4331	/* Bit 13 : Disable PPI channel 13. */
bogdanm	87:6213f644d804	4332	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	87:6213f644d804	4333	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	87:6213f644d804	4334	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4335	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4336	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4337
bogdanm	87:6213f644d804	4338	/* Bit 12 : Disable PPI channel 12. */
bogdanm	87:6213f644d804	4339	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	87:6213f644d804	4340	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	87:6213f644d804	4341	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4342	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4343	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4344
bogdanm	87:6213f644d804	4345	/* Bit 11 : Disable PPI channel 11. */
bogdanm	87:6213f644d804	4346	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	87:6213f644d804	4347	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	87:6213f644d804	4348	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4349	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4350	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4351
bogdanm	87:6213f644d804	4352	/* Bit 10 : Disable PPI channel 10. */
bogdanm	87:6213f644d804	4353	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	87:6213f644d804	4354	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	87:6213f644d804	4355	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4356	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4357	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4358
bogdanm	87:6213f644d804	4359	/* Bit 9 : Disable PPI channel 9. */
bogdanm	87:6213f644d804	4360	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	87:6213f644d804	4361	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	87:6213f644d804	4362	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4363	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4364	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4365
bogdanm	87:6213f644d804	4366	/* Bit 8 : Disable PPI channel 8. */
bogdanm	87:6213f644d804	4367	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	87:6213f644d804	4368	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	87:6213f644d804	4369	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4370	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4371	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4372
bogdanm	87:6213f644d804	4373	/* Bit 7 : Disable PPI channel 7. */
bogdanm	87:6213f644d804	4374	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	87:6213f644d804	4375	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	87:6213f644d804	4376	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4377	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4378	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4379
bogdanm	87:6213f644d804	4380	/* Bit 6 : Disable PPI channel 6. */
bogdanm	87:6213f644d804	4381	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	87:6213f644d804	4382	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	87:6213f644d804	4383	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4384	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4385	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4386
bogdanm	87:6213f644d804	4387	/* Bit 5 : Disable PPI channel 5. */
bogdanm	87:6213f644d804	4388	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	87:6213f644d804	4389	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	87:6213f644d804	4390	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4391	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4392	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4393
bogdanm	87:6213f644d804	4394	/* Bit 4 : Disable PPI channel 4. */
bogdanm	87:6213f644d804	4395	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	87:6213f644d804	4396	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	87:6213f644d804	4397	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4398	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4399	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4400
bogdanm	87:6213f644d804	4401	/* Bit 3 : Disable PPI channel 3. */
bogdanm	87:6213f644d804	4402	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	87:6213f644d804	4403	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	87:6213f644d804	4404	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4405	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4406	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4407
bogdanm	87:6213f644d804	4408	/* Bit 2 : Disable PPI channel 2. */
bogdanm	87:6213f644d804	4409	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	87:6213f644d804	4410	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	87:6213f644d804	4411	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4412	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4413	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4414
bogdanm	87:6213f644d804	4415	/* Bit 1 : Disable PPI channel 1. */
bogdanm	87:6213f644d804	4416	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	87:6213f644d804	4417	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	87:6213f644d804	4418	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4419	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4420	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4421
bogdanm	87:6213f644d804	4422	/* Bit 0 : Disable PPI channel 0. */
bogdanm	87:6213f644d804	4423	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	87:6213f644d804	4424	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	87:6213f644d804	4425	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
bogdanm	87:6213f644d804	4426	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
bogdanm	87:6213f644d804	4427	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
bogdanm	87:6213f644d804	4428
bogdanm	87:6213f644d804	4429	/* Register: PPI_CHG */
bogdanm	87:6213f644d804	4430	/* Description: Channel group configuration. */
bogdanm	87:6213f644d804	4431
bogdanm	87:6213f644d804	4432	/* Bit 31 : Include CH31 in channel group. */
bogdanm	87:6213f644d804	4433	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
bogdanm	87:6213f644d804	4434	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
bogdanm	87:6213f644d804	4435	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4436	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4437
bogdanm	87:6213f644d804	4438	/* Bit 30 : Include CH30 in channel group. */
bogdanm	87:6213f644d804	4439	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
bogdanm	87:6213f644d804	4440	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
bogdanm	87:6213f644d804	4441	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4442	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4443
bogdanm	87:6213f644d804	4444	/* Bit 29 : Include CH29 in channel group. */
bogdanm	87:6213f644d804	4445	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
bogdanm	87:6213f644d804	4446	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
bogdanm	87:6213f644d804	4447	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4448	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4449
bogdanm	87:6213f644d804	4450	/* Bit 28 : Include CH28 in channel group. */
bogdanm	87:6213f644d804	4451	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
bogdanm	87:6213f644d804	4452	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
bogdanm	87:6213f644d804	4453	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4454	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4455
bogdanm	87:6213f644d804	4456	/* Bit 27 : Include CH27 in channel group. */
bogdanm	87:6213f644d804	4457	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
bogdanm	87:6213f644d804	4458	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
bogdanm	87:6213f644d804	4459	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4460	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4461
bogdanm	87:6213f644d804	4462	/* Bit 26 : Include CH26 in channel group. */
bogdanm	87:6213f644d804	4463	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
bogdanm	87:6213f644d804	4464	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
bogdanm	87:6213f644d804	4465	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4466	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4467
bogdanm	87:6213f644d804	4468	/* Bit 25 : Include CH25 in channel group. */
bogdanm	87:6213f644d804	4469	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
bogdanm	87:6213f644d804	4470	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
bogdanm	87:6213f644d804	4471	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4472	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4473
bogdanm	87:6213f644d804	4474	/* Bit 24 : Include CH24 in channel group. */
bogdanm	87:6213f644d804	4475	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
bogdanm	87:6213f644d804	4476	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
bogdanm	87:6213f644d804	4477	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4478	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4479
bogdanm	87:6213f644d804	4480	/* Bit 23 : Include CH23 in channel group. */
bogdanm	87:6213f644d804	4481	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
bogdanm	87:6213f644d804	4482	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
bogdanm	87:6213f644d804	4483	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4484	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4485
bogdanm	87:6213f644d804	4486	/* Bit 22 : Include CH22 in channel group. */
bogdanm	87:6213f644d804	4487	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
bogdanm	87:6213f644d804	4488	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
bogdanm	87:6213f644d804	4489	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4490	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4491
bogdanm	87:6213f644d804	4492	/* Bit 21 : Include CH21 in channel group. */
bogdanm	87:6213f644d804	4493	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
bogdanm	87:6213f644d804	4494	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
bogdanm	87:6213f644d804	4495	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4496	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4497
bogdanm	87:6213f644d804	4498	/* Bit 20 : Include CH20 in channel group. */
bogdanm	87:6213f644d804	4499	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
bogdanm	87:6213f644d804	4500	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
bogdanm	87:6213f644d804	4501	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4502	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4503
bogdanm	87:6213f644d804	4504	/* Bit 15 : Include CH15 in channel group. */
bogdanm	87:6213f644d804	4505	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
bogdanm	87:6213f644d804	4506	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
bogdanm	87:6213f644d804	4507	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4508	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4509
bogdanm	87:6213f644d804	4510	/* Bit 14 : Include CH14 in channel group. */
bogdanm	87:6213f644d804	4511	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
bogdanm	87:6213f644d804	4512	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
bogdanm	87:6213f644d804	4513	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4514	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4515
bogdanm	87:6213f644d804	4516	/* Bit 13 : Include CH13 in channel group. */
bogdanm	87:6213f644d804	4517	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
bogdanm	87:6213f644d804	4518	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
bogdanm	87:6213f644d804	4519	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4520	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4521
bogdanm	87:6213f644d804	4522	/* Bit 12 : Include CH12 in channel group. */
bogdanm	87:6213f644d804	4523	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
bogdanm	87:6213f644d804	4524	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
bogdanm	87:6213f644d804	4525	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4526	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4527
bogdanm	87:6213f644d804	4528	/* Bit 11 : Include CH11 in channel group. */
bogdanm	87:6213f644d804	4529	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
bogdanm	87:6213f644d804	4530	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
bogdanm	87:6213f644d804	4531	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4532	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4533
bogdanm	87:6213f644d804	4534	/* Bit 10 : Include CH10 in channel group. */
bogdanm	87:6213f644d804	4535	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
bogdanm	87:6213f644d804	4536	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
bogdanm	87:6213f644d804	4537	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4538	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4539
bogdanm	87:6213f644d804	4540	/* Bit 9 : Include CH9 in channel group. */
bogdanm	87:6213f644d804	4541	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
bogdanm	87:6213f644d804	4542	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
bogdanm	87:6213f644d804	4543	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4544	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4545
bogdanm	87:6213f644d804	4546	/* Bit 8 : Include CH8 in channel group. */
bogdanm	87:6213f644d804	4547	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
bogdanm	87:6213f644d804	4548	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
bogdanm	87:6213f644d804	4549	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4550	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4551
bogdanm	87:6213f644d804	4552	/* Bit 7 : Include CH7 in channel group. */
bogdanm	87:6213f644d804	4553	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
bogdanm	87:6213f644d804	4554	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
bogdanm	87:6213f644d804	4555	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4556	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4557
bogdanm	87:6213f644d804	4558	/* Bit 6 : Include CH6 in channel group. */
bogdanm	87:6213f644d804	4559	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
bogdanm	87:6213f644d804	4560	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
bogdanm	87:6213f644d804	4561	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4562	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4563
bogdanm	87:6213f644d804	4564	/* Bit 5 : Include CH5 in channel group. */
bogdanm	87:6213f644d804	4565	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
bogdanm	87:6213f644d804	4566	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
bogdanm	87:6213f644d804	4567	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4568	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4569
bogdanm	87:6213f644d804	4570	/* Bit 4 : Include CH4 in channel group. */
bogdanm	87:6213f644d804	4571	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
bogdanm	87:6213f644d804	4572	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
bogdanm	87:6213f644d804	4573	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4574	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4575
bogdanm	87:6213f644d804	4576	/* Bit 3 : Include CH3 in channel group. */
bogdanm	87:6213f644d804	4577	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
bogdanm	87:6213f644d804	4578	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
bogdanm	87:6213f644d804	4579	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4580	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4581
bogdanm	87:6213f644d804	4582	/* Bit 2 : Include CH2 in channel group. */
bogdanm	87:6213f644d804	4583	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
bogdanm	87:6213f644d804	4584	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
bogdanm	87:6213f644d804	4585	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4586	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4587
bogdanm	87:6213f644d804	4588	/* Bit 1 : Include CH1 in channel group. */
bogdanm	87:6213f644d804	4589	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
bogdanm	87:6213f644d804	4590	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
bogdanm	87:6213f644d804	4591	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4592	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4593
bogdanm	87:6213f644d804	4594	/* Bit 0 : Include CH0 in channel group. */
bogdanm	87:6213f644d804	4595	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
bogdanm	87:6213f644d804	4596	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
bogdanm	87:6213f644d804	4597	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
bogdanm	87:6213f644d804	4598	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
bogdanm	87:6213f644d804	4599
bogdanm	87:6213f644d804	4600
bogdanm	87:6213f644d804	4601	/* Peripheral: QDEC */
bogdanm	87:6213f644d804	4602	/* Description: Rotary decoder. */
bogdanm	87:6213f644d804	4603
bogdanm	87:6213f644d804	4604	/* Register: QDEC_SHORTS */
Kojto	97:433970e64889	4605	/* Description: Shortcuts for the QDEC. */
Kojto	97:433970e64889	4606
Kojto	97:433970e64889	4607	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
bogdanm	87:6213f644d804	4608	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
bogdanm	87:6213f644d804	4609	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
bogdanm	87:6213f644d804	4610	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4611	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4612
Kojto	97:433970e64889	4613	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
bogdanm	87:6213f644d804	4614	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
bogdanm	87:6213f644d804	4615	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
bogdanm	87:6213f644d804	4616	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4617	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4618
bogdanm	87:6213f644d804	4619	/* Register: QDEC_INTENSET */
bogdanm	87:6213f644d804	4620	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	4621
bogdanm	87:6213f644d804	4622	/* Bit 2 : Enable interrupt on ACCOF event. */
bogdanm	87:6213f644d804	4623	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
bogdanm	87:6213f644d804	4624	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
bogdanm	87:6213f644d804	4625	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4626	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4627	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4628
bogdanm	87:6213f644d804	4629	/* Bit 1 : Enable interrupt on REPORTRDY event. */
bogdanm	87:6213f644d804	4630	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
bogdanm	87:6213f644d804	4631	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
bogdanm	87:6213f644d804	4632	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4633	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4634	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4635
bogdanm	87:6213f644d804	4636	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
bogdanm	87:6213f644d804	4637	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
bogdanm	87:6213f644d804	4638	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
bogdanm	87:6213f644d804	4639	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4640	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4641	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4642
bogdanm	87:6213f644d804	4643	/* Register: QDEC_INTENCLR */
bogdanm	87:6213f644d804	4644	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	4645
bogdanm	87:6213f644d804	4646	/* Bit 2 : Disable interrupt on ACCOF event. */
bogdanm	87:6213f644d804	4647	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
bogdanm	87:6213f644d804	4648	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
bogdanm	87:6213f644d804	4649	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4650	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4651	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4652
bogdanm	87:6213f644d804	4653	/* Bit 1 : Disable interrupt on REPORTRDY event. */
bogdanm	87:6213f644d804	4654	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
bogdanm	87:6213f644d804	4655	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
bogdanm	87:6213f644d804	4656	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4657	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4658	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4659
bogdanm	87:6213f644d804	4660	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
bogdanm	87:6213f644d804	4661	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
bogdanm	87:6213f644d804	4662	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
bogdanm	87:6213f644d804	4663	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4664	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4665	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4666
bogdanm	87:6213f644d804	4667	/* Register: QDEC_ENABLE */
bogdanm	87:6213f644d804	4668	/* Description: Enable the QDEC. */
bogdanm	87:6213f644d804	4669
bogdanm	87:6213f644d804	4670	/* Bit 0 : Enable or disable QDEC. */
bogdanm	87:6213f644d804	4671	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	4672	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	4673	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
bogdanm	87:6213f644d804	4674	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
bogdanm	87:6213f644d804	4675
bogdanm	87:6213f644d804	4676	/* Register: QDEC_LEDPOL */
bogdanm	87:6213f644d804	4677	/* Description: LED output pin polarity. */
bogdanm	87:6213f644d804	4678
bogdanm	87:6213f644d804	4679	/* Bit 0 : LED output pin polarity. */
bogdanm	87:6213f644d804	4680	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
bogdanm	87:6213f644d804	4681	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
bogdanm	87:6213f644d804	4682	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
bogdanm	87:6213f644d804	4683	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
bogdanm	87:6213f644d804	4684
bogdanm	87:6213f644d804	4685	/* Register: QDEC_SAMPLEPER */
bogdanm	87:6213f644d804	4686	/* Description: Sample period. */
bogdanm	87:6213f644d804	4687
bogdanm	87:6213f644d804	4688	/* Bits 2..0 : Sample period. */
bogdanm	87:6213f644d804	4689	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
bogdanm	87:6213f644d804	4690	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
bogdanm	87:6213f644d804	4691	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
bogdanm	87:6213f644d804	4692	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
bogdanm	87:6213f644d804	4693	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
bogdanm	87:6213f644d804	4694	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
bogdanm	87:6213f644d804	4695	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
bogdanm	87:6213f644d804	4696	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
bogdanm	87:6213f644d804	4697	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
bogdanm	87:6213f644d804	4698	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
bogdanm	87:6213f644d804	4699
bogdanm	87:6213f644d804	4700	/* Register: QDEC_SAMPLE */
bogdanm	87:6213f644d804	4701	/* Description: Motion sample value. */
bogdanm	87:6213f644d804	4702
bogdanm	87:6213f644d804	4703	/* Bits 31..0 : Last sample taken in compliment to 2. */
bogdanm	87:6213f644d804	4704	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
bogdanm	87:6213f644d804	4705	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
bogdanm	87:6213f644d804	4706
bogdanm	87:6213f644d804	4707	/* Register: QDEC_REPORTPER */
bogdanm	87:6213f644d804	4708	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
bogdanm	87:6213f644d804	4709
bogdanm	87:6213f644d804	4710	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
bogdanm	87:6213f644d804	4711	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
bogdanm	87:6213f644d804	4712	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
bogdanm	87:6213f644d804	4713	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
bogdanm	87:6213f644d804	4714	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
bogdanm	87:6213f644d804	4715	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
bogdanm	87:6213f644d804	4716	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
bogdanm	87:6213f644d804	4717	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
bogdanm	87:6213f644d804	4718	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
bogdanm	87:6213f644d804	4719	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
bogdanm	87:6213f644d804	4720	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
bogdanm	87:6213f644d804	4721
bogdanm	87:6213f644d804	4722	/* Register: QDEC_DBFEN */
bogdanm	87:6213f644d804	4723	/* Description: Enable debouncer input filters. */
bogdanm	87:6213f644d804	4724
bogdanm	87:6213f644d804	4725	/* Bit 0 : Enable debounce input filters. */
bogdanm	87:6213f644d804	4726	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
bogdanm	87:6213f644d804	4727	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
bogdanm	87:6213f644d804	4728	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
bogdanm	87:6213f644d804	4729	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
bogdanm	87:6213f644d804	4730
bogdanm	87:6213f644d804	4731	/* Register: QDEC_LEDPRE */
bogdanm	87:6213f644d804	4732	/* Description: Time LED is switched ON before the sample. */
bogdanm	87:6213f644d804	4733
Kojto	97:433970e64889	4734	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
bogdanm	87:6213f644d804	4735	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
Kojto	97:433970e64889	4736	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
bogdanm	87:6213f644d804	4737
bogdanm	87:6213f644d804	4738	/* Register: QDEC_ACCDBL */
bogdanm	87:6213f644d804	4739	/* Description: Accumulated double (error) transitions register. */
bogdanm	87:6213f644d804	4740
bogdanm	87:6213f644d804	4741	/* Bits 3..0 : Accumulated double (error) transitions. */
bogdanm	87:6213f644d804	4742	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
bogdanm	87:6213f644d804	4743	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
bogdanm	87:6213f644d804	4744
bogdanm	87:6213f644d804	4745	/* Register: QDEC_ACCDBLREAD */
bogdanm	87:6213f644d804	4746	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
bogdanm	87:6213f644d804	4747
bogdanm	87:6213f644d804	4748	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
bogdanm	87:6213f644d804	4749	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
bogdanm	87:6213f644d804	4750	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
bogdanm	87:6213f644d804	4751
bogdanm	87:6213f644d804	4752	/* Register: QDEC_POWER */
bogdanm	87:6213f644d804	4753	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	4754
bogdanm	87:6213f644d804	4755	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	4756	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	4757	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	4758	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	4759	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	4760
bogdanm	87:6213f644d804	4761
bogdanm	87:6213f644d804	4762	/* Peripheral: RADIO */
bogdanm	87:6213f644d804	4763	/* Description: The radio. */
bogdanm	87:6213f644d804	4764
bogdanm	87:6213f644d804	4765	/* Register: RADIO_SHORTS */
Kojto	97:433970e64889	4766	/* Description: Shortcuts for the radio. */
bogdanm	87:6213f644d804	4767
bogdanm	87:6213f644d804	4768	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
bogdanm	87:6213f644d804	4769	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
bogdanm	87:6213f644d804	4770	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
bogdanm	87:6213f644d804	4771	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4772	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4773
bogdanm	87:6213f644d804	4774	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
bogdanm	87:6213f644d804	4775	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
bogdanm	87:6213f644d804	4776	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
bogdanm	87:6213f644d804	4777	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4778	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4779
bogdanm	87:6213f644d804	4780	/* Bit 5 : Shortcut between END event and START task. */
bogdanm	87:6213f644d804	4781	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
bogdanm	87:6213f644d804	4782	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
bogdanm	87:6213f644d804	4783	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4784	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4785
bogdanm	87:6213f644d804	4786	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
bogdanm	87:6213f644d804	4787	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
bogdanm	87:6213f644d804	4788	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
bogdanm	87:6213f644d804	4789	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4790	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4791
bogdanm	87:6213f644d804	4792	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
bogdanm	87:6213f644d804	4793	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
bogdanm	87:6213f644d804	4794	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
bogdanm	87:6213f644d804	4795	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4796	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4797
bogdanm	87:6213f644d804	4798	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
bogdanm	87:6213f644d804	4799	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
bogdanm	87:6213f644d804	4800	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
bogdanm	87:6213f644d804	4801	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4802	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4803
bogdanm	87:6213f644d804	4804	/* Bit 1 : Shortcut between END event and DISABLE task. */
bogdanm	87:6213f644d804	4805	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
bogdanm	87:6213f644d804	4806	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
bogdanm	87:6213f644d804	4807	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4808	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4809
bogdanm	87:6213f644d804	4810	/* Bit 0 : Shortcut between READY event and START task. */
bogdanm	87:6213f644d804	4811	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
bogdanm	87:6213f644d804	4812	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
bogdanm	87:6213f644d804	4813	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	4814	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	4815
bogdanm	87:6213f644d804	4816	/* Register: RADIO_INTENSET */
bogdanm	87:6213f644d804	4817	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	4818
bogdanm	87:6213f644d804	4819	/* Bit 10 : Enable interrupt on BCMATCH event. */
bogdanm	87:6213f644d804	4820	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
bogdanm	87:6213f644d804	4821	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
bogdanm	87:6213f644d804	4822	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4823	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4824	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4825
bogdanm	87:6213f644d804	4826	/* Bit 7 : Enable interrupt on RSSIEND event. */
bogdanm	87:6213f644d804	4827	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
bogdanm	87:6213f644d804	4828	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
bogdanm	87:6213f644d804	4829	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4830	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4831	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4832
bogdanm	87:6213f644d804	4833	/* Bit 6 : Enable interrupt on DEVMISS event. */
bogdanm	87:6213f644d804	4834	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
bogdanm	87:6213f644d804	4835	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
bogdanm	87:6213f644d804	4836	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4837	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4838	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4839
bogdanm	87:6213f644d804	4840	/* Bit 5 : Enable interrupt on DEVMATCH event. */
bogdanm	87:6213f644d804	4841	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
bogdanm	87:6213f644d804	4842	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
bogdanm	87:6213f644d804	4843	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4844	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4845	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4846
bogdanm	87:6213f644d804	4847	/* Bit 4 : Enable interrupt on DISABLED event. */
bogdanm	87:6213f644d804	4848	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
bogdanm	87:6213f644d804	4849	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
bogdanm	87:6213f644d804	4850	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4851	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4852	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4853
bogdanm	87:6213f644d804	4854	/* Bit 3 : Enable interrupt on END event. */
bogdanm	87:6213f644d804	4855	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
bogdanm	87:6213f644d804	4856	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	87:6213f644d804	4857	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4858	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4859	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4860
bogdanm	87:6213f644d804	4861	/* Bit 2 : Enable interrupt on PAYLOAD event. */
bogdanm	87:6213f644d804	4862	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
bogdanm	87:6213f644d804	4863	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
bogdanm	87:6213f644d804	4864	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4865	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4866	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4867
bogdanm	87:6213f644d804	4868	/* Bit 1 : Enable interrupt on ADDRESS event. */
bogdanm	87:6213f644d804	4869	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
bogdanm	87:6213f644d804	4870	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	87:6213f644d804	4871	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4872	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4873	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4874
bogdanm	87:6213f644d804	4875	/* Bit 0 : Enable interrupt on READY event. */
bogdanm	87:6213f644d804	4876	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	87:6213f644d804	4877	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	87:6213f644d804	4878	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4879	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4880	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	4881
bogdanm	87:6213f644d804	4882	/* Register: RADIO_INTENCLR */
bogdanm	87:6213f644d804	4883	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	4884
bogdanm	87:6213f644d804	4885	/* Bit 10 : Disable interrupt on BCMATCH event. */
bogdanm	87:6213f644d804	4886	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
bogdanm	87:6213f644d804	4887	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
bogdanm	87:6213f644d804	4888	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4889	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4890	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4891
bogdanm	87:6213f644d804	4892	/* Bit 7 : Disable interrupt on RSSIEND event. */
bogdanm	87:6213f644d804	4893	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
bogdanm	87:6213f644d804	4894	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
bogdanm	87:6213f644d804	4895	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4896	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4897	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4898
bogdanm	87:6213f644d804	4899	/* Bit 6 : Disable interrupt on DEVMISS event. */
bogdanm	87:6213f644d804	4900	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
bogdanm	87:6213f644d804	4901	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
bogdanm	87:6213f644d804	4902	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4903	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4904	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4905
bogdanm	87:6213f644d804	4906	/* Bit 5 : Disable interrupt on DEVMATCH event. */
bogdanm	87:6213f644d804	4907	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
bogdanm	87:6213f644d804	4908	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
bogdanm	87:6213f644d804	4909	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4910	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4911	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4912
bogdanm	87:6213f644d804	4913	/* Bit 4 : Disable interrupt on DISABLED event. */
bogdanm	87:6213f644d804	4914	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
bogdanm	87:6213f644d804	4915	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
bogdanm	87:6213f644d804	4916	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4917	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4918	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4919
bogdanm	87:6213f644d804	4920	/* Bit 3 : Disable interrupt on END event. */
bogdanm	87:6213f644d804	4921	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
bogdanm	87:6213f644d804	4922	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	87:6213f644d804	4923	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4924	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4925	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4926
bogdanm	87:6213f644d804	4927	/* Bit 2 : Disable interrupt on PAYLOAD event. */
bogdanm	87:6213f644d804	4928	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
bogdanm	87:6213f644d804	4929	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
bogdanm	87:6213f644d804	4930	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4931	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4932	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4933
bogdanm	87:6213f644d804	4934	/* Bit 1 : Disable interrupt on ADDRESS event. */
bogdanm	87:6213f644d804	4935	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
bogdanm	87:6213f644d804	4936	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	87:6213f644d804	4937	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4938	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4939	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4940
bogdanm	87:6213f644d804	4941	/* Bit 0 : Disable interrupt on READY event. */
bogdanm	87:6213f644d804	4942	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
bogdanm	87:6213f644d804	4943	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	87:6213f644d804	4944	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	4945	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	4946	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	4947
bogdanm	87:6213f644d804	4948	/* Register: RADIO_CRCSTATUS */
bogdanm	87:6213f644d804	4949	/* Description: CRC status of received packet. */
bogdanm	87:6213f644d804	4950
bogdanm	87:6213f644d804	4951	/* Bit 0 : CRC status of received packet. */
bogdanm	87:6213f644d804	4952	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
bogdanm	87:6213f644d804	4953	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
bogdanm	87:6213f644d804	4954	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
bogdanm	87:6213f644d804	4955	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
bogdanm	87:6213f644d804	4956
bogdanm	87:6213f644d804	4957	/* Register: RADIO_RXMATCH */
bogdanm	87:6213f644d804	4958	/* Description: Received address. */
bogdanm	87:6213f644d804	4959
bogdanm	87:6213f644d804	4960	/* Bits 2..0 : Logical address in which previous packet was received. */
bogdanm	87:6213f644d804	4961	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
bogdanm	87:6213f644d804	4962	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
bogdanm	87:6213f644d804	4963
bogdanm	87:6213f644d804	4964	/* Register: RADIO_RXCRC */
bogdanm	87:6213f644d804	4965	/* Description: Received CRC. */
bogdanm	87:6213f644d804	4966
bogdanm	87:6213f644d804	4967	/* Bits 23..0 : CRC field of previously received packet. */
bogdanm	87:6213f644d804	4968	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
bogdanm	87:6213f644d804	4969	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
bogdanm	87:6213f644d804	4970
bogdanm	87:6213f644d804	4971	/* Register: RADIO_DAI */
bogdanm	87:6213f644d804	4972	/* Description: Device address match index. */
bogdanm	87:6213f644d804	4973
Kojto	97:433970e64889	4974	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
bogdanm	87:6213f644d804	4975	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
bogdanm	87:6213f644d804	4976	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
bogdanm	87:6213f644d804	4977
bogdanm	87:6213f644d804	4978	/* Register: RADIO_FREQUENCY */
bogdanm	87:6213f644d804	4979	/* Description: Frequency. */
bogdanm	87:6213f644d804	4980
bogdanm	87:6213f644d804	4981	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
bogdanm	87:6213f644d804	4982	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	87:6213f644d804	4983	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	87:6213f644d804	4984
bogdanm	87:6213f644d804	4985	/* Register: RADIO_TXPOWER */
bogdanm	87:6213f644d804	4986	/* Description: Output power. */
bogdanm	87:6213f644d804	4987
bogdanm	87:6213f644d804	4988	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
bogdanm	87:6213f644d804	4989	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
bogdanm	87:6213f644d804	4990	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
Kojto	122:f9eeca106725	4991	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
bogdanm	87:6213f644d804	4992	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
Kojto	122:f9eeca106725	4993	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
Kojto	122:f9eeca106725	4994	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
Kojto	122:f9eeca106725	4995	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
Kojto	122:f9eeca106725	4996	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
bogdanm	87:6213f644d804	4997	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
Kojto	122:f9eeca106725	4998	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
bogdanm	87:6213f644d804	4999
bogdanm	87:6213f644d804	5000	/* Register: RADIO_MODE */
bogdanm	87:6213f644d804	5001	/* Description: Data rate and modulation. */
bogdanm	87:6213f644d804	5002
bogdanm	87:6213f644d804	5003	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
bogdanm	87:6213f644d804	5004	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	87:6213f644d804	5005	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	87:6213f644d804	5006	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
bogdanm	87:6213f644d804	5007	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
bogdanm	87:6213f644d804	5008	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
bogdanm	87:6213f644d804	5009	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
bogdanm	87:6213f644d804	5010
bogdanm	87:6213f644d804	5011	/* Register: RADIO_PCNF0 */
bogdanm	87:6213f644d804	5012	/* Description: Packet configuration 0. */
bogdanm	87:6213f644d804	5013
bogdanm	87:6213f644d804	5014	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
bogdanm	87:6213f644d804	5015	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
bogdanm	87:6213f644d804	5016	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
bogdanm	87:6213f644d804	5017
bogdanm	87:6213f644d804	5018	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
bogdanm	87:6213f644d804	5019	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
bogdanm	87:6213f644d804	5020	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
bogdanm	87:6213f644d804	5021
bogdanm	87:6213f644d804	5022	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
bogdanm	87:6213f644d804	5023	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
bogdanm	87:6213f644d804	5024	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
bogdanm	87:6213f644d804	5025
bogdanm	87:6213f644d804	5026	/* Register: RADIO_PCNF1 */
bogdanm	87:6213f644d804	5027	/* Description: Packet configuration 1. */
bogdanm	87:6213f644d804	5028
bogdanm	87:6213f644d804	5029	/* Bit 25 : Packet whitening enable. */
bogdanm	87:6213f644d804	5030	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
bogdanm	87:6213f644d804	5031	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
bogdanm	87:6213f644d804	5032	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
bogdanm	87:6213f644d804	5033	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
bogdanm	87:6213f644d804	5034
bogdanm	87:6213f644d804	5035	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
bogdanm	87:6213f644d804	5036	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
bogdanm	87:6213f644d804	5037	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
bogdanm	87:6213f644d804	5038	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
bogdanm	87:6213f644d804	5039	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
bogdanm	87:6213f644d804	5040
bogdanm	87:6213f644d804	5041	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
bogdanm	87:6213f644d804	5042	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
bogdanm	87:6213f644d804	5043	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
bogdanm	87:6213f644d804	5044
bogdanm	87:6213f644d804	5045	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
bogdanm	87:6213f644d804	5046	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
bogdanm	87:6213f644d804	5047	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
bogdanm	87:6213f644d804	5048
bogdanm	87:6213f644d804	5049	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
bogdanm	87:6213f644d804	5050	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
bogdanm	87:6213f644d804	5051	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
bogdanm	87:6213f644d804	5052
bogdanm	87:6213f644d804	5053	/* Register: RADIO_PREFIX0 */
bogdanm	87:6213f644d804	5054	/* Description: Prefixes bytes for logical addresses 0 to 3. */
bogdanm	87:6213f644d804	5055
bogdanm	87:6213f644d804	5056	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
bogdanm	87:6213f644d804	5057	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
bogdanm	87:6213f644d804	5058	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
bogdanm	87:6213f644d804	5059
bogdanm	87:6213f644d804	5060	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
bogdanm	87:6213f644d804	5061	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
bogdanm	87:6213f644d804	5062	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
bogdanm	87:6213f644d804	5063
bogdanm	87:6213f644d804	5064	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
bogdanm	87:6213f644d804	5065	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
bogdanm	87:6213f644d804	5066	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
bogdanm	87:6213f644d804	5067
bogdanm	87:6213f644d804	5068	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
bogdanm	87:6213f644d804	5069	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
bogdanm	87:6213f644d804	5070	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
bogdanm	87:6213f644d804	5071
bogdanm	87:6213f644d804	5072	/* Register: RADIO_PREFIX1 */
bogdanm	87:6213f644d804	5073	/* Description: Prefixes bytes for logical addresses 4 to 7. */
bogdanm	87:6213f644d804	5074
bogdanm	87:6213f644d804	5075	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
bogdanm	87:6213f644d804	5076	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
bogdanm	87:6213f644d804	5077	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
bogdanm	87:6213f644d804	5078
bogdanm	87:6213f644d804	5079	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
bogdanm	87:6213f644d804	5080	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
bogdanm	87:6213f644d804	5081	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
bogdanm	87:6213f644d804	5082
bogdanm	87:6213f644d804	5083	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
bogdanm	87:6213f644d804	5084	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
bogdanm	87:6213f644d804	5085	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
bogdanm	87:6213f644d804	5086
bogdanm	87:6213f644d804	5087	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
bogdanm	87:6213f644d804	5088	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
bogdanm	87:6213f644d804	5089	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
bogdanm	87:6213f644d804	5090
bogdanm	87:6213f644d804	5091	/* Register: RADIO_TXADDRESS */
bogdanm	87:6213f644d804	5092	/* Description: Transmit address select. */
bogdanm	87:6213f644d804	5093
bogdanm	87:6213f644d804	5094	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
bogdanm	87:6213f644d804	5095	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
bogdanm	87:6213f644d804	5096	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
bogdanm	87:6213f644d804	5097
bogdanm	87:6213f644d804	5098	/* Register: RADIO_RXADDRESSES */
bogdanm	87:6213f644d804	5099	/* Description: Receive address select. */
bogdanm	87:6213f644d804	5100
bogdanm	87:6213f644d804	5101	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
bogdanm	87:6213f644d804	5102	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
bogdanm	87:6213f644d804	5103	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
bogdanm	87:6213f644d804	5104	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
bogdanm	87:6213f644d804	5105	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
bogdanm	87:6213f644d804	5106
bogdanm	87:6213f644d804	5107	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
bogdanm	87:6213f644d804	5108	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
bogdanm	87:6213f644d804	5109	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
bogdanm	87:6213f644d804	5110	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
bogdanm	87:6213f644d804	5111	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
bogdanm	87:6213f644d804	5112
bogdanm	87:6213f644d804	5113	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
bogdanm	87:6213f644d804	5114	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
bogdanm	87:6213f644d804	5115	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
bogdanm	87:6213f644d804	5116	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
bogdanm	87:6213f644d804	5117	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
bogdanm	87:6213f644d804	5118
bogdanm	87:6213f644d804	5119	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
bogdanm	87:6213f644d804	5120	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
bogdanm	87:6213f644d804	5121	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
bogdanm	87:6213f644d804	5122	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
bogdanm	87:6213f644d804	5123	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
bogdanm	87:6213f644d804	5124
bogdanm	87:6213f644d804	5125	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
bogdanm	87:6213f644d804	5126	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
bogdanm	87:6213f644d804	5127	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
bogdanm	87:6213f644d804	5128	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
bogdanm	87:6213f644d804	5129	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
bogdanm	87:6213f644d804	5130
bogdanm	87:6213f644d804	5131	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
bogdanm	87:6213f644d804	5132	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
bogdanm	87:6213f644d804	5133	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
bogdanm	87:6213f644d804	5134	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
bogdanm	87:6213f644d804	5135	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
bogdanm	87:6213f644d804	5136
bogdanm	87:6213f644d804	5137	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
bogdanm	87:6213f644d804	5138	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
bogdanm	87:6213f644d804	5139	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
bogdanm	87:6213f644d804	5140	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
bogdanm	87:6213f644d804	5141	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
bogdanm	87:6213f644d804	5142
bogdanm	87:6213f644d804	5143	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
bogdanm	87:6213f644d804	5144	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
bogdanm	87:6213f644d804	5145	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
bogdanm	87:6213f644d804	5146	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
bogdanm	87:6213f644d804	5147	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
bogdanm	87:6213f644d804	5148
bogdanm	87:6213f644d804	5149	/* Register: RADIO_CRCCNF */
bogdanm	87:6213f644d804	5150	/* Description: CRC configuration. */
bogdanm	87:6213f644d804	5151
bogdanm	87:6213f644d804	5152	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
Kojto	97:433970e64889	5153	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
Kojto	97:433970e64889	5154	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
Kojto	97:433970e64889	5155	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
Kojto	97:433970e64889	5156	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
bogdanm	87:6213f644d804	5157
bogdanm	87:6213f644d804	5158	/* Bits 1..0 : CRC length. Decision point: START task. */
bogdanm	87:6213f644d804	5159	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
bogdanm	87:6213f644d804	5160	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
bogdanm	87:6213f644d804	5161	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
bogdanm	87:6213f644d804	5162	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
bogdanm	87:6213f644d804	5163	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
bogdanm	87:6213f644d804	5164	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
bogdanm	87:6213f644d804	5165
bogdanm	87:6213f644d804	5166	/* Register: RADIO_CRCPOLY */
bogdanm	87:6213f644d804	5167	/* Description: CRC polynomial. */
bogdanm	87:6213f644d804	5168
Kojto	97:433970e64889	5169	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
Kojto	97:433970e64889	5170	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
Kojto	97:433970e64889	5171	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
bogdanm	87:6213f644d804	5172
bogdanm	87:6213f644d804	5173	/* Register: RADIO_CRCINIT */
bogdanm	87:6213f644d804	5174	/* Description: CRC initial value. */
bogdanm	87:6213f644d804	5175
bogdanm	87:6213f644d804	5176	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
bogdanm	87:6213f644d804	5177	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
bogdanm	87:6213f644d804	5178	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
bogdanm	87:6213f644d804	5179
bogdanm	87:6213f644d804	5180	/* Register: RADIO_TEST */
bogdanm	87:6213f644d804	5181	/* Description: Test features enable register. */
bogdanm	87:6213f644d804	5182
bogdanm	87:6213f644d804	5183	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
Kojto	97:433970e64889	5184	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
Kojto	97:433970e64889	5185	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
Kojto	97:433970e64889	5186	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
Kojto	97:433970e64889	5187	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
bogdanm	87:6213f644d804	5188
bogdanm	87:6213f644d804	5189	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
Kojto	97:433970e64889	5190	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
Kojto	97:433970e64889	5191	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
Kojto	97:433970e64889	5192	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
Kojto	97:433970e64889	5193	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
bogdanm	87:6213f644d804	5194
bogdanm	87:6213f644d804	5195	/* Register: RADIO_TIFS */
bogdanm	87:6213f644d804	5196	/* Description: Inter Frame Spacing in microseconds. */
bogdanm	87:6213f644d804	5197
bogdanm	87:6213f644d804	5198	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
bogdanm	87:6213f644d804	5199	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
bogdanm	87:6213f644d804	5200	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
bogdanm	87:6213f644d804	5201
bogdanm	87:6213f644d804	5202	/* Register: RADIO_RSSISAMPLE */
bogdanm	87:6213f644d804	5203	/* Description: RSSI sample. */
bogdanm	87:6213f644d804	5204
bogdanm	87:6213f644d804	5205	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
bogdanm	87:6213f644d804	5206	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
bogdanm	87:6213f644d804	5207	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
bogdanm	87:6213f644d804	5208
bogdanm	87:6213f644d804	5209	/* Register: RADIO_STATE */
bogdanm	87:6213f644d804	5210	/* Description: Current radio state. */
bogdanm	87:6213f644d804	5211
bogdanm	87:6213f644d804	5212	/* Bits 3..0 : Current radio state. */
bogdanm	87:6213f644d804	5213	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
bogdanm	87:6213f644d804	5214	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
bogdanm	87:6213f644d804	5215	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
bogdanm	87:6213f644d804	5216	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
bogdanm	87:6213f644d804	5217	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
bogdanm	87:6213f644d804	5218	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
bogdanm	87:6213f644d804	5219	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
bogdanm	87:6213f644d804	5220	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
bogdanm	87:6213f644d804	5221	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
bogdanm	87:6213f644d804	5222	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
bogdanm	87:6213f644d804	5223	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
bogdanm	87:6213f644d804	5224
bogdanm	87:6213f644d804	5225	/* Register: RADIO_DATAWHITEIV */
bogdanm	87:6213f644d804	5226	/* Description: Data whitening initial value. */
bogdanm	87:6213f644d804	5227
Kojto	97:433970e64889	5228	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
bogdanm	87:6213f644d804	5229	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
Kojto	97:433970e64889	5230	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
bogdanm	87:6213f644d804	5231
bogdanm	87:6213f644d804	5232	/* Register: RADIO_DAP */
bogdanm	87:6213f644d804	5233	/* Description: Device address prefix. */
bogdanm	87:6213f644d804	5234
bogdanm	87:6213f644d804	5235	/* Bits 15..0 : Device address prefix. */
bogdanm	87:6213f644d804	5236	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
bogdanm	87:6213f644d804	5237	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
bogdanm	87:6213f644d804	5238
bogdanm	87:6213f644d804	5239	/* Register: RADIO_DACNF */
bogdanm	87:6213f644d804	5240	/* Description: Device address match configuration. */
bogdanm	87:6213f644d804	5241
bogdanm	87:6213f644d804	5242	/* Bit 15 : TxAdd for device address 7. */
bogdanm	87:6213f644d804	5243	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
bogdanm	87:6213f644d804	5244	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
bogdanm	87:6213f644d804	5245
bogdanm	87:6213f644d804	5246	/* Bit 14 : TxAdd for device address 6. */
bogdanm	87:6213f644d804	5247	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
bogdanm	87:6213f644d804	5248	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
bogdanm	87:6213f644d804	5249
bogdanm	87:6213f644d804	5250	/* Bit 13 : TxAdd for device address 5. */
bogdanm	87:6213f644d804	5251	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
bogdanm	87:6213f644d804	5252	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
bogdanm	87:6213f644d804	5253
bogdanm	87:6213f644d804	5254	/* Bit 12 : TxAdd for device address 4. */
bogdanm	87:6213f644d804	5255	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
bogdanm	87:6213f644d804	5256	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
bogdanm	87:6213f644d804	5257
bogdanm	87:6213f644d804	5258	/* Bit 11 : TxAdd for device address 3. */
bogdanm	87:6213f644d804	5259	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
bogdanm	87:6213f644d804	5260	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
bogdanm	87:6213f644d804	5261
bogdanm	87:6213f644d804	5262	/* Bit 10 : TxAdd for device address 2. */
bogdanm	87:6213f644d804	5263	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
bogdanm	87:6213f644d804	5264	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
bogdanm	87:6213f644d804	5265
bogdanm	87:6213f644d804	5266	/* Bit 9 : TxAdd for device address 1. */
bogdanm	87:6213f644d804	5267	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
bogdanm	87:6213f644d804	5268	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
bogdanm	87:6213f644d804	5269
bogdanm	87:6213f644d804	5270	/* Bit 8 : TxAdd for device address 0. */
bogdanm	87:6213f644d804	5271	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
bogdanm	87:6213f644d804	5272	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
bogdanm	87:6213f644d804	5273
bogdanm	87:6213f644d804	5274	/* Bit 7 : Enable or disable device address matching using device address 7. */
bogdanm	87:6213f644d804	5275	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
bogdanm	87:6213f644d804	5276	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
bogdanm	87:6213f644d804	5277	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	5278	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	5279
bogdanm	87:6213f644d804	5280	/* Bit 6 : Enable or disable device address matching using device address 6. */
bogdanm	87:6213f644d804	5281	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
bogdanm	87:6213f644d804	5282	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
bogdanm	87:6213f644d804	5283	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	5284	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	5285
bogdanm	87:6213f644d804	5286	/* Bit 5 : Enable or disable device address matching using device address 5. */
bogdanm	87:6213f644d804	5287	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
bogdanm	87:6213f644d804	5288	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
bogdanm	87:6213f644d804	5289	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	5290	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	5291
bogdanm	87:6213f644d804	5292	/* Bit 4 : Enable or disable device address matching using device address 4. */
bogdanm	87:6213f644d804	5293	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
bogdanm	87:6213f644d804	5294	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
bogdanm	87:6213f644d804	5295	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	5296	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	5297
bogdanm	87:6213f644d804	5298	/* Bit 3 : Enable or disable device address matching using device address 3. */
bogdanm	87:6213f644d804	5299	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
bogdanm	87:6213f644d804	5300	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
bogdanm	87:6213f644d804	5301	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	5302	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	5303
bogdanm	87:6213f644d804	5304	/* Bit 2 : Enable or disable device address matching using device address 2. */
bogdanm	87:6213f644d804	5305	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
bogdanm	87:6213f644d804	5306	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
bogdanm	87:6213f644d804	5307	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	5308	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	5309
bogdanm	87:6213f644d804	5310	/* Bit 1 : Enable or disable device address matching using device address 1. */
bogdanm	87:6213f644d804	5311	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
bogdanm	87:6213f644d804	5312	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
bogdanm	87:6213f644d804	5313	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	5314	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	5315
bogdanm	87:6213f644d804	5316	/* Bit 0 : Enable or disable device address matching using device address 0. */
bogdanm	87:6213f644d804	5317	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
bogdanm	87:6213f644d804	5318	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
bogdanm	87:6213f644d804	5319	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
bogdanm	87:6213f644d804	5320	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
bogdanm	87:6213f644d804	5321
bogdanm	87:6213f644d804	5322	/* Register: RADIO_OVERRIDE0 */
bogdanm	87:6213f644d804	5323	/* Description: Trim value override register 0. */
bogdanm	87:6213f644d804	5324
Kojto	97:433970e64889	5325	/* Bits 31..0 : Trim value override 0. */
bogdanm	87:6213f644d804	5326	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
bogdanm	87:6213f644d804	5327	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
bogdanm	87:6213f644d804	5328
bogdanm	87:6213f644d804	5329	/* Register: RADIO_OVERRIDE1 */
bogdanm	87:6213f644d804	5330	/* Description: Trim value override register 1. */
bogdanm	87:6213f644d804	5331
Kojto	97:433970e64889	5332	/* Bits 31..0 : Trim value override 1. */
bogdanm	87:6213f644d804	5333	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
bogdanm	87:6213f644d804	5334	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
bogdanm	87:6213f644d804	5335
bogdanm	87:6213f644d804	5336	/* Register: RADIO_OVERRIDE2 */
bogdanm	87:6213f644d804	5337	/* Description: Trim value override register 2. */
bogdanm	87:6213f644d804	5338
Kojto	97:433970e64889	5339	/* Bits 31..0 : Trim value override 2. */
bogdanm	87:6213f644d804	5340	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
bogdanm	87:6213f644d804	5341	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
bogdanm	87:6213f644d804	5342
bogdanm	87:6213f644d804	5343	/* Register: RADIO_OVERRIDE3 */
bogdanm	87:6213f644d804	5344	/* Description: Trim value override register 3. */
bogdanm	87:6213f644d804	5345
Kojto	97:433970e64889	5346	/* Bits 31..0 : Trim value override 3. */
bogdanm	87:6213f644d804	5347	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
bogdanm	87:6213f644d804	5348	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
bogdanm	87:6213f644d804	5349
bogdanm	87:6213f644d804	5350	/* Register: RADIO_OVERRIDE4 */
bogdanm	87:6213f644d804	5351	/* Description: Trim value override register 4. */
bogdanm	87:6213f644d804	5352
bogdanm	87:6213f644d804	5353	/* Bit 31 : Enable or disable override of default trim values. */
bogdanm	87:6213f644d804	5354	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	5355	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	5356	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
bogdanm	87:6213f644d804	5357	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
bogdanm	87:6213f644d804	5358
Kojto	97:433970e64889	5359	/* Bits 27..0 : Trim value override 4. */
bogdanm	87:6213f644d804	5360	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
bogdanm	87:6213f644d804	5361	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
bogdanm	87:6213f644d804	5362
bogdanm	87:6213f644d804	5363	/* Register: RADIO_POWER */
bogdanm	87:6213f644d804	5364	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	5365
bogdanm	87:6213f644d804	5366	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	5367	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	5368	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	5369	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	5370	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	5371
bogdanm	87:6213f644d804	5372
bogdanm	87:6213f644d804	5373	/* Peripheral: RNG */
bogdanm	87:6213f644d804	5374	/* Description: Random Number Generator. */
bogdanm	87:6213f644d804	5375
bogdanm	87:6213f644d804	5376	/* Register: RNG_SHORTS */
Kojto	97:433970e64889	5377	/* Description: Shortcuts for the RNG. */
Kojto	97:433970e64889	5378
Kojto	97:433970e64889	5379	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
bogdanm	87:6213f644d804	5380	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
bogdanm	87:6213f644d804	5381	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
bogdanm	87:6213f644d804	5382	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	5383	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	5384
bogdanm	87:6213f644d804	5385	/* Register: RNG_INTENSET */
bogdanm	87:6213f644d804	5386	/* Description: Interrupt enable set register */
bogdanm	87:6213f644d804	5387
bogdanm	87:6213f644d804	5388	/* Bit 0 : Enable interrupt on VALRDY event. */
bogdanm	87:6213f644d804	5389	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
bogdanm	87:6213f644d804	5390	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
bogdanm	87:6213f644d804	5391	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5392	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5393	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5394
bogdanm	87:6213f644d804	5395	/* Register: RNG_INTENCLR */
bogdanm	87:6213f644d804	5396	/* Description: Interrupt enable clear register */
bogdanm	87:6213f644d804	5397
bogdanm	87:6213f644d804	5398	/* Bit 0 : Disable interrupt on VALRDY event. */
bogdanm	87:6213f644d804	5399	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
bogdanm	87:6213f644d804	5400	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
bogdanm	87:6213f644d804	5401	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5402	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5403	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5404
bogdanm	87:6213f644d804	5405	/* Register: RNG_CONFIG */
bogdanm	87:6213f644d804	5406	/* Description: Configuration register. */
bogdanm	87:6213f644d804	5407
bogdanm	87:6213f644d804	5408	/* Bit 0 : Digital error correction enable. */
bogdanm	87:6213f644d804	5409	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
bogdanm	87:6213f644d804	5410	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
bogdanm	87:6213f644d804	5411	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
bogdanm	87:6213f644d804	5412	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
bogdanm	87:6213f644d804	5413
bogdanm	87:6213f644d804	5414	/* Register: RNG_VALUE */
bogdanm	87:6213f644d804	5415	/* Description: RNG random number. */
bogdanm	87:6213f644d804	5416
bogdanm	87:6213f644d804	5417	/* Bits 7..0 : Generated random number. */
bogdanm	87:6213f644d804	5418	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
bogdanm	87:6213f644d804	5419	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
bogdanm	87:6213f644d804	5420
bogdanm	87:6213f644d804	5421	/* Register: RNG_POWER */
bogdanm	87:6213f644d804	5422	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	5423
bogdanm	87:6213f644d804	5424	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	5425	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	5426	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	5427	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	5428	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	5429
bogdanm	87:6213f644d804	5430
bogdanm	87:6213f644d804	5431	/* Peripheral: RTC */
bogdanm	87:6213f644d804	5432	/* Description: Real time counter 0. */
bogdanm	87:6213f644d804	5433
bogdanm	87:6213f644d804	5434	/* Register: RTC_INTENSET */
bogdanm	87:6213f644d804	5435	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	5436
bogdanm	87:6213f644d804	5437	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
bogdanm	87:6213f644d804	5438	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	87:6213f644d804	5439	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	87:6213f644d804	5440	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5441	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5442	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5443
bogdanm	87:6213f644d804	5444	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
bogdanm	87:6213f644d804	5445	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	87:6213f644d804	5446	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	87:6213f644d804	5447	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5448	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5449	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5450
bogdanm	87:6213f644d804	5451	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
bogdanm	87:6213f644d804	5452	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	87:6213f644d804	5453	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	87:6213f644d804	5454	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5455	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5456	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5457
bogdanm	87:6213f644d804	5458	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
bogdanm	87:6213f644d804	5459	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	87:6213f644d804	5460	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	87:6213f644d804	5461	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5462	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5463	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5464
bogdanm	87:6213f644d804	5465	/* Bit 1 : Enable interrupt on OVRFLW event. */
bogdanm	87:6213f644d804	5466	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	87:6213f644d804	5467	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	87:6213f644d804	5468	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5469	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5470	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5471
bogdanm	87:6213f644d804	5472	/* Bit 0 : Enable interrupt on TICK event. */
bogdanm	87:6213f644d804	5473	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	87:6213f644d804	5474	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	87:6213f644d804	5475	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5476	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5477	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5478
bogdanm	87:6213f644d804	5479	/* Register: RTC_INTENCLR */
bogdanm	87:6213f644d804	5480	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	5481
bogdanm	87:6213f644d804	5482	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
bogdanm	87:6213f644d804	5483	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	87:6213f644d804	5484	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	87:6213f644d804	5485	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5486	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5487	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5488
bogdanm	87:6213f644d804	5489	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
bogdanm	87:6213f644d804	5490	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	87:6213f644d804	5491	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	87:6213f644d804	5492	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5493	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5494	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5495
bogdanm	87:6213f644d804	5496	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
bogdanm	87:6213f644d804	5497	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	87:6213f644d804	5498	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	87:6213f644d804	5499	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5500	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5501	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5502
bogdanm	87:6213f644d804	5503	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
bogdanm	87:6213f644d804	5504	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	87:6213f644d804	5505	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	87:6213f644d804	5506	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5507	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5508	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5509
bogdanm	87:6213f644d804	5510	/* Bit 1 : Disable interrupt on OVRFLW event. */
bogdanm	87:6213f644d804	5511	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	87:6213f644d804	5512	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	87:6213f644d804	5513	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5514	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5515	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5516
bogdanm	87:6213f644d804	5517	/* Bit 0 : Disable interrupt on TICK event. */
bogdanm	87:6213f644d804	5518	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	87:6213f644d804	5519	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	87:6213f644d804	5520	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5521	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5522	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5523
bogdanm	87:6213f644d804	5524	/* Register: RTC_EVTEN */
bogdanm	87:6213f644d804	5525	/* Description: Configures event enable routing to PPI for each RTC event. */
bogdanm	87:6213f644d804	5526
bogdanm	87:6213f644d804	5527	/* Bit 19 : COMPARE[3] event enable. */
bogdanm	87:6213f644d804	5528	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	87:6213f644d804	5529	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	87:6213f644d804	5530	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5531	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5532
bogdanm	87:6213f644d804	5533	/* Bit 18 : COMPARE[2] event enable. */
bogdanm	87:6213f644d804	5534	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	87:6213f644d804	5535	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	87:6213f644d804	5536	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5537	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5538
bogdanm	87:6213f644d804	5539	/* Bit 17 : COMPARE[1] event enable. */
bogdanm	87:6213f644d804	5540	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	87:6213f644d804	5541	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	87:6213f644d804	5542	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5543	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5544
bogdanm	87:6213f644d804	5545	/* Bit 16 : COMPARE[0] event enable. */
bogdanm	87:6213f644d804	5546	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	87:6213f644d804	5547	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	87:6213f644d804	5548	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5549	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5550
bogdanm	87:6213f644d804	5551	/* Bit 1 : OVRFLW event enable. */
bogdanm	87:6213f644d804	5552	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	87:6213f644d804	5553	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	87:6213f644d804	5554	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5555	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5556
bogdanm	87:6213f644d804	5557	/* Bit 0 : TICK event enable. */
bogdanm	87:6213f644d804	5558	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	87:6213f644d804	5559	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	87:6213f644d804	5560	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5561	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5562
bogdanm	87:6213f644d804	5563	/* Register: RTC_EVTENSET */
bogdanm	87:6213f644d804	5564	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
bogdanm	87:6213f644d804	5565
bogdanm	87:6213f644d804	5566	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
bogdanm	87:6213f644d804	5567	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	87:6213f644d804	5568	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	87:6213f644d804	5569	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5570	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5571	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
bogdanm	87:6213f644d804	5572
bogdanm	87:6213f644d804	5573	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
bogdanm	87:6213f644d804	5574	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	87:6213f644d804	5575	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	87:6213f644d804	5576	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5577	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5578	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
bogdanm	87:6213f644d804	5579
bogdanm	87:6213f644d804	5580	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
bogdanm	87:6213f644d804	5581	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	87:6213f644d804	5582	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	87:6213f644d804	5583	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5584	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5585	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
bogdanm	87:6213f644d804	5586
bogdanm	87:6213f644d804	5587	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
bogdanm	87:6213f644d804	5588	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	87:6213f644d804	5589	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	87:6213f644d804	5590	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5591	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5592	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
bogdanm	87:6213f644d804	5593
bogdanm	87:6213f644d804	5594	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
bogdanm	87:6213f644d804	5595	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	87:6213f644d804	5596	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	87:6213f644d804	5597	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5598	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5599	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
bogdanm	87:6213f644d804	5600
bogdanm	87:6213f644d804	5601	/* Bit 0 : Enable routing to PPI of TICK event. */
bogdanm	87:6213f644d804	5602	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	87:6213f644d804	5603	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	87:6213f644d804	5604	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5605	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5606	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
bogdanm	87:6213f644d804	5607
bogdanm	87:6213f644d804	5608	/* Register: RTC_EVTENCLR */
bogdanm	87:6213f644d804	5609	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
bogdanm	87:6213f644d804	5610
bogdanm	87:6213f644d804	5611	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
bogdanm	87:6213f644d804	5612	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	87:6213f644d804	5613	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	87:6213f644d804	5614	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5615	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5616	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
bogdanm	87:6213f644d804	5617
bogdanm	87:6213f644d804	5618	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
bogdanm	87:6213f644d804	5619	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	87:6213f644d804	5620	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	87:6213f644d804	5621	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5622	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5623	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
bogdanm	87:6213f644d804	5624
bogdanm	87:6213f644d804	5625	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
bogdanm	87:6213f644d804	5626	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	87:6213f644d804	5627	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	87:6213f644d804	5628	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5629	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5630	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
bogdanm	87:6213f644d804	5631
bogdanm	87:6213f644d804	5632	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
bogdanm	87:6213f644d804	5633	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	87:6213f644d804	5634	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	87:6213f644d804	5635	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5636	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5637	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
bogdanm	87:6213f644d804	5638
bogdanm	87:6213f644d804	5639	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
bogdanm	87:6213f644d804	5640	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
bogdanm	87:6213f644d804	5641	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
bogdanm	87:6213f644d804	5642	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5643	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5644	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
bogdanm	87:6213f644d804	5645
bogdanm	87:6213f644d804	5646	/* Bit 0 : Disable routing to PPI of TICK event. */
bogdanm	87:6213f644d804	5647	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
bogdanm	87:6213f644d804	5648	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
bogdanm	87:6213f644d804	5649	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
bogdanm	87:6213f644d804	5650	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
bogdanm	87:6213f644d804	5651	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
bogdanm	87:6213f644d804	5652
bogdanm	87:6213f644d804	5653	/* Register: RTC_COUNTER */
bogdanm	87:6213f644d804	5654	/* Description: Current COUNTER value. */
bogdanm	87:6213f644d804	5655
bogdanm	87:6213f644d804	5656	/* Bits 23..0 : Counter value. */
bogdanm	87:6213f644d804	5657	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
bogdanm	87:6213f644d804	5658	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
bogdanm	87:6213f644d804	5659
bogdanm	87:6213f644d804	5660	/* Register: RTC_PRESCALER */
bogdanm	87:6213f644d804	5661	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
bogdanm	87:6213f644d804	5662
bogdanm	87:6213f644d804	5663	/* Bits 11..0 : RTC PRESCALER value. */
bogdanm	87:6213f644d804	5664	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
bogdanm	87:6213f644d804	5665	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
bogdanm	87:6213f644d804	5666
bogdanm	87:6213f644d804	5667	/* Register: RTC_CC */
bogdanm	87:6213f644d804	5668	/* Description: Capture/compare registers. */
bogdanm	87:6213f644d804	5669
bogdanm	87:6213f644d804	5670	/* Bits 23..0 : Compare value. */
bogdanm	87:6213f644d804	5671	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
bogdanm	87:6213f644d804	5672	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
bogdanm	87:6213f644d804	5673
bogdanm	87:6213f644d804	5674	/* Register: RTC_POWER */
bogdanm	87:6213f644d804	5675	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	5676
bogdanm	87:6213f644d804	5677	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	5678	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	5679	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	5680	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	5681	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	5682
bogdanm	87:6213f644d804	5683
bogdanm	87:6213f644d804	5684	/* Peripheral: SPI */
bogdanm	87:6213f644d804	5685	/* Description: SPI master 0. */
bogdanm	87:6213f644d804	5686
bogdanm	87:6213f644d804	5687	/* Register: SPI_INTENSET */
bogdanm	87:6213f644d804	5688	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	5689
bogdanm	87:6213f644d804	5690	/* Bit 2 : Enable interrupt on READY event. */
bogdanm	87:6213f644d804	5691	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
bogdanm	87:6213f644d804	5692	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
bogdanm	87:6213f644d804	5693	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5694	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5695	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5696
bogdanm	87:6213f644d804	5697	/* Register: SPI_INTENCLR */
bogdanm	87:6213f644d804	5698	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	5699
bogdanm	87:6213f644d804	5700	/* Bit 2 : Disable interrupt on READY event. */
bogdanm	87:6213f644d804	5701	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
bogdanm	87:6213f644d804	5702	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
bogdanm	87:6213f644d804	5703	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5704	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5705	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5706
bogdanm	87:6213f644d804	5707	/* Register: SPI_ENABLE */
bogdanm	87:6213f644d804	5708	/* Description: Enable SPI. */
bogdanm	87:6213f644d804	5709
bogdanm	87:6213f644d804	5710	/* Bits 2..0 : Enable or disable SPI. */
bogdanm	87:6213f644d804	5711	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	5712	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	5713	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
bogdanm	87:6213f644d804	5714	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
bogdanm	87:6213f644d804	5715
bogdanm	87:6213f644d804	5716	/* Register: SPI_RXD */
bogdanm	87:6213f644d804	5717	/* Description: RX data. */
bogdanm	87:6213f644d804	5718
bogdanm	87:6213f644d804	5719	/* Bits 7..0 : RX data from last transfer. */
bogdanm	87:6213f644d804	5720	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	87:6213f644d804	5721	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	87:6213f644d804	5722
bogdanm	87:6213f644d804	5723	/* Register: SPI_TXD */
bogdanm	87:6213f644d804	5724	/* Description: TX data. */
bogdanm	87:6213f644d804	5725
bogdanm	87:6213f644d804	5726	/* Bits 7..0 : TX data for next transfer. */
bogdanm	87:6213f644d804	5727	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	87:6213f644d804	5728	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	87:6213f644d804	5729
bogdanm	87:6213f644d804	5730	/* Register: SPI_FREQUENCY */
bogdanm	87:6213f644d804	5731	/* Description: SPI frequency */
bogdanm	87:6213f644d804	5732
bogdanm	87:6213f644d804	5733	/* Bits 31..0 : SPI data rate. */
bogdanm	87:6213f644d804	5734	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	87:6213f644d804	5735	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	87:6213f644d804	5736	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
bogdanm	87:6213f644d804	5737	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
bogdanm	87:6213f644d804	5738	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
bogdanm	87:6213f644d804	5739	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
bogdanm	87:6213f644d804	5740	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
bogdanm	87:6213f644d804	5741	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
bogdanm	87:6213f644d804	5742	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
bogdanm	87:6213f644d804	5743
bogdanm	87:6213f644d804	5744	/* Register: SPI_CONFIG */
bogdanm	87:6213f644d804	5745	/* Description: Configuration register. */
bogdanm	87:6213f644d804	5746
bogdanm	87:6213f644d804	5747	/* Bit 2 : Serial clock (SCK) polarity. */
bogdanm	87:6213f644d804	5748	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
bogdanm	87:6213f644d804	5749	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
bogdanm	87:6213f644d804	5750	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
bogdanm	87:6213f644d804	5751	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
bogdanm	87:6213f644d804	5752
bogdanm	87:6213f644d804	5753	/* Bit 1 : Serial clock (SCK) phase. */
bogdanm	87:6213f644d804	5754	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
bogdanm	87:6213f644d804	5755	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
bogdanm	87:6213f644d804	5756	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
bogdanm	87:6213f644d804	5757	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
bogdanm	87:6213f644d804	5758
bogdanm	87:6213f644d804	5759	/* Bit 0 : Bit order. */
bogdanm	87:6213f644d804	5760	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
bogdanm	87:6213f644d804	5761	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
bogdanm	87:6213f644d804	5762	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
bogdanm	87:6213f644d804	5763	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
bogdanm	87:6213f644d804	5764
bogdanm	87:6213f644d804	5765	/* Register: SPI_POWER */
bogdanm	87:6213f644d804	5766	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	5767
bogdanm	87:6213f644d804	5768	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	5769	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	5770	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	5771	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	5772	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	5773
bogdanm	87:6213f644d804	5774
Kojto	97:433970e64889	5775	/* Peripheral: SPIM */
Kojto	97:433970e64889	5776	/* Description: SPI master with easyDMA 1. */
Kojto	97:433970e64889	5777
Kojto	97:433970e64889	5778	/* Register: SPIM_INTENSET */
Kojto	97:433970e64889	5779	/* Description: Interrupt enable set register. */
Kojto	97:433970e64889	5780
Kojto	97:433970e64889	5781	/* Bit 19 : Enable interrupt on STARTED event. */
Kojto	97:433970e64889	5782	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
Kojto	97:433970e64889	5783	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
Kojto	97:433970e64889	5784	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5785	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5786	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	5787
Kojto	97:433970e64889	5788	/* Bit 8 : Enable interrupt on ENDTX event. */
Kojto	97:433970e64889	5789	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
Kojto	97:433970e64889	5790	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
Kojto	97:433970e64889	5791	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5792	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5793	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	5794
Kojto	97:433970e64889	5795	/* Bit 4 : Enable interrupt on ENDRX event. */
Kojto	97:433970e64889	5796	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	97:433970e64889	5797	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	97:433970e64889	5798	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5799	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5800	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	5801
Kojto	97:433970e64889	5802	/* Bit 1 : Enable interrupt on STOPPED event. */
Kojto	97:433970e64889	5803	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	97:433970e64889	5804	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	97:433970e64889	5805	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5806	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5807	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	5808
Kojto	97:433970e64889	5809	/* Register: SPIM_INTENCLR */
Kojto	97:433970e64889	5810	/* Description: Interrupt enable clear register. */
Kojto	97:433970e64889	5811
Kojto	97:433970e64889	5812	/* Bit 19 : Disable interrupt on STARTED event. */
Kojto	97:433970e64889	5813	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
Kojto	97:433970e64889	5814	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
Kojto	97:433970e64889	5815	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5816	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5817	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	5818
Kojto	97:433970e64889	5819	/* Bit 8 : Disable interrupt on ENDTX event. */
Kojto	97:433970e64889	5820	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
Kojto	97:433970e64889	5821	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
Kojto	97:433970e64889	5822	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5823	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5824	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	5825
Kojto	97:433970e64889	5826	/* Bit 4 : Disable interrupt on ENDRX event. */
Kojto	97:433970e64889	5827	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	97:433970e64889	5828	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	97:433970e64889	5829	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5830	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5831	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	5832
Kojto	97:433970e64889	5833	/* Bit 1 : Disable interrupt on STOPPED event. */
Kojto	97:433970e64889	5834	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	97:433970e64889	5835	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	97:433970e64889	5836	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	5837	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	5838	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	5839
Kojto	97:433970e64889	5840	/* Register: SPIM_ENABLE */
Kojto	97:433970e64889	5841	/* Description: Enable SPIM. */
Kojto	97:433970e64889	5842
Kojto	97:433970e64889	5843	/* Bits 3..0 : Enable or disable SPIM. */
Kojto	97:433970e64889	5844	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	97:433970e64889	5845	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	97:433970e64889	5846	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
Kojto	97:433970e64889	5847	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
Kojto	97:433970e64889	5848
Kojto	97:433970e64889	5849	/* Register: SPIM_FREQUENCY */
Kojto	97:433970e64889	5850	/* Description: SPI frequency. */
Kojto	97:433970e64889	5851
Kojto	97:433970e64889	5852	/* Bits 31..0 : SPI master data rate. */
Kojto	97:433970e64889	5853	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	97:433970e64889	5854	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	97:433970e64889	5855	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
Kojto	97:433970e64889	5856	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
Kojto	97:433970e64889	5857	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
Kojto	97:433970e64889	5858	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
Kojto	97:433970e64889	5859	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
Kojto	97:433970e64889	5860	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
Kojto	97:433970e64889	5861	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
Kojto	97:433970e64889	5862
Kojto	97:433970e64889	5863	/* Register: SPIM_RXD_PTR */
Kojto	97:433970e64889	5864	/* Description: Data pointer. */
Kojto	97:433970e64889	5865
Kojto	97:433970e64889	5866	/* Bits 31..0 : Data pointer. */
Kojto	97:433970e64889	5867	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
Kojto	97:433970e64889	5868	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
Kojto	97:433970e64889	5869
Kojto	97:433970e64889	5870	/* Register: SPIM_RXD_MAXCNT */
Kojto	97:433970e64889	5871	/* Description: Maximum number of buffer bytes to receive. */
Kojto	97:433970e64889	5872
Kojto	97:433970e64889	5873	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
Kojto	97:433970e64889	5874	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
Kojto	97:433970e64889	5875	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
Kojto	97:433970e64889	5876
Kojto	97:433970e64889	5877	/* Register: SPIM_RXD_AMOUNT */
Kojto	97:433970e64889	5878	/* Description: Number of bytes received in the last transaction. */
Kojto	97:433970e64889	5879
Kojto	97:433970e64889	5880	/* Bits 7..0 : Number of bytes received in the last transaction. */
Kojto	97:433970e64889	5881	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
Kojto	97:433970e64889	5882	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
Kojto	97:433970e64889	5883
Kojto	97:433970e64889	5884	/* Register: SPIM_TXD_PTR */
Kojto	97:433970e64889	5885	/* Description: Data pointer. */
Kojto	97:433970e64889	5886
Kojto	97:433970e64889	5887	/* Bits 31..0 : Data pointer. */
Kojto	97:433970e64889	5888	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
Kojto	97:433970e64889	5889	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
Kojto	97:433970e64889	5890
Kojto	97:433970e64889	5891	/* Register: SPIM_TXD_MAXCNT */
Kojto	97:433970e64889	5892	/* Description: Maximum number of buffer bytes to send. */
Kojto	97:433970e64889	5893
Kojto	97:433970e64889	5894	/* Bits 7..0 : Maximum number of buffer bytes to send. */
Kojto	97:433970e64889	5895	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
Kojto	97:433970e64889	5896	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
Kojto	97:433970e64889	5897
Kojto	97:433970e64889	5898	/* Register: SPIM_TXD_AMOUNT */
Kojto	97:433970e64889	5899	/* Description: Number of bytes sent in the last transaction. */
Kojto	97:433970e64889	5900
Kojto	97:433970e64889	5901	/* Bits 7..0 : Number of bytes sent in the last transaction. */
Kojto	97:433970e64889	5902	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
Kojto	97:433970e64889	5903	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
Kojto	97:433970e64889	5904
Kojto	122:f9eeca106725	5905	/* Register: SPIM_CONFIG */
Kojto	122:f9eeca106725	5906	/* Description: Configuration register. */
Kojto	122:f9eeca106725	5907
Kojto	122:f9eeca106725	5908	/* Bit 2 : Serial clock (SCK) polarity. */
Kojto	122:f9eeca106725	5909	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
Kojto	122:f9eeca106725	5910	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
Kojto	122:f9eeca106725	5911	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
Kojto	122:f9eeca106725	5912	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
Kojto	122:f9eeca106725	5913
Kojto	122:f9eeca106725	5914	/* Bit 1 : Serial clock (SCK) phase. */
Kojto	122:f9eeca106725	5915	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
Kojto	122:f9eeca106725	5916	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
Kojto	122:f9eeca106725	5917	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
Kojto	122:f9eeca106725	5918	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
Kojto	122:f9eeca106725	5919
Kojto	122:f9eeca106725	5920	/* Bit 0 : Bit order. */
Kojto	122:f9eeca106725	5921	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
Kojto	122:f9eeca106725	5922	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
Kojto	122:f9eeca106725	5923	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
Kojto	122:f9eeca106725	5924	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
Kojto	122:f9eeca106725	5925
Kojto	122:f9eeca106725	5926	/* Register: SPIM_ORC */
Kojto	122:f9eeca106725	5927	/* Description: Over-read character. */
Kojto	122:f9eeca106725	5928
Kojto	122:f9eeca106725	5929	/* Bits 7..0 : Over-read character. */
Kojto	122:f9eeca106725	5930	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
Kojto	122:f9eeca106725	5931	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
Kojto	122:f9eeca106725	5932
Kojto	122:f9eeca106725	5933	/* Register: SPIM_POWER */
Kojto	122:f9eeca106725	5934	/* Description: Peripheral power control. */
Kojto	122:f9eeca106725	5935
Kojto	122:f9eeca106725	5936	/* Bit 0 : Peripheral power control. */
Kojto	122:f9eeca106725	5937	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	122:f9eeca106725	5938	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	122:f9eeca106725	5939	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	122:f9eeca106725	5940	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	122:f9eeca106725	5941
Kojto	97:433970e64889	5942
bogdanm	87:6213f644d804	5943	/* Peripheral: SPIS */
bogdanm	87:6213f644d804	5944	/* Description: SPI slave 1. */
bogdanm	87:6213f644d804	5945
bogdanm	87:6213f644d804	5946	/* Register: SPIS_SHORTS */
bogdanm	87:6213f644d804	5947	/* Description: Shortcuts for SPIS. */
bogdanm	87:6213f644d804	5948
bogdanm	87:6213f644d804	5949	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
bogdanm	87:6213f644d804	5950	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
bogdanm	87:6213f644d804	5951	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
bogdanm	87:6213f644d804	5952	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	5953	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	5954
bogdanm	87:6213f644d804	5955	/* Register: SPIS_INTENSET */
bogdanm	87:6213f644d804	5956	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	5957
bogdanm	87:6213f644d804	5958	/* Bit 10 : Enable interrupt on ACQUIRED event. */
bogdanm	87:6213f644d804	5959	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
bogdanm	87:6213f644d804	5960	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
bogdanm	87:6213f644d804	5961	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5962	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5963	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5964
Kojto	122:f9eeca106725	5965	/* Bit 4 : enable interrupt on ENDRX event. */
Kojto	122:f9eeca106725	5966	#define SPIS_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	122:f9eeca106725	5967	#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	122:f9eeca106725	5968	#define SPIS_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	122:f9eeca106725	5969	#define SPIS_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	122:f9eeca106725	5970	#define SPIS_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
Kojto	122:f9eeca106725	5971
bogdanm	87:6213f644d804	5972	/* Bit 1 : Enable interrupt on END event. */
bogdanm	87:6213f644d804	5973	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
bogdanm	87:6213f644d804	5974	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
bogdanm	87:6213f644d804	5975	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5976	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5977	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	5978
bogdanm	87:6213f644d804	5979	/* Register: SPIS_INTENCLR */
bogdanm	87:6213f644d804	5980	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	5981
bogdanm	87:6213f644d804	5982	/* Bit 10 : Disable interrupt on ACQUIRED event. */
bogdanm	87:6213f644d804	5983	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
bogdanm	87:6213f644d804	5984	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
bogdanm	87:6213f644d804	5985	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	5986	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	5987	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	5988
Kojto	122:f9eeca106725	5989	/* Bit 4 : Disable interrupt on ENDRX event. */
Kojto	122:f9eeca106725	5990	#define SPIS_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	122:f9eeca106725	5991	#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	122:f9eeca106725	5992	#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	122:f9eeca106725	5993	#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	122:f9eeca106725	5994	#define SPIS_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	122:f9eeca106725	5995
bogdanm	87:6213f644d804	5996	/* Bit 1 : Disable interrupt on END event. */
bogdanm	87:6213f644d804	5997	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
bogdanm	87:6213f644d804	5998	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
bogdanm	87:6213f644d804	5999	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6000	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6001	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6002
bogdanm	87:6213f644d804	6003	/* Register: SPIS_SEMSTAT */
bogdanm	87:6213f644d804	6004	/* Description: Semaphore status. */
bogdanm	87:6213f644d804	6005
bogdanm	87:6213f644d804	6006	/* Bits 1..0 : Semaphore status. */
bogdanm	87:6213f644d804	6007	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
bogdanm	87:6213f644d804	6008	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
bogdanm	87:6213f644d804	6009	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
bogdanm	87:6213f644d804	6010	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
bogdanm	87:6213f644d804	6011	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
bogdanm	87:6213f644d804	6012	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
bogdanm	87:6213f644d804	6013
bogdanm	87:6213f644d804	6014	/* Register: SPIS_STATUS */
bogdanm	87:6213f644d804	6015	/* Description: Status from last transaction. */
bogdanm	87:6213f644d804	6016
bogdanm	87:6213f644d804	6017	/* Bit 1 : RX buffer overflow detected, and prevented. */
bogdanm	87:6213f644d804	6018	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
bogdanm	87:6213f644d804	6019	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
bogdanm	87:6213f644d804	6020	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
bogdanm	87:6213f644d804	6021	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
bogdanm	87:6213f644d804	6022	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
bogdanm	87:6213f644d804	6023
bogdanm	87:6213f644d804	6024	/* Bit 0 : TX buffer overread detected, and prevented. */
bogdanm	87:6213f644d804	6025	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
bogdanm	87:6213f644d804	6026	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
bogdanm	87:6213f644d804	6027	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
bogdanm	87:6213f644d804	6028	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
bogdanm	87:6213f644d804	6029	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
bogdanm	87:6213f644d804	6030
bogdanm	87:6213f644d804	6031	/* Register: SPIS_ENABLE */
bogdanm	87:6213f644d804	6032	/* Description: Enable SPIS. */
bogdanm	87:6213f644d804	6033
bogdanm	87:6213f644d804	6034	/* Bits 2..0 : Enable or disable SPIS. */
bogdanm	87:6213f644d804	6035	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	6036	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	6037	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
bogdanm	87:6213f644d804	6038	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
bogdanm	87:6213f644d804	6039
bogdanm	87:6213f644d804	6040	/* Register: SPIS_MAXRX */
bogdanm	87:6213f644d804	6041	/* Description: Maximum number of bytes in the receive buffer. */
bogdanm	87:6213f644d804	6042
bogdanm	87:6213f644d804	6043	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
bogdanm	87:6213f644d804	6044	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
bogdanm	87:6213f644d804	6045	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
bogdanm	87:6213f644d804	6046
bogdanm	87:6213f644d804	6047	/* Register: SPIS_AMOUNTRX */
bogdanm	87:6213f644d804	6048	/* Description: Number of bytes received in last granted transaction. */
bogdanm	87:6213f644d804	6049
bogdanm	87:6213f644d804	6050	/* Bits 7..0 : Number of bytes received in last granted transaction. */
bogdanm	87:6213f644d804	6051	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
bogdanm	87:6213f644d804	6052	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
bogdanm	87:6213f644d804	6053
bogdanm	87:6213f644d804	6054	/* Register: SPIS_MAXTX */
bogdanm	87:6213f644d804	6055	/* Description: Maximum number of bytes in the transmit buffer. */
bogdanm	87:6213f644d804	6056
bogdanm	87:6213f644d804	6057	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
bogdanm	87:6213f644d804	6058	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
bogdanm	87:6213f644d804	6059	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
bogdanm	87:6213f644d804	6060
bogdanm	87:6213f644d804	6061	/* Register: SPIS_AMOUNTTX */
bogdanm	87:6213f644d804	6062	/* Description: Number of bytes transmitted in last granted transaction. */
bogdanm	87:6213f644d804	6063
bogdanm	87:6213f644d804	6064	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
bogdanm	87:6213f644d804	6065	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
bogdanm	87:6213f644d804	6066	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
bogdanm	87:6213f644d804	6067
bogdanm	87:6213f644d804	6068	/* Register: SPIS_CONFIG */
bogdanm	87:6213f644d804	6069	/* Description: Configuration register. */
bogdanm	87:6213f644d804	6070
bogdanm	87:6213f644d804	6071	/* Bit 2 : Serial clock (SCK) polarity. */
bogdanm	87:6213f644d804	6072	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
bogdanm	87:6213f644d804	6073	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
bogdanm	87:6213f644d804	6074	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
bogdanm	87:6213f644d804	6075	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
bogdanm	87:6213f644d804	6076
bogdanm	87:6213f644d804	6077	/* Bit 1 : Serial clock (SCK) phase. */
bogdanm	87:6213f644d804	6078	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
bogdanm	87:6213f644d804	6079	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
bogdanm	87:6213f644d804	6080	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
bogdanm	87:6213f644d804	6081	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
bogdanm	87:6213f644d804	6082
bogdanm	87:6213f644d804	6083	/* Bit 0 : Bit order. */
bogdanm	87:6213f644d804	6084	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
bogdanm	87:6213f644d804	6085	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
bogdanm	87:6213f644d804	6086	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
bogdanm	87:6213f644d804	6087	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
bogdanm	87:6213f644d804	6088
bogdanm	87:6213f644d804	6089	/* Register: SPIS_DEF */
bogdanm	87:6213f644d804	6090	/* Description: Default character. */
bogdanm	87:6213f644d804	6091
bogdanm	87:6213f644d804	6092	/* Bits 7..0 : Default character. */
bogdanm	87:6213f644d804	6093	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
bogdanm	87:6213f644d804	6094	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
bogdanm	87:6213f644d804	6095
bogdanm	87:6213f644d804	6096	/* Register: SPIS_ORC */
bogdanm	87:6213f644d804	6097	/* Description: Over-read character. */
bogdanm	87:6213f644d804	6098
bogdanm	87:6213f644d804	6099	/* Bits 7..0 : Over-read character. */
bogdanm	87:6213f644d804	6100	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
bogdanm	87:6213f644d804	6101	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
bogdanm	87:6213f644d804	6102
bogdanm	87:6213f644d804	6103	/* Register: SPIS_POWER */
bogdanm	87:6213f644d804	6104	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	6105
bogdanm	87:6213f644d804	6106	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	6107	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	6108	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	6109	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	6110	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	6111
bogdanm	87:6213f644d804	6112
bogdanm	87:6213f644d804	6113	/* Peripheral: TEMP */
bogdanm	87:6213f644d804	6114	/* Description: Temperature Sensor. */
bogdanm	87:6213f644d804	6115
bogdanm	87:6213f644d804	6116	/* Register: TEMP_INTENSET */
bogdanm	87:6213f644d804	6117	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	6118
bogdanm	87:6213f644d804	6119	/* Bit 0 : Enable interrupt on DATARDY event. */
bogdanm	87:6213f644d804	6120	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
bogdanm	87:6213f644d804	6121	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
bogdanm	87:6213f644d804	6122	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6123	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6124	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6125
bogdanm	87:6213f644d804	6126	/* Register: TEMP_INTENCLR */
bogdanm	87:6213f644d804	6127	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	6128
bogdanm	87:6213f644d804	6129	/* Bit 0 : Disable interrupt on DATARDY event. */
bogdanm	87:6213f644d804	6130	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
bogdanm	87:6213f644d804	6131	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
bogdanm	87:6213f644d804	6132	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6133	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6134	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6135
bogdanm	87:6213f644d804	6136	/* Register: TEMP_POWER */
bogdanm	87:6213f644d804	6137	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	6138
bogdanm	87:6213f644d804	6139	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	6140	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	6141	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	6142	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	6143	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	6144
bogdanm	87:6213f644d804	6145
bogdanm	87:6213f644d804	6146	/* Peripheral: TIMER */
bogdanm	87:6213f644d804	6147	/* Description: Timer 0. */
bogdanm	87:6213f644d804	6148
bogdanm	87:6213f644d804	6149	/* Register: TIMER_SHORTS */
bogdanm	87:6213f644d804	6150	/* Description: Shortcuts for Timer. */
bogdanm	87:6213f644d804	6151
bogdanm	87:6213f644d804	6152	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
bogdanm	87:6213f644d804	6153	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
bogdanm	87:6213f644d804	6154	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
bogdanm	87:6213f644d804	6155	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6156	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6157
bogdanm	87:6213f644d804	6158	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
bogdanm	87:6213f644d804	6159	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
bogdanm	87:6213f644d804	6160	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
bogdanm	87:6213f644d804	6161	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6162	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6163
bogdanm	87:6213f644d804	6164	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
bogdanm	87:6213f644d804	6165	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
bogdanm	87:6213f644d804	6166	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
bogdanm	87:6213f644d804	6167	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6168	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6169
bogdanm	87:6213f644d804	6170	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
bogdanm	87:6213f644d804	6171	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
bogdanm	87:6213f644d804	6172	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
bogdanm	87:6213f644d804	6173	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6174	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6175
bogdanm	87:6213f644d804	6176	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
bogdanm	87:6213f644d804	6177	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
bogdanm	87:6213f644d804	6178	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
bogdanm	87:6213f644d804	6179	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6180	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6181
bogdanm	87:6213f644d804	6182	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
bogdanm	87:6213f644d804	6183	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
bogdanm	87:6213f644d804	6184	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
bogdanm	87:6213f644d804	6185	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6186	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6187
bogdanm	87:6213f644d804	6188	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
bogdanm	87:6213f644d804	6189	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
bogdanm	87:6213f644d804	6190	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
bogdanm	87:6213f644d804	6191	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6192	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6193
bogdanm	87:6213f644d804	6194	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
bogdanm	87:6213f644d804	6195	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
bogdanm	87:6213f644d804	6196	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
bogdanm	87:6213f644d804	6197	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6198	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6199
bogdanm	87:6213f644d804	6200	/* Register: TIMER_INTENSET */
bogdanm	87:6213f644d804	6201	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	6202
bogdanm	87:6213f644d804	6203	/* Bit 19 : Enable interrupt on COMPARE[3] */
bogdanm	87:6213f644d804	6204	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	87:6213f644d804	6205	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	87:6213f644d804	6206	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6207	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6208	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6209
bogdanm	87:6213f644d804	6210	/* Bit 18 : Enable interrupt on COMPARE[2] */
bogdanm	87:6213f644d804	6211	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	87:6213f644d804	6212	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	87:6213f644d804	6213	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6214	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6215	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6216
bogdanm	87:6213f644d804	6217	/* Bit 17 : Enable interrupt on COMPARE[1] */
bogdanm	87:6213f644d804	6218	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	87:6213f644d804	6219	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	87:6213f644d804	6220	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6221	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6222	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6223
bogdanm	87:6213f644d804	6224	/* Bit 16 : Enable interrupt on COMPARE[0] */
bogdanm	87:6213f644d804	6225	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	87:6213f644d804	6226	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	87:6213f644d804	6227	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6228	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6229	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6230
bogdanm	87:6213f644d804	6231	/* Register: TIMER_INTENCLR */
bogdanm	87:6213f644d804	6232	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	6233
bogdanm	87:6213f644d804	6234	/* Bit 19 : Disable interrupt on COMPARE[3] */
bogdanm	87:6213f644d804	6235	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
bogdanm	87:6213f644d804	6236	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
bogdanm	87:6213f644d804	6237	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6238	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6239	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6240
bogdanm	87:6213f644d804	6241	/* Bit 18 : Disable interrupt on COMPARE[2] */
bogdanm	87:6213f644d804	6242	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
bogdanm	87:6213f644d804	6243	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
bogdanm	87:6213f644d804	6244	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6245	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6246	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6247
bogdanm	87:6213f644d804	6248	/* Bit 17 : Disable interrupt on COMPARE[1] */
bogdanm	87:6213f644d804	6249	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
bogdanm	87:6213f644d804	6250	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
bogdanm	87:6213f644d804	6251	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6252	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6253	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6254
bogdanm	87:6213f644d804	6255	/* Bit 16 : Disable interrupt on COMPARE[0] */
bogdanm	87:6213f644d804	6256	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
bogdanm	87:6213f644d804	6257	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
bogdanm	87:6213f644d804	6258	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6259	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6260	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6261
bogdanm	87:6213f644d804	6262	/* Register: TIMER_MODE */
bogdanm	87:6213f644d804	6263	/* Description: Timer Mode selection. */
bogdanm	87:6213f644d804	6264
bogdanm	87:6213f644d804	6265	/* Bit 0 : Select Normal or Counter mode. */
bogdanm	87:6213f644d804	6266	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
bogdanm	87:6213f644d804	6267	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
bogdanm	87:6213f644d804	6268	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
bogdanm	87:6213f644d804	6269	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
bogdanm	87:6213f644d804	6270
bogdanm	87:6213f644d804	6271	/* Register: TIMER_BITMODE */
bogdanm	87:6213f644d804	6272	/* Description: Sets timer behaviour. */
bogdanm	87:6213f644d804	6273
bogdanm	87:6213f644d804	6274	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
bogdanm	87:6213f644d804	6275	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
bogdanm	87:6213f644d804	6276	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
bogdanm	87:6213f644d804	6277	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
bogdanm	87:6213f644d804	6278	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
bogdanm	87:6213f644d804	6279	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
bogdanm	87:6213f644d804	6280	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
bogdanm	87:6213f644d804	6281
bogdanm	87:6213f644d804	6282	/* Register: TIMER_PRESCALER */
bogdanm	87:6213f644d804	6283	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
bogdanm	87:6213f644d804	6284
bogdanm	87:6213f644d804	6285	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
bogdanm	87:6213f644d804	6286	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
bogdanm	87:6213f644d804	6287	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
bogdanm	87:6213f644d804	6288
bogdanm	87:6213f644d804	6289	/* Register: TIMER_POWER */
bogdanm	87:6213f644d804	6290	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	6291
bogdanm	87:6213f644d804	6292	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	6293	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	6294	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	6295	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	6296	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	6297
bogdanm	87:6213f644d804	6298
bogdanm	87:6213f644d804	6299	/* Peripheral: TWI */
bogdanm	87:6213f644d804	6300	/* Description: Two-wire interface master 0. */
bogdanm	87:6213f644d804	6301
bogdanm	87:6213f644d804	6302	/* Register: TWI_SHORTS */
bogdanm	87:6213f644d804	6303	/* Description: Shortcuts for TWI. */
bogdanm	87:6213f644d804	6304
bogdanm	87:6213f644d804	6305	/* Bit 1 : Shortcut between BB event and the STOP task. */
bogdanm	87:6213f644d804	6306	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
bogdanm	87:6213f644d804	6307	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
bogdanm	87:6213f644d804	6308	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6309	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6310
bogdanm	87:6213f644d804	6311	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
bogdanm	87:6213f644d804	6312	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
bogdanm	87:6213f644d804	6313	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
bogdanm	87:6213f644d804	6314	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6315	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6316
bogdanm	87:6213f644d804	6317	/* Register: TWI_INTENSET */
bogdanm	87:6213f644d804	6318	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	6319
Kojto	97:433970e64889	6320	/* Bit 18 : Enable interrupt on SUSPENDED event. */
Kojto	97:433970e64889	6321	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
Kojto	97:433970e64889	6322	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
Kojto	97:433970e64889	6323	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6324	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6325	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6326
bogdanm	87:6213f644d804	6327	/* Bit 14 : Enable interrupt on BB event. */
bogdanm	87:6213f644d804	6328	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
bogdanm	87:6213f644d804	6329	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
bogdanm	87:6213f644d804	6330	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6331	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6332	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6333
bogdanm	87:6213f644d804	6334	/* Bit 9 : Enable interrupt on ERROR event. */
bogdanm	87:6213f644d804	6335	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	87:6213f644d804	6336	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	87:6213f644d804	6337	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6338	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6339	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6340
bogdanm	87:6213f644d804	6341	/* Bit 7 : Enable interrupt on TXDSENT event. */
bogdanm	87:6213f644d804	6342	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
bogdanm	87:6213f644d804	6343	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
bogdanm	87:6213f644d804	6344	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6345	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6346	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6347
bogdanm	87:6213f644d804	6348	/* Bit 2 : Enable interrupt on READY event. */
bogdanm	87:6213f644d804	6349	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
bogdanm	87:6213f644d804	6350	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
bogdanm	87:6213f644d804	6351	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6352	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6353	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6354
bogdanm	87:6213f644d804	6355	/* Bit 1 : Enable interrupt on STOPPED event. */
bogdanm	87:6213f644d804	6356	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
bogdanm	87:6213f644d804	6357	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
bogdanm	87:6213f644d804	6358	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6359	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6360	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6361
bogdanm	87:6213f644d804	6362	/* Register: TWI_INTENCLR */
bogdanm	87:6213f644d804	6363	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	6364
Kojto	97:433970e64889	6365	/* Bit 18 : Disable interrupt on SUSPENDED event. */
Kojto	97:433970e64889	6366	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
Kojto	97:433970e64889	6367	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
Kojto	97:433970e64889	6368	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6369	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6370	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6371
bogdanm	87:6213f644d804	6372	/* Bit 14 : Disable interrupt on BB event. */
bogdanm	87:6213f644d804	6373	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
bogdanm	87:6213f644d804	6374	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
bogdanm	87:6213f644d804	6375	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6376	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6377	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6378
bogdanm	87:6213f644d804	6379	/* Bit 9 : Disable interrupt on ERROR event. */
bogdanm	87:6213f644d804	6380	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	87:6213f644d804	6381	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	87:6213f644d804	6382	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6383	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6384	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6385
bogdanm	87:6213f644d804	6386	/* Bit 7 : Disable interrupt on TXDSENT event. */
bogdanm	87:6213f644d804	6387	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
bogdanm	87:6213f644d804	6388	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
bogdanm	87:6213f644d804	6389	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6390	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6391	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6392
bogdanm	87:6213f644d804	6393	/* Bit 2 : Disable interrupt on RXDREADY event. */
bogdanm	87:6213f644d804	6394	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
bogdanm	87:6213f644d804	6395	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
bogdanm	87:6213f644d804	6396	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6397	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6398	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6399
bogdanm	87:6213f644d804	6400	/* Bit 1 : Disable interrupt on STOPPED event. */
bogdanm	87:6213f644d804	6401	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
bogdanm	87:6213f644d804	6402	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
bogdanm	87:6213f644d804	6403	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6404	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6405	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6406
bogdanm	87:6213f644d804	6407	/* Register: TWI_ERRORSRC */
bogdanm	87:6213f644d804	6408	/* Description: Two-wire error source. Write error field to 1 to clear error. */
bogdanm	87:6213f644d804	6409
bogdanm	87:6213f644d804	6410	/* Bit 2 : NACK received after sending a data byte. */
bogdanm	87:6213f644d804	6411	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
bogdanm	87:6213f644d804	6412	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
bogdanm	87:6213f644d804	6413	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
bogdanm	87:6213f644d804	6414	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
bogdanm	87:6213f644d804	6415	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
bogdanm	87:6213f644d804	6416
bogdanm	87:6213f644d804	6417	/* Bit 1 : NACK received after sending the address. */
bogdanm	87:6213f644d804	6418	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
bogdanm	87:6213f644d804	6419	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
bogdanm	87:6213f644d804	6420	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
bogdanm	87:6213f644d804	6421	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
bogdanm	87:6213f644d804	6422	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
bogdanm	87:6213f644d804	6423
Kojto	122:f9eeca106725	6424	/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
Kojto	122:f9eeca106725	6425	#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
Kojto	122:f9eeca106725	6426	#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
Kojto	122:f9eeca106725	6427	#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
Kojto	122:f9eeca106725	6428	#define TWI_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
Kojto	122:f9eeca106725	6429	#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
Kojto	122:f9eeca106725	6430
bogdanm	87:6213f644d804	6431	/* Register: TWI_ENABLE */
bogdanm	87:6213f644d804	6432	/* Description: Enable two-wire master. */
bogdanm	87:6213f644d804	6433
bogdanm	87:6213f644d804	6434	/* Bits 2..0 : Enable or disable W2M */
bogdanm	87:6213f644d804	6435	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	6436	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	6437	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
bogdanm	87:6213f644d804	6438	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
bogdanm	87:6213f644d804	6439
bogdanm	87:6213f644d804	6440	/* Register: TWI_RXD */
bogdanm	87:6213f644d804	6441	/* Description: RX data register. */
bogdanm	87:6213f644d804	6442
bogdanm	87:6213f644d804	6443	/* Bits 7..0 : RX data from last transfer. */
bogdanm	87:6213f644d804	6444	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	87:6213f644d804	6445	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	87:6213f644d804	6446
bogdanm	87:6213f644d804	6447	/* Register: TWI_TXD */
bogdanm	87:6213f644d804	6448	/* Description: TX data register. */
bogdanm	87:6213f644d804	6449
bogdanm	87:6213f644d804	6450	/* Bits 7..0 : TX data for next transfer. */
bogdanm	87:6213f644d804	6451	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	87:6213f644d804	6452	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	87:6213f644d804	6453
bogdanm	87:6213f644d804	6454	/* Register: TWI_FREQUENCY */
bogdanm	87:6213f644d804	6455	/* Description: Two-wire frequency. */
bogdanm	87:6213f644d804	6456
bogdanm	87:6213f644d804	6457	/* Bits 31..0 : Two-wire master clock frequency. */
bogdanm	87:6213f644d804	6458	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
bogdanm	87:6213f644d804	6459	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
bogdanm	87:6213f644d804	6460	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
bogdanm	87:6213f644d804	6461	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
bogdanm	87:6213f644d804	6462	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
bogdanm	87:6213f644d804	6463
bogdanm	87:6213f644d804	6464	/* Register: TWI_ADDRESS */
bogdanm	87:6213f644d804	6465	/* Description: Address used in the two-wire transfer. */
bogdanm	87:6213f644d804	6466
bogdanm	87:6213f644d804	6467	/* Bits 6..0 : Two-wire address. */
bogdanm	87:6213f644d804	6468	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
bogdanm	87:6213f644d804	6469	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
bogdanm	87:6213f644d804	6470
bogdanm	87:6213f644d804	6471	/* Register: TWI_POWER */
bogdanm	87:6213f644d804	6472	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	6473
bogdanm	87:6213f644d804	6474	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	6475	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	6476	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	6477	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	6478	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	6479
bogdanm	87:6213f644d804	6480
bogdanm	87:6213f644d804	6481	/* Peripheral: UART */
bogdanm	87:6213f644d804	6482	/* Description: Universal Asynchronous Receiver/Transmitter. */
bogdanm	87:6213f644d804	6483
bogdanm	87:6213f644d804	6484	/* Register: UART_SHORTS */
Kojto	97:433970e64889	6485	/* Description: Shortcuts for UART. */
bogdanm	87:6213f644d804	6486
Kojto	122:f9eeca106725	6487	/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
bogdanm	87:6213f644d804	6488	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
bogdanm	87:6213f644d804	6489	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
bogdanm	87:6213f644d804	6490	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6491	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6492
Kojto	122:f9eeca106725	6493	/* Bit 3 : Shortcut between CTS event and STARTRX task. */
bogdanm	87:6213f644d804	6494	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
bogdanm	87:6213f644d804	6495	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
bogdanm	87:6213f644d804	6496	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
bogdanm	87:6213f644d804	6497	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
bogdanm	87:6213f644d804	6498
bogdanm	87:6213f644d804	6499	/* Register: UART_INTENSET */
bogdanm	87:6213f644d804	6500	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	6501
bogdanm	87:6213f644d804	6502	/* Bit 17 : Enable interrupt on RXTO event. */
bogdanm	87:6213f644d804	6503	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
bogdanm	87:6213f644d804	6504	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
bogdanm	87:6213f644d804	6505	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6506	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6507	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6508
bogdanm	87:6213f644d804	6509	/* Bit 9 : Enable interrupt on ERROR event. */
bogdanm	87:6213f644d804	6510	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	87:6213f644d804	6511	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	87:6213f644d804	6512	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6513	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6514	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6515
bogdanm	87:6213f644d804	6516	/* Bit 7 : Enable interrupt on TXRDY event. */
bogdanm	87:6213f644d804	6517	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
bogdanm	87:6213f644d804	6518	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
bogdanm	87:6213f644d804	6519	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6520	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6521	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6522
bogdanm	87:6213f644d804	6523	/* Bit 2 : Enable interrupt on RXRDY event. */
bogdanm	87:6213f644d804	6524	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
bogdanm	87:6213f644d804	6525	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
bogdanm	87:6213f644d804	6526	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6527	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6528	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6529
bogdanm	87:6213f644d804	6530	/* Bit 1 : Enable interrupt on NCTS event. */
bogdanm	87:6213f644d804	6531	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
bogdanm	87:6213f644d804	6532	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
bogdanm	87:6213f644d804	6533	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6534	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6535	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6536
bogdanm	87:6213f644d804	6537	/* Bit 0 : Enable interrupt on CTS event. */
bogdanm	87:6213f644d804	6538	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
bogdanm	87:6213f644d804	6539	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
bogdanm	87:6213f644d804	6540	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6541	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6542	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6543
bogdanm	87:6213f644d804	6544	/* Register: UART_INTENCLR */
bogdanm	87:6213f644d804	6545	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	6546
bogdanm	87:6213f644d804	6547	/* Bit 17 : Disable interrupt on RXTO event. */
bogdanm	87:6213f644d804	6548	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
bogdanm	87:6213f644d804	6549	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
bogdanm	87:6213f644d804	6550	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6551	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6552	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6553
bogdanm	87:6213f644d804	6554	/* Bit 9 : Disable interrupt on ERROR event. */
bogdanm	87:6213f644d804	6555	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
bogdanm	87:6213f644d804	6556	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
bogdanm	87:6213f644d804	6557	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6558	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6559	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6560
bogdanm	87:6213f644d804	6561	/* Bit 7 : Disable interrupt on TXRDY event. */
bogdanm	87:6213f644d804	6562	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
bogdanm	87:6213f644d804	6563	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
bogdanm	87:6213f644d804	6564	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6565	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6566	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6567
bogdanm	87:6213f644d804	6568	/* Bit 2 : Disable interrupt on RXRDY event. */
bogdanm	87:6213f644d804	6569	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
bogdanm	87:6213f644d804	6570	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
bogdanm	87:6213f644d804	6571	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6572	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6573	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6574
bogdanm	87:6213f644d804	6575	/* Bit 1 : Disable interrupt on NCTS event. */
bogdanm	87:6213f644d804	6576	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
bogdanm	87:6213f644d804	6577	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
bogdanm	87:6213f644d804	6578	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6579	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6580	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6581
bogdanm	87:6213f644d804	6582	/* Bit 0 : Disable interrupt on CTS event. */
bogdanm	87:6213f644d804	6583	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
bogdanm	87:6213f644d804	6584	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
bogdanm	87:6213f644d804	6585	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6586	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6587	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6588
bogdanm	87:6213f644d804	6589	/* Register: UART_ERRORSRC */
bogdanm	87:6213f644d804	6590	/* Description: Error source. Write error field to 1 to clear error. */
bogdanm	87:6213f644d804	6591
bogdanm	87:6213f644d804	6592	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
bogdanm	87:6213f644d804	6593	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
bogdanm	87:6213f644d804	6594	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
bogdanm	87:6213f644d804	6595	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
bogdanm	87:6213f644d804	6596	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
bogdanm	87:6213f644d804	6597	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
bogdanm	87:6213f644d804	6598
bogdanm	87:6213f644d804	6599	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
bogdanm	87:6213f644d804	6600	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
bogdanm	87:6213f644d804	6601	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
bogdanm	87:6213f644d804	6602	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
bogdanm	87:6213f644d804	6603	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
bogdanm	87:6213f644d804	6604	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
bogdanm	87:6213f644d804	6605
bogdanm	87:6213f644d804	6606	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
bogdanm	87:6213f644d804	6607	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
bogdanm	87:6213f644d804	6608	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
bogdanm	87:6213f644d804	6609	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
bogdanm	87:6213f644d804	6610	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
bogdanm	87:6213f644d804	6611	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
bogdanm	87:6213f644d804	6612
bogdanm	87:6213f644d804	6613	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
bogdanm	87:6213f644d804	6614	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
bogdanm	87:6213f644d804	6615	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
bogdanm	87:6213f644d804	6616	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
bogdanm	87:6213f644d804	6617	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
bogdanm	87:6213f644d804	6618	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
bogdanm	87:6213f644d804	6619
bogdanm	87:6213f644d804	6620	/* Register: UART_ENABLE */
bogdanm	87:6213f644d804	6621	/* Description: Enable UART and acquire IOs. */
bogdanm	87:6213f644d804	6622
bogdanm	87:6213f644d804	6623	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
bogdanm	87:6213f644d804	6624	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
bogdanm	87:6213f644d804	6625	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
bogdanm	87:6213f644d804	6626	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
bogdanm	87:6213f644d804	6627	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
bogdanm	87:6213f644d804	6628
bogdanm	87:6213f644d804	6629	/* Register: UART_RXD */
Kojto	97:433970e64889	6630	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
bogdanm	87:6213f644d804	6631
bogdanm	87:6213f644d804	6632	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
bogdanm	87:6213f644d804	6633	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
bogdanm	87:6213f644d804	6634	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
bogdanm	87:6213f644d804	6635
bogdanm	87:6213f644d804	6636	/* Register: UART_TXD */
bogdanm	87:6213f644d804	6637	/* Description: TXD register. */
bogdanm	87:6213f644d804	6638
bogdanm	87:6213f644d804	6639	/* Bits 7..0 : TX data for transfer. */
bogdanm	87:6213f644d804	6640	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
bogdanm	87:6213f644d804	6641	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
bogdanm	87:6213f644d804	6642
bogdanm	87:6213f644d804	6643	/* Register: UART_BAUDRATE */
bogdanm	87:6213f644d804	6644	/* Description: UART Baudrate. */
bogdanm	87:6213f644d804	6645
bogdanm	87:6213f644d804	6646	/* Bits 31..0 : UART baudrate. */
bogdanm	87:6213f644d804	6647	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
bogdanm	87:6213f644d804	6648	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
bogdanm	87:6213f644d804	6649	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
bogdanm	87:6213f644d804	6650	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
bogdanm	87:6213f644d804	6651	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
bogdanm	87:6213f644d804	6652	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
bogdanm	87:6213f644d804	6653	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
bogdanm	87:6213f644d804	6654	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
bogdanm	87:6213f644d804	6655	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
bogdanm	87:6213f644d804	6656	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
bogdanm	87:6213f644d804	6657	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
bogdanm	87:6213f644d804	6658	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
bogdanm	87:6213f644d804	6659	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
bogdanm	87:6213f644d804	6660	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
bogdanm	87:6213f644d804	6661	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
bogdanm	87:6213f644d804	6662	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
Kojto	122:f9eeca106725	6663	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /!< 921600 baud. /
bogdanm	87:6213f644d804	6664	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
bogdanm	87:6213f644d804	6665
bogdanm	87:6213f644d804	6666	/* Register: UART_CONFIG */
bogdanm	87:6213f644d804	6667	/* Description: Configuration of parity and hardware flow control register. */
bogdanm	87:6213f644d804	6668
bogdanm	87:6213f644d804	6669	/* Bits 3..1 : Include parity bit. */
bogdanm	87:6213f644d804	6670	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
bogdanm	87:6213f644d804	6671	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
bogdanm	87:6213f644d804	6672	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
bogdanm	87:6213f644d804	6673	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
bogdanm	87:6213f644d804	6674
bogdanm	87:6213f644d804	6675	/* Bit 0 : Hardware flow control. */
bogdanm	87:6213f644d804	6676	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
bogdanm	87:6213f644d804	6677	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
bogdanm	87:6213f644d804	6678	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
bogdanm	87:6213f644d804	6679	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
bogdanm	87:6213f644d804	6680
bogdanm	87:6213f644d804	6681	/* Register: UART_POWER */
bogdanm	87:6213f644d804	6682	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	6683
bogdanm	87:6213f644d804	6684	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	6685	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	6686	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	6687	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	6688	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	6689
bogdanm	87:6213f644d804	6690
bogdanm	87:6213f644d804	6691	/* Peripheral: UICR */
bogdanm	87:6213f644d804	6692	/* Description: User Information Configuration. */
bogdanm	87:6213f644d804	6693
bogdanm	87:6213f644d804	6694	/* Register: UICR_RBPCONF */
bogdanm	87:6213f644d804	6695	/* Description: Readback protection configuration. */
bogdanm	87:6213f644d804	6696
bogdanm	87:6213f644d804	6697	/* Bits 15..8 : Readback protect all code in the device. */
bogdanm	87:6213f644d804	6698	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
bogdanm	87:6213f644d804	6699	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
Kojto	122:f9eeca106725	6700	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
bogdanm	87:6213f644d804	6701	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
bogdanm	87:6213f644d804	6702
bogdanm	87:6213f644d804	6703	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
bogdanm	87:6213f644d804	6704	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
bogdanm	87:6213f644d804	6705	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
Kojto	122:f9eeca106725	6706	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
bogdanm	87:6213f644d804	6707	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
bogdanm	87:6213f644d804	6708
bogdanm	87:6213f644d804	6709	/* Register: UICR_XTALFREQ */
bogdanm	87:6213f644d804	6710	/* Description: Reset value for CLOCK XTALFREQ register. */
bogdanm	87:6213f644d804	6711
bogdanm	87:6213f644d804	6712	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
bogdanm	87:6213f644d804	6713	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
bogdanm	87:6213f644d804	6714	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
Kojto	122:f9eeca106725	6715	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
bogdanm	87:6213f644d804	6716	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
bogdanm	87:6213f644d804	6717
bogdanm	87:6213f644d804	6718	/* Register: UICR_FWID */
bogdanm	87:6213f644d804	6719	/* Description: Firmware ID. */
bogdanm	87:6213f644d804	6720
bogdanm	87:6213f644d804	6721	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
bogdanm	87:6213f644d804	6722	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
bogdanm	87:6213f644d804	6723	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
bogdanm	87:6213f644d804	6724
bogdanm	87:6213f644d804	6725
bogdanm	87:6213f644d804	6726	/* Peripheral: WDT */
bogdanm	87:6213f644d804	6727	/* Description: Watchdog Timer. */
bogdanm	87:6213f644d804	6728
bogdanm	87:6213f644d804	6729	/* Register: WDT_INTENSET */
bogdanm	87:6213f644d804	6730	/* Description: Interrupt enable set register. */
bogdanm	87:6213f644d804	6731
bogdanm	87:6213f644d804	6732	/* Bit 0 : Enable interrupt on TIMEOUT event. */
bogdanm	87:6213f644d804	6733	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
bogdanm	87:6213f644d804	6734	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
bogdanm	87:6213f644d804	6735	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6736	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6737	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
bogdanm	87:6213f644d804	6738
bogdanm	87:6213f644d804	6739	/* Register: WDT_INTENCLR */
bogdanm	87:6213f644d804	6740	/* Description: Interrupt enable clear register. */
bogdanm	87:6213f644d804	6741
bogdanm	87:6213f644d804	6742	/* Bit 0 : Disable interrupt on TIMEOUT event. */
bogdanm	87:6213f644d804	6743	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
bogdanm	87:6213f644d804	6744	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
bogdanm	87:6213f644d804	6745	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
bogdanm	87:6213f644d804	6746	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
bogdanm	87:6213f644d804	6747	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
bogdanm	87:6213f644d804	6748
bogdanm	87:6213f644d804	6749	/* Register: WDT_RUNSTATUS */
bogdanm	87:6213f644d804	6750	/* Description: Watchdog running status. */
bogdanm	87:6213f644d804	6751
bogdanm	87:6213f644d804	6752	/* Bit 0 : Watchdog running status. */
bogdanm	87:6213f644d804	6753	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
bogdanm	87:6213f644d804	6754	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
bogdanm	87:6213f644d804	6755	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
bogdanm	87:6213f644d804	6756	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
bogdanm	87:6213f644d804	6757
bogdanm	87:6213f644d804	6758	/* Register: WDT_REQSTATUS */
bogdanm	87:6213f644d804	6759	/* Description: Request status. */
bogdanm	87:6213f644d804	6760
bogdanm	87:6213f644d804	6761	/* Bit 7 : Request status for RR[7]. */
bogdanm	87:6213f644d804	6762	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
bogdanm	87:6213f644d804	6763	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
bogdanm	87:6213f644d804	6764	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
bogdanm	87:6213f644d804	6765	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
bogdanm	87:6213f644d804	6766
bogdanm	87:6213f644d804	6767	/* Bit 6 : Request status for RR[6]. */
bogdanm	87:6213f644d804	6768	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
bogdanm	87:6213f644d804	6769	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
bogdanm	87:6213f644d804	6770	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
bogdanm	87:6213f644d804	6771	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
bogdanm	87:6213f644d804	6772
bogdanm	87:6213f644d804	6773	/* Bit 5 : Request status for RR[5]. */
bogdanm	87:6213f644d804	6774	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
bogdanm	87:6213f644d804	6775	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
bogdanm	87:6213f644d804	6776	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
bogdanm	87:6213f644d804	6777	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
bogdanm	87:6213f644d804	6778
bogdanm	87:6213f644d804	6779	/* Bit 4 : Request status for RR[4]. */
bogdanm	87:6213f644d804	6780	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
bogdanm	87:6213f644d804	6781	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
bogdanm	87:6213f644d804	6782	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
bogdanm	87:6213f644d804	6783	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
bogdanm	87:6213f644d804	6784
bogdanm	87:6213f644d804	6785	/* Bit 3 : Request status for RR[3]. */
bogdanm	87:6213f644d804	6786	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
bogdanm	87:6213f644d804	6787	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
bogdanm	87:6213f644d804	6788	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
bogdanm	87:6213f644d804	6789	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
bogdanm	87:6213f644d804	6790
bogdanm	87:6213f644d804	6791	/* Bit 2 : Request status for RR[2]. */
bogdanm	87:6213f644d804	6792	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
bogdanm	87:6213f644d804	6793	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
bogdanm	87:6213f644d804	6794	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
bogdanm	87:6213f644d804	6795	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
bogdanm	87:6213f644d804	6796
bogdanm	87:6213f644d804	6797	/* Bit 1 : Request status for RR[1]. */
bogdanm	87:6213f644d804	6798	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
bogdanm	87:6213f644d804	6799	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
bogdanm	87:6213f644d804	6800	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
bogdanm	87:6213f644d804	6801	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
bogdanm	87:6213f644d804	6802
bogdanm	87:6213f644d804	6803	/* Bit 0 : Request status for RR[0]. */
bogdanm	87:6213f644d804	6804	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
bogdanm	87:6213f644d804	6805	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
bogdanm	87:6213f644d804	6806	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
bogdanm	87:6213f644d804	6807	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
bogdanm	87:6213f644d804	6808
bogdanm	87:6213f644d804	6809	/* Register: WDT_RREN */
bogdanm	87:6213f644d804	6810	/* Description: Reload request enable. */
bogdanm	87:6213f644d804	6811
bogdanm	87:6213f644d804	6812	/* Bit 7 : Enable or disable RR[7] register. */
bogdanm	87:6213f644d804	6813	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
bogdanm	87:6213f644d804	6814	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
bogdanm	87:6213f644d804	6815	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
bogdanm	87:6213f644d804	6816	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
bogdanm	87:6213f644d804	6817
bogdanm	87:6213f644d804	6818	/* Bit 6 : Enable or disable RR[6] register. */
bogdanm	87:6213f644d804	6819	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
bogdanm	87:6213f644d804	6820	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
bogdanm	87:6213f644d804	6821	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
bogdanm	87:6213f644d804	6822	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
bogdanm	87:6213f644d804	6823
bogdanm	87:6213f644d804	6824	/* Bit 5 : Enable or disable RR[5] register. */
bogdanm	87:6213f644d804	6825	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
bogdanm	87:6213f644d804	6826	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
bogdanm	87:6213f644d804	6827	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
bogdanm	87:6213f644d804	6828	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
bogdanm	87:6213f644d804	6829
bogdanm	87:6213f644d804	6830	/* Bit 4 : Enable or disable RR[4] register. */
bogdanm	87:6213f644d804	6831	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
bogdanm	87:6213f644d804	6832	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
bogdanm	87:6213f644d804	6833	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
bogdanm	87:6213f644d804	6834	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
bogdanm	87:6213f644d804	6835
bogdanm	87:6213f644d804	6836	/* Bit 3 : Enable or disable RR[3] register. */
bogdanm	87:6213f644d804	6837	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
bogdanm	87:6213f644d804	6838	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
bogdanm	87:6213f644d804	6839	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
bogdanm	87:6213f644d804	6840	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
bogdanm	87:6213f644d804	6841
bogdanm	87:6213f644d804	6842	/* Bit 2 : Enable or disable RR[2] register. */
bogdanm	87:6213f644d804	6843	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
bogdanm	87:6213f644d804	6844	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
bogdanm	87:6213f644d804	6845	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
bogdanm	87:6213f644d804	6846	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
bogdanm	87:6213f644d804	6847
bogdanm	87:6213f644d804	6848	/* Bit 1 : Enable or disable RR[1] register. */
bogdanm	87:6213f644d804	6849	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
bogdanm	87:6213f644d804	6850	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
bogdanm	87:6213f644d804	6851	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
bogdanm	87:6213f644d804	6852	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
bogdanm	87:6213f644d804	6853
bogdanm	87:6213f644d804	6854	/* Bit 0 : Enable or disable RR[0] register. */
bogdanm	87:6213f644d804	6855	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
bogdanm	87:6213f644d804	6856	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
bogdanm	87:6213f644d804	6857	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
bogdanm	87:6213f644d804	6858	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
bogdanm	87:6213f644d804	6859
bogdanm	87:6213f644d804	6860	/* Register: WDT_CONFIG */
bogdanm	87:6213f644d804	6861	/* Description: Configuration register. */
bogdanm	87:6213f644d804	6862
bogdanm	87:6213f644d804	6863	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
bogdanm	87:6213f644d804	6864	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
bogdanm	87:6213f644d804	6865	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
bogdanm	87:6213f644d804	6866	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
bogdanm	87:6213f644d804	6867	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
bogdanm	87:6213f644d804	6868
bogdanm	87:6213f644d804	6869	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
bogdanm	87:6213f644d804	6870	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
bogdanm	87:6213f644d804	6871	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
bogdanm	87:6213f644d804	6872	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
bogdanm	87:6213f644d804	6873	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
bogdanm	87:6213f644d804	6874
bogdanm	87:6213f644d804	6875	/* Register: WDT_RR */
bogdanm	87:6213f644d804	6876	/* Description: Reload requests registers. */
bogdanm	87:6213f644d804	6877
bogdanm	87:6213f644d804	6878	/* Bits 31..0 : Reload register. */
bogdanm	87:6213f644d804	6879	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
bogdanm	87:6213f644d804	6880	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
bogdanm	87:6213f644d804	6881	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
bogdanm	87:6213f644d804	6882
bogdanm	87:6213f644d804	6883	/* Register: WDT_POWER */
bogdanm	87:6213f644d804	6884	/* Description: Peripheral power control. */
bogdanm	87:6213f644d804	6885
bogdanm	87:6213f644d804	6886	/* Bit 0 : Peripheral power control. */
bogdanm	87:6213f644d804	6887	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
bogdanm	87:6213f644d804	6888	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
bogdanm	87:6213f644d804	6889	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
bogdanm	87:6213f644d804	6890	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
bogdanm	87:6213f644d804	6891
bogdanm	87:6213f644d804	6892
bogdanm	87:6213f644d804	6893	/lint --flb "Leave library region" /
bogdanm	87:6213f644d804	6894	#endif

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Created:	17 Jan 2017
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Commits:	136
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TARGET_HRM1017/nrf51_bitfields.h@122:f9eeca106725, 2016-07-07 (annotated)

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