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TARGET_LPC1768/TOOLCHAIN_ARM_STD/LPC1768.sct@64:e3affc9e7238, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 12:28:09 2013 +0300
Revision:
64:e3affc9e7238
Parent:
LPC1768/ARM/LPC1768.sct@40:976df7c37ad5
Child:
65:5798e58a58b1
New build system structure, new target (LPC1347), bug fixes (I2C read/write errors, LPC11U24 memory map and others)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1
emilmont 27:7110ebee3484 2 LR_IROM1 0x00000000 0x80000 { ; load region size_region
emilmont 27:7110ebee3484 3 ER_IROM1 0x00000000 0x80000 { ; load address = execution address
emilmont 27:7110ebee3484 4 *.o (RESET, +First)
emilmont 27:7110ebee3484 5 *(InRoot$$Sections)
emilmont 27:7110ebee3484 6 .ANY (+RO)
emilmont 27:7110ebee3484 7 }
emilmont 27:7110ebee3484 8 ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
emilmont 27:7110ebee3484 9 ; 32KB - 0xC8 = 0x7F38
emilmont 27:7110ebee3484 10 RW_IRAM1 0x100000C8 0x7F38 {
emilmont 27:7110ebee3484 11 .ANY (+RW +ZI)
emilmont 27:7110ebee3484 12 }
emilmont 40:976df7c37ad5 13 RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM
emilmont 27:7110ebee3484 14 .ANY (AHBSRAM0)
emilmont 27:7110ebee3484 15 }
emilmont 27:7110ebee3484 16 RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
emilmont 27:7110ebee3484 17 .ANY (AHBSRAM1)
emilmont 27:7110ebee3484 18 }
emilmont 27:7110ebee3484 19 RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
emilmont 27:7110ebee3484 20 .ANY (CANRAM)
emilmont 27:7110ebee3484 21 }
emilmont 27:7110ebee3484 22 }