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TARGET_NUCLEO_F103RB/stm32_hal_legacy.h@120:7c328cabac7e, 2016-05-10 (annotated)

Committer:
Kojto
Date:
Tue May 10 12:23:43 2016 -0500
Revision:
120:7c328cabac7e
Parent:
96:487b796308b0 
Release 120 of the mbed library



Changes:

- ST - STMF3XX/F4XX - directories removal

     - STMF3 - pwm range fix

     - STMF1 - Cube driver update

- Renesas - RZ_A1H - async i2c, serial and spi addition

- Freescale - KSDK2 update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 96:487b796308b0 1 /**
Kojto 96:487b796308b0 2 ******************************************************************************
Kojto 96:487b796308b0 3 * @file stm32_hal_legacy.h
Kojto 96:487b796308b0 4 * @author MCD Application Team
Kojto 120:7c328cabac7e 5 * @version V1.0.4
Kojto 120:7c328cabac7e 6 * @date 29-April-2016
Kojto 96:487b796308b0 7 * @brief This file contains aliases definition for the STM32Cube HAL constants
Kojto 96:487b796308b0 8 * macros and functions maintained for legacy purpose.
Kojto 96:487b796308b0 9 ******************************************************************************
Kojto 96:487b796308b0 10 * @attention
Kojto 96:487b796308b0 11 *
Kojto 120:7c328cabac7e 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 96:487b796308b0 13 *
Kojto 96:487b796308b0 14 * Redistribution and use in source and binary forms, with or without modification,
Kojto 96:487b796308b0 15 * are permitted provided that the following conditions are met:
Kojto 96:487b796308b0 16 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 96:487b796308b0 17 * this list of conditions and the following disclaimer.
Kojto 96:487b796308b0 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 96:487b796308b0 19 * this list of conditions and the following disclaimer in the documentation
Kojto 96:487b796308b0 20 * and/or other materials provided with the distribution.
Kojto 96:487b796308b0 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 96:487b796308b0 22 * may be used to endorse or promote products derived from this software
Kojto 96:487b796308b0 23 * without specific prior written permission.
Kojto 96:487b796308b0 24 *
Kojto 96:487b796308b0 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 96:487b796308b0 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 96:487b796308b0 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 96:487b796308b0 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 96:487b796308b0 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 96:487b796308b0 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 96:487b796308b0 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 96:487b796308b0 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 120:7c328cabac7e 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 96:487b796308b0 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 96:487b796308b0 35 *
Kojto 96:487b796308b0 36 ******************************************************************************
Kojto 96:487b796308b0 37 */
Kojto 96:487b796308b0 38
Kojto 96:487b796308b0 39 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 96:487b796308b0 40 #ifndef __STM32_HAL_LEGACY
Kojto 96:487b796308b0 41 #define __STM32_HAL_LEGACY
Kojto 96:487b796308b0 42
Kojto 96:487b796308b0 43 #ifdef __cplusplus
Kojto 96:487b796308b0 44 extern "C" {
Kojto 96:487b796308b0 45 #endif
Kojto 96:487b796308b0 46
Kojto 96:487b796308b0 47 /* Includes ------------------------------------------------------------------*/
Kojto 96:487b796308b0 48 /* Exported types ------------------------------------------------------------*/
Kojto 96:487b796308b0 49 /* Exported constants --------------------------------------------------------*/
Kojto 96:487b796308b0 50
Kojto 96:487b796308b0 51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 52 * @{
Kojto 96:487b796308b0 53 */
Kojto 120:7c328cabac7e 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
Kojto 120:7c328cabac7e 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
Kojto 96:487b796308b0 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
Kojto 96:487b796308b0 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
Kojto 96:487b796308b0 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
Kojto 96:487b796308b0 59
Kojto 96:487b796308b0 60 /**
Kojto 96:487b796308b0 61 * @}
Kojto 96:487b796308b0 62 */
Kojto 96:487b796308b0 63
Kojto 96:487b796308b0 64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 65 * @{
Kojto 96:487b796308b0 66 */
Kojto 96:487b796308b0 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
Kojto 96:487b796308b0 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
Kojto 96:487b796308b0 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
Kojto 96:487b796308b0 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
Kojto 96:487b796308b0 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
Kojto 96:487b796308b0 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
Kojto 96:487b796308b0 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
Kojto 96:487b796308b0 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
Kojto 96:487b796308b0 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
Kojto 96:487b796308b0 76 #define REGULAR_GROUP ADC_REGULAR_GROUP
Kojto 96:487b796308b0 77 #define INJECTED_GROUP ADC_INJECTED_GROUP
Kojto 96:487b796308b0 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
Kojto 96:487b796308b0 79 #define AWD_EVENT ADC_AWD_EVENT
Kojto 96:487b796308b0 80 #define AWD1_EVENT ADC_AWD1_EVENT
Kojto 96:487b796308b0 81 #define AWD2_EVENT ADC_AWD2_EVENT
Kojto 96:487b796308b0 82 #define AWD3_EVENT ADC_AWD3_EVENT
Kojto 96:487b796308b0 83 #define OVR_EVENT ADC_OVR_EVENT
Kojto 96:487b796308b0 84 #define JQOVF_EVENT ADC_JQOVF_EVENT
Kojto 96:487b796308b0 85 #define ALL_CHANNELS ADC_ALL_CHANNELS
Kojto 96:487b796308b0 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
Kojto 96:487b796308b0 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
Kojto 96:487b796308b0 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
Kojto 96:487b796308b0 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
Kojto 96:487b796308b0 90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
Kojto 96:487b796308b0 91 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
Kojto 96:487b796308b0 92 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
Kojto 120:7c328cabac7e 93 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
Kojto 120:7c328cabac7e 94 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
Kojto 96:487b796308b0 95 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
Kojto 96:487b796308b0 96 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
Kojto 96:487b796308b0 97 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
Kojto 96:487b796308b0 98 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
Kojto 96:487b796308b0 99 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
Kojto 96:487b796308b0 100 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
Kojto 96:487b796308b0 101 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
Kojto 120:7c328cabac7e 102 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
Kojto 120:7c328cabac7e 103 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
Kojto 120:7c328cabac7e 104 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
Kojto 120:7c328cabac7e 105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
Kojto 120:7c328cabac7e 106 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
Kojto 96:487b796308b0 107
Kojto 120:7c328cabac7e 108 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
Kojto 120:7c328cabac7e 109 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
Kojto 120:7c328cabac7e 110 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
Kojto 120:7c328cabac7e 111 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
Kojto 120:7c328cabac7e 112 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
Kojto 120:7c328cabac7e 113 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
Kojto 120:7c328cabac7e 114 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
Kojto 96:487b796308b0 115 /**
Kojto 96:487b796308b0 116 * @}
Kojto 96:487b796308b0 117 */
Kojto 96:487b796308b0 118
Kojto 96:487b796308b0 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 120 * @{
Kojto 96:487b796308b0 121 */
Kojto 96:487b796308b0 122
Kojto 96:487b796308b0 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
Kojto 96:487b796308b0 124
Kojto 96:487b796308b0 125 /**
Kojto 96:487b796308b0 126 * @}
Kojto 96:487b796308b0 127 */
Kojto 96:487b796308b0 128
Kojto 96:487b796308b0 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 130 * @{
Kojto 96:487b796308b0 131 */
Kojto 120:7c328cabac7e 132 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
Kojto 120:7c328cabac7e 133 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Kojto 120:7c328cabac7e 134 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
Kojto 120:7c328cabac7e 135 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Kojto 120:7c328cabac7e 136 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
Kojto 120:7c328cabac7e 137 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
Kojto 120:7c328cabac7e 138 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
Kojto 120:7c328cabac7e 139 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
Kojto 120:7c328cabac7e 140 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
Kojto 120:7c328cabac7e 141 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
Kojto 120:7c328cabac7e 142 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 120:7c328cabac7e 143 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
Kojto 120:7c328cabac7e 144 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
Kojto 120:7c328cabac7e 145 #endif /* STM32F373xC || STM32F378xx */
Kojto 120:7c328cabac7e 146
Kojto 120:7c328cabac7e 147 #if defined(STM32L0) || defined(STM32L4)
Kojto 120:7c328cabac7e 148 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
Kojto 120:7c328cabac7e 149
Kojto 120:7c328cabac7e 150 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
Kojto 120:7c328cabac7e 151 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
Kojto 120:7c328cabac7e 152 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
Kojto 120:7c328cabac7e 153
Kojto 120:7c328cabac7e 154 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
Kojto 120:7c328cabac7e 155 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
Kojto 120:7c328cabac7e 156 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
Kojto 120:7c328cabac7e 157 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
Kojto 120:7c328cabac7e 158 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
Kojto 120:7c328cabac7e 159 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
Kojto 120:7c328cabac7e 160 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
Kojto 120:7c328cabac7e 161 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
Kojto 120:7c328cabac7e 162 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
Kojto 120:7c328cabac7e 163 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
Kojto 120:7c328cabac7e 164 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
Kojto 120:7c328cabac7e 165 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
Kojto 120:7c328cabac7e 166 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
Kojto 120:7c328cabac7e 167
Kojto 120:7c328cabac7e 168 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
Kojto 120:7c328cabac7e 169 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
Kojto 96:487b796308b0 170
Kojto 120:7c328cabac7e 171 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
Kojto 120:7c328cabac7e 172 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
Kojto 120:7c328cabac7e 173 #if defined(COMP_CSR_LOCK)
Kojto 120:7c328cabac7e 174 #define COMP_FLAG_LOCK COMP_CSR_LOCK
Kojto 120:7c328cabac7e 175 #elif defined(COMP_CSR_COMP1LOCK)
Kojto 120:7c328cabac7e 176 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
Kojto 120:7c328cabac7e 177 #elif defined(COMP_CSR_COMPxLOCK)
Kojto 120:7c328cabac7e 178 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
Kojto 120:7c328cabac7e 179 #endif
Kojto 120:7c328cabac7e 180
Kojto 120:7c328cabac7e 181 #if defined(STM32L4)
Kojto 120:7c328cabac7e 182 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
Kojto 120:7c328cabac7e 183 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
Kojto 120:7c328cabac7e 184 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
Kojto 120:7c328cabac7e 185 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
Kojto 120:7c328cabac7e 186 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
Kojto 120:7c328cabac7e 187 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
Kojto 120:7c328cabac7e 188 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
Kojto 120:7c328cabac7e 189 #endif
Kojto 120:7c328cabac7e 190
Kojto 120:7c328cabac7e 191 #if defined(STM32L0)
Kojto 120:7c328cabac7e 192 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
Kojto 120:7c328cabac7e 193 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
Kojto 120:7c328cabac7e 194 #else
Kojto 120:7c328cabac7e 195 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
Kojto 120:7c328cabac7e 196 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
Kojto 120:7c328cabac7e 197 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
Kojto 120:7c328cabac7e 198 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
Kojto 120:7c328cabac7e 199 #endif
Kojto 120:7c328cabac7e 200
Kojto 120:7c328cabac7e 201 #endif
Kojto 120:7c328cabac7e 202 /**
Kojto 120:7c328cabac7e 203 * @}
Kojto 120:7c328cabac7e 204 */
Kojto 120:7c328cabac7e 205
Kojto 120:7c328cabac7e 206 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
Kojto 120:7c328cabac7e 207 * @{
Kojto 120:7c328cabac7e 208 */
Kojto 120:7c328cabac7e 209 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
Kojto 96:487b796308b0 210 /**
Kojto 96:487b796308b0 211 * @}
Kojto 96:487b796308b0 212 */
Kojto 96:487b796308b0 213
Kojto 96:487b796308b0 214 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 215 * @{
Kojto 96:487b796308b0 216 */
Kojto 96:487b796308b0 217
Kojto 96:487b796308b0 218 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
Kojto 96:487b796308b0 219 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
Kojto 96:487b796308b0 220
Kojto 96:487b796308b0 221 /**
Kojto 96:487b796308b0 222 * @}
Kojto 96:487b796308b0 223 */
Kojto 96:487b796308b0 224
Kojto 96:487b796308b0 225 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 226 * @{
Kojto 96:487b796308b0 227 */
Kojto 96:487b796308b0 228
Kojto 96:487b796308b0 229 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
Kojto 96:487b796308b0 230 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
Kojto 96:487b796308b0 231 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
Kojto 120:7c328cabac7e 232 #define DAC_WAVE_NONE ((uint32_t)0x00000000U)
Kojto 120:7c328cabac7e 233 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
Kojto 120:7c328cabac7e 234 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
Kojto 120:7c328cabac7e 235 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
Kojto 120:7c328cabac7e 236 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
Kojto 120:7c328cabac7e 237 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
Kojto 96:487b796308b0 238
Kojto 96:487b796308b0 239 /**
Kojto 96:487b796308b0 240 * @}
Kojto 96:487b796308b0 241 */
Kojto 96:487b796308b0 242
Kojto 120:7c328cabac7e 243 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
Kojto 120:7c328cabac7e 244 * @{
Kojto 120:7c328cabac7e 245 */
Kojto 120:7c328cabac7e 246 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
Kojto 120:7c328cabac7e 247 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
Kojto 120:7c328cabac7e 248 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
Kojto 120:7c328cabac7e 249 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
Kojto 120:7c328cabac7e 250 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
Kojto 120:7c328cabac7e 251 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto 120:7c328cabac7e 252 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
Kojto 120:7c328cabac7e 253 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
Kojto 120:7c328cabac7e 254 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
Kojto 120:7c328cabac7e 255 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
Kojto 120:7c328cabac7e 256 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto 120:7c328cabac7e 257 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
Kojto 120:7c328cabac7e 258 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
Kojto 120:7c328cabac7e 259 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
Kojto 120:7c328cabac7e 260 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
Kojto 120:7c328cabac7e 261
Kojto 120:7c328cabac7e 262 #define IS_HAL_REMAPDMA IS_DMA_REMAP
Kojto 120:7c328cabac7e 263 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
Kojto 120:7c328cabac7e 264 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
Kojto 120:7c328cabac7e 265
Kojto 120:7c328cabac7e 266
Kojto 120:7c328cabac7e 267
Kojto 120:7c328cabac7e 268 /**
Kojto 120:7c328cabac7e 269 * @}
Kojto 120:7c328cabac7e 270 */
Kojto 96:487b796308b0 271
Kojto 96:487b796308b0 272 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 273 * @{
Kojto 96:487b796308b0 274 */
Kojto 96:487b796308b0 275
Kojto 96:487b796308b0 276 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
Kojto 96:487b796308b0 277 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 96:487b796308b0 278 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
Kojto 96:487b796308b0 279 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
Kojto 96:487b796308b0 280 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
Kojto 96:487b796308b0 281 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
Kojto 96:487b796308b0 282 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
Kojto 96:487b796308b0 283 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
Kojto 96:487b796308b0 284 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
Kojto 96:487b796308b0 285 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
Kojto 96:487b796308b0 286 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
Kojto 96:487b796308b0 287 #define OBEX_PCROP OPTIONBYTE_PCROP
Kojto 96:487b796308b0 288 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
Kojto 96:487b796308b0 289 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
Kojto 96:487b796308b0 290 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
Kojto 96:487b796308b0 291 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
Kojto 96:487b796308b0 292 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
Kojto 96:487b796308b0 293 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
Kojto 96:487b796308b0 294 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
Kojto 96:487b796308b0 295 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
Kojto 96:487b796308b0 296 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
Kojto 96:487b796308b0 297 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
Kojto 96:487b796308b0 298 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
Kojto 96:487b796308b0 299 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
Kojto 96:487b796308b0 300 #define PAGESIZE FLASH_PAGE_SIZE
Kojto 96:487b796308b0 301 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
Kojto 96:487b796308b0 302 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 96:487b796308b0 303 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Kojto 96:487b796308b0 304 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
Kojto 96:487b796308b0 305 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
Kojto 96:487b796308b0 306 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
Kojto 96:487b796308b0 307 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
Kojto 96:487b796308b0 308 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
Kojto 96:487b796308b0 309 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
Kojto 96:487b796308b0 310 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
Kojto 96:487b796308b0 311 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
Kojto 96:487b796308b0 312 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
Kojto 96:487b796308b0 313 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
Kojto 96:487b796308b0 314 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
Kojto 96:487b796308b0 315 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
Kojto 96:487b796308b0 316 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
Kojto 96:487b796308b0 317 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
Kojto 96:487b796308b0 318 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
Kojto 96:487b796308b0 319 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
Kojto 96:487b796308b0 320 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
Kojto 96:487b796308b0 321 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
Kojto 96:487b796308b0 322 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
Kojto 96:487b796308b0 323 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
Kojto 96:487b796308b0 324 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
Kojto 96:487b796308b0 325 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
Kojto 96:487b796308b0 326 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
Kojto 96:487b796308b0 327 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
Kojto 96:487b796308b0 328 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
Kojto 96:487b796308b0 329 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
Kojto 96:487b796308b0 330 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
Kojto 96:487b796308b0 331 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
Kojto 96:487b796308b0 332 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
Kojto 96:487b796308b0 333 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
Kojto 96:487b796308b0 334 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
Kojto 96:487b796308b0 335 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
Kojto 96:487b796308b0 336 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
Kojto 120:7c328cabac7e 337 #define OB_WDG_SW OB_IWDG_SW
Kojto 120:7c328cabac7e 338 #define OB_WDG_HW OB_IWDG_HW
Kojto 120:7c328cabac7e 339 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
Kojto 120:7c328cabac7e 340 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
Kojto 120:7c328cabac7e 341 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
Kojto 120:7c328cabac7e 342 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
Kojto 120:7c328cabac7e 343 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
Kojto 120:7c328cabac7e 344 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
Kojto 120:7c328cabac7e 345 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
Kojto 120:7c328cabac7e 346 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
Kojto 96:487b796308b0 347 /**
Kojto 96:487b796308b0 348 * @}
Kojto 96:487b796308b0 349 */
Kojto 96:487b796308b0 350
Kojto 96:487b796308b0 351 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 352 * @{
Kojto 96:487b796308b0 353 */
Kojto 96:487b796308b0 354
Kojto 120:7c328cabac7e 355 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
Kojto 120:7c328cabac7e 356 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
Kojto 120:7c328cabac7e 357 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
Kojto 120:7c328cabac7e 358 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
Kojto 120:7c328cabac7e 359 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
Kojto 120:7c328cabac7e 360 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
Kojto 120:7c328cabac7e 361 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
Kojto 120:7c328cabac7e 362 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
Kojto 120:7c328cabac7e 363 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
Kojto 96:487b796308b0 364 /**
Kojto 96:487b796308b0 365 * @}
Kojto 96:487b796308b0 366 */
Kojto 96:487b796308b0 367
Kojto 96:487b796308b0 368
Kojto 120:7c328cabac7e 369 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
Kojto 120:7c328cabac7e 370 * @{
Kojto 120:7c328cabac7e 371 */
Kojto 120:7c328cabac7e 372 #if defined(STM32L4) || defined(STM32F7)
Kojto 120:7c328cabac7e 373 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
Kojto 120:7c328cabac7e 374 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
Kojto 120:7c328cabac7e 375 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
Kojto 120:7c328cabac7e 376 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
Kojto 120:7c328cabac7e 377 #else
Kojto 120:7c328cabac7e 378 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
Kojto 120:7c328cabac7e 379 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
Kojto 120:7c328cabac7e 380 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
Kojto 120:7c328cabac7e 381 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
Kojto 120:7c328cabac7e 382 #endif
Kojto 120:7c328cabac7e 383 /**
Kojto 120:7c328cabac7e 384 * @}
Kojto 120:7c328cabac7e 385 */
Kojto 120:7c328cabac7e 386
Kojto 96:487b796308b0 387 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 388 * @{
Kojto 96:487b796308b0 389 */
Kojto 96:487b796308b0 390
Kojto 96:487b796308b0 391 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
Kojto 96:487b796308b0 392 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
Kojto 96:487b796308b0 393 /**
Kojto 96:487b796308b0 394 * @}
Kojto 96:487b796308b0 395 */
Kojto 96:487b796308b0 396
Kojto 96:487b796308b0 397 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 398 * @{
Kojto 96:487b796308b0 399 */
Kojto 96:487b796308b0 400 #define GET_GPIO_SOURCE GPIO_GET_INDEX
Kojto 96:487b796308b0 401 #define GET_GPIO_INDEX GPIO_GET_INDEX
Kojto 120:7c328cabac7e 402
Kojto 120:7c328cabac7e 403 #if defined(STM32F4)
Kojto 120:7c328cabac7e 404 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
Kojto 120:7c328cabac7e 405 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
Kojto 120:7c328cabac7e 406 #endif
Kojto 120:7c328cabac7e 407
Kojto 120:7c328cabac7e 408 #if defined(STM32F7)
Kojto 120:7c328cabac7e 409 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto 120:7c328cabac7e 410 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto 120:7c328cabac7e 411 #endif
Kojto 120:7c328cabac7e 412
Kojto 120:7c328cabac7e 413 #if defined(STM32L4)
Kojto 120:7c328cabac7e 414 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto 120:7c328cabac7e 415 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto 120:7c328cabac7e 416 #endif
Kojto 120:7c328cabac7e 417
Kojto 120:7c328cabac7e 418 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
Kojto 120:7c328cabac7e 419 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
Kojto 120:7c328cabac7e 420 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
Kojto 120:7c328cabac7e 421
Kojto 120:7c328cabac7e 422 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
Kojto 120:7c328cabac7e 423 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
Kojto 120:7c328cabac7e 424 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
Kojto 120:7c328cabac7e 425 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
Kojto 120:7c328cabac7e 426 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
Kojto 120:7c328cabac7e 427 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
Kojto 120:7c328cabac7e 428
Kojto 120:7c328cabac7e 429 #if defined(STM32L1)
Kojto 120:7c328cabac7e 430 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
Kojto 120:7c328cabac7e 431 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
Kojto 120:7c328cabac7e 432 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
Kojto 120:7c328cabac7e 433 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
Kojto 120:7c328cabac7e 434 #endif /* STM32L1 */
Kojto 120:7c328cabac7e 435
Kojto 120:7c328cabac7e 436 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
Kojto 120:7c328cabac7e 437 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
Kojto 120:7c328cabac7e 438 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
Kojto 120:7c328cabac7e 439 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
Kojto 120:7c328cabac7e 440 #endif /* STM32F0 || STM32F3 || STM32F1 */
Kojto 120:7c328cabac7e 441
Kojto 120:7c328cabac7e 442 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
Kojto 96:487b796308b0 443 /**
Kojto 96:487b796308b0 444 * @}
Kojto 96:487b796308b0 445 */
Kojto 96:487b796308b0 446
Kojto 120:7c328cabac7e 447 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
Kojto 120:7c328cabac7e 448 * @{
Kojto 120:7c328cabac7e 449 */
Kojto 120:7c328cabac7e 450 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
Kojto 120:7c328cabac7e 451 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
Kojto 120:7c328cabac7e 452 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
Kojto 120:7c328cabac7e 453 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
Kojto 120:7c328cabac7e 454 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
Kojto 120:7c328cabac7e 455 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
Kojto 120:7c328cabac7e 456 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
Kojto 120:7c328cabac7e 457 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
Kojto 120:7c328cabac7e 458 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
Kojto 120:7c328cabac7e 459
Kojto 120:7c328cabac7e 460 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
Kojto 120:7c328cabac7e 461 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
Kojto 120:7c328cabac7e 462 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
Kojto 120:7c328cabac7e 463 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
Kojto 120:7c328cabac7e 464 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
Kojto 120:7c328cabac7e 465 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
Kojto 120:7c328cabac7e 466 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
Kojto 120:7c328cabac7e 467 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
Kojto 120:7c328cabac7e 468 /**
Kojto 120:7c328cabac7e 469 * @}
Kojto 120:7c328cabac7e 470 */
Kojto 96:487b796308b0 471
Kojto 96:487b796308b0 472 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 473 * @{
Kojto 96:487b796308b0 474 */
Kojto 96:487b796308b0 475 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
Kojto 96:487b796308b0 476 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
Kojto 96:487b796308b0 477 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
Kojto 96:487b796308b0 478 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
Kojto 96:487b796308b0 479 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
Kojto 96:487b796308b0 480 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
Kojto 96:487b796308b0 481 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
Kojto 96:487b796308b0 482 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
Kojto 120:7c328cabac7e 483 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
Kojto 120:7c328cabac7e 484 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 120:7c328cabac7e 485 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 120:7c328cabac7e 486 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 120:7c328cabac7e 487 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 120:7c328cabac7e 488 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 120:7c328cabac7e 489 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 120:7c328cabac7e 490 #endif
Kojto 96:487b796308b0 491 /**
Kojto 96:487b796308b0 492 * @}
Kojto 96:487b796308b0 493 */
Kojto 96:487b796308b0 494
Kojto 96:487b796308b0 495 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 496 * @{
Kojto 96:487b796308b0 497 */
Kojto 96:487b796308b0 498 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 499 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 500
Kojto 96:487b796308b0 501 /**
Kojto 96:487b796308b0 502 * @}
Kojto 96:487b796308b0 503 */
Kojto 96:487b796308b0 504
Kojto 96:487b796308b0 505 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 506 * @{
Kojto 96:487b796308b0 507 */
Kojto 96:487b796308b0 508 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
Kojto 96:487b796308b0 509 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
Kojto 96:487b796308b0 510 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
Kojto 96:487b796308b0 511 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
Kojto 96:487b796308b0 512 /**
Kojto 96:487b796308b0 513 * @}
Kojto 96:487b796308b0 514 */
Kojto 96:487b796308b0 515
Kojto 120:7c328cabac7e 516 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
Kojto 120:7c328cabac7e 517 * @{
Kojto 120:7c328cabac7e 518 */
Kojto 120:7c328cabac7e 519
Kojto 120:7c328cabac7e 520 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
Kojto 120:7c328cabac7e 521 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
Kojto 120:7c328cabac7e 522 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
Kojto 120:7c328cabac7e 523 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
Kojto 120:7c328cabac7e 524
Kojto 120:7c328cabac7e 525 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
Kojto 120:7c328cabac7e 526 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
Kojto 120:7c328cabac7e 527 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
Kojto 120:7c328cabac7e 528
Kojto 120:7c328cabac7e 529 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
Kojto 120:7c328cabac7e 530 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto 120:7c328cabac7e 531 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto 120:7c328cabac7e 532 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto 120:7c328cabac7e 533
Kojto 120:7c328cabac7e 534 /* The following 3 definition have also been present in a temporary version of lptim.h */
Kojto 120:7c328cabac7e 535 /* They need to be renamed also to the right name, just in case */
Kojto 120:7c328cabac7e 536 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto 120:7c328cabac7e 537 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto 120:7c328cabac7e 538 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto 120:7c328cabac7e 539
Kojto 120:7c328cabac7e 540 /**
Kojto 120:7c328cabac7e 541 * @}
Kojto 120:7c328cabac7e 542 */
Kojto 120:7c328cabac7e 543
Kojto 96:487b796308b0 544 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 545 * @{
Kojto 96:487b796308b0 546 */
Kojto 120:7c328cabac7e 547 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
Kojto 120:7c328cabac7e 548 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
Kojto 120:7c328cabac7e 549 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
Kojto 120:7c328cabac7e 550 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
Kojto 120:7c328cabac7e 551
Kojto 96:487b796308b0 552 #define NAND_AddressTypedef NAND_AddressTypeDef
Kojto 96:487b796308b0 553
Kojto 120:7c328cabac7e 554 #define __ARRAY_ADDRESS ARRAY_ADDRESS
Kojto 120:7c328cabac7e 555 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
Kojto 120:7c328cabac7e 556 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
Kojto 120:7c328cabac7e 557 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
Kojto 120:7c328cabac7e 558 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
Kojto 96:487b796308b0 559 /**
Kojto 96:487b796308b0 560 * @}
Kojto 96:487b796308b0 561 */
Kojto 96:487b796308b0 562
Kojto 96:487b796308b0 563 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 564 * @{
Kojto 96:487b796308b0 565 */
Kojto 96:487b796308b0 566 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
Kojto 96:487b796308b0 567 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
Kojto 96:487b796308b0 568 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
Kojto 96:487b796308b0 569 #define NOR_ERROR HAL_NOR_STATUS_ERROR
Kojto 96:487b796308b0 570 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Kojto 96:487b796308b0 571
Kojto 120:7c328cabac7e 572 #define __NOR_WRITE NOR_WRITE
Kojto 120:7c328cabac7e 573 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
Kojto 96:487b796308b0 574 /**
Kojto 96:487b796308b0 575 * @}
Kojto 96:487b796308b0 576 */
Kojto 96:487b796308b0 577
Kojto 96:487b796308b0 578 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 579 * @{
Kojto 96:487b796308b0 580 */
Kojto 96:487b796308b0 581
Kojto 96:487b796308b0 582 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
Kojto 96:487b796308b0 583 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
Kojto 96:487b796308b0 584 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
Kojto 96:487b796308b0 585 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
Kojto 96:487b796308b0 586
Kojto 96:487b796308b0 587 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
Kojto 96:487b796308b0 588 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
Kojto 96:487b796308b0 589 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
Kojto 96:487b796308b0 590 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
Kojto 96:487b796308b0 591
Kojto 96:487b796308b0 592 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 96:487b796308b0 593 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 594
Kojto 96:487b796308b0 595 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 96:487b796308b0 596 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 597
Kojto 96:487b796308b0 598 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
Kojto 96:487b796308b0 599 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 600
Kojto 96:487b796308b0 601 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 602
Kojto 96:487b796308b0 603 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
Kojto 96:487b796308b0 604 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
Kojto 96:487b796308b0 605 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
Kojto 96:487b796308b0 606
Kojto 96:487b796308b0 607 /**
Kojto 96:487b796308b0 608 * @}
Kojto 96:487b796308b0 609 */
Kojto 96:487b796308b0 610
Kojto 96:487b796308b0 611 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 612 * @{
Kojto 96:487b796308b0 613 */
Kojto 96:487b796308b0 614 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
Kojto 120:7c328cabac7e 615 #if defined(STM32F7)
Kojto 120:7c328cabac7e 616 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
Kojto 120:7c328cabac7e 617 #endif
Kojto 96:487b796308b0 618 /**
Kojto 96:487b796308b0 619 * @}
Kojto 96:487b796308b0 620 */
Kojto 96:487b796308b0 621
Kojto 96:487b796308b0 622 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 623 * @{
Kojto 96:487b796308b0 624 */
Kojto 96:487b796308b0 625
Kojto 96:487b796308b0 626 /* Compact Flash-ATA registers description */
Kojto 96:487b796308b0 627 #define CF_DATA ATA_DATA
Kojto 96:487b796308b0 628 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
Kojto 96:487b796308b0 629 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
Kojto 96:487b796308b0 630 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
Kojto 96:487b796308b0 631 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
Kojto 96:487b796308b0 632 #define CF_CARD_HEAD ATA_CARD_HEAD
Kojto 96:487b796308b0 633 #define CF_STATUS_CMD ATA_STATUS_CMD
Kojto 96:487b796308b0 634 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
Kojto 96:487b796308b0 635 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
Kojto 96:487b796308b0 636
Kojto 96:487b796308b0 637 /* Compact Flash-ATA commands */
Kojto 96:487b796308b0 638 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
Kojto 96:487b796308b0 639 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
Kojto 96:487b796308b0 640 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
Kojto 96:487b796308b0 641 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
Kojto 96:487b796308b0 642
Kojto 96:487b796308b0 643 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
Kojto 96:487b796308b0 644 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
Kojto 96:487b796308b0 645 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
Kojto 96:487b796308b0 646 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
Kojto 96:487b796308b0 647 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
Kojto 96:487b796308b0 648 /**
Kojto 96:487b796308b0 649 * @}
Kojto 96:487b796308b0 650 */
Kojto 96:487b796308b0 651
Kojto 96:487b796308b0 652 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 653 * @{
Kojto 96:487b796308b0 654 */
Kojto 96:487b796308b0 655
Kojto 96:487b796308b0 656 #define FORMAT_BIN RTC_FORMAT_BIN
Kojto 96:487b796308b0 657 #define FORMAT_BCD RTC_FORMAT_BCD
Kojto 96:487b796308b0 658
Kojto 96:487b796308b0 659 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Kojto 96:487b796308b0 660 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 96:487b796308b0 661 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 96:487b796308b0 662 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 96:487b796308b0 663 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 96:487b796308b0 664
Kojto 120:7c328cabac7e 665 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 96:487b796308b0 666 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 120:7c328cabac7e 667 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 120:7c328cabac7e 668 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 120:7c328cabac7e 669 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 96:487b796308b0 670 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 120:7c328cabac7e 671 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 120:7c328cabac7e 672 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 120:7c328cabac7e 673
Kojto 120:7c328cabac7e 674 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
Kojto 120:7c328cabac7e 675 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
Kojto 120:7c328cabac7e 676 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
Kojto 120:7c328cabac7e 677 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
Kojto 120:7c328cabac7e 678
Kojto 120:7c328cabac7e 679 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
Kojto 120:7c328cabac7e 680 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
Kojto 120:7c328cabac7e 681 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
Kojto 120:7c328cabac7e 682
Kojto 120:7c328cabac7e 683 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
Kojto 120:7c328cabac7e 684 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
Kojto 120:7c328cabac7e 685 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
Kojto 96:487b796308b0 686
Kojto 96:487b796308b0 687 /**
Kojto 96:487b796308b0 688 * @}
Kojto 96:487b796308b0 689 */
Kojto 96:487b796308b0 690
Kojto 96:487b796308b0 691
Kojto 96:487b796308b0 692 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 693 * @{
Kojto 96:487b796308b0 694 */
Kojto 96:487b796308b0 695 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Kojto 96:487b796308b0 696 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Kojto 96:487b796308b0 697
Kojto 96:487b796308b0 698 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 699 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 700 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 701 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 702
Kojto 96:487b796308b0 703 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
Kojto 96:487b796308b0 704 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
Kojto 96:487b796308b0 705
Kojto 96:487b796308b0 706 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
Kojto 96:487b796308b0 707 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
Kojto 96:487b796308b0 708 /**
Kojto 96:487b796308b0 709 * @}
Kojto 96:487b796308b0 710 */
Kojto 96:487b796308b0 711
Kojto 96:487b796308b0 712
Kojto 120:7c328cabac7e 713 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 714 * @{
Kojto 96:487b796308b0 715 */
Kojto 96:487b796308b0 716 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
Kojto 96:487b796308b0 717 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
Kojto 96:487b796308b0 718 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
Kojto 96:487b796308b0 719 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
Kojto 96:487b796308b0 720 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
Kojto 96:487b796308b0 721 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
Kojto 96:487b796308b0 722 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
Kojto 96:487b796308b0 723 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
Kojto 120:7c328cabac7e 724 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
Kojto 120:7c328cabac7e 725 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
Kojto 96:487b796308b0 726 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
Kojto 96:487b796308b0 727 /**
Kojto 96:487b796308b0 728 * @}
Kojto 96:487b796308b0 729 */
Kojto 96:487b796308b0 730
Kojto 120:7c328cabac7e 731 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 732 * @{
Kojto 96:487b796308b0 733 */
Kojto 96:487b796308b0 734 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
Kojto 96:487b796308b0 735 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
Kojto 96:487b796308b0 736
Kojto 96:487b796308b0 737 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
Kojto 96:487b796308b0 738 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
Kojto 96:487b796308b0 739
Kojto 96:487b796308b0 740 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
Kojto 96:487b796308b0 741 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Kojto 96:487b796308b0 742
Kojto 96:487b796308b0 743 /**
Kojto 96:487b796308b0 744 * @}
Kojto 96:487b796308b0 745 */
Kojto 96:487b796308b0 746
Kojto 96:487b796308b0 747 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 748 * @{
Kojto 96:487b796308b0 749 */
Kojto 96:487b796308b0 750 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Kojto 96:487b796308b0 751 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Kojto 96:487b796308b0 752
Kojto 96:487b796308b0 753 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
Kojto 96:487b796308b0 754 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
Kojto 96:487b796308b0 755 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
Kojto 96:487b796308b0 756 #define TIM_DMABase_DIER TIM_DMABASE_DIER
Kojto 96:487b796308b0 757 #define TIM_DMABase_SR TIM_DMABASE_SR
Kojto 96:487b796308b0 758 #define TIM_DMABase_EGR TIM_DMABASE_EGR
Kojto 96:487b796308b0 759 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Kojto 96:487b796308b0 760 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Kojto 96:487b796308b0 761 #define TIM_DMABase_CCER TIM_DMABASE_CCER
Kojto 96:487b796308b0 762 #define TIM_DMABase_CNT TIM_DMABASE_CNT
Kojto 96:487b796308b0 763 #define TIM_DMABase_PSC TIM_DMABASE_PSC
Kojto 96:487b796308b0 764 #define TIM_DMABase_ARR TIM_DMABASE_ARR
Kojto 96:487b796308b0 765 #define TIM_DMABase_RCR TIM_DMABASE_RCR
Kojto 96:487b796308b0 766 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
Kojto 96:487b796308b0 767 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
Kojto 96:487b796308b0 768 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
Kojto 96:487b796308b0 769 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
Kojto 96:487b796308b0 770 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
Kojto 96:487b796308b0 771 #define TIM_DMABase_DCR TIM_DMABASE_DCR
Kojto 96:487b796308b0 772 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
Kojto 96:487b796308b0 773 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
Kojto 96:487b796308b0 774 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
Kojto 96:487b796308b0 775 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
Kojto 96:487b796308b0 776 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
Kojto 96:487b796308b0 777 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
Kojto 96:487b796308b0 778 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
Kojto 120:7c328cabac7e 779 #define TIM_DMABase_OR TIM_DMABASE_OR
Kojto 96:487b796308b0 780
Kojto 96:487b796308b0 781 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
Kojto 96:487b796308b0 782 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
Kojto 96:487b796308b0 783 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
Kojto 96:487b796308b0 784 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
Kojto 96:487b796308b0 785 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
Kojto 96:487b796308b0 786 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
Kojto 96:487b796308b0 787 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
Kojto 96:487b796308b0 788 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
Kojto 96:487b796308b0 789 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
Kojto 96:487b796308b0 790
Kojto 96:487b796308b0 791 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
Kojto 96:487b796308b0 792 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
Kojto 96:487b796308b0 793 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
Kojto 96:487b796308b0 794 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
Kojto 96:487b796308b0 795 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
Kojto 96:487b796308b0 796 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
Kojto 96:487b796308b0 797 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
Kojto 96:487b796308b0 798 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
Kojto 96:487b796308b0 799 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
Kojto 96:487b796308b0 800 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
Kojto 96:487b796308b0 801 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
Kojto 96:487b796308b0 802 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
Kojto 96:487b796308b0 803 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
Kojto 96:487b796308b0 804 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
Kojto 96:487b796308b0 805 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
Kojto 96:487b796308b0 806 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
Kojto 96:487b796308b0 807 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
Kojto 96:487b796308b0 808 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
Kojto 96:487b796308b0 809
Kojto 96:487b796308b0 810 /**
Kojto 96:487b796308b0 811 * @}
Kojto 96:487b796308b0 812 */
Kojto 96:487b796308b0 813
Kojto 120:7c328cabac7e 814 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
Kojto 120:7c328cabac7e 815 * @{
Kojto 120:7c328cabac7e 816 */
Kojto 120:7c328cabac7e 817 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
Kojto 120:7c328cabac7e 818 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
Kojto 120:7c328cabac7e 819 /**
Kojto 120:7c328cabac7e 820 * @}
Kojto 120:7c328cabac7e 821 */
Kojto 120:7c328cabac7e 822
Kojto 96:487b796308b0 823 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 824 * @{
Kojto 96:487b796308b0 825 */
Kojto 96:487b796308b0 826 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 827 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 828 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 829 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 830
Kojto 96:487b796308b0 831 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Kojto 96:487b796308b0 832 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Kojto 96:487b796308b0 833
Kojto 96:487b796308b0 834 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
Kojto 96:487b796308b0 835 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Kojto 96:487b796308b0 836 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Kojto 96:487b796308b0 837 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
Kojto 96:487b796308b0 838
Kojto 96:487b796308b0 839 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
Kojto 96:487b796308b0 840 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Kojto 96:487b796308b0 841 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Kojto 96:487b796308b0 842 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Kojto 96:487b796308b0 843
Kojto 96:487b796308b0 844 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
Kojto 96:487b796308b0 845 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
Kojto 96:487b796308b0 846
Kojto 96:487b796308b0 847 /**
Kojto 96:487b796308b0 848 * @}
Kojto 96:487b796308b0 849 */
Kojto 96:487b796308b0 850
Kojto 96:487b796308b0 851
Kojto 96:487b796308b0 852 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 853 * @{
Kojto 96:487b796308b0 854 */
Kojto 96:487b796308b0 855
Kojto 96:487b796308b0 856 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
Kojto 96:487b796308b0 857 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
Kojto 96:487b796308b0 858
Kojto 96:487b796308b0 859 #define USARTNACK_ENABLED USART_NACK_ENABLE
Kojto 96:487b796308b0 860 #define USARTNACK_DISABLED USART_NACK_DISABLE
Kojto 96:487b796308b0 861 /**
Kojto 96:487b796308b0 862 * @}
Kojto 96:487b796308b0 863 */
Kojto 96:487b796308b0 864
Kojto 96:487b796308b0 865 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 866 * @{
Kojto 96:487b796308b0 867 */
Kojto 96:487b796308b0 868 #define CFR_BASE WWDG_CFR_BASE
Kojto 96:487b796308b0 869
Kojto 96:487b796308b0 870 /**
Kojto 96:487b796308b0 871 * @}
Kojto 96:487b796308b0 872 */
Kojto 96:487b796308b0 873
Kojto 96:487b796308b0 874 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 875 * @{
Kojto 96:487b796308b0 876 */
Kojto 96:487b796308b0 877 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
Kojto 96:487b796308b0 878 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
Kojto 96:487b796308b0 879 #define CAN_IT_RQCP0 CAN_IT_TME
Kojto 96:487b796308b0 880 #define CAN_IT_RQCP1 CAN_IT_TME
Kojto 96:487b796308b0 881 #define CAN_IT_RQCP2 CAN_IT_TME
Kojto 96:487b796308b0 882 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 96:487b796308b0 883 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 120:7c328cabac7e 884 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
Kojto 120:7c328cabac7e 885 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
Kojto 120:7c328cabac7e 886 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
Kojto 96:487b796308b0 887
Kojto 96:487b796308b0 888 /**
Kojto 96:487b796308b0 889 * @}
Kojto 96:487b796308b0 890 */
Kojto 96:487b796308b0 891
Kojto 96:487b796308b0 892 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 893 * @{
Kojto 96:487b796308b0 894 */
Kojto 96:487b796308b0 895
Kojto 96:487b796308b0 896 #define VLAN_TAG ETH_VLAN_TAG
Kojto 96:487b796308b0 897 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
Kojto 96:487b796308b0 898 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
Kojto 96:487b796308b0 899 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
Kojto 96:487b796308b0 900 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
Kojto 96:487b796308b0 901 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
Kojto 96:487b796308b0 902 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
Kojto 96:487b796308b0 903 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
Kojto 96:487b796308b0 904
Kojto 120:7c328cabac7e 905 #define ETH_MMCCR ((uint32_t)0x00000100U)
Kojto 120:7c328cabac7e 906 #define ETH_MMCRIR ((uint32_t)0x00000104U)
Kojto 120:7c328cabac7e 907 #define ETH_MMCTIR ((uint32_t)0x00000108U)
Kojto 120:7c328cabac7e 908 #define ETH_MMCRIMR ((uint32_t)0x0000010CU)
Kojto 120:7c328cabac7e 909 #define ETH_MMCTIMR ((uint32_t)0x00000110U)
Kojto 120:7c328cabac7e 910 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
Kojto 120:7c328cabac7e 911 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
Kojto 120:7c328cabac7e 912 #define ETH_MMCTGFCR ((uint32_t)0x00000168U)
Kojto 120:7c328cabac7e 913 #define ETH_MMCRFCECR ((uint32_t)0x00000194U)
Kojto 120:7c328cabac7e 914 #define ETH_MMCRFAECR ((uint32_t)0x00000198U)
Kojto 120:7c328cabac7e 915 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
Kojto 120:7c328cabac7e 916
Kojto 120:7c328cabac7e 917 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
Kojto 120:7c328cabac7e 918 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
Kojto 120:7c328cabac7e 919 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
Kojto 120:7c328cabac7e 920 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
Kojto 120:7c328cabac7e 921 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
Kojto 120:7c328cabac7e 922 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
Kojto 120:7c328cabac7e 923 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
Kojto 120:7c328cabac7e 924 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
Kojto 120:7c328cabac7e 925 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
Kojto 120:7c328cabac7e 926 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
Kojto 120:7c328cabac7e 927 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
Kojto 120:7c328cabac7e 928 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
Kojto 120:7c328cabac7e 929 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
Kojto 120:7c328cabac7e 930 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
Kojto 120:7c328cabac7e 931 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
Kojto 120:7c328cabac7e 932 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
Kojto 120:7c328cabac7e 933 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
Kojto 120:7c328cabac7e 934 #if defined(STM32F1)
Kojto 120:7c328cabac7e 935 #else
Kojto 120:7c328cabac7e 936 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
Kojto 120:7c328cabac7e 937 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
Kojto 120:7c328cabac7e 938 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
Kojto 120:7c328cabac7e 939 #endif
Kojto 120:7c328cabac7e 940 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
Kojto 120:7c328cabac7e 941 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
Kojto 120:7c328cabac7e 942 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
Kojto 120:7c328cabac7e 943 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
Kojto 120:7c328cabac7e 944 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
Kojto 120:7c328cabac7e 945 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto 120:7c328cabac7e 946 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
Kojto 96:487b796308b0 947
Kojto 96:487b796308b0 948 /**
Kojto 96:487b796308b0 949 * @}
Kojto 96:487b796308b0 950 */
Kojto 120:7c328cabac7e 951
Kojto 120:7c328cabac7e 952 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
Kojto 120:7c328cabac7e 953 * @{
Kojto 120:7c328cabac7e 954 */
Kojto 120:7c328cabac7e 955 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
Kojto 120:7c328cabac7e 956 #define DCMI_IT_OVF DCMI_IT_OVR
Kojto 120:7c328cabac7e 957 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
Kojto 120:7c328cabac7e 958 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
Kojto 120:7c328cabac7e 959
Kojto 120:7c328cabac7e 960 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
Kojto 120:7c328cabac7e 961 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
Kojto 120:7c328cabac7e 962 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
Kojto 120:7c328cabac7e 963
Kojto 120:7c328cabac7e 964 /**
Kojto 120:7c328cabac7e 965 * @}
Kojto 120:7c328cabac7e 966 */
Kojto 120:7c328cabac7e 967
Kojto 120:7c328cabac7e 968 #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
Kojto 120:7c328cabac7e 969 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 120:7c328cabac7e 970 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
Kojto 120:7c328cabac7e 971 * @{
Kojto 120:7c328cabac7e 972 */
Kojto 120:7c328cabac7e 973 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
Kojto 120:7c328cabac7e 974 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
Kojto 120:7c328cabac7e 975 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
Kojto 120:7c328cabac7e 976 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
Kojto 120:7c328cabac7e 977 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
Kojto 120:7c328cabac7e 978
Kojto 120:7c328cabac7e 979 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
Kojto 120:7c328cabac7e 980 #define CM_RGB888 DMA2D_INPUT_RGB888
Kojto 120:7c328cabac7e 981 #define CM_RGB565 DMA2D_INPUT_RGB565
Kojto 120:7c328cabac7e 982 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
Kojto 120:7c328cabac7e 983 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
Kojto 120:7c328cabac7e 984 #define CM_L8 DMA2D_INPUT_L8
Kojto 120:7c328cabac7e 985 #define CM_AL44 DMA2D_INPUT_AL44
Kojto 120:7c328cabac7e 986 #define CM_AL88 DMA2D_INPUT_AL88
Kojto 120:7c328cabac7e 987 #define CM_L4 DMA2D_INPUT_L4
Kojto 120:7c328cabac7e 988 #define CM_A8 DMA2D_INPUT_A8
Kojto 120:7c328cabac7e 989 #define CM_A4 DMA2D_INPUT_A4
Kojto 120:7c328cabac7e 990 /**
Kojto 120:7c328cabac7e 991 * @}
Kojto 120:7c328cabac7e 992 */
Kojto 120:7c328cabac7e 993 #endif /* STM32L4xx || STM32F7*/
Kojto 96:487b796308b0 994
Kojto 96:487b796308b0 995 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
Kojto 96:487b796308b0 996 * @{
Kojto 96:487b796308b0 997 */
Kojto 96:487b796308b0 998
Kojto 96:487b796308b0 999 /**
Kojto 96:487b796308b0 1000 * @}
Kojto 96:487b796308b0 1001 */
Kojto 96:487b796308b0 1002
Kojto 96:487b796308b0 1003 /* Exported functions --------------------------------------------------------*/
Kojto 96:487b796308b0 1004
Kojto 96:487b796308b0 1005 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1006 * @{
Kojto 96:487b796308b0 1007 */
Kojto 96:487b796308b0 1008 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
Kojto 96:487b796308b0 1009 /**
Kojto 96:487b796308b0 1010 * @}
Kojto 96:487b796308b0 1011 */
Kojto 96:487b796308b0 1012
Kojto 96:487b796308b0 1013 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1014 * @{
Kojto 96:487b796308b0 1015 */
Kojto 120:7c328cabac7e 1016 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
Kojto 120:7c328cabac7e 1017 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
Kojto 96:487b796308b0 1018 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
Kojto 96:487b796308b0 1019 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
Kojto 96:487b796308b0 1020 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
Kojto 96:487b796308b0 1021 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
Kojto 96:487b796308b0 1022
Kojto 96:487b796308b0 1023 /*HASH Algorithm Selection*/
Kojto 96:487b796308b0 1024
Kojto 96:487b796308b0 1025 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
Kojto 96:487b796308b0 1026 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
Kojto 96:487b796308b0 1027 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
Kojto 96:487b796308b0 1028 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
Kojto 96:487b796308b0 1029
Kojto 96:487b796308b0 1030 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
Kojto 96:487b796308b0 1031 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
Kojto 96:487b796308b0 1032
Kojto 96:487b796308b0 1033 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
Kojto 96:487b796308b0 1034 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Kojto 96:487b796308b0 1035 /**
Kojto 96:487b796308b0 1036 * @}
Kojto 96:487b796308b0 1037 */
Kojto 96:487b796308b0 1038
Kojto 96:487b796308b0 1039 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1040 * @{
Kojto 96:487b796308b0 1041 */
Kojto 96:487b796308b0 1042 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
Kojto 96:487b796308b0 1043 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
Kojto 96:487b796308b0 1044 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
Kojto 96:487b796308b0 1045 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
Kojto 96:487b796308b0 1046 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
Kojto 96:487b796308b0 1047 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
Kojto 120:7c328cabac7e 1048 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
Kojto 96:487b796308b0 1049 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
Kojto 120:7c328cabac7e 1050 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
Kojto 120:7c328cabac7e 1051 #if defined(STM32L0)
Kojto 120:7c328cabac7e 1052 #else
Kojto 120:7c328cabac7e 1053 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
Kojto 120:7c328cabac7e 1054 #endif
Kojto 120:7c328cabac7e 1055 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
Kojto 120:7c328cabac7e 1056 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
Kojto 96:487b796308b0 1057 /**
Kojto 96:487b796308b0 1058 * @}
Kojto 96:487b796308b0 1059 */
Kojto 96:487b796308b0 1060
Kojto 96:487b796308b0 1061 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1062 * @{
Kojto 96:487b796308b0 1063 */
Kojto 96:487b796308b0 1064 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
Kojto 96:487b796308b0 1065 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
Kojto 96:487b796308b0 1066 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
Kojto 96:487b796308b0 1067 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
Kojto 96:487b796308b0 1068 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
Kojto 96:487b796308b0 1069 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
Kojto 96:487b796308b0 1070 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
Kojto 96:487b796308b0 1071
Kojto 96:487b796308b0 1072 /**
Kojto 96:487b796308b0 1073 * @}
Kojto 96:487b796308b0 1074 */
Kojto 96:487b796308b0 1075
Kojto 96:487b796308b0 1076 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1077 * @{
Kojto 96:487b796308b0 1078 */
Kojto 120:7c328cabac7e 1079 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
Kojto 120:7c328cabac7e 1080 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
Kojto 120:7c328cabac7e 1081 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
Kojto 120:7c328cabac7e 1082 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
Kojto 96:487b796308b0 1083
Kojto 120:7c328cabac7e 1084 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
Kojto 96:487b796308b0 1085 /**
Kojto 96:487b796308b0 1086 * @}
Kojto 96:487b796308b0 1087 */
Kojto 96:487b796308b0 1088
Kojto 96:487b796308b0 1089 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
Kojto 96:487b796308b0 1090 * @{
Kojto 96:487b796308b0 1091 */
Kojto 96:487b796308b0 1092 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
Kojto 96:487b796308b0 1093 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
Kojto 96:487b796308b0 1094 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
Kojto 96:487b796308b0 1095 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
Kojto 96:487b796308b0 1096 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
Kojto 96:487b796308b0 1097 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
Kojto 96:487b796308b0 1098 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
Kojto 96:487b796308b0 1099 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
Kojto 96:487b796308b0 1100 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
Kojto 96:487b796308b0 1101 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
Kojto 96:487b796308b0 1102 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
Kojto 96:487b796308b0 1103 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
Kojto 96:487b796308b0 1104 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
Kojto 96:487b796308b0 1105 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
Kojto 96:487b796308b0 1106 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
Kojto 96:487b796308b0 1107 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
Kojto 96:487b796308b0 1108
Kojto 96:487b796308b0 1109 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
Kojto 96:487b796308b0 1110 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
Kojto 96:487b796308b0 1111 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
Kojto 96:487b796308b0 1112 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
Kojto 96:487b796308b0 1113 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
Kojto 96:487b796308b0 1114 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
Kojto 96:487b796308b0 1115 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
Kojto 96:487b796308b0 1116
Kojto 96:487b796308b0 1117 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
Kojto 96:487b796308b0 1118 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
Kojto 96:487b796308b0 1119
Kojto 96:487b796308b0 1120 #define DBP_BitNumber DBP_BIT_NUMBER
Kojto 96:487b796308b0 1121 #define PVDE_BitNumber PVDE_BIT_NUMBER
Kojto 96:487b796308b0 1122 #define PMODE_BitNumber PMODE_BIT_NUMBER
Kojto 96:487b796308b0 1123 #define EWUP_BitNumber EWUP_BIT_NUMBER
Kojto 96:487b796308b0 1124 #define FPDS_BitNumber FPDS_BIT_NUMBER
Kojto 96:487b796308b0 1125 #define ODEN_BitNumber ODEN_BIT_NUMBER
Kojto 96:487b796308b0 1126 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
Kojto 96:487b796308b0 1127 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
Kojto 96:487b796308b0 1128 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
Kojto 96:487b796308b0 1129 #define BRE_BitNumber BRE_BIT_NUMBER
Kojto 96:487b796308b0 1130
Kojto 96:487b796308b0 1131 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
Kojto 96:487b796308b0 1132
Kojto 96:487b796308b0 1133 /**
Kojto 96:487b796308b0 1134 * @}
Kojto 96:487b796308b0 1135 */
Kojto 96:487b796308b0 1136
Kojto 96:487b796308b0 1137 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1138 * @{
Kojto 96:487b796308b0 1139 */
Kojto 96:487b796308b0 1140 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
Kojto 96:487b796308b0 1141 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
Kojto 96:487b796308b0 1142 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
Kojto 96:487b796308b0 1143 /**
Kojto 96:487b796308b0 1144 * @}
Kojto 96:487b796308b0 1145 */
Kojto 96:487b796308b0 1146
Kojto 96:487b796308b0 1147 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1148 * @{
Kojto 96:487b796308b0 1149 */
Kojto 96:487b796308b0 1150 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
Kojto 96:487b796308b0 1151 /**
Kojto 96:487b796308b0 1152 * @}
Kojto 96:487b796308b0 1153 */
Kojto 96:487b796308b0 1154
Kojto 96:487b796308b0 1155 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1156 * @{
Kojto 96:487b796308b0 1157 */
Kojto 96:487b796308b0 1158 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
Kojto 96:487b796308b0 1159 #define HAL_TIM_DMAError TIM_DMAError
Kojto 96:487b796308b0 1160 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
Kojto 96:487b796308b0 1161 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
Kojto 96:487b796308b0 1162 /**
Kojto 96:487b796308b0 1163 * @}
Kojto 96:487b796308b0 1164 */
Kojto 96:487b796308b0 1165
Kojto 96:487b796308b0 1166 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1167 * @{
Kojto 96:487b796308b0 1168 */
Kojto 96:487b796308b0 1169 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
Kojto 96:487b796308b0 1170 /**
Kojto 96:487b796308b0 1171 * @}
Kojto 96:487b796308b0 1172 */
Kojto 120:7c328cabac7e 1173
Kojto 120:7c328cabac7e 1174 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
Kojto 120:7c328cabac7e 1175 * @{
Kojto 120:7c328cabac7e 1176 */
Kojto 120:7c328cabac7e 1177 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
Kojto 120:7c328cabac7e 1178 /**
Kojto 120:7c328cabac7e 1179 * @}
Kojto 120:7c328cabac7e 1180 */
Kojto 96:487b796308b0 1181
Kojto 96:487b796308b0 1182
Kojto 120:7c328cabac7e 1183 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
Kojto 96:487b796308b0 1184 * @{
Kojto 96:487b796308b0 1185 */
Kojto 96:487b796308b0 1186
Kojto 96:487b796308b0 1187 /**
Kojto 96:487b796308b0 1188 * @}
Kojto 96:487b796308b0 1189 */
Kojto 96:487b796308b0 1190
Kojto 96:487b796308b0 1191 /* Exported macros ------------------------------------------------------------*/
Kojto 96:487b796308b0 1192
Kojto 96:487b796308b0 1193 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1194 * @{
Kojto 96:487b796308b0 1195 */
Kojto 96:487b796308b0 1196 #define AES_IT_CC CRYP_IT_CC
Kojto 96:487b796308b0 1197 #define AES_IT_ERR CRYP_IT_ERR
Kojto 96:487b796308b0 1198 #define AES_FLAG_CCF CRYP_FLAG_CCF
Kojto 96:487b796308b0 1199 /**
Kojto 96:487b796308b0 1200 * @}
Kojto 96:487b796308b0 1201 */
Kojto 96:487b796308b0 1202
Kojto 96:487b796308b0 1203 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1204 * @{
Kojto 96:487b796308b0 1205 */
Kojto 96:487b796308b0 1206 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
Kojto 96:487b796308b0 1207 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
Kojto 96:487b796308b0 1208 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
Kojto 96:487b796308b0 1209 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
Kojto 96:487b796308b0 1210 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
Kojto 96:487b796308b0 1211 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
Kojto 120:7c328cabac7e 1212 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
Kojto 120:7c328cabac7e 1213 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
Kojto 96:487b796308b0 1214 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
Kojto 96:487b796308b0 1215 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
Kojto 96:487b796308b0 1216 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
Kojto 120:7c328cabac7e 1217 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
Kojto 120:7c328cabac7e 1218 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
Kojto 120:7c328cabac7e 1219
Kojto 96:487b796308b0 1220 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
Kojto 96:487b796308b0 1221 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
Kojto 96:487b796308b0 1222 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
Kojto 96:487b796308b0 1223 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
Kojto 96:487b796308b0 1224 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Kojto 96:487b796308b0 1225
Kojto 96:487b796308b0 1226 /**
Kojto 96:487b796308b0 1227 * @}
Kojto 96:487b796308b0 1228 */
Kojto 96:487b796308b0 1229
Kojto 96:487b796308b0 1230
Kojto 96:487b796308b0 1231 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1232 * @{
Kojto 96:487b796308b0 1233 */
Kojto 96:487b796308b0 1234 #define __ADC_ENABLE __HAL_ADC_ENABLE
Kojto 96:487b796308b0 1235 #define __ADC_DISABLE __HAL_ADC_DISABLE
Kojto 96:487b796308b0 1236 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Kojto 96:487b796308b0 1237 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Kojto 96:487b796308b0 1238 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 96:487b796308b0 1239 #define __ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 96:487b796308b0 1240 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Kojto 96:487b796308b0 1241 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Kojto 96:487b796308b0 1242 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Kojto 96:487b796308b0 1243 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Kojto 96:487b796308b0 1244 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Kojto 96:487b796308b0 1245 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Kojto 96:487b796308b0 1246 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Kojto 96:487b796308b0 1247
Kojto 96:487b796308b0 1248 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 96:487b796308b0 1249 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
Kojto 96:487b796308b0 1250 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Kojto 96:487b796308b0 1251 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Kojto 96:487b796308b0 1252 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Kojto 96:487b796308b0 1253 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
Kojto 96:487b796308b0 1254 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Kojto 96:487b796308b0 1255 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Kojto 96:487b796308b0 1256 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Kojto 96:487b796308b0 1257 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Kojto 96:487b796308b0 1258 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Kojto 96:487b796308b0 1259 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Kojto 96:487b796308b0 1260 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Kojto 96:487b796308b0 1261 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
Kojto 96:487b796308b0 1262 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
Kojto 96:487b796308b0 1263 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
Kojto 96:487b796308b0 1264 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
Kojto 96:487b796308b0 1265 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
Kojto 96:487b796308b0 1266 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
Kojto 96:487b796308b0 1267 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
Kojto 96:487b796308b0 1268
Kojto 96:487b796308b0 1269 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
Kojto 96:487b796308b0 1270 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
Kojto 96:487b796308b0 1271 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
Kojto 96:487b796308b0 1272 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
Kojto 96:487b796308b0 1273 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
Kojto 96:487b796308b0 1274 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 96:487b796308b0 1275 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 96:487b796308b0 1276 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
Kojto 96:487b796308b0 1277 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
Kojto 96:487b796308b0 1278 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
Kojto 96:487b796308b0 1279
Kojto 96:487b796308b0 1280 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
Kojto 96:487b796308b0 1281 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
Kojto 96:487b796308b0 1282 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
Kojto 96:487b796308b0 1283 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
Kojto 96:487b796308b0 1284 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
Kojto 96:487b796308b0 1285 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
Kojto 96:487b796308b0 1286 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
Kojto 96:487b796308b0 1287 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
Kojto 96:487b796308b0 1288
Kojto 96:487b796308b0 1289 #define __HAL_ADC_SQR1 ADC_SQR1
Kojto 96:487b796308b0 1290 #define __HAL_ADC_SMPR1 ADC_SMPR1
Kojto 96:487b796308b0 1291 #define __HAL_ADC_SMPR2 ADC_SMPR2
Kojto 96:487b796308b0 1292 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
Kojto 96:487b796308b0 1293 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
Kojto 96:487b796308b0 1294 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
Kojto 96:487b796308b0 1295 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
Kojto 96:487b796308b0 1296 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
Kojto 96:487b796308b0 1297 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
Kojto 96:487b796308b0 1298 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
Kojto 96:487b796308b0 1299 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
Kojto 96:487b796308b0 1300 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 96:487b796308b0 1301 #define __HAL_ADC_JSQR ADC_JSQR
Kojto 96:487b796308b0 1302
Kojto 96:487b796308b0 1303 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
Kojto 96:487b796308b0 1304 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
Kojto 96:487b796308b0 1305 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Kojto 96:487b796308b0 1306 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
Kojto 96:487b796308b0 1307 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Kojto 96:487b796308b0 1308 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
Kojto 96:487b796308b0 1309 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Kojto 96:487b796308b0 1310 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
Kojto 96:487b796308b0 1311
Kojto 96:487b796308b0 1312 /**
Kojto 96:487b796308b0 1313 * @}
Kojto 96:487b796308b0 1314 */
Kojto 96:487b796308b0 1315
Kojto 96:487b796308b0 1316 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1317 * @{
Kojto 96:487b796308b0 1318 */
Kojto 96:487b796308b0 1319 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
Kojto 96:487b796308b0 1320 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
Kojto 96:487b796308b0 1321 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
Kojto 120:7c328cabac7e 1322 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
Kojto 120:7c328cabac7e 1323
Kojto 96:487b796308b0 1324 /**
Kojto 96:487b796308b0 1325 * @}
Kojto 96:487b796308b0 1326 */
Kojto 96:487b796308b0 1327
Kojto 96:487b796308b0 1328 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1329 * @{
Kojto 96:487b796308b0 1330 */
Kojto 96:487b796308b0 1331 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
Kojto 96:487b796308b0 1332 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
Kojto 96:487b796308b0 1333 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
Kojto 96:487b796308b0 1334 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
Kojto 96:487b796308b0 1335 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
Kojto 96:487b796308b0 1336 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
Kojto 96:487b796308b0 1337 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
Kojto 96:487b796308b0 1338 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
Kojto 96:487b796308b0 1339 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
Kojto 96:487b796308b0 1340 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
Kojto 96:487b796308b0 1341 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
Kojto 96:487b796308b0 1342 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
Kojto 96:487b796308b0 1343 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
Kojto 96:487b796308b0 1344 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
Kojto 96:487b796308b0 1345 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
Kojto 96:487b796308b0 1346 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
Kojto 96:487b796308b0 1347
Kojto 96:487b796308b0 1348 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
Kojto 96:487b796308b0 1349 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
Kojto 96:487b796308b0 1350 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
Kojto 96:487b796308b0 1351 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
Kojto 96:487b796308b0 1352 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
Kojto 96:487b796308b0 1353 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
Kojto 96:487b796308b0 1354 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
Kojto 96:487b796308b0 1355 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
Kojto 96:487b796308b0 1356 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
Kojto 96:487b796308b0 1357 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
Kojto 96:487b796308b0 1358 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
Kojto 96:487b796308b0 1359 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
Kojto 96:487b796308b0 1360 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Kojto 96:487b796308b0 1361 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Kojto 96:487b796308b0 1362
Kojto 96:487b796308b0 1363
Kojto 96:487b796308b0 1364 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Kojto 96:487b796308b0 1365 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Kojto 96:487b796308b0 1366 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Kojto 96:487b796308b0 1367 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
Kojto 96:487b796308b0 1368 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
Kojto 96:487b796308b0 1369 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Kojto 96:487b796308b0 1370 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Kojto 96:487b796308b0 1371 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Kojto 96:487b796308b0 1372 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Kojto 96:487b796308b0 1373 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Kojto 96:487b796308b0 1374 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Kojto 96:487b796308b0 1375 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
Kojto 96:487b796308b0 1376 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Kojto 96:487b796308b0 1377 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Kojto 96:487b796308b0 1378 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Kojto 96:487b796308b0 1379 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Kojto 96:487b796308b0 1380 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Kojto 96:487b796308b0 1381 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Kojto 96:487b796308b0 1382 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Kojto 96:487b796308b0 1383 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
Kojto 96:487b796308b0 1384 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
Kojto 96:487b796308b0 1385 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
Kojto 96:487b796308b0 1386 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
Kojto 96:487b796308b0 1387 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
Kojto 96:487b796308b0 1388
Kojto 96:487b796308b0 1389 /**
Kojto 96:487b796308b0 1390 * @}
Kojto 96:487b796308b0 1391 */
Kojto 96:487b796308b0 1392
Kojto 96:487b796308b0 1393 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1394 * @{
Kojto 96:487b796308b0 1395 */
Kojto 120:7c328cabac7e 1396 #if defined(STM32F3)
Kojto 120:7c328cabac7e 1397 #define COMP_START __HAL_COMP_ENABLE
Kojto 120:7c328cabac7e 1398 #define COMP_STOP __HAL_COMP_DISABLE
Kojto 120:7c328cabac7e 1399 #define COMP_LOCK __HAL_COMP_LOCK
Kojto 120:7c328cabac7e 1400
Kojto 120:7c328cabac7e 1401 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 120:7c328cabac7e 1402 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1403 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1404 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1405 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1406 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1407 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1408 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1409 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1410 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1411 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1412 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1413 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1414 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1415 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1416 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
Kojto 120:7c328cabac7e 1417 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1418 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1419 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
Kojto 120:7c328cabac7e 1420 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1421 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1422 __HAL_COMP_COMP6_EXTI_GET_FLAG())
Kojto 120:7c328cabac7e 1423 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1424 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1425 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
Kojto 120:7c328cabac7e 1426 # endif
Kojto 120:7c328cabac7e 1427 # if defined(STM32F302xE) || defined(STM32F302xC)
Kojto 120:7c328cabac7e 1428 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1429 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1430 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1431 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1432 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1433 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1434 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1435 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1436 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1437 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1438 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1439 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1440 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1441 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1442 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1443 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1444 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1445 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1446 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1447 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
Kojto 120:7c328cabac7e 1448 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1449 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1450 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1451 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
Kojto 120:7c328cabac7e 1452 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1453 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1454 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1455 __HAL_COMP_COMP6_EXTI_GET_FLAG())
Kojto 120:7c328cabac7e 1456 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1457 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1458 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1459 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
Kojto 120:7c328cabac7e 1460 # endif
Kojto 120:7c328cabac7e 1461 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 120:7c328cabac7e 1462 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1463 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1464 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1465 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1466 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1467 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1468 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1469 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1470 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1471 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1472 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1473 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1474 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1475 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1476 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1477 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1478 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1479 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1480 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1481 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1482 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1483 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1484 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1485 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1486 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1487 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1488 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1489 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1490 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1491 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1492 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1493 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1494 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1495 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1496 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
Kojto 120:7c328cabac7e 1497 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1498 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1499 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1500 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1501 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1502 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1503 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
Kojto 120:7c328cabac7e 1504 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1505 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1506 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1507 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1508 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1509 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1510 __HAL_COMP_COMP7_EXTI_GET_FLAG())
Kojto 120:7c328cabac7e 1511 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1512 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1513 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1514 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1515 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1516 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1517 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
Kojto 120:7c328cabac7e 1518 # endif
Kojto 120:7c328cabac7e 1519 # if defined(STM32F373xC) ||defined(STM32F378xx)
Kojto 96:487b796308b0 1520 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 96:487b796308b0 1521 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1522 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 96:487b796308b0 1523 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto 96:487b796308b0 1524 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 96:487b796308b0 1525 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1526 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 96:487b796308b0 1527 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1528 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 96:487b796308b0 1529 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto 120:7c328cabac7e 1530 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 96:487b796308b0 1531 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto 120:7c328cabac7e 1532 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 96:487b796308b0 1533 __HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto 120:7c328cabac7e 1534 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 96:487b796308b0 1535 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto 120:7c328cabac7e 1536 # endif
Kojto 120:7c328cabac7e 1537 #else
Kojto 120:7c328cabac7e 1538 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1539 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1540 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 120:7c328cabac7e 1541 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto 120:7c328cabac7e 1542 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1543 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1544 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 120:7c328cabac7e 1545 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto 120:7c328cabac7e 1546 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 1547 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto 120:7c328cabac7e 1548 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 1549 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto 120:7c328cabac7e 1550 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 1551 __HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto 120:7c328cabac7e 1552 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 1553 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto 120:7c328cabac7e 1554 #endif
Kojto 120:7c328cabac7e 1555
Kojto 96:487b796308b0 1556 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
Kojto 96:487b796308b0 1557
Kojto 120:7c328cabac7e 1558 #if defined(STM32L0) || defined(STM32L4)
Kojto 120:7c328cabac7e 1559 /* Note: On these STM32 families, the only argument of this macro */
Kojto 120:7c328cabac7e 1560 /* is COMP_FLAG_LOCK. */
Kojto 120:7c328cabac7e 1561 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
Kojto 120:7c328cabac7e 1562 /* argument. */
Kojto 120:7c328cabac7e 1563 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
Kojto 120:7c328cabac7e 1564 #endif
Kojto 120:7c328cabac7e 1565 /**
Kojto 120:7c328cabac7e 1566 * @}
Kojto 120:7c328cabac7e 1567 */
Kojto 120:7c328cabac7e 1568
Kojto 120:7c328cabac7e 1569 #if defined(STM32L0) || defined(STM32L4)
Kojto 120:7c328cabac7e 1570 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
Kojto 120:7c328cabac7e 1571 * @{
Kojto 120:7c328cabac7e 1572 */
Kojto 120:7c328cabac7e 1573 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
Kojto 120:7c328cabac7e 1574 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
Kojto 120:7c328cabac7e 1575 /**
Kojto 120:7c328cabac7e 1576 * @}
Kojto 120:7c328cabac7e 1577 */
Kojto 120:7c328cabac7e 1578 #endif
Kojto 120:7c328cabac7e 1579
Kojto 120:7c328cabac7e 1580 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 120:7c328cabac7e 1581 * @{
Kojto 120:7c328cabac7e 1582 */
Kojto 120:7c328cabac7e 1583
Kojto 120:7c328cabac7e 1584 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
Kojto 120:7c328cabac7e 1585 ((WAVE) == DAC_WAVE_NOISE)|| \
Kojto 120:7c328cabac7e 1586 ((WAVE) == DAC_WAVE_TRIANGLE))
Kojto 120:7c328cabac7e 1587
Kojto 96:487b796308b0 1588 /**
Kojto 96:487b796308b0 1589 * @}
Kojto 96:487b796308b0 1590 */
Kojto 96:487b796308b0 1591
Kojto 96:487b796308b0 1592 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1593 * @{
Kojto 96:487b796308b0 1594 */
Kojto 96:487b796308b0 1595
Kojto 96:487b796308b0 1596 #define IS_WRPAREA IS_OB_WRPAREA
Kojto 96:487b796308b0 1597 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
Kojto 96:487b796308b0 1598 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
Kojto 96:487b796308b0 1599 #define IS_TYPEERASE IS_FLASH_TYPEERASE
Kojto 120:7c328cabac7e 1600 #define IS_NBSECTORS IS_FLASH_NBSECTORS
Kojto 120:7c328cabac7e 1601 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
Kojto 96:487b796308b0 1602
Kojto 96:487b796308b0 1603 /**
Kojto 96:487b796308b0 1604 * @}
Kojto 96:487b796308b0 1605 */
Kojto 96:487b796308b0 1606
Kojto 96:487b796308b0 1607 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1608 * @{
Kojto 96:487b796308b0 1609 */
Kojto 96:487b796308b0 1610
Kojto 96:487b796308b0 1611 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
Kojto 96:487b796308b0 1612 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
Kojto 96:487b796308b0 1613 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Kojto 96:487b796308b0 1614 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
Kojto 96:487b796308b0 1615 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Kojto 96:487b796308b0 1616 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Kojto 96:487b796308b0 1617 #define __HAL_I2C_SPEED I2C_SPEED
Kojto 96:487b796308b0 1618 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Kojto 96:487b796308b0 1619 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Kojto 96:487b796308b0 1620 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Kojto 96:487b796308b0 1621 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Kojto 96:487b796308b0 1622 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Kojto 96:487b796308b0 1623 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Kojto 96:487b796308b0 1624 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
Kojto 96:487b796308b0 1625 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
Kojto 96:487b796308b0 1626 /**
Kojto 96:487b796308b0 1627 * @}
Kojto 96:487b796308b0 1628 */
Kojto 96:487b796308b0 1629
Kojto 96:487b796308b0 1630 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1631 * @{
Kojto 96:487b796308b0 1632 */
Kojto 96:487b796308b0 1633
Kojto 96:487b796308b0 1634 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
Kojto 96:487b796308b0 1635 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
Kojto 96:487b796308b0 1636
Kojto 96:487b796308b0 1637 /**
Kojto 96:487b796308b0 1638 * @}
Kojto 96:487b796308b0 1639 */
Kojto 96:487b796308b0 1640
Kojto 96:487b796308b0 1641 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1642 * @{
Kojto 96:487b796308b0 1643 */
Kojto 96:487b796308b0 1644
Kojto 96:487b796308b0 1645 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
Kojto 96:487b796308b0 1646 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
Kojto 96:487b796308b0 1647
Kojto 96:487b796308b0 1648 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 96:487b796308b0 1649 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 96:487b796308b0 1650 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 96:487b796308b0 1651 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 96:487b796308b0 1652
Kojto 96:487b796308b0 1653 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
Kojto 96:487b796308b0 1654
Kojto 96:487b796308b0 1655
Kojto 96:487b796308b0 1656 /**
Kojto 96:487b796308b0 1657 * @}
Kojto 96:487b796308b0 1658 */
Kojto 96:487b796308b0 1659
Kojto 96:487b796308b0 1660
Kojto 96:487b796308b0 1661 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1662 * @{
Kojto 96:487b796308b0 1663 */
Kojto 96:487b796308b0 1664 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
Kojto 96:487b796308b0 1665 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
Kojto 96:487b796308b0 1666 /**
Kojto 96:487b796308b0 1667 * @}
Kojto 96:487b796308b0 1668 */
Kojto 96:487b796308b0 1669
Kojto 96:487b796308b0 1670
Kojto 96:487b796308b0 1671 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1672 * @{
Kojto 96:487b796308b0 1673 */
Kojto 96:487b796308b0 1674
Kojto 96:487b796308b0 1675 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Kojto 96:487b796308b0 1676 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
Kojto 96:487b796308b0 1677 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
Kojto 96:487b796308b0 1678
Kojto 96:487b796308b0 1679 /**
Kojto 96:487b796308b0 1680 * @}
Kojto 96:487b796308b0 1681 */
Kojto 120:7c328cabac7e 1682
Kojto 120:7c328cabac7e 1683
Kojto 120:7c328cabac7e 1684 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
Kojto 120:7c328cabac7e 1685 * @{
Kojto 120:7c328cabac7e 1686 */
Kojto 120:7c328cabac7e 1687 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
Kojto 120:7c328cabac7e 1688 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
Kojto 120:7c328cabac7e 1689 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
Kojto 120:7c328cabac7e 1690 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
Kojto 120:7c328cabac7e 1691 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
Kojto 120:7c328cabac7e 1692 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
Kojto 120:7c328cabac7e 1693 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
Kojto 120:7c328cabac7e 1694 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
Kojto 120:7c328cabac7e 1695 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
Kojto 120:7c328cabac7e 1696 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
Kojto 120:7c328cabac7e 1697 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
Kojto 120:7c328cabac7e 1698 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
Kojto 120:7c328cabac7e 1699 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
Kojto 120:7c328cabac7e 1700
Kojto 120:7c328cabac7e 1701 /**
Kojto 120:7c328cabac7e 1702 * @}
Kojto 120:7c328cabac7e 1703 */
Kojto 120:7c328cabac7e 1704
Kojto 96:487b796308b0 1705
Kojto 96:487b796308b0 1706 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 1707 * @{
Kojto 96:487b796308b0 1708 */
Kojto 96:487b796308b0 1709 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 96:487b796308b0 1710 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 96:487b796308b0 1711 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 96:487b796308b0 1712 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 1713 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 96:487b796308b0 1714 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 1715 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
Kojto 96:487b796308b0 1716 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
Kojto 96:487b796308b0 1717 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
Kojto 96:487b796308b0 1718 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
Kojto 96:487b796308b0 1719 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
Kojto 96:487b796308b0 1720 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
Kojto 96:487b796308b0 1721 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
Kojto 96:487b796308b0 1722 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
Kojto 96:487b796308b0 1723 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
Kojto 96:487b796308b0 1724 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
Kojto 120:7c328cabac7e 1725 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
Kojto 96:487b796308b0 1726 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 96:487b796308b0 1727 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 96:487b796308b0 1728 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 96:487b796308b0 1729 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 1730 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 96:487b796308b0 1731 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 1732 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 1733 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 120:7c328cabac7e 1734 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
Kojto 120:7c328cabac7e 1735 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
Kojto 96:487b796308b0 1736 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Kojto 96:487b796308b0 1737 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Kojto 96:487b796308b0 1738 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Kojto 96:487b796308b0 1739 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Kojto 96:487b796308b0 1740 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Kojto 96:487b796308b0 1741 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 1742 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
Kojto 96:487b796308b0 1743 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
Kojto 96:487b796308b0 1744
Kojto 96:487b796308b0 1745 #if defined (STM32F4)
Kojto 96:487b796308b0 1746 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
Kojto 96:487b796308b0 1747 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
Kojto 96:487b796308b0 1748 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
Kojto 96:487b796308b0 1749 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
Kojto 96:487b796308b0 1750 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
Kojto 96:487b796308b0 1751 #else
Kojto 96:487b796308b0 1752 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 1753 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
Kojto 96:487b796308b0 1754 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
Kojto 96:487b796308b0 1755 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
Kojto 96:487b796308b0 1756 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
Kojto 96:487b796308b0 1757 #endif /* STM32F4 */
Kojto 96:487b796308b0 1758 /**
Kojto 96:487b796308b0 1759 * @}
Kojto 96:487b796308b0 1760 */
Kojto 96:487b796308b0 1761
Kojto 96:487b796308b0 1762
Kojto 120:7c328cabac7e 1763 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
Kojto 96:487b796308b0 1764 * @{
Kojto 96:487b796308b0 1765 */
Kojto 120:7c328cabac7e 1766
Kojto 120:7c328cabac7e 1767 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
Kojto 120:7c328cabac7e 1768 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
Kojto 120:7c328cabac7e 1769
Kojto 120:7c328cabac7e 1770 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
Kojto 120:7c328cabac7e 1771 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
Kojto 120:7c328cabac7e 1772
Kojto 96:487b796308b0 1773 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
Kojto 96:487b796308b0 1774 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
Kojto 96:487b796308b0 1775 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1776 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1777 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
Kojto 96:487b796308b0 1778 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
Kojto 120:7c328cabac7e 1779 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
Kojto 120:7c328cabac7e 1780 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
Kojto 120:7c328cabac7e 1781 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
Kojto 120:7c328cabac7e 1782 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
Kojto 120:7c328cabac7e 1783 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 1784 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1785 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
Kojto 96:487b796308b0 1786 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
Kojto 96:487b796308b0 1787 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
Kojto 96:487b796308b0 1788 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
Kojto 96:487b796308b0 1789 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
Kojto 96:487b796308b0 1790 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
Kojto 96:487b796308b0 1791 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
Kojto 96:487b796308b0 1792 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Kojto 96:487b796308b0 1793 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
Kojto 96:487b796308b0 1794 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Kojto 96:487b796308b0 1795 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1796 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1797 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
Kojto 96:487b796308b0 1798 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
Kojto 96:487b796308b0 1799 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1800 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1801 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
Kojto 96:487b796308b0 1802 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
Kojto 96:487b796308b0 1803 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 96:487b796308b0 1804 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
Kojto 96:487b796308b0 1805 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto 96:487b796308b0 1806 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto 96:487b796308b0 1807 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto 96:487b796308b0 1808 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto 96:487b796308b0 1809 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
Kojto 96:487b796308b0 1810 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
Kojto 96:487b796308b0 1811 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
Kojto 96:487b796308b0 1812 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
Kojto 96:487b796308b0 1813 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Kojto 96:487b796308b0 1814 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
Kojto 96:487b796308b0 1815 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
Kojto 96:487b796308b0 1816 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
Kojto 96:487b796308b0 1817 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
Kojto 96:487b796308b0 1818 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
Kojto 96:487b796308b0 1819 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
Kojto 96:487b796308b0 1820 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
Kojto 96:487b796308b0 1821 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
Kojto 96:487b796308b0 1822 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
Kojto 96:487b796308b0 1823 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
Kojto 96:487b796308b0 1824 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
Kojto 96:487b796308b0 1825 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 96:487b796308b0 1826 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 96:487b796308b0 1827 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1828 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1829 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 96:487b796308b0 1830 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 120:7c328cabac7e 1831 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 120:7c328cabac7e 1832 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 120:7c328cabac7e 1833 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 120:7c328cabac7e 1834 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 96:487b796308b0 1835 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
Kojto 96:487b796308b0 1836 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
Kojto 96:487b796308b0 1837 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
Kojto 96:487b796308b0 1838 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
Kojto 96:487b796308b0 1839 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
Kojto 96:487b796308b0 1840 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
Kojto 120:7c328cabac7e 1841 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
Kojto 120:7c328cabac7e 1842 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
Kojto 120:7c328cabac7e 1843 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
Kojto 120:7c328cabac7e 1844 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
Kojto 120:7c328cabac7e 1845 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 1846 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1847 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Kojto 96:487b796308b0 1848 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Kojto 96:487b796308b0 1849 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Kojto 96:487b796308b0 1850 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Kojto 96:487b796308b0 1851 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1852 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1853 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Kojto 96:487b796308b0 1854 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
Kojto 96:487b796308b0 1855 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
Kojto 96:487b796308b0 1856 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Kojto 96:487b796308b0 1857 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Kojto 96:487b796308b0 1858 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Kojto 96:487b796308b0 1859 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Kojto 96:487b796308b0 1860 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Kojto 96:487b796308b0 1861 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1862 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1863 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Kojto 96:487b796308b0 1864 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Kojto 120:7c328cabac7e 1865 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
Kojto 120:7c328cabac7e 1866 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
Kojto 120:7c328cabac7e 1867 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
Kojto 120:7c328cabac7e 1868 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
Kojto 96:487b796308b0 1869 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
Kojto 96:487b796308b0 1870 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Kojto 96:487b796308b0 1871 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1872 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1873 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Kojto 96:487b796308b0 1874 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Kojto 96:487b796308b0 1875 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Kojto 96:487b796308b0 1876 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Kojto 96:487b796308b0 1877 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1878 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1879 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
Kojto 96:487b796308b0 1880 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
Kojto 96:487b796308b0 1881 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kojto 96:487b796308b0 1882 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kojto 96:487b796308b0 1883 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1884 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1885 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
Kojto 96:487b796308b0 1886 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
Kojto 96:487b796308b0 1887 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
Kojto 96:487b796308b0 1888 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
Kojto 96:487b796308b0 1889 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
Kojto 96:487b796308b0 1890 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
Kojto 96:487b796308b0 1891 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
Kojto 96:487b796308b0 1892 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
Kojto 96:487b796308b0 1893 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
Kojto 96:487b796308b0 1894 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
Kojto 96:487b796308b0 1895 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
Kojto 96:487b796308b0 1896 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
Kojto 96:487b796308b0 1897 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
Kojto 96:487b796308b0 1898 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
Kojto 96:487b796308b0 1899 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1900 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1901 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
Kojto 96:487b796308b0 1902 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
Kojto 120:7c328cabac7e 1903 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
Kojto 120:7c328cabac7e 1904 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
Kojto 120:7c328cabac7e 1905 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
Kojto 120:7c328cabac7e 1906 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
Kojto 120:7c328cabac7e 1907 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 1908 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1909 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
Kojto 96:487b796308b0 1910 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
Kojto 96:487b796308b0 1911 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1912 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1913 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
Kojto 96:487b796308b0 1914 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
Kojto 96:487b796308b0 1915 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
Kojto 96:487b796308b0 1916 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
Kojto 96:487b796308b0 1917 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
Kojto 96:487b796308b0 1918 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
Kojto 96:487b796308b0 1919 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1920 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1921 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
Kojto 96:487b796308b0 1922 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Kojto 96:487b796308b0 1923 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
Kojto 96:487b796308b0 1924 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Kojto 96:487b796308b0 1925 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1926 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1927 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
Kojto 96:487b796308b0 1928 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
Kojto 96:487b796308b0 1929 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
Kojto 96:487b796308b0 1930 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
Kojto 96:487b796308b0 1931 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1932 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1933 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
Kojto 96:487b796308b0 1934 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
Kojto 96:487b796308b0 1935 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
Kojto 96:487b796308b0 1936 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
Kojto 96:487b796308b0 1937 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1938 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1939 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
Kojto 96:487b796308b0 1940 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
Kojto 96:487b796308b0 1941 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Kojto 96:487b796308b0 1942 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
Kojto 96:487b796308b0 1943 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1944 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1945 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
Kojto 96:487b796308b0 1946 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
Kojto 96:487b796308b0 1947 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
Kojto 96:487b796308b0 1948 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
Kojto 96:487b796308b0 1949 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1950 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1951 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
Kojto 96:487b796308b0 1952 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
Kojto 96:487b796308b0 1953 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
Kojto 96:487b796308b0 1954 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
Kojto 96:487b796308b0 1955 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1956 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1957 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
Kojto 96:487b796308b0 1958 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
Kojto 96:487b796308b0 1959 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
Kojto 96:487b796308b0 1960 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
Kojto 96:487b796308b0 1961 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1962 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1963 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
Kojto 96:487b796308b0 1964 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
Kojto 96:487b796308b0 1965 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
Kojto 96:487b796308b0 1966 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
Kojto 96:487b796308b0 1967 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1968 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1969 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
Kojto 96:487b796308b0 1970 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
Kojto 96:487b796308b0 1971 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
Kojto 96:487b796308b0 1972 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
Kojto 96:487b796308b0 1973 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1974 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1975 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Kojto 96:487b796308b0 1976 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Kojto 96:487b796308b0 1977 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Kojto 96:487b796308b0 1978 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Kojto 96:487b796308b0 1979 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1980 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1981 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Kojto 96:487b796308b0 1982 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
Kojto 96:487b796308b0 1983 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
Kojto 96:487b796308b0 1984 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Kojto 96:487b796308b0 1985 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1986 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1987 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Kojto 96:487b796308b0 1988 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Kojto 96:487b796308b0 1989 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Kojto 96:487b796308b0 1990 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Kojto 96:487b796308b0 1991 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1992 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1993 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Kojto 96:487b796308b0 1994 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Kojto 96:487b796308b0 1995 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Kojto 96:487b796308b0 1996 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Kojto 96:487b796308b0 1997 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 1998 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 1999 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Kojto 96:487b796308b0 2000 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Kojto 96:487b796308b0 2001 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Kojto 96:487b796308b0 2002 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Kojto 96:487b796308b0 2003 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2004 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2005 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
Kojto 96:487b796308b0 2006 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
Kojto 96:487b796308b0 2007 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
Kojto 96:487b796308b0 2008 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
Kojto 96:487b796308b0 2009 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2010 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2011 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
Kojto 96:487b796308b0 2012 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
Kojto 96:487b796308b0 2013 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
Kojto 96:487b796308b0 2014 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
Kojto 96:487b796308b0 2015 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2016 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2017 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
Kojto 96:487b796308b0 2018 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
Kojto 96:487b796308b0 2019 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
Kojto 96:487b796308b0 2020 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
Kojto 96:487b796308b0 2021 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2022 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2023 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
Kojto 96:487b796308b0 2024 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
Kojto 96:487b796308b0 2025 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
Kojto 96:487b796308b0 2026 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
Kojto 96:487b796308b0 2027 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2028 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2029 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
Kojto 96:487b796308b0 2030 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
Kojto 96:487b796308b0 2031 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
Kojto 96:487b796308b0 2032 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
Kojto 96:487b796308b0 2033 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2034 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2035 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Kojto 96:487b796308b0 2036 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
Kojto 96:487b796308b0 2037 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Kojto 96:487b796308b0 2038 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
Kojto 96:487b796308b0 2039 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2040 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2041 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
Kojto 96:487b796308b0 2042 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
Kojto 96:487b796308b0 2043 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
Kojto 96:487b796308b0 2044 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
Kojto 96:487b796308b0 2045 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2046 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2047 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
Kojto 96:487b796308b0 2048 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
Kojto 96:487b796308b0 2049 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 96:487b796308b0 2050 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 96:487b796308b0 2051 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
Kojto 96:487b796308b0 2052 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
Kojto 96:487b796308b0 2053 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2054 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2055 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
Kojto 96:487b796308b0 2056 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
Kojto 96:487b796308b0 2057 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
Kojto 96:487b796308b0 2058 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
Kojto 96:487b796308b0 2059 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2060 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2061 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
Kojto 96:487b796308b0 2062 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
Kojto 96:487b796308b0 2063 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
Kojto 96:487b796308b0 2064 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
Kojto 96:487b796308b0 2065 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2066 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2067 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
Kojto 96:487b796308b0 2068 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
Kojto 96:487b796308b0 2069 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
Kojto 96:487b796308b0 2070 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
Kojto 96:487b796308b0 2071 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2072 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2073 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
Kojto 96:487b796308b0 2074 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
Kojto 96:487b796308b0 2075 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
Kojto 96:487b796308b0 2076 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
Kojto 96:487b796308b0 2077 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2078 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2079 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2080 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2081 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
Kojto 96:487b796308b0 2082 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
Kojto 96:487b796308b0 2083 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2084 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2085 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
Kojto 96:487b796308b0 2086 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
Kojto 96:487b796308b0 2087 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
Kojto 96:487b796308b0 2088 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Kojto 96:487b796308b0 2089 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2090 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2091 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Kojto 96:487b796308b0 2092 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Kojto 96:487b796308b0 2093 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Kojto 96:487b796308b0 2094 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Kojto 96:487b796308b0 2095 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2096 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2097 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Kojto 96:487b796308b0 2098 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Kojto 96:487b796308b0 2099 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Kojto 96:487b796308b0 2100 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Kojto 96:487b796308b0 2101 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Kojto 96:487b796308b0 2102 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Kojto 96:487b796308b0 2103 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Kojto 96:487b796308b0 2104 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Kojto 96:487b796308b0 2105 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Kojto 96:487b796308b0 2106 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Kojto 96:487b796308b0 2107 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Kojto 96:487b796308b0 2108 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Kojto 96:487b796308b0 2109 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Kojto 96:487b796308b0 2110 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
Kojto 96:487b796308b0 2111 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Kojto 96:487b796308b0 2112 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Kojto 96:487b796308b0 2113 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Kojto 96:487b796308b0 2114 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Kojto 96:487b796308b0 2115 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Kojto 96:487b796308b0 2116 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Kojto 96:487b796308b0 2117 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Kojto 96:487b796308b0 2118 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
Kojto 96:487b796308b0 2119 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
Kojto 96:487b796308b0 2120 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
Kojto 96:487b796308b0 2121 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2122 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2123 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
Kojto 96:487b796308b0 2124 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
Kojto 96:487b796308b0 2125 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
Kojto 96:487b796308b0 2126 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
Kojto 96:487b796308b0 2127 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2128 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2129 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
Kojto 96:487b796308b0 2130 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
Kojto 96:487b796308b0 2131 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
Kojto 96:487b796308b0 2132 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
Kojto 96:487b796308b0 2133 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2134 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2135 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
Kojto 96:487b796308b0 2136 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
Kojto 96:487b796308b0 2137 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
Kojto 96:487b796308b0 2138 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
Kojto 96:487b796308b0 2139 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2140 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2141 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
Kojto 96:487b796308b0 2142 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
Kojto 96:487b796308b0 2143 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
Kojto 96:487b796308b0 2144 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
Kojto 96:487b796308b0 2145 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2146 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2147 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
Kojto 96:487b796308b0 2148 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
Kojto 96:487b796308b0 2149 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
Kojto 96:487b796308b0 2150 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
Kojto 96:487b796308b0 2151 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2152 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2153 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
Kojto 96:487b796308b0 2154 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
Kojto 96:487b796308b0 2155 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
Kojto 96:487b796308b0 2156 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
Kojto 96:487b796308b0 2157 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2158 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2159 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
Kojto 96:487b796308b0 2160 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
Kojto 96:487b796308b0 2161 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Kojto 96:487b796308b0 2162 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
Kojto 96:487b796308b0 2163 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2164 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2165 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Kojto 96:487b796308b0 2166 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
Kojto 96:487b796308b0 2167 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
Kojto 96:487b796308b0 2168 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
Kojto 96:487b796308b0 2169 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2170 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2171 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
Kojto 96:487b796308b0 2172 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
Kojto 96:487b796308b0 2173 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
Kojto 96:487b796308b0 2174 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
Kojto 96:487b796308b0 2175 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2176 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2177 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
Kojto 96:487b796308b0 2178 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
Kojto 96:487b796308b0 2179 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
Kojto 96:487b796308b0 2180 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
Kojto 96:487b796308b0 2181 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
Kojto 96:487b796308b0 2182 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Kojto 96:487b796308b0 2183 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
Kojto 96:487b796308b0 2184 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
Kojto 96:487b796308b0 2185 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2186 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2187 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
Kojto 96:487b796308b0 2188 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
Kojto 96:487b796308b0 2189 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Kojto 96:487b796308b0 2190 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Kojto 96:487b796308b0 2191 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2192 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2193 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
Kojto 96:487b796308b0 2194 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
Kojto 96:487b796308b0 2195 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Kojto 96:487b796308b0 2196 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Kojto 96:487b796308b0 2197 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2198 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2199 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Kojto 96:487b796308b0 2200 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Kojto 96:487b796308b0 2201 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
Kojto 96:487b796308b0 2202 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
Kojto 96:487b796308b0 2203 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2204 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2205 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
Kojto 96:487b796308b0 2206 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
Kojto 96:487b796308b0 2207 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
Kojto 96:487b796308b0 2208 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
Kojto 96:487b796308b0 2209 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2210 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2211 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
Kojto 96:487b796308b0 2212 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
Kojto 96:487b796308b0 2213 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
Kojto 96:487b796308b0 2214 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
Kojto 96:487b796308b0 2215 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2216 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2217 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Kojto 96:487b796308b0 2218 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Kojto 120:7c328cabac7e 2219 #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
Kojto 120:7c328cabac7e 2220 #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
Kojto 120:7c328cabac7e 2221 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2222 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2223 #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
Kojto 120:7c328cabac7e 2224 #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
Kojto 120:7c328cabac7e 2225 #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
Kojto 120:7c328cabac7e 2226 #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
Kojto 120:7c328cabac7e 2227 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2228 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2229 #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
Kojto 120:7c328cabac7e 2230 #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
Kojto 120:7c328cabac7e 2231 #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
Kojto 120:7c328cabac7e 2232 #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
Kojto 120:7c328cabac7e 2233 #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
Kojto 120:7c328cabac7e 2234 #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
Kojto 120:7c328cabac7e 2235 #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
Kojto 120:7c328cabac7e 2236 #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
Kojto 120:7c328cabac7e 2237 #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
Kojto 120:7c328cabac7e 2238 #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
Kojto 120:7c328cabac7e 2239 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Kojto 120:7c328cabac7e 2240 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Kojto 120:7c328cabac7e 2241 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Kojto 120:7c328cabac7e 2242 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2243 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2244 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Kojto 96:487b796308b0 2245 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Kojto 96:487b796308b0 2246 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
Kojto 96:487b796308b0 2247 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
Kojto 96:487b796308b0 2248 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
Kojto 96:487b796308b0 2249 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2250 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2251 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
Kojto 96:487b796308b0 2252 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
Kojto 96:487b796308b0 2253 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
Kojto 96:487b796308b0 2254 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
Kojto 96:487b796308b0 2255 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
Kojto 96:487b796308b0 2256 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
Kojto 96:487b796308b0 2257 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2258 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2259 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
Kojto 96:487b796308b0 2260 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
Kojto 96:487b796308b0 2261 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
Kojto 96:487b796308b0 2262 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
Kojto 96:487b796308b0 2263 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2264 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2265 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
Kojto 96:487b796308b0 2266 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
Kojto 96:487b796308b0 2267 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2268 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2269 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
Kojto 96:487b796308b0 2270 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Kojto 96:487b796308b0 2271 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
Kojto 96:487b796308b0 2272 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
Kojto 96:487b796308b0 2273
Kojto 96:487b796308b0 2274 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 96:487b796308b0 2275 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 96:487b796308b0 2276 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2277 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2278 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
Kojto 96:487b796308b0 2279 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
Kojto 96:487b796308b0 2280 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
Kojto 96:487b796308b0 2281 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
Kojto 96:487b796308b0 2282 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2283 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2284 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2285 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2286 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2287 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2288 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2289 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2290 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
Kojto 96:487b796308b0 2291 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
Kojto 96:487b796308b0 2292 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
Kojto 96:487b796308b0 2293 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
Kojto 96:487b796308b0 2294 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
Kojto 96:487b796308b0 2295 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2296 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2297 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
Kojto 96:487b796308b0 2298 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
Kojto 96:487b796308b0 2299 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
Kojto 96:487b796308b0 2300 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
Kojto 96:487b796308b0 2301 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
Kojto 96:487b796308b0 2302 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2303 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2304 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
Kojto 96:487b796308b0 2305 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
Kojto 96:487b796308b0 2306 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
Kojto 96:487b796308b0 2307 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
Kojto 96:487b796308b0 2308 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2309 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2310 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
Kojto 96:487b796308b0 2311 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
Kojto 96:487b796308b0 2312 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
Kojto 96:487b796308b0 2313 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
Kojto 96:487b796308b0 2314 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2315 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2316 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2317 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2318 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2319 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2320 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2321 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2322 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2323 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2324 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2325 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2326 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2327 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Kojto 96:487b796308b0 2328 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Kojto 96:487b796308b0 2329 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2330 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2331 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
Kojto 96:487b796308b0 2332 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Kojto 96:487b796308b0 2333 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Kojto 96:487b796308b0 2334 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Kojto 96:487b796308b0 2335 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Kojto 96:487b796308b0 2336 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Kojto 96:487b796308b0 2337 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2338 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2339 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Kojto 96:487b796308b0 2340 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Kojto 96:487b796308b0 2341 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Kojto 96:487b796308b0 2342 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Kojto 96:487b796308b0 2343 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2344 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2345 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
Kojto 96:487b796308b0 2346 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Kojto 96:487b796308b0 2347 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Kojto 96:487b796308b0 2348 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Kojto 96:487b796308b0 2349 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2350 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2351 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Kojto 96:487b796308b0 2352 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Kojto 96:487b796308b0 2353 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
Kojto 96:487b796308b0 2354 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
Kojto 96:487b796308b0 2355 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2356 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2357 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
Kojto 96:487b796308b0 2358 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
Kojto 96:487b796308b0 2359 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
Kojto 96:487b796308b0 2360 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2361 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2362 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
Kojto 96:487b796308b0 2363 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
Kojto 96:487b796308b0 2364 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
Kojto 96:487b796308b0 2365 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
Kojto 96:487b796308b0 2366 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
Kojto 96:487b796308b0 2367 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
Kojto 96:487b796308b0 2368 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2369 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2370 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Kojto 96:487b796308b0 2371 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Kojto 96:487b796308b0 2372 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Kojto 96:487b796308b0 2373 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Kojto 96:487b796308b0 2374 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2375 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2376 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Kojto 96:487b796308b0 2377 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Kojto 96:487b796308b0 2378 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Kojto 96:487b796308b0 2379 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
Kojto 96:487b796308b0 2380 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
Kojto 96:487b796308b0 2381 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2382 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2383 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2384 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto 120:7c328cabac7e 2385 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto 120:7c328cabac7e 2386 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2387 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2388 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2389 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2390 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
Kojto 120:7c328cabac7e 2391 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
Kojto 120:7c328cabac7e 2392 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto 120:7c328cabac7e 2393 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto 120:7c328cabac7e 2394 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2395 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2396 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
Kojto 120:7c328cabac7e 2397 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
Kojto 120:7c328cabac7e 2398 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 120:7c328cabac7e 2399 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2400 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2401 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2402 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2403 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2404 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2405 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2406 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2407 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2408 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
Kojto 120:7c328cabac7e 2409 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
Kojto 120:7c328cabac7e 2410 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2411 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2412 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 120:7c328cabac7e 2413 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 120:7c328cabac7e 2414 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2415 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2416 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
Kojto 120:7c328cabac7e 2417 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
Kojto 120:7c328cabac7e 2418 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Kojto 96:487b796308b0 2419 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
Kojto 120:7c328cabac7e 2420 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2421 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
Kojto 96:487b796308b0 2422
Kojto 96:487b796308b0 2423 /* alias define maintained for legacy */
Kojto 96:487b796308b0 2424 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 96:487b796308b0 2425 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 96:487b796308b0 2426
Kojto 120:7c328cabac7e 2427 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
Kojto 120:7c328cabac7e 2428 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
Kojto 120:7c328cabac7e 2429 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
Kojto 120:7c328cabac7e 2430 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
Kojto 120:7c328cabac7e 2431 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
Kojto 120:7c328cabac7e 2432 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
Kojto 120:7c328cabac7e 2433 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
Kojto 120:7c328cabac7e 2434 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
Kojto 120:7c328cabac7e 2435 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
Kojto 120:7c328cabac7e 2436 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
Kojto 120:7c328cabac7e 2437 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
Kojto 120:7c328cabac7e 2438 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
Kojto 120:7c328cabac7e 2439 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
Kojto 120:7c328cabac7e 2440 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
Kojto 120:7c328cabac7e 2441 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
Kojto 120:7c328cabac7e 2442 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
Kojto 120:7c328cabac7e 2443 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
Kojto 120:7c328cabac7e 2444 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
Kojto 120:7c328cabac7e 2445 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
Kojto 120:7c328cabac7e 2446 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
Kojto 120:7c328cabac7e 2447 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
Kojto 120:7c328cabac7e 2448 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
Kojto 120:7c328cabac7e 2449
Kojto 120:7c328cabac7e 2450 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
Kojto 120:7c328cabac7e 2451 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
Kojto 120:7c328cabac7e 2452 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
Kojto 120:7c328cabac7e 2453 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
Kojto 120:7c328cabac7e 2454 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
Kojto 120:7c328cabac7e 2455 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
Kojto 120:7c328cabac7e 2456 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
Kojto 120:7c328cabac7e 2457 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
Kojto 120:7c328cabac7e 2458 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
Kojto 120:7c328cabac7e 2459 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
Kojto 120:7c328cabac7e 2460 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
Kojto 120:7c328cabac7e 2461 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
Kojto 120:7c328cabac7e 2462 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
Kojto 120:7c328cabac7e 2463 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
Kojto 120:7c328cabac7e 2464 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
Kojto 120:7c328cabac7e 2465 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
Kojto 120:7c328cabac7e 2466 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
Kojto 120:7c328cabac7e 2467 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
Kojto 120:7c328cabac7e 2468 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
Kojto 120:7c328cabac7e 2469 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
Kojto 120:7c328cabac7e 2470 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
Kojto 120:7c328cabac7e 2471 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
Kojto 120:7c328cabac7e 2472
Kojto 120:7c328cabac7e 2473 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2474 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2475 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2476 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2477 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2478 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2479 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2480 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2481 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2482 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2483 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2484 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2485 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2486 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2487 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2488 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2489 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2490 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2491 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2492 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2493 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2494 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2495 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2496 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2497 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2498 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2499 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2500 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2501 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2502 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2503 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2504 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2505 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2506 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2507 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2508 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2509 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2510 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2511 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2512 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2513 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2514 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2515 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2516 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2517 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2518 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2519 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2520 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2521 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2522 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2523 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2524 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2525 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2526 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2527 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2528 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2529 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2530 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2531 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2532 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2533 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2534 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2535 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2536 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2537 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2538 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2539 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2540 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2541 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2542 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2543 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2544 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2545 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2546 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2547 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2548 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2549 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2550 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2551 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2552 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2553 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2554 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2555 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2556 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2557 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2558 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2559 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2560 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2561 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2562 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2563 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2564 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2565 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2566 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2567 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2568 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2569 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2570 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2571 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2572 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2573 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2574 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2575 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2576 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2577 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2578 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2579 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2580 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2581 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2582 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2583 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2584 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2585 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2586 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2587 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2588 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2589
Kojto 120:7c328cabac7e 2590 #if defined(STM32F4)
Kojto 120:7c328cabac7e 2591 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 120:7c328cabac7e 2592 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 120:7c328cabac7e 2593 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2594 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2595 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 120:7c328cabac7e 2596 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 120:7c328cabac7e 2597 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2598 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2599 #define Sdmmc1ClockSelection SdioClockSelection
Kojto 120:7c328cabac7e 2600 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
Kojto 120:7c328cabac7e 2601 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
Kojto 120:7c328cabac7e 2602 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
Kojto 120:7c328cabac7e 2603 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
Kojto 120:7c328cabac7e 2604 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
Kojto 120:7c328cabac7e 2605 #endif
Kojto 120:7c328cabac7e 2606
Kojto 120:7c328cabac7e 2607 #if defined(STM32F7) || defined(STM32L4)
Kojto 120:7c328cabac7e 2608 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
Kojto 120:7c328cabac7e 2609 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
Kojto 120:7c328cabac7e 2610 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2611 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2612 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
Kojto 120:7c328cabac7e 2613 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
Kojto 120:7c328cabac7e 2614 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2615 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2616 #define SdioClockSelection Sdmmc1ClockSelection
Kojto 120:7c328cabac7e 2617 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
Kojto 120:7c328cabac7e 2618 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
Kojto 120:7c328cabac7e 2619 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
Kojto 120:7c328cabac7e 2620 #endif
Kojto 120:7c328cabac7e 2621
Kojto 120:7c328cabac7e 2622 #if defined(STM32F7)
Kojto 120:7c328cabac7e 2623 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
Kojto 120:7c328cabac7e 2624 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
Kojto 120:7c328cabac7e 2625 #endif
Kojto 120:7c328cabac7e 2626
Kojto 96:487b796308b0 2627 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
Kojto 96:487b796308b0 2628 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
Kojto 96:487b796308b0 2629
Kojto 120:7c328cabac7e 2630 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
Kojto 120:7c328cabac7e 2631
Kojto 120:7c328cabac7e 2632 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
Kojto 120:7c328cabac7e 2633 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
Kojto 120:7c328cabac7e 2634 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
Kojto 120:7c328cabac7e 2635 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
Kojto 120:7c328cabac7e 2636 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
Kojto 120:7c328cabac7e 2637
Kojto 120:7c328cabac7e 2638 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
Kojto 120:7c328cabac7e 2639
Kojto 120:7c328cabac7e 2640 #if defined(STM32L0)
Kojto 120:7c328cabac7e 2641 #define RCC_IT_LSECSS RCC_IT_CSSLSE
Kojto 120:7c328cabac7e 2642 #define RCC_IT_CSS RCC_IT_CSSHSE
Kojto 120:7c328cabac7e 2643 #endif
Kojto 120:7c328cabac7e 2644
Kojto 120:7c328cabac7e 2645 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
Kojto 120:7c328cabac7e 2646 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
Kojto 120:7c328cabac7e 2647 #define RCC_MCO_NODIV RCC_MCODIV_1
Kojto 120:7c328cabac7e 2648 #define RCC_MCO_DIV1 RCC_MCODIV_1
Kojto 120:7c328cabac7e 2649 #define RCC_MCO_DIV2 RCC_MCODIV_2
Kojto 120:7c328cabac7e 2650 #define RCC_MCO_DIV4 RCC_MCODIV_4
Kojto 120:7c328cabac7e 2651 #define RCC_MCO_DIV8 RCC_MCODIV_8
Kojto 120:7c328cabac7e 2652 #define RCC_MCO_DIV16 RCC_MCODIV_16
Kojto 120:7c328cabac7e 2653 #define RCC_MCO_DIV32 RCC_MCODIV_32
Kojto 120:7c328cabac7e 2654 #define RCC_MCO_DIV64 RCC_MCODIV_64
Kojto 120:7c328cabac7e 2655 #define RCC_MCO_DIV128 RCC_MCODIV_128
Kojto 120:7c328cabac7e 2656 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
Kojto 120:7c328cabac7e 2657 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
Kojto 120:7c328cabac7e 2658 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
Kojto 120:7c328cabac7e 2659 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
Kojto 120:7c328cabac7e 2660 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
Kojto 120:7c328cabac7e 2661 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
Kojto 120:7c328cabac7e 2662 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
Kojto 120:7c328cabac7e 2663 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
Kojto 120:7c328cabac7e 2664 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
Kojto 120:7c328cabac7e 2665 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
Kojto 120:7c328cabac7e 2666 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
Kojto 120:7c328cabac7e 2667
Kojto 120:7c328cabac7e 2668 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
Kojto 120:7c328cabac7e 2669
Kojto 120:7c328cabac7e 2670 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
Kojto 120:7c328cabac7e 2671 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
Kojto 120:7c328cabac7e 2672 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
Kojto 120:7c328cabac7e 2673 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
Kojto 120:7c328cabac7e 2674 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
Kojto 120:7c328cabac7e 2675 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
Kojto 120:7c328cabac7e 2676 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
Kojto 120:7c328cabac7e 2677 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
Kojto 96:487b796308b0 2678
Kojto 96:487b796308b0 2679 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
Kojto 120:7c328cabac7e 2680 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
Kojto 120:7c328cabac7e 2681 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
Kojto 120:7c328cabac7e 2682 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
Kojto 120:7c328cabac7e 2683 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
Kojto 96:487b796308b0 2684 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
Kojto 120:7c328cabac7e 2685 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
Kojto 96:487b796308b0 2686 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
Kojto 120:7c328cabac7e 2687 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
Kojto 96:487b796308b0 2688 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
Kojto 96:487b796308b0 2689 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
Kojto 96:487b796308b0 2690 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
Kojto 120:7c328cabac7e 2691 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
Kojto 96:487b796308b0 2692 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
Kojto 120:7c328cabac7e 2693 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
Kojto 120:7c328cabac7e 2694 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
Kojto 96:487b796308b0 2695 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
Kojto 120:7c328cabac7e 2696 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
Kojto 120:7c328cabac7e 2697 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
Kojto 120:7c328cabac7e 2698 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
Kojto 120:7c328cabac7e 2699 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
Kojto 96:487b796308b0 2700 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
Kojto 96:487b796308b0 2701 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
Kojto 120:7c328cabac7e 2702 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
Kojto 120:7c328cabac7e 2703 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
Kojto 120:7c328cabac7e 2704 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
Kojto 96:487b796308b0 2705 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
Kojto 96:487b796308b0 2706 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
Kojto 96:487b796308b0 2707 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
Kojto 96:487b796308b0 2708 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
Kojto 96:487b796308b0 2709 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
Kojto 96:487b796308b0 2710 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
Kojto 96:487b796308b0 2711
Kojto 96:487b796308b0 2712 #define CR_HSION_BB RCC_CR_HSION_BB
Kojto 96:487b796308b0 2713 #define CR_CSSON_BB RCC_CR_CSSON_BB
Kojto 96:487b796308b0 2714 #define CR_PLLON_BB RCC_CR_PLLON_BB
Kojto 96:487b796308b0 2715 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
Kojto 120:7c328cabac7e 2716 #define CR_MSION_BB RCC_CR_MSION_BB
Kojto 120:7c328cabac7e 2717 #define CSR_LSION_BB RCC_CSR_LSION_BB
Kojto 120:7c328cabac7e 2718 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
Kojto 120:7c328cabac7e 2719 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
Kojto 120:7c328cabac7e 2720 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
Kojto 120:7c328cabac7e 2721 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
Kojto 96:487b796308b0 2722 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
Kojto 96:487b796308b0 2723 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
Kojto 96:487b796308b0 2724 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
Kojto 120:7c328cabac7e 2725 #define CR_HSEON_BB RCC_CR_HSEON_BB
Kojto 120:7c328cabac7e 2726 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
Kojto 96:487b796308b0 2727 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
Kojto 96:487b796308b0 2728 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
Kojto 96:487b796308b0 2729
Kojto 120:7c328cabac7e 2730 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
Kojto 120:7c328cabac7e 2731 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
Kojto 120:7c328cabac7e 2732 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
Kojto 120:7c328cabac7e 2733 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
Kojto 120:7c328cabac7e 2734 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
Kojto 120:7c328cabac7e 2735
Kojto 120:7c328cabac7e 2736 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
Kojto 120:7c328cabac7e 2737
Kojto 120:7c328cabac7e 2738 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
Kojto 120:7c328cabac7e 2739 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
Kojto 120:7c328cabac7e 2740
Kojto 120:7c328cabac7e 2741 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
Kojto 120:7c328cabac7e 2742 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
Kojto 120:7c328cabac7e 2743 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
Kojto 120:7c328cabac7e 2744 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
Kojto 120:7c328cabac7e 2745 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
Kojto 120:7c328cabac7e 2746 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
Kojto 120:7c328cabac7e 2747
Kojto 120:7c328cabac7e 2748 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
Kojto 120:7c328cabac7e 2749 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
Kojto 120:7c328cabac7e 2750 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
Kojto 120:7c328cabac7e 2751 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
Kojto 120:7c328cabac7e 2752 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
Kojto 120:7c328cabac7e 2753 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
Kojto 120:7c328cabac7e 2754 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
Kojto 120:7c328cabac7e 2755 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
Kojto 120:7c328cabac7e 2756 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
Kojto 120:7c328cabac7e 2757 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
Kojto 120:7c328cabac7e 2758 #define DfsdmClockSelection Dfsdm1ClockSelection
Kojto 120:7c328cabac7e 2759 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
Kojto 120:7c328cabac7e 2760 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
Kojto 120:7c328cabac7e 2761 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
Kojto 120:7c328cabac7e 2762 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
Kojto 120:7c328cabac7e 2763 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
Kojto 120:7c328cabac7e 2764
Kojto 96:487b796308b0 2765 /**
Kojto 96:487b796308b0 2766 * @}
Kojto 96:487b796308b0 2767 */
Kojto 96:487b796308b0 2768
Kojto 96:487b796308b0 2769 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2770 * @{
Kojto 96:487b796308b0 2771 */
Kojto 120:7c328cabac7e 2772 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
Kojto 96:487b796308b0 2773
Kojto 96:487b796308b0 2774 /**
Kojto 96:487b796308b0 2775 * @}
Kojto 96:487b796308b0 2776 */
Kojto 96:487b796308b0 2777
Kojto 96:487b796308b0 2778 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2779 * @{
Kojto 96:487b796308b0 2780 */
Kojto 96:487b796308b0 2781
Kojto 96:487b796308b0 2782 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 2783 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
Kojto 96:487b796308b0 2784 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Kojto 96:487b796308b0 2785
Kojto 120:7c328cabac7e 2786 #if defined (STM32F1)
Kojto 96:487b796308b0 2787 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
Kojto 96:487b796308b0 2788
Kojto 96:487b796308b0 2789 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
Kojto 96:487b796308b0 2790
Kojto 96:487b796308b0 2791 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
Kojto 96:487b796308b0 2792
Kojto 96:487b796308b0 2793 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
Kojto 96:487b796308b0 2794
Kojto 96:487b796308b0 2795 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
Kojto 120:7c328cabac7e 2796 #else
Kojto 120:7c328cabac7e 2797 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 2798 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
Kojto 120:7c328cabac7e 2799 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Kojto 120:7c328cabac7e 2800 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 2801 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
Kojto 120:7c328cabac7e 2802 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Kojto 120:7c328cabac7e 2803 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 2804 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
Kojto 120:7c328cabac7e 2805 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Kojto 120:7c328cabac7e 2806 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 2807 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
Kojto 120:7c328cabac7e 2808 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Kojto 120:7c328cabac7e 2809 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
Kojto 120:7c328cabac7e 2810 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
Kojto 120:7c328cabac7e 2811 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
Kojto 120:7c328cabac7e 2812 #endif /* STM32F1 */
Kojto 96:487b796308b0 2813
Kojto 96:487b796308b0 2814 #define IS_ALARM IS_RTC_ALARM
Kojto 96:487b796308b0 2815 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
Kojto 96:487b796308b0 2816 #define IS_TAMPER IS_RTC_TAMPER
Kojto 96:487b796308b0 2817 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
Kojto 96:487b796308b0 2818 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
Kojto 96:487b796308b0 2819 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
Kojto 96:487b796308b0 2820 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
Kojto 96:487b796308b0 2821 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
Kojto 96:487b796308b0 2822 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
Kojto 96:487b796308b0 2823 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
Kojto 96:487b796308b0 2824 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
Kojto 96:487b796308b0 2825 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
Kojto 96:487b796308b0 2826 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
Kojto 96:487b796308b0 2827 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
Kojto 96:487b796308b0 2828
Kojto 96:487b796308b0 2829 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
Kojto 96:487b796308b0 2830 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
Kojto 96:487b796308b0 2831
Kojto 96:487b796308b0 2832 /**
Kojto 96:487b796308b0 2833 * @}
Kojto 96:487b796308b0 2834 */
Kojto 96:487b796308b0 2835
Kojto 96:487b796308b0 2836 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2837 * @{
Kojto 96:487b796308b0 2838 */
Kojto 96:487b796308b0 2839
Kojto 96:487b796308b0 2840 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
Kojto 96:487b796308b0 2841 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
Kojto 120:7c328cabac7e 2842
Kojto 120:7c328cabac7e 2843 #if defined(STM32F4)
Kojto 120:7c328cabac7e 2844 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
Kojto 120:7c328cabac7e 2845 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
Kojto 120:7c328cabac7e 2846 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
Kojto 120:7c328cabac7e 2847 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
Kojto 120:7c328cabac7e 2848 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
Kojto 120:7c328cabac7e 2849 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
Kojto 120:7c328cabac7e 2850 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
Kojto 120:7c328cabac7e 2851 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
Kojto 120:7c328cabac7e 2852 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
Kojto 120:7c328cabac7e 2853 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
Kojto 120:7c328cabac7e 2854 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
Kojto 120:7c328cabac7e 2855 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
Kojto 120:7c328cabac7e 2856 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
Kojto 120:7c328cabac7e 2857 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
Kojto 120:7c328cabac7e 2858 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
Kojto 120:7c328cabac7e 2859 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
Kojto 120:7c328cabac7e 2860 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
Kojto 120:7c328cabac7e 2861 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
Kojto 120:7c328cabac7e 2862 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
Kojto 120:7c328cabac7e 2863 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
Kojto 120:7c328cabac7e 2864 /* alias CMSIS */
Kojto 120:7c328cabac7e 2865 #define SDMMC1_IRQn SDIO_IRQn
Kojto 120:7c328cabac7e 2866 #define SDMMC1_IRQHandler SDIO_IRQHandler
Kojto 120:7c328cabac7e 2867 #endif
Kojto 120:7c328cabac7e 2868
Kojto 120:7c328cabac7e 2869 #if defined(STM32F7) || defined(STM32L4)
Kojto 120:7c328cabac7e 2870 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
Kojto 120:7c328cabac7e 2871 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
Kojto 120:7c328cabac7e 2872 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
Kojto 120:7c328cabac7e 2873 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
Kojto 120:7c328cabac7e 2874 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
Kojto 120:7c328cabac7e 2875 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
Kojto 120:7c328cabac7e 2876 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
Kojto 120:7c328cabac7e 2877 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
Kojto 120:7c328cabac7e 2878 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
Kojto 120:7c328cabac7e 2879 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
Kojto 120:7c328cabac7e 2880 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
Kojto 120:7c328cabac7e 2881 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
Kojto 120:7c328cabac7e 2882 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
Kojto 120:7c328cabac7e 2883 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
Kojto 120:7c328cabac7e 2884 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
Kojto 120:7c328cabac7e 2885 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
Kojto 120:7c328cabac7e 2886 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
Kojto 120:7c328cabac7e 2887 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
Kojto 120:7c328cabac7e 2888 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
Kojto 120:7c328cabac7e 2889 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
Kojto 120:7c328cabac7e 2890 /* alias CMSIS for compatibilities */
Kojto 120:7c328cabac7e 2891 #define SDIO_IRQn SDMMC1_IRQn
Kojto 120:7c328cabac7e 2892 #define SDIO_IRQHandler SDMMC1_IRQHandler
Kojto 120:7c328cabac7e 2893 #endif
Kojto 96:487b796308b0 2894 /**
Kojto 96:487b796308b0 2895 * @}
Kojto 96:487b796308b0 2896 */
Kojto 96:487b796308b0 2897
Kojto 96:487b796308b0 2898 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2899 * @{
Kojto 96:487b796308b0 2900 */
Kojto 96:487b796308b0 2901
Kojto 96:487b796308b0 2902 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Kojto 96:487b796308b0 2903 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Kojto 96:487b796308b0 2904 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Kojto 96:487b796308b0 2905 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Kojto 96:487b796308b0 2906 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Kojto 96:487b796308b0 2907 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Kojto 96:487b796308b0 2908
Kojto 96:487b796308b0 2909 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 96:487b796308b0 2910 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 96:487b796308b0 2911
Kojto 96:487b796308b0 2912 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
Kojto 96:487b796308b0 2913
Kojto 96:487b796308b0 2914 /**
Kojto 96:487b796308b0 2915 * @}
Kojto 96:487b796308b0 2916 */
Kojto 96:487b796308b0 2917
Kojto 96:487b796308b0 2918 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2919 * @{
Kojto 96:487b796308b0 2920 */
Kojto 96:487b796308b0 2921 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
Kojto 96:487b796308b0 2922 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
Kojto 96:487b796308b0 2923 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
Kojto 96:487b796308b0 2924 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
Kojto 96:487b796308b0 2925 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
Kojto 96:487b796308b0 2926 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
Kojto 96:487b796308b0 2927 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
Kojto 96:487b796308b0 2928 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
Kojto 96:487b796308b0 2929 /**
Kojto 96:487b796308b0 2930 * @}
Kojto 96:487b796308b0 2931 */
Kojto 96:487b796308b0 2932
Kojto 96:487b796308b0 2933 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2934 * @{
Kojto 96:487b796308b0 2935 */
Kojto 96:487b796308b0 2936
Kojto 96:487b796308b0 2937 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
Kojto 96:487b796308b0 2938 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
Kojto 96:487b796308b0 2939 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
Kojto 96:487b796308b0 2940
Kojto 96:487b796308b0 2941 /**
Kojto 96:487b796308b0 2942 * @}
Kojto 96:487b796308b0 2943 */
Kojto 96:487b796308b0 2944
Kojto 96:487b796308b0 2945 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2946 * @{
Kojto 96:487b796308b0 2947 */
Kojto 96:487b796308b0 2948
Kojto 96:487b796308b0 2949 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 96:487b796308b0 2950 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 96:487b796308b0 2951 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 96:487b796308b0 2952 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 96:487b796308b0 2953
Kojto 96:487b796308b0 2954 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
Kojto 96:487b796308b0 2955
Kojto 96:487b796308b0 2956 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Kojto 96:487b796308b0 2957 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
Kojto 96:487b796308b0 2958
Kojto 96:487b796308b0 2959 /**
Kojto 96:487b796308b0 2960 * @}
Kojto 96:487b796308b0 2961 */
Kojto 96:487b796308b0 2962
Kojto 96:487b796308b0 2963
Kojto 96:487b796308b0 2964 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2965 * @{
Kojto 96:487b796308b0 2966 */
Kojto 96:487b796308b0 2967
Kojto 96:487b796308b0 2968 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
Kojto 96:487b796308b0 2969 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
Kojto 96:487b796308b0 2970 #define __USART_ENABLE __HAL_USART_ENABLE
Kojto 96:487b796308b0 2971 #define __USART_DISABLE __HAL_USART_DISABLE
Kojto 96:487b796308b0 2972
Kojto 96:487b796308b0 2973 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 96:487b796308b0 2974 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 96:487b796308b0 2975
Kojto 96:487b796308b0 2976 /**
Kojto 96:487b796308b0 2977 * @}
Kojto 96:487b796308b0 2978 */
Kojto 96:487b796308b0 2979
Kojto 96:487b796308b0 2980 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 2981 * @{
Kojto 96:487b796308b0 2982 */
Kojto 96:487b796308b0 2983 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
Kojto 96:487b796308b0 2984
Kojto 96:487b796308b0 2985 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
Kojto 96:487b796308b0 2986 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
Kojto 96:487b796308b0 2987 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 96:487b796308b0 2988 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
Kojto 96:487b796308b0 2989
Kojto 96:487b796308b0 2990 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
Kojto 96:487b796308b0 2991 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
Kojto 96:487b796308b0 2992 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 96:487b796308b0 2993 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
Kojto 96:487b796308b0 2994
Kojto 96:487b796308b0 2995 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
Kojto 96:487b796308b0 2996 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
Kojto 96:487b796308b0 2997 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
Kojto 96:487b796308b0 2998 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 2999 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 3000 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 3001 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 96:487b796308b0 3002
Kojto 96:487b796308b0 3003 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Kojto 96:487b796308b0 3004 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Kojto 96:487b796308b0 3005 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Kojto 96:487b796308b0 3006 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 3007 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 3008 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 3009 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 96:487b796308b0 3010 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 96:487b796308b0 3011
Kojto 96:487b796308b0 3012 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Kojto 96:487b796308b0 3013 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Kojto 96:487b796308b0 3014 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Kojto 96:487b796308b0 3015 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 3016 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 96:487b796308b0 3017 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 96:487b796308b0 3018 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 96:487b796308b0 3019 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 96:487b796308b0 3020
Kojto 96:487b796308b0 3021 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Kojto 96:487b796308b0 3022 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Kojto 96:487b796308b0 3023
Kojto 96:487b796308b0 3024 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Kojto 96:487b796308b0 3025 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
Kojto 96:487b796308b0 3026 /**
Kojto 96:487b796308b0 3027 * @}
Kojto 96:487b796308b0 3028 */
Kojto 96:487b796308b0 3029
Kojto 96:487b796308b0 3030 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 3031 * @{
Kojto 96:487b796308b0 3032 */
Kojto 96:487b796308b0 3033 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
Kojto 96:487b796308b0 3034 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
Kojto 96:487b796308b0 3035
Kojto 96:487b796308b0 3036 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 96:487b796308b0 3037 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
Kojto 96:487b796308b0 3038
Kojto 120:7c328cabac7e 3039 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 120:7c328cabac7e 3040
Kojto 96:487b796308b0 3041 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
Kojto 96:487b796308b0 3042 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
Kojto 96:487b796308b0 3043 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
Kojto 96:487b796308b0 3044 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
Kojto 96:487b796308b0 3045 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
Kojto 96:487b796308b0 3046 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
Kojto 96:487b796308b0 3047 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
Kojto 96:487b796308b0 3048 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
Kojto 96:487b796308b0 3049 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
Kojto 96:487b796308b0 3050 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
Kojto 96:487b796308b0 3051 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
Kojto 96:487b796308b0 3052 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
Kojto 96:487b796308b0 3053
Kojto 120:7c328cabac7e 3054 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
Kojto 96:487b796308b0 3055 /**
Kojto 96:487b796308b0 3056 * @}
Kojto 96:487b796308b0 3057 */
Kojto 96:487b796308b0 3058
Kojto 96:487b796308b0 3059 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 3060 * @{
Kojto 96:487b796308b0 3061 */
Kojto 96:487b796308b0 3062
Kojto 96:487b796308b0 3063 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
Kojto 96:487b796308b0 3064 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
Kojto 96:487b796308b0 3065 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
Kojto 96:487b796308b0 3066 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
Kojto 96:487b796308b0 3067 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
Kojto 96:487b796308b0 3068 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
Kojto 96:487b796308b0 3069 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
Kojto 96:487b796308b0 3070
Kojto 96:487b796308b0 3071 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
Kojto 96:487b796308b0 3072 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
Kojto 96:487b796308b0 3073 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
Kojto 96:487b796308b0 3074 /**
Kojto 96:487b796308b0 3075 * @}
Kojto 96:487b796308b0 3076 */
Kojto 96:487b796308b0 3077
Kojto 96:487b796308b0 3078 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 3079 * @{
Kojto 96:487b796308b0 3080 */
Kojto 96:487b796308b0 3081 #define __HAL_LTDC_LAYER LTDC_LAYER
Kojto 96:487b796308b0 3082 /**
Kojto 96:487b796308b0 3083 * @}
Kojto 96:487b796308b0 3084 */
Kojto 96:487b796308b0 3085
Kojto 96:487b796308b0 3086 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 3087 * @{
Kojto 96:487b796308b0 3088 */
Kojto 96:487b796308b0 3089 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
Kojto 96:487b796308b0 3090 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
Kojto 96:487b796308b0 3091 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
Kojto 96:487b796308b0 3092 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
Kojto 96:487b796308b0 3093 #define SAI_STREOMODE SAI_STEREOMODE
Kojto 120:7c328cabac7e 3094 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
Kojto 120:7c328cabac7e 3095 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
Kojto 120:7c328cabac7e 3096 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
Kojto 120:7c328cabac7e 3097 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
Kojto 120:7c328cabac7e 3098 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
Kojto 120:7c328cabac7e 3099 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
Kojto 120:7c328cabac7e 3100 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
Kojto 120:7c328cabac7e 3101 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
Kojto 120:7c328cabac7e 3102 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
Kojto 96:487b796308b0 3103 /**
Kojto 96:487b796308b0 3104 * @}
Kojto 96:487b796308b0 3105 */
Kojto 96:487b796308b0 3106
Kojto 96:487b796308b0 3107
Kojto 96:487b796308b0 3108 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
Kojto 96:487b796308b0 3109 * @{
Kojto 96:487b796308b0 3110 */
Kojto 96:487b796308b0 3111
Kojto 96:487b796308b0 3112 /**
Kojto 96:487b796308b0 3113 * @}
Kojto 96:487b796308b0 3114 */
Kojto 96:487b796308b0 3115
Kojto 96:487b796308b0 3116 #ifdef __cplusplus
Kojto 96:487b796308b0 3117 }
Kojto 96:487b796308b0 3118 #endif
Kojto 96:487b796308b0 3119
Kojto 96:487b796308b0 3120 #endif /* ___STM32_HAL_LEGACY */
Kojto 96:487b796308b0 3121
Kojto 96:487b796308b0 3122 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 3123