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LPC1768/ARM/core_cm3.h@39:737756e0b479, 2012-03-12 (annotated)

Committer:: emilmont
Date:: Mon Mar 12 11:16:34 2012 +0000
Revision:: 39:737756e0b479
Parent:: 33:5364839841bd

[12 March 2012] Update CMSIS core to V3.0

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	27:7110ebee3484	1	/************************************************************************//
emilmont	27:7110ebee3484	2	* @file core_cm3.h
emilmont	27:7110ebee3484	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
emilmont	39:737756e0b479	4	* @version V3.01
emilmont	39:737756e0b479	5	* @date 06. March 2012
emilmont	27:7110ebee3484	6	*
emilmont	27:7110ebee3484	7	* @note
emilmont	39:737756e0b479	8	* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont	27:7110ebee3484	9	*
emilmont	27:7110ebee3484	10	* @par
emilmont	33:5364839841bd	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont	33:5364839841bd	12	* processor based microcontrollers. This file can be freely distributed
emilmont	33:5364839841bd	13	* within development tools that are supporting such ARM based processors.
emilmont	27:7110ebee3484	14	*
emilmont	27:7110ebee3484	15	* @par
emilmont	27:7110ebee3484	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont	27:7110ebee3484	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont	27:7110ebee3484	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont	27:7110ebee3484	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont	27:7110ebee3484	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont	27:7110ebee3484	21	*
emilmont	27:7110ebee3484	22	******************************************************************************/
emilmont	33:5364839841bd	23	#if defined ( __ICCARM__ )
emilmont	27:7110ebee3484	24	#pragma system_include /* treat file as system include file for MISRA check */
emilmont	27:7110ebee3484	25	#endif
emilmont	27:7110ebee3484	26
emilmont	27:7110ebee3484	27	#ifdef __cplusplus
emilmont	27:7110ebee3484	28	extern "C" {
emilmont	33:5364839841bd	29	#endif
emilmont	27:7110ebee3484	30
emilmont	27:7110ebee3484	31	#ifndef __CORE_CM3_H_GENERIC
emilmont	27:7110ebee3484	32	#define __CORE_CM3_H_GENERIC
emilmont	27:7110ebee3484	33
emilmont	33:5364839841bd	34	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont	33:5364839841bd	35	CMSIS violates the following MISRA-C:2004 rules:
emilmont	39:737756e0b479	36
emilmont	33:5364839841bd	37	\li Required Rule 8.5, object/function definition in header file.<br>
emilmont	39:737756e0b479	38	Function definitions in header files are used to allow 'inlining'.
emilmont	27:7110ebee3484	39
emilmont	33:5364839841bd	40	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont	33:5364839841bd	41	Unions are used for effective representation of core registers.
emilmont	39:737756e0b479	42
emilmont	33:5364839841bd	43	\li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont	39:737756e0b479	44	Function-like macros are used to allow more efficient code.
emilmont	27:7110ebee3484	45	*/
emilmont	27:7110ebee3484	46
emilmont	27:7110ebee3484	47
emilmont	27:7110ebee3484	48	/*******************************************************************************
emilmont	27:7110ebee3484	49	* CMSIS definitions
emilmont	27:7110ebee3484	50	******************************************************************************/
emilmont	33:5364839841bd	51	/** \ingroup Cortex_M3
emilmont	27:7110ebee3484	52	@{
emilmont	27:7110ebee3484	53	*/
emilmont	27:7110ebee3484	54
emilmont	27:7110ebee3484	55	/* CMSIS CM3 definitions */
emilmont	33:5364839841bd	56	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
emilmont	39:737756e0b479	57	#define __CM3_CMSIS_VERSION_SUB (0x01) /!< [15:0] CMSIS HAL sub version /
emilmont	33:5364839841bd	58	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
emilmont	33:5364839841bd	59	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
emilmont	27:7110ebee3484	60
emilmont	33:5364839841bd	61	#define __CORTEX_M (0x03) /!< Cortex-M Core /
emilmont	27:7110ebee3484	62
emilmont	27:7110ebee3484	63
emilmont	33:5364839841bd	64	#if defined ( __CC_ARM )
emilmont	27:7110ebee3484	65	#define __ASM __asm /!< asm keyword for ARM Compiler /
emilmont	27:7110ebee3484	66	#define __INLINE __inline /!< inline keyword for ARM Compiler /
emilmont	39:737756e0b479	67	#define __STATIC_INLINE static __inline
emilmont	27:7110ebee3484	68
emilmont	27:7110ebee3484	69	#elif defined ( __ICCARM__ )
emilmont	39:737756e0b479	70	#define __ASM __asm /!< asm keyword for IAR Compiler /
emilmont	39:737756e0b479	71	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
emilmont	39:737756e0b479	72	#define __STATIC_INLINE static inline
emilmont	39:737756e0b479	73
emilmont	39:737756e0b479	74	#elif defined ( __TMS470__ )
emilmont	39:737756e0b479	75	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
emilmont	39:737756e0b479	76	#define __STATIC_INLINE static inline
emilmont	27:7110ebee3484	77
emilmont	33:5364839841bd	78	#elif defined ( __GNUC__ )
emilmont	27:7110ebee3484	79	#define __ASM __asm /!< asm keyword for GNU Compiler /
emilmont	27:7110ebee3484	80	#define __INLINE inline /!< inline keyword for GNU Compiler /
emilmont	39:737756e0b479	81	#define __STATIC_INLINE static inline
emilmont	27:7110ebee3484	82
emilmont	33:5364839841bd	83	#elif defined ( __TASKING__ )
emilmont	27:7110ebee3484	84	#define __ASM __asm /!< asm keyword for TASKING Compiler /
emilmont	27:7110ebee3484	85	#define __INLINE inline /!< inline keyword for TASKING Compiler /
emilmont	39:737756e0b479	86	#define __STATIC_INLINE static inline
emilmont	27:7110ebee3484	87
emilmont	27:7110ebee3484	88	#endif
emilmont	27:7110ebee3484	89
emilmont	33:5364839841bd	90	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont	33:5364839841bd	91	*/
emilmont	33:5364839841bd	92	#define __FPU_USED 0
emilmont	33:5364839841bd	93
emilmont	33:5364839841bd	94	#if defined ( __CC_ARM )
emilmont	33:5364839841bd	95	#if defined __TARGET_FPU_VFP
emilmont	33:5364839841bd	96	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	33:5364839841bd	97	#endif
emilmont	33:5364839841bd	98
emilmont	33:5364839841bd	99	#elif defined ( __ICCARM__ )
emilmont	33:5364839841bd	100	#if defined __ARMVFP__
emilmont	33:5364839841bd	101	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	33:5364839841bd	102	#endif
emilmont	33:5364839841bd	103
emilmont	39:737756e0b479	104	#elif defined ( __TMS470__ )
emilmont	39:737756e0b479	105	#if defined __TI__VFP_SUPPORT____
emilmont	39:737756e0b479	106	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	39:737756e0b479	107	#endif
emilmont	39:737756e0b479	108
emilmont	33:5364839841bd	109	#elif defined ( __GNUC__ )
emilmont	33:5364839841bd	110	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont	33:5364839841bd	111	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	33:5364839841bd	112	#endif
emilmont	33:5364839841bd	113
emilmont	33:5364839841bd	114	#elif defined ( __TASKING__ )
emilmont	33:5364839841bd	115	/* add preprocessor checks */
emilmont	33:5364839841bd	116	#endif
emilmont	33:5364839841bd	117
emilmont	33:5364839841bd	118	#include <stdint.h> /* standard types definitions */
emilmont	33:5364839841bd	119	#include <core_cmInstr.h> /* Core Instruction Access */
emilmont	33:5364839841bd	120	#include <core_cmFunc.h> /* Core Function Access */
emilmont	27:7110ebee3484	121
emilmont	27:7110ebee3484	122	#endif /* __CORE_CM3_H_GENERIC */
emilmont	27:7110ebee3484	123
emilmont	27:7110ebee3484	124	#ifndef __CMSIS_GENERIC
emilmont	27:7110ebee3484	125
emilmont	27:7110ebee3484	126	#ifndef __CORE_CM3_H_DEPENDANT
emilmont	27:7110ebee3484	127	#define __CORE_CM3_H_DEPENDANT
emilmont	27:7110ebee3484	128
emilmont	33:5364839841bd	129	/* check device defines and use defaults */
emilmont	33:5364839841bd	130	#if defined __CHECK_DEVICE_DEFINES
emilmont	33:5364839841bd	131	#ifndef __CM3_REV
emilmont	33:5364839841bd	132	#define __CM3_REV 0x0200
emilmont	33:5364839841bd	133	#warning "__CM3_REV not defined in device header file; using default!"
emilmont	33:5364839841bd	134	#endif
emilmont	33:5364839841bd	135
emilmont	33:5364839841bd	136	#ifndef __MPU_PRESENT
emilmont	33:5364839841bd	137	#define __MPU_PRESENT 0
emilmont	33:5364839841bd	138	#warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont	33:5364839841bd	139	#endif
emilmont	33:5364839841bd	140
emilmont	33:5364839841bd	141	#ifndef __NVIC_PRIO_BITS
emilmont	33:5364839841bd	142	#define __NVIC_PRIO_BITS 4
emilmont	33:5364839841bd	143	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont	33:5364839841bd	144	#endif
emilmont	33:5364839841bd	145
emilmont	33:5364839841bd	146	#ifndef __Vendor_SysTickConfig
emilmont	33:5364839841bd	147	#define __Vendor_SysTickConfig 0
emilmont	33:5364839841bd	148	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont	33:5364839841bd	149	#endif
emilmont	33:5364839841bd	150	#endif
emilmont	33:5364839841bd	151
emilmont	27:7110ebee3484	152	/* IO definitions (access restrictions to peripheral registers) */
emilmont	33:5364839841bd	153	/**
emilmont	33:5364839841bd	154	\defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont	39:737756e0b479	155
emilmont	33:5364839841bd	156	<strong>IO Type Qualifiers</strong> are used
emilmont	33:5364839841bd	157	\li to specify the access to peripheral variables.
emilmont	33:5364839841bd	158	\li for automatic generation of peripheral register debug information.
emilmont	33:5364839841bd	159	*/
emilmont	27:7110ebee3484	160	#ifdef __cplusplus
emilmont	33:5364839841bd	161	#define __I volatile /!< Defines 'read only' permissions /
emilmont	27:7110ebee3484	162	#else
emilmont	33:5364839841bd	163	#define __I volatile const /!< Defines 'read only' permissions /
emilmont	27:7110ebee3484	164	#endif
emilmont	33:5364839841bd	165	#define __O volatile /!< Defines 'write only' permissions /
emilmont	33:5364839841bd	166	#define __IO volatile /!< Defines 'read / write' permissions /
emilmont	27:7110ebee3484	167
emilmont	33:5364839841bd	168	/@} end of group Cortex_M3 /
emilmont	27:7110ebee3484	169
emilmont	27:7110ebee3484	170
emilmont	27:7110ebee3484	171
emilmont	27:7110ebee3484	172	/*******************************************************************************
emilmont	27:7110ebee3484	173	* Register Abstraction
emilmont	27:7110ebee3484	174	Core Register contain:
emilmont	27:7110ebee3484	175	- Core Register
emilmont	27:7110ebee3484	176	- Core NVIC Register
emilmont	27:7110ebee3484	177	- Core SCB Register
emilmont	27:7110ebee3484	178	- Core SysTick Register
emilmont	27:7110ebee3484	179	- Core Debug Register
emilmont	27:7110ebee3484	180	- Core MPU Register
emilmont	33:5364839841bd	181	******************************************************************************/
emilmont	33:5364839841bd	182	/** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont	33:5364839841bd	183	\brief Type definitions and defines for Cortex-M processor based devices.
emilmont	27:7110ebee3484	184	*/
emilmont	27:7110ebee3484	185
emilmont	33:5364839841bd	186	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	187	\defgroup CMSIS_CORE Status and Control Registers
emilmont	33:5364839841bd	188	\brief Core Register type definitions.
emilmont	27:7110ebee3484	189	@{
emilmont	27:7110ebee3484	190	*/
emilmont	27:7110ebee3484	191
emilmont	27:7110ebee3484	192	/** \brief Union type to access the Application Program Status Register (APSR).
emilmont	27:7110ebee3484	193	*/
emilmont	27:7110ebee3484	194	typedef union
emilmont	27:7110ebee3484	195	{
emilmont	27:7110ebee3484	196	struct
emilmont	27:7110ebee3484	197	{
emilmont	27:7110ebee3484	198	#if (__CORTEX_M != 0x04)
emilmont	27:7110ebee3484	199	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
emilmont	27:7110ebee3484	200	#else
emilmont	27:7110ebee3484	201	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
emilmont	27:7110ebee3484	202	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	27:7110ebee3484	203	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
emilmont	27:7110ebee3484	204	#endif
emilmont	27:7110ebee3484	205	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	27:7110ebee3484	206	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	27:7110ebee3484	207	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	27:7110ebee3484	208	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	27:7110ebee3484	209	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	27:7110ebee3484	210	} b; /!< Structure used for bit access /
emilmont	33:5364839841bd	211	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	212	} APSR_Type;
emilmont	27:7110ebee3484	213
emilmont	27:7110ebee3484	214
emilmont	27:7110ebee3484	215	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont	27:7110ebee3484	216	*/
emilmont	27:7110ebee3484	217	typedef union
emilmont	27:7110ebee3484	218	{
emilmont	27:7110ebee3484	219	struct
emilmont	27:7110ebee3484	220	{
emilmont	27:7110ebee3484	221	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	27:7110ebee3484	222	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
emilmont	27:7110ebee3484	223	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	224	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	225	} IPSR_Type;
emilmont	27:7110ebee3484	226
emilmont	27:7110ebee3484	227
emilmont	27:7110ebee3484	228	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont	27:7110ebee3484	229	*/
emilmont	27:7110ebee3484	230	typedef union
emilmont	27:7110ebee3484	231	{
emilmont	27:7110ebee3484	232	struct
emilmont	27:7110ebee3484	233	{
emilmont	27:7110ebee3484	234	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	27:7110ebee3484	235	#if (__CORTEX_M != 0x04)
emilmont	27:7110ebee3484	236	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
emilmont	27:7110ebee3484	237	#else
emilmont	27:7110ebee3484	238	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
emilmont	27:7110ebee3484	239	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	27:7110ebee3484	240	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
emilmont	27:7110ebee3484	241	#endif
emilmont	27:7110ebee3484	242	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
emilmont	27:7110ebee3484	243	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
emilmont	27:7110ebee3484	244	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	27:7110ebee3484	245	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	27:7110ebee3484	246	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	27:7110ebee3484	247	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	27:7110ebee3484	248	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	27:7110ebee3484	249	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	250	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	251	} xPSR_Type;
emilmont	27:7110ebee3484	252
emilmont	27:7110ebee3484	253
emilmont	27:7110ebee3484	254	/** \brief Union type to access the Control Registers (CONTROL).
emilmont	27:7110ebee3484	255	*/
emilmont	27:7110ebee3484	256	typedef union
emilmont	27:7110ebee3484	257	{
emilmont	27:7110ebee3484	258	struct
emilmont	27:7110ebee3484	259	{
emilmont	27:7110ebee3484	260	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
emilmont	27:7110ebee3484	261	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
emilmont	27:7110ebee3484	262	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
emilmont	27:7110ebee3484	263	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
emilmont	27:7110ebee3484	264	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	265	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	266	} CONTROL_Type;
emilmont	27:7110ebee3484	267
emilmont	27:7110ebee3484	268	/@} end of group CMSIS_CORE /
emilmont	27:7110ebee3484	269
emilmont	27:7110ebee3484	270
emilmont	33:5364839841bd	271	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	272	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont	33:5364839841bd	273	\brief Type definitions for the NVIC Registers
emilmont	27:7110ebee3484	274	@{
emilmont	27:7110ebee3484	275	*/
emilmont	27:7110ebee3484	276
emilmont	27:7110ebee3484	277	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont	27:7110ebee3484	278	*/
emilmont	27:7110ebee3484	279	typedef struct
emilmont	27:7110ebee3484	280	{
emilmont	27:7110ebee3484	281	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
emilmont	33:5364839841bd	282	uint32_t RESERVED0[24];
emilmont	27:7110ebee3484	283	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
emilmont	33:5364839841bd	284	uint32_t RSERVED1[24];
emilmont	27:7110ebee3484	285	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
emilmont	33:5364839841bd	286	uint32_t RESERVED2[24];
emilmont	27:7110ebee3484	287	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
emilmont	33:5364839841bd	288	uint32_t RESERVED3[24];
emilmont	27:7110ebee3484	289	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
emilmont	33:5364839841bd	290	uint32_t RESERVED4[56];
emilmont	27:7110ebee3484	291	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
emilmont	33:5364839841bd	292	uint32_t RESERVED5[644];
emilmont	27:7110ebee3484	293	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
emilmont	33:5364839841bd	294	} NVIC_Type;
emilmont	33:5364839841bd	295
emilmont	33:5364839841bd	296	/* Software Triggered Interrupt Register Definitions */
emilmont	33:5364839841bd	297	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
emilmont	33:5364839841bd	298	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
emilmont	27:7110ebee3484	299
emilmont	27:7110ebee3484	300	/@} end of group CMSIS_NVIC /
emilmont	27:7110ebee3484	301
emilmont	27:7110ebee3484	302
emilmont	33:5364839841bd	303	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	304	\defgroup CMSIS_SCB System Control Block (SCB)
emilmont	33:5364839841bd	305	\brief Type definitions for the System Control Block Registers
emilmont	27:7110ebee3484	306	@{
emilmont	27:7110ebee3484	307	*/
emilmont	27:7110ebee3484	308
emilmont	27:7110ebee3484	309	/** \brief Structure type to access the System Control Block (SCB).
emilmont	27:7110ebee3484	310	*/
emilmont	27:7110ebee3484	311	typedef struct
emilmont	27:7110ebee3484	312	{
emilmont	33:5364839841bd	313	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
emilmont	33:5364839841bd	314	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
emilmont	27:7110ebee3484	315	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
emilmont	33:5364839841bd	316	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
emilmont	27:7110ebee3484	317	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
emilmont	27:7110ebee3484	318	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
emilmont	27:7110ebee3484	319	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
emilmont	27:7110ebee3484	320	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
emilmont	27:7110ebee3484	321	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
emilmont	33:5364839841bd	322	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
emilmont	27:7110ebee3484	323	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
emilmont	33:5364839841bd	324	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
emilmont	33:5364839841bd	325	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
emilmont	27:7110ebee3484	326	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
emilmont	27:7110ebee3484	327	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
emilmont	27:7110ebee3484	328	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
emilmont	27:7110ebee3484	329	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
emilmont	27:7110ebee3484	330	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
emilmont	33:5364839841bd	331	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
emilmont	33:5364839841bd	332	uint32_t RESERVED0[5];
emilmont	33:5364839841bd	333	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
emilmont	33:5364839841bd	334	} SCB_Type;
emilmont	27:7110ebee3484	335
emilmont	27:7110ebee3484	336	/* SCB CPUID Register Definitions */
emilmont	27:7110ebee3484	337	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
emilmont	27:7110ebee3484	338	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
emilmont	27:7110ebee3484	339
emilmont	27:7110ebee3484	340	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
emilmont	27:7110ebee3484	341	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
emilmont	27:7110ebee3484	342
emilmont	33:5364839841bd	343	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
emilmont	33:5364839841bd	344	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
emilmont	33:5364839841bd	345
emilmont	27:7110ebee3484	346	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
emilmont	27:7110ebee3484	347	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
emilmont	27:7110ebee3484	348
emilmont	27:7110ebee3484	349	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
emilmont	27:7110ebee3484	350	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
emilmont	27:7110ebee3484	351
emilmont	27:7110ebee3484	352	/* SCB Interrupt Control State Register Definitions */
emilmont	27:7110ebee3484	353	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
emilmont	27:7110ebee3484	354	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
emilmont	27:7110ebee3484	355
emilmont	27:7110ebee3484	356	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
emilmont	27:7110ebee3484	357	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
emilmont	27:7110ebee3484	358
emilmont	27:7110ebee3484	359	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
emilmont	27:7110ebee3484	360	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
emilmont	27:7110ebee3484	361
emilmont	27:7110ebee3484	362	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
emilmont	27:7110ebee3484	363	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
emilmont	27:7110ebee3484	364
emilmont	27:7110ebee3484	365	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
emilmont	27:7110ebee3484	366	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
emilmont	27:7110ebee3484	367
emilmont	27:7110ebee3484	368	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
emilmont	27:7110ebee3484	369	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
emilmont	27:7110ebee3484	370
emilmont	27:7110ebee3484	371	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
emilmont	27:7110ebee3484	372	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
emilmont	27:7110ebee3484	373
emilmont	27:7110ebee3484	374	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
emilmont	27:7110ebee3484	375	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
emilmont	27:7110ebee3484	376
emilmont	27:7110ebee3484	377	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
emilmont	27:7110ebee3484	378	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
emilmont	27:7110ebee3484	379
emilmont	27:7110ebee3484	380	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
emilmont	27:7110ebee3484	381	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
emilmont	27:7110ebee3484	382
emilmont	33:5364839841bd	383	/* SCB Vector Table Offset Register Definitions */
emilmont	33:5364839841bd	384	#if (__CM3_REV < 0x0201) /* core r2p1 */
emilmont	27:7110ebee3484	385	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
emilmont	27:7110ebee3484	386	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
emilmont	27:7110ebee3484	387
emilmont	27:7110ebee3484	388	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	27:7110ebee3484	389	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	33:5364839841bd	390	#else
emilmont	33:5364839841bd	391	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	33:5364839841bd	392	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	33:5364839841bd	393	#endif
emilmont	27:7110ebee3484	394
emilmont	27:7110ebee3484	395	/* SCB Application Interrupt and Reset Control Register Definitions */
emilmont	27:7110ebee3484	396	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
emilmont	27:7110ebee3484	397	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
emilmont	27:7110ebee3484	398
emilmont	27:7110ebee3484	399	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
emilmont	27:7110ebee3484	400	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
emilmont	27:7110ebee3484	401
emilmont	27:7110ebee3484	402	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
emilmont	27:7110ebee3484	403	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
emilmont	27:7110ebee3484	404
emilmont	27:7110ebee3484	405	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
emilmont	27:7110ebee3484	406	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
emilmont	27:7110ebee3484	407
emilmont	27:7110ebee3484	408	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
emilmont	27:7110ebee3484	409	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
emilmont	27:7110ebee3484	410
emilmont	27:7110ebee3484	411	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
emilmont	27:7110ebee3484	412	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
emilmont	27:7110ebee3484	413
emilmont	27:7110ebee3484	414	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
emilmont	27:7110ebee3484	415	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
emilmont	27:7110ebee3484	416
emilmont	27:7110ebee3484	417	/* SCB System Control Register Definitions */
emilmont	27:7110ebee3484	418	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
emilmont	27:7110ebee3484	419	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
emilmont	27:7110ebee3484	420
emilmont	27:7110ebee3484	421	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
emilmont	27:7110ebee3484	422	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
emilmont	27:7110ebee3484	423
emilmont	27:7110ebee3484	424	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
emilmont	27:7110ebee3484	425	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
emilmont	27:7110ebee3484	426
emilmont	27:7110ebee3484	427	/* SCB Configuration Control Register Definitions */
emilmont	27:7110ebee3484	428	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
emilmont	27:7110ebee3484	429	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
emilmont	27:7110ebee3484	430
emilmont	27:7110ebee3484	431	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
emilmont	27:7110ebee3484	432	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
emilmont	27:7110ebee3484	433
emilmont	27:7110ebee3484	434	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
emilmont	27:7110ebee3484	435	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
emilmont	27:7110ebee3484	436
emilmont	27:7110ebee3484	437	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
emilmont	27:7110ebee3484	438	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
emilmont	27:7110ebee3484	439
emilmont	27:7110ebee3484	440	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
emilmont	27:7110ebee3484	441	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
emilmont	27:7110ebee3484	442
emilmont	27:7110ebee3484	443	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
emilmont	27:7110ebee3484	444	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
emilmont	27:7110ebee3484	445
emilmont	27:7110ebee3484	446	/* SCB System Handler Control and State Register Definitions */
emilmont	27:7110ebee3484	447	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
emilmont	27:7110ebee3484	448	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
emilmont	27:7110ebee3484	449
emilmont	27:7110ebee3484	450	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
emilmont	27:7110ebee3484	451	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
emilmont	27:7110ebee3484	452
emilmont	27:7110ebee3484	453	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
emilmont	27:7110ebee3484	454	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
emilmont	27:7110ebee3484	455
emilmont	27:7110ebee3484	456	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
emilmont	27:7110ebee3484	457	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
emilmont	27:7110ebee3484	458
emilmont	27:7110ebee3484	459	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
emilmont	27:7110ebee3484	460	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
emilmont	27:7110ebee3484	461
emilmont	27:7110ebee3484	462	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
emilmont	27:7110ebee3484	463	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
emilmont	27:7110ebee3484	464
emilmont	27:7110ebee3484	465	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
emilmont	27:7110ebee3484	466	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
emilmont	27:7110ebee3484	467
emilmont	27:7110ebee3484	468	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
emilmont	27:7110ebee3484	469	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
emilmont	27:7110ebee3484	470
emilmont	27:7110ebee3484	471	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
emilmont	27:7110ebee3484	472	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
emilmont	27:7110ebee3484	473
emilmont	27:7110ebee3484	474	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
emilmont	27:7110ebee3484	475	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
emilmont	27:7110ebee3484	476
emilmont	27:7110ebee3484	477	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
emilmont	27:7110ebee3484	478	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
emilmont	33:5364839841bd	479
emilmont	27:7110ebee3484	480	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
emilmont	27:7110ebee3484	481	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
emilmont	27:7110ebee3484	482
emilmont	27:7110ebee3484	483	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
emilmont	27:7110ebee3484	484	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
emilmont	27:7110ebee3484	485
emilmont	27:7110ebee3484	486	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
emilmont	27:7110ebee3484	487	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
emilmont	27:7110ebee3484	488
emilmont	27:7110ebee3484	489	/* SCB Configurable Fault Status Registers Definitions */
emilmont	27:7110ebee3484	490	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
emilmont	27:7110ebee3484	491	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
emilmont	27:7110ebee3484	492
emilmont	27:7110ebee3484	493	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
emilmont	27:7110ebee3484	494	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
emilmont	27:7110ebee3484	495
emilmont	27:7110ebee3484	496	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
emilmont	27:7110ebee3484	497	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
emilmont	27:7110ebee3484	498
emilmont	27:7110ebee3484	499	/* SCB Hard Fault Status Registers Definitions */
emilmont	27:7110ebee3484	500	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
emilmont	27:7110ebee3484	501	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
emilmont	27:7110ebee3484	502
emilmont	27:7110ebee3484	503	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
emilmont	27:7110ebee3484	504	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
emilmont	27:7110ebee3484	505
emilmont	27:7110ebee3484	506	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
emilmont	27:7110ebee3484	507	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
emilmont	27:7110ebee3484	508
emilmont	27:7110ebee3484	509	/* SCB Debug Fault Status Register Definitions */
emilmont	27:7110ebee3484	510	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
emilmont	27:7110ebee3484	511	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
emilmont	27:7110ebee3484	512
emilmont	27:7110ebee3484	513	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
emilmont	27:7110ebee3484	514	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
emilmont	27:7110ebee3484	515
emilmont	27:7110ebee3484	516	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
emilmont	27:7110ebee3484	517	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
emilmont	27:7110ebee3484	518
emilmont	27:7110ebee3484	519	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
emilmont	27:7110ebee3484	520	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
emilmont	27:7110ebee3484	521
emilmont	27:7110ebee3484	522	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
emilmont	27:7110ebee3484	523	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
emilmont	27:7110ebee3484	524
emilmont	27:7110ebee3484	525	/@} end of group CMSIS_SCB /
emilmont	27:7110ebee3484	526
emilmont	27:7110ebee3484	527
emilmont	33:5364839841bd	528	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	529	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont	33:5364839841bd	530	\brief Type definitions for the System Control and ID Register not in the SCB
emilmont	33:5364839841bd	531	@{
emilmont	33:5364839841bd	532	*/
emilmont	33:5364839841bd	533
emilmont	33:5364839841bd	534	/** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont	33:5364839841bd	535	*/
emilmont	33:5364839841bd	536	typedef struct
emilmont	33:5364839841bd	537	{
emilmont	33:5364839841bd	538	uint32_t RESERVED0[1];
emilmont	33:5364839841bd	539	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
emilmont	33:5364839841bd	540	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
emilmont	33:5364839841bd	541	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
emilmont	33:5364839841bd	542	#else
emilmont	33:5364839841bd	543	uint32_t RESERVED1[1];
emilmont	33:5364839841bd	544	#endif
emilmont	33:5364839841bd	545	} SCnSCB_Type;
emilmont	33:5364839841bd	546
emilmont	33:5364839841bd	547	/* Interrupt Controller Type Register Definitions */
emilmont	33:5364839841bd	548	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
emilmont	33:5364839841bd	549	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
emilmont	33:5364839841bd	550
emilmont	33:5364839841bd	551	/* Auxiliary Control Register Definitions */
emilmont	33:5364839841bd	552
emilmont	33:5364839841bd	553	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
emilmont	33:5364839841bd	554	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
emilmont	33:5364839841bd	555
emilmont	33:5364839841bd	556	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
emilmont	33:5364839841bd	557	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
emilmont	33:5364839841bd	558
emilmont	33:5364839841bd	559	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
emilmont	33:5364839841bd	560	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
emilmont	33:5364839841bd	561
emilmont	33:5364839841bd	562	/@} end of group CMSIS_SCnotSCB /
emilmont	33:5364839841bd	563
emilmont	33:5364839841bd	564
emilmont	33:5364839841bd	565	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	566	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont	33:5364839841bd	567	\brief Type definitions for the System Timer Registers.
emilmont	27:7110ebee3484	568	@{
emilmont	27:7110ebee3484	569	*/
emilmont	27:7110ebee3484	570
emilmont	27:7110ebee3484	571	/** \brief Structure type to access the System Timer (SysTick).
emilmont	27:7110ebee3484	572	*/
emilmont	27:7110ebee3484	573	typedef struct
emilmont	27:7110ebee3484	574	{
emilmont	27:7110ebee3484	575	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
emilmont	27:7110ebee3484	576	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
emilmont	27:7110ebee3484	577	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
emilmont	27:7110ebee3484	578	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
emilmont	27:7110ebee3484	579	} SysTick_Type;
emilmont	27:7110ebee3484	580
emilmont	27:7110ebee3484	581	/* SysTick Control / Status Register Definitions */
emilmont	27:7110ebee3484	582	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
emilmont	27:7110ebee3484	583	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
emilmont	27:7110ebee3484	584
emilmont	27:7110ebee3484	585	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
emilmont	27:7110ebee3484	586	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
emilmont	27:7110ebee3484	587
emilmont	27:7110ebee3484	588	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
emilmont	27:7110ebee3484	589	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
emilmont	27:7110ebee3484	590
emilmont	27:7110ebee3484	591	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
emilmont	27:7110ebee3484	592	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
emilmont	27:7110ebee3484	593
emilmont	27:7110ebee3484	594	/* SysTick Reload Register Definitions */
emilmont	27:7110ebee3484	595	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
emilmont	27:7110ebee3484	596	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
emilmont	27:7110ebee3484	597
emilmont	27:7110ebee3484	598	/* SysTick Current Register Definitions */
emilmont	27:7110ebee3484	599	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
emilmont	27:7110ebee3484	600	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
emilmont	27:7110ebee3484	601
emilmont	27:7110ebee3484	602	/* SysTick Calibration Register Definitions */
emilmont	27:7110ebee3484	603	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
emilmont	27:7110ebee3484	604	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
emilmont	27:7110ebee3484	605
emilmont	27:7110ebee3484	606	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
emilmont	27:7110ebee3484	607	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
emilmont	27:7110ebee3484	608
emilmont	27:7110ebee3484	609	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
emilmont	27:7110ebee3484	610	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
emilmont	27:7110ebee3484	611
emilmont	27:7110ebee3484	612	/@} end of group CMSIS_SysTick /
emilmont	27:7110ebee3484	613
emilmont	27:7110ebee3484	614
emilmont	33:5364839841bd	615	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	616	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont	33:5364839841bd	617	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont	27:7110ebee3484	618	@{
emilmont	27:7110ebee3484	619	*/
emilmont	27:7110ebee3484	620
emilmont	27:7110ebee3484	621	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont	27:7110ebee3484	622	*/
emilmont	27:7110ebee3484	623	typedef struct
emilmont	27:7110ebee3484	624	{
emilmont	33:5364839841bd	625	__O union
emilmont	27:7110ebee3484	626	{
emilmont	27:7110ebee3484	627	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
emilmont	27:7110ebee3484	628	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
emilmont	27:7110ebee3484	629	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
emilmont	27:7110ebee3484	630	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
emilmont	33:5364839841bd	631	uint32_t RESERVED0[864];
emilmont	33:5364839841bd	632	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
emilmont	33:5364839841bd	633	uint32_t RESERVED1[15];
emilmont	33:5364839841bd	634	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
emilmont	33:5364839841bd	635	uint32_t RESERVED2[15];
emilmont	33:5364839841bd	636	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
emilmont	33:5364839841bd	637	} ITM_Type;
emilmont	27:7110ebee3484	638
emilmont	27:7110ebee3484	639	/* ITM Trace Privilege Register Definitions */
emilmont	33:5364839841bd	640	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
emilmont	33:5364839841bd	641	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
emilmont	27:7110ebee3484	642
emilmont	27:7110ebee3484	643	/* ITM Trace Control Register Definitions */
emilmont	33:5364839841bd	644	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
emilmont	33:5364839841bd	645	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
emilmont	27:7110ebee3484	646
emilmont	33:5364839841bd	647	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
emilmont	33:5364839841bd	648	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
emilmont	27:7110ebee3484	649
emilmont	33:5364839841bd	650	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
emilmont	33:5364839841bd	651	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
emilmont	27:7110ebee3484	652
emilmont	33:5364839841bd	653	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
emilmont	33:5364839841bd	654	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
emilmont	27:7110ebee3484	655
emilmont	33:5364839841bd	656	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
emilmont	33:5364839841bd	657	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
emilmont	27:7110ebee3484	658
emilmont	33:5364839841bd	659	#define ITM_TCR_TXENA_Pos 3 /!< ITM TCR: TXENA Position /
emilmont	33:5364839841bd	660	#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /!< ITM TCR: TXENA Mask /
emilmont	27:7110ebee3484	661
emilmont	33:5364839841bd	662	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
emilmont	33:5364839841bd	663	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
emilmont	27:7110ebee3484	664
emilmont	33:5364839841bd	665	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
emilmont	33:5364839841bd	666	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
emilmont	27:7110ebee3484	667
emilmont	33:5364839841bd	668	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
emilmont	33:5364839841bd	669	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
emilmont	27:7110ebee3484	670
emilmont	27:7110ebee3484	671	/@}/ /* end of group CMSIS_ITM */
emilmont	27:7110ebee3484	672
emilmont	27:7110ebee3484	673
emilmont	39:737756e0b479	674	/** \ingroup CMSIS_core_register
emilmont	39:737756e0b479	675	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
emilmont	39:737756e0b479	676	\brief Type definitions for the Data Watchpoint and Trace (DWT)
emilmont	39:737756e0b479	677	@{
emilmont	39:737756e0b479	678	*/
emilmont	39:737756e0b479	679
emilmont	39:737756e0b479	680	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
emilmont	39:737756e0b479	681	*/
emilmont	39:737756e0b479	682	typedef struct
emilmont	39:737756e0b479	683	{
emilmont	39:737756e0b479	684	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
emilmont	39:737756e0b479	685	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
emilmont	39:737756e0b479	686	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
emilmont	39:737756e0b479	687	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
emilmont	39:737756e0b479	688	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
emilmont	39:737756e0b479	689	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
emilmont	39:737756e0b479	690	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
emilmont	39:737756e0b479	691	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
emilmont	39:737756e0b479	692	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
emilmont	39:737756e0b479	693	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
emilmont	39:737756e0b479	694	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
emilmont	39:737756e0b479	695	uint32_t RESERVED0[1];
emilmont	39:737756e0b479	696	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
emilmont	39:737756e0b479	697	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
emilmont	39:737756e0b479	698	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
emilmont	39:737756e0b479	699	uint32_t RESERVED1[1];
emilmont	39:737756e0b479	700	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
emilmont	39:737756e0b479	701	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
emilmont	39:737756e0b479	702	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
emilmont	39:737756e0b479	703	uint32_t RESERVED2[1];
emilmont	39:737756e0b479	704	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
emilmont	39:737756e0b479	705	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
emilmont	39:737756e0b479	706	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
emilmont	39:737756e0b479	707	} DWT_Type;
emilmont	39:737756e0b479	708
emilmont	39:737756e0b479	709	/* DWT Control Register Definitions */
emilmont	39:737756e0b479	710	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
emilmont	39:737756e0b479	711	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
emilmont	39:737756e0b479	712
emilmont	39:737756e0b479	713	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
emilmont	39:737756e0b479	714	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
emilmont	39:737756e0b479	715
emilmont	39:737756e0b479	716	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
emilmont	39:737756e0b479	717	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
emilmont	39:737756e0b479	718
emilmont	39:737756e0b479	719	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
emilmont	39:737756e0b479	720	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
emilmont	39:737756e0b479	721
emilmont	39:737756e0b479	722	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
emilmont	39:737756e0b479	723	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
emilmont	39:737756e0b479	724
emilmont	39:737756e0b479	725	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
emilmont	39:737756e0b479	726	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
emilmont	39:737756e0b479	727
emilmont	39:737756e0b479	728	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
emilmont	39:737756e0b479	729	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
emilmont	39:737756e0b479	730
emilmont	39:737756e0b479	731	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
emilmont	39:737756e0b479	732	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
emilmont	39:737756e0b479	733
emilmont	39:737756e0b479	734	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
emilmont	39:737756e0b479	735	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
emilmont	39:737756e0b479	736
emilmont	39:737756e0b479	737	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
emilmont	39:737756e0b479	738	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
emilmont	39:737756e0b479	739
emilmont	39:737756e0b479	740	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
emilmont	39:737756e0b479	741	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
emilmont	39:737756e0b479	742
emilmont	39:737756e0b479	743	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
emilmont	39:737756e0b479	744	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
emilmont	39:737756e0b479	745
emilmont	39:737756e0b479	746	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
emilmont	39:737756e0b479	747	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
emilmont	39:737756e0b479	748
emilmont	39:737756e0b479	749	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
emilmont	39:737756e0b479	750	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
emilmont	39:737756e0b479	751
emilmont	39:737756e0b479	752	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
emilmont	39:737756e0b479	753	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
emilmont	39:737756e0b479	754
emilmont	39:737756e0b479	755	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
emilmont	39:737756e0b479	756	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
emilmont	39:737756e0b479	757
emilmont	39:737756e0b479	758	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
emilmont	39:737756e0b479	759	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
emilmont	39:737756e0b479	760
emilmont	39:737756e0b479	761	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
emilmont	39:737756e0b479	762	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
emilmont	39:737756e0b479	763
emilmont	39:737756e0b479	764	/* DWT CPI Count Register Definitions */
emilmont	39:737756e0b479	765	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
emilmont	39:737756e0b479	766	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
emilmont	39:737756e0b479	767
emilmont	39:737756e0b479	768	/* DWT Exception Overhead Count Register Definitions */
emilmont	39:737756e0b479	769	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
emilmont	39:737756e0b479	770	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
emilmont	39:737756e0b479	771
emilmont	39:737756e0b479	772	/* DWT Sleep Count Register Definitions */
emilmont	39:737756e0b479	773	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
emilmont	39:737756e0b479	774	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
emilmont	39:737756e0b479	775
emilmont	39:737756e0b479	776	/* DWT LSU Count Register Definitions */
emilmont	39:737756e0b479	777	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
emilmont	39:737756e0b479	778	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
emilmont	39:737756e0b479	779
emilmont	39:737756e0b479	780	/* DWT Folded-instruction Count Register Definitions */
emilmont	39:737756e0b479	781	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
emilmont	39:737756e0b479	782	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
emilmont	39:737756e0b479	783
emilmont	39:737756e0b479	784	/* DWT Comparator Mask Register Definitions */
emilmont	39:737756e0b479	785	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
emilmont	39:737756e0b479	786	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
emilmont	39:737756e0b479	787
emilmont	39:737756e0b479	788	/* DWT Comparator Function Register Definitions */
emilmont	39:737756e0b479	789	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
emilmont	39:737756e0b479	790	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
emilmont	39:737756e0b479	791
emilmont	39:737756e0b479	792	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
emilmont	39:737756e0b479	793	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
emilmont	39:737756e0b479	794
emilmont	39:737756e0b479	795	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
emilmont	39:737756e0b479	796	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
emilmont	39:737756e0b479	797
emilmont	39:737756e0b479	798	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
emilmont	39:737756e0b479	799	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
emilmont	39:737756e0b479	800
emilmont	39:737756e0b479	801	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
emilmont	39:737756e0b479	802	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
emilmont	39:737756e0b479	803
emilmont	39:737756e0b479	804	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
emilmont	39:737756e0b479	805	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
emilmont	39:737756e0b479	806
emilmont	39:737756e0b479	807	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
emilmont	39:737756e0b479	808	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
emilmont	39:737756e0b479	809
emilmont	39:737756e0b479	810	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
emilmont	39:737756e0b479	811	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
emilmont	39:737756e0b479	812
emilmont	39:737756e0b479	813	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
emilmont	39:737756e0b479	814	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
emilmont	39:737756e0b479	815
emilmont	39:737756e0b479	816	/@}/ /* end of group CMSIS_DWT */
emilmont	39:737756e0b479	817
emilmont	39:737756e0b479	818
emilmont	39:737756e0b479	819	/** \ingroup CMSIS_core_register
emilmont	39:737756e0b479	820	\defgroup CMSIS_TPI Trace Port Interface (TPI)
emilmont	39:737756e0b479	821	\brief Type definitions for the Trace Port Interface (TPI)
emilmont	39:737756e0b479	822	@{
emilmont	39:737756e0b479	823	*/
emilmont	39:737756e0b479	824
emilmont	39:737756e0b479	825	/** \brief Structure type to access the Trace Port Interface Register (TPI).
emilmont	39:737756e0b479	826	*/
emilmont	39:737756e0b479	827	typedef struct
emilmont	39:737756e0b479	828	{
emilmont	39:737756e0b479	829	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
emilmont	39:737756e0b479	830	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
emilmont	39:737756e0b479	831	uint32_t RESERVED0[2];
emilmont	39:737756e0b479	832	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
emilmont	39:737756e0b479	833	uint32_t RESERVED1[55];
emilmont	39:737756e0b479	834	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
emilmont	39:737756e0b479	835	uint32_t RESERVED2[131];
emilmont	39:737756e0b479	836	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
emilmont	39:737756e0b479	837	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
emilmont	39:737756e0b479	838	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
emilmont	39:737756e0b479	839	uint32_t RESERVED3[759];
emilmont	39:737756e0b479	840	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
emilmont	39:737756e0b479	841	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
emilmont	39:737756e0b479	842	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
emilmont	39:737756e0b479	843	uint32_t RESERVED4[1];
emilmont	39:737756e0b479	844	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
emilmont	39:737756e0b479	845	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
emilmont	39:737756e0b479	846	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
emilmont	39:737756e0b479	847	uint32_t RESERVED5[39];
emilmont	39:737756e0b479	848	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
emilmont	39:737756e0b479	849	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
emilmont	39:737756e0b479	850	uint32_t RESERVED7[8];
emilmont	39:737756e0b479	851	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
emilmont	39:737756e0b479	852	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
emilmont	39:737756e0b479	853	} TPI_Type;
emilmont	39:737756e0b479	854
emilmont	39:737756e0b479	855	/* TPI Asynchronous Clock Prescaler Register Definitions */
emilmont	39:737756e0b479	856	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
emilmont	39:737756e0b479	857	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
emilmont	39:737756e0b479	858
emilmont	39:737756e0b479	859	/* TPI Selected Pin Protocol Register Definitions */
emilmont	39:737756e0b479	860	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
emilmont	39:737756e0b479	861	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
emilmont	39:737756e0b479	862
emilmont	39:737756e0b479	863	/* TPI Formatter and Flush Status Register Definitions */
emilmont	39:737756e0b479	864	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
emilmont	39:737756e0b479	865	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
emilmont	39:737756e0b479	866
emilmont	39:737756e0b479	867	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
emilmont	39:737756e0b479	868	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
emilmont	39:737756e0b479	869
emilmont	39:737756e0b479	870	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
emilmont	39:737756e0b479	871	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
emilmont	39:737756e0b479	872
emilmont	39:737756e0b479	873	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
emilmont	39:737756e0b479	874	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
emilmont	39:737756e0b479	875
emilmont	39:737756e0b479	876	/* TPI Formatter and Flush Control Register Definitions */
emilmont	39:737756e0b479	877	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
emilmont	39:737756e0b479	878	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
emilmont	39:737756e0b479	879
emilmont	39:737756e0b479	880	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
emilmont	39:737756e0b479	881	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
emilmont	39:737756e0b479	882
emilmont	39:737756e0b479	883	/* TPI TRIGGER Register Definitions */
emilmont	39:737756e0b479	884	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
emilmont	39:737756e0b479	885	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
emilmont	39:737756e0b479	886
emilmont	39:737756e0b479	887	/* TPI Integration ETM Data Register Definitions (FIFO0) */
emilmont	39:737756e0b479	888	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
emilmont	39:737756e0b479	889	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
emilmont	39:737756e0b479	890
emilmont	39:737756e0b479	891	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
emilmont	39:737756e0b479	892	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
emilmont	39:737756e0b479	893
emilmont	39:737756e0b479	894	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
emilmont	39:737756e0b479	895	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
emilmont	39:737756e0b479	896
emilmont	39:737756e0b479	897	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
emilmont	39:737756e0b479	898	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
emilmont	39:737756e0b479	899
emilmont	39:737756e0b479	900	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
emilmont	39:737756e0b479	901	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
emilmont	39:737756e0b479	902
emilmont	39:737756e0b479	903	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
emilmont	39:737756e0b479	904	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
emilmont	39:737756e0b479	905
emilmont	39:737756e0b479	906	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
emilmont	39:737756e0b479	907	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
emilmont	39:737756e0b479	908
emilmont	39:737756e0b479	909	/* TPI ITATBCTR2 Register Definitions */
emilmont	39:737756e0b479	910	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
emilmont	39:737756e0b479	911	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
emilmont	39:737756e0b479	912
emilmont	39:737756e0b479	913	/* TPI Integration ITM Data Register Definitions (FIFO1) */
emilmont	39:737756e0b479	914	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
emilmont	39:737756e0b479	915	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
emilmont	39:737756e0b479	916
emilmont	39:737756e0b479	917	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
emilmont	39:737756e0b479	918	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
emilmont	39:737756e0b479	919
emilmont	39:737756e0b479	920	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
emilmont	39:737756e0b479	921	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
emilmont	39:737756e0b479	922
emilmont	39:737756e0b479	923	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
emilmont	39:737756e0b479	924	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
emilmont	39:737756e0b479	925
emilmont	39:737756e0b479	926	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
emilmont	39:737756e0b479	927	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
emilmont	39:737756e0b479	928
emilmont	39:737756e0b479	929	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
emilmont	39:737756e0b479	930	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
emilmont	39:737756e0b479	931
emilmont	39:737756e0b479	932	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
emilmont	39:737756e0b479	933	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
emilmont	39:737756e0b479	934
emilmont	39:737756e0b479	935	/* TPI ITATBCTR0 Register Definitions */
emilmont	39:737756e0b479	936	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
emilmont	39:737756e0b479	937	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
emilmont	39:737756e0b479	938
emilmont	39:737756e0b479	939	/* TPI Integration Mode Control Register Definitions */
emilmont	39:737756e0b479	940	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
emilmont	39:737756e0b479	941	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
emilmont	39:737756e0b479	942
emilmont	39:737756e0b479	943	/* TPI DEVID Register Definitions */
emilmont	39:737756e0b479	944	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
emilmont	39:737756e0b479	945	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
emilmont	39:737756e0b479	946
emilmont	39:737756e0b479	947	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
emilmont	39:737756e0b479	948	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
emilmont	39:737756e0b479	949
emilmont	39:737756e0b479	950	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
emilmont	39:737756e0b479	951	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
emilmont	39:737756e0b479	952
emilmont	39:737756e0b479	953	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
emilmont	39:737756e0b479	954	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
emilmont	39:737756e0b479	955
emilmont	39:737756e0b479	956	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
emilmont	39:737756e0b479	957	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
emilmont	39:737756e0b479	958
emilmont	39:737756e0b479	959	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
emilmont	39:737756e0b479	960	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
emilmont	39:737756e0b479	961
emilmont	39:737756e0b479	962	/* TPI DEVTYPE Register Definitions */
emilmont	39:737756e0b479	963	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
emilmont	39:737756e0b479	964	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
emilmont	39:737756e0b479	965
emilmont	39:737756e0b479	966	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
emilmont	39:737756e0b479	967	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
emilmont	39:737756e0b479	968
emilmont	39:737756e0b479	969	/@}/ /* end of group CMSIS_TPI */
emilmont	39:737756e0b479	970
emilmont	39:737756e0b479	971
emilmont	27:7110ebee3484	972	#if (__MPU_PRESENT == 1)
emilmont	33:5364839841bd	973	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	974	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont	33:5364839841bd	975	\brief Type definitions for the Memory Protection Unit (MPU)
emilmont	27:7110ebee3484	976	@{
emilmont	27:7110ebee3484	977	*/
emilmont	27:7110ebee3484	978
emilmont	27:7110ebee3484	979	/** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont	27:7110ebee3484	980	*/
emilmont	27:7110ebee3484	981	typedef struct
emilmont	27:7110ebee3484	982	{
emilmont	27:7110ebee3484	983	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
emilmont	27:7110ebee3484	984	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
emilmont	27:7110ebee3484	985	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
emilmont	27:7110ebee3484	986	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
emilmont	27:7110ebee3484	987	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
emilmont	27:7110ebee3484	988	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
emilmont	27:7110ebee3484	989	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
emilmont	27:7110ebee3484	990	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
emilmont	27:7110ebee3484	991	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
emilmont	27:7110ebee3484	992	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
emilmont	27:7110ebee3484	993	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
emilmont	33:5364839841bd	994	} MPU_Type;
emilmont	27:7110ebee3484	995
emilmont	27:7110ebee3484	996	/* MPU Type Register */
emilmont	27:7110ebee3484	997	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
emilmont	27:7110ebee3484	998	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
emilmont	27:7110ebee3484	999
emilmont	27:7110ebee3484	1000	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
emilmont	27:7110ebee3484	1001	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
emilmont	27:7110ebee3484	1002
emilmont	27:7110ebee3484	1003	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
emilmont	27:7110ebee3484	1004	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
emilmont	27:7110ebee3484	1005
emilmont	27:7110ebee3484	1006	/* MPU Control Register */
emilmont	27:7110ebee3484	1007	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
emilmont	27:7110ebee3484	1008	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
emilmont	27:7110ebee3484	1009
emilmont	27:7110ebee3484	1010	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
emilmont	27:7110ebee3484	1011	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
emilmont	27:7110ebee3484	1012
emilmont	27:7110ebee3484	1013	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
emilmont	27:7110ebee3484	1014	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
emilmont	27:7110ebee3484	1015
emilmont	27:7110ebee3484	1016	/* MPU Region Number Register */
emilmont	27:7110ebee3484	1017	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
emilmont	27:7110ebee3484	1018	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
emilmont	27:7110ebee3484	1019
emilmont	27:7110ebee3484	1020	/* MPU Region Base Address Register */
emilmont	27:7110ebee3484	1021	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
emilmont	27:7110ebee3484	1022	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
emilmont	27:7110ebee3484	1023
emilmont	27:7110ebee3484	1024	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
emilmont	27:7110ebee3484	1025	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
emilmont	27:7110ebee3484	1026
emilmont	27:7110ebee3484	1027	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
emilmont	27:7110ebee3484	1028	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
emilmont	27:7110ebee3484	1029
emilmont	27:7110ebee3484	1030	/* MPU Region Attribute and Size Register */
emilmont	33:5364839841bd	1031	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
emilmont	33:5364839841bd	1032	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
emilmont	27:7110ebee3484	1033
emilmont	27:7110ebee3484	1034	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
emilmont	27:7110ebee3484	1035	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
emilmont	27:7110ebee3484	1036
emilmont	27:7110ebee3484	1037	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
emilmont	27:7110ebee3484	1038	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
emilmont	27:7110ebee3484	1039
emilmont	33:5364839841bd	1040	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
emilmont	33:5364839841bd	1041	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
emilmont	27:7110ebee3484	1042
emilmont	27:7110ebee3484	1043	/@} end of group CMSIS_MPU /
emilmont	27:7110ebee3484	1044	#endif
emilmont	27:7110ebee3484	1045
emilmont	27:7110ebee3484	1046
emilmont	33:5364839841bd	1047	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	1048	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont	33:5364839841bd	1049	\brief Type definitions for the Core Debug Registers
emilmont	27:7110ebee3484	1050	@{
emilmont	27:7110ebee3484	1051	*/
emilmont	27:7110ebee3484	1052
emilmont	27:7110ebee3484	1053	/** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont	27:7110ebee3484	1054	*/
emilmont	27:7110ebee3484	1055	typedef struct
emilmont	27:7110ebee3484	1056	{
emilmont	27:7110ebee3484	1057	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
emilmont	27:7110ebee3484	1058	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
emilmont	27:7110ebee3484	1059	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
emilmont	27:7110ebee3484	1060	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
emilmont	27:7110ebee3484	1061	} CoreDebug_Type;
emilmont	27:7110ebee3484	1062
emilmont	27:7110ebee3484	1063	/* Debug Halting Control and Status Register */
emilmont	27:7110ebee3484	1064	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
emilmont	27:7110ebee3484	1065	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
emilmont	27:7110ebee3484	1066
emilmont	27:7110ebee3484	1067	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
emilmont	27:7110ebee3484	1068	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
emilmont	27:7110ebee3484	1069
emilmont	27:7110ebee3484	1070	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
emilmont	27:7110ebee3484	1071	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
emilmont	27:7110ebee3484	1072
emilmont	27:7110ebee3484	1073	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
emilmont	27:7110ebee3484	1074	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
emilmont	27:7110ebee3484	1075
emilmont	27:7110ebee3484	1076	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
emilmont	27:7110ebee3484	1077	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
emilmont	27:7110ebee3484	1078
emilmont	27:7110ebee3484	1079	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
emilmont	27:7110ebee3484	1080	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
emilmont	27:7110ebee3484	1081
emilmont	27:7110ebee3484	1082	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
emilmont	27:7110ebee3484	1083	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
emilmont	27:7110ebee3484	1084
emilmont	27:7110ebee3484	1085	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
emilmont	27:7110ebee3484	1086	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
emilmont	27:7110ebee3484	1087
emilmont	27:7110ebee3484	1088	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
emilmont	27:7110ebee3484	1089	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
emilmont	27:7110ebee3484	1090
emilmont	27:7110ebee3484	1091	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
emilmont	27:7110ebee3484	1092	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
emilmont	27:7110ebee3484	1093
emilmont	27:7110ebee3484	1094	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
emilmont	27:7110ebee3484	1095	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
emilmont	27:7110ebee3484	1096
emilmont	27:7110ebee3484	1097	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
emilmont	27:7110ebee3484	1098	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
emilmont	27:7110ebee3484	1099
emilmont	27:7110ebee3484	1100	/* Debug Core Register Selector Register */
emilmont	27:7110ebee3484	1101	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
emilmont	27:7110ebee3484	1102	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
emilmont	27:7110ebee3484	1103
emilmont	27:7110ebee3484	1104	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
emilmont	27:7110ebee3484	1105	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
emilmont	27:7110ebee3484	1106
emilmont	27:7110ebee3484	1107	/* Debug Exception and Monitor Control Register */
emilmont	27:7110ebee3484	1108	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
emilmont	27:7110ebee3484	1109	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
emilmont	27:7110ebee3484	1110
emilmont	27:7110ebee3484	1111	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
emilmont	27:7110ebee3484	1112	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
emilmont	27:7110ebee3484	1113
emilmont	27:7110ebee3484	1114	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
emilmont	27:7110ebee3484	1115	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
emilmont	27:7110ebee3484	1116
emilmont	27:7110ebee3484	1117	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
emilmont	27:7110ebee3484	1118	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
emilmont	27:7110ebee3484	1119
emilmont	27:7110ebee3484	1120	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
emilmont	27:7110ebee3484	1121	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
emilmont	27:7110ebee3484	1122
emilmont	27:7110ebee3484	1123	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
emilmont	27:7110ebee3484	1124	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
emilmont	27:7110ebee3484	1125
emilmont	27:7110ebee3484	1126	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
emilmont	27:7110ebee3484	1127	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
emilmont	27:7110ebee3484	1128
emilmont	27:7110ebee3484	1129	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
emilmont	27:7110ebee3484	1130	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
emilmont	27:7110ebee3484	1131
emilmont	27:7110ebee3484	1132	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
emilmont	27:7110ebee3484	1133	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
emilmont	27:7110ebee3484	1134
emilmont	27:7110ebee3484	1135	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
emilmont	27:7110ebee3484	1136	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
emilmont	27:7110ebee3484	1137
emilmont	27:7110ebee3484	1138	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
emilmont	27:7110ebee3484	1139	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
emilmont	27:7110ebee3484	1140
emilmont	27:7110ebee3484	1141	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
emilmont	27:7110ebee3484	1142	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
emilmont	27:7110ebee3484	1143
emilmont	27:7110ebee3484	1144	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
emilmont	27:7110ebee3484	1145	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
emilmont	27:7110ebee3484	1146
emilmont	27:7110ebee3484	1147	/@} end of group CMSIS_CoreDebug /
emilmont	27:7110ebee3484	1148
emilmont	27:7110ebee3484	1149
emilmont	33:5364839841bd	1150	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	1151	\defgroup CMSIS_core_base Core Definitions
emilmont	33:5364839841bd	1152	\brief Definitions for base addresses, unions, and structures.
emilmont	27:7110ebee3484	1153	@{
emilmont	27:7110ebee3484	1154	*/
emilmont	33:5364839841bd	1155
emilmont	27:7110ebee3484	1156	/* Memory mapping of Cortex-M3 Hardware */
emilmont	33:5364839841bd	1157	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
emilmont	33:5364839841bd	1158	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
emilmont	39:737756e0b479	1159	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
emilmont	39:737756e0b479	1160	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
emilmont	33:5364839841bd	1161	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
emilmont	33:5364839841bd	1162	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
emilmont	33:5364839841bd	1163	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
emilmont	33:5364839841bd	1164	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
emilmont	27:7110ebee3484	1165
emilmont	33:5364839841bd	1166	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
emilmont	33:5364839841bd	1167	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
emilmont	33:5364839841bd	1168	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
emilmont	33:5364839841bd	1169	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
emilmont	33:5364839841bd	1170	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
emilmont	39:737756e0b479	1171	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
emilmont	39:737756e0b479	1172	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
emilmont	33:5364839841bd	1173	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
emilmont	27:7110ebee3484	1174
emilmont	27:7110ebee3484	1175	#if (__MPU_PRESENT == 1)
emilmont	33:5364839841bd	1176	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
emilmont	33:5364839841bd	1177	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
emilmont	27:7110ebee3484	1178	#endif
emilmont	27:7110ebee3484	1179
emilmont	27:7110ebee3484	1180	/@} /
emilmont	27:7110ebee3484	1181
emilmont	27:7110ebee3484	1182
emilmont	27:7110ebee3484	1183
emilmont	27:7110ebee3484	1184	/*******************************************************************************
emilmont	27:7110ebee3484	1185	* Hardware Abstraction Layer
emilmont	27:7110ebee3484	1186	Core Function Interface contains:
emilmont	27:7110ebee3484	1187	- Core NVIC Functions
emilmont	27:7110ebee3484	1188	- Core SysTick Functions
emilmont	27:7110ebee3484	1189	- Core Debug Functions
emilmont	27:7110ebee3484	1190	- Core Register Access Functions
emilmont	33:5364839841bd	1191	******************************************************************************/
emilmont	33:5364839841bd	1192	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont	27:7110ebee3484	1193	*/
emilmont	27:7110ebee3484	1194
emilmont	27:7110ebee3484	1195
emilmont	27:7110ebee3484	1196
emilmont	27:7110ebee3484	1197	/* ########################## NVIC functions #################################### */
emilmont	33:5364839841bd	1198	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	33:5364839841bd	1199	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont	33:5364839841bd	1200	\brief Functions that manage interrupts and exceptions via the NVIC.
emilmont	33:5364839841bd	1201	@{
emilmont	27:7110ebee3484	1202	*/
emilmont	27:7110ebee3484	1203
emilmont	27:7110ebee3484	1204	/** \brief Set Priority Grouping
emilmont	27:7110ebee3484	1205
emilmont	33:5364839841bd	1206	The function sets the priority grouping field using the required unlock sequence.
emilmont	27:7110ebee3484	1207	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont	27:7110ebee3484	1208	Only values from 0..7 are used.
emilmont	27:7110ebee3484	1209	In case of a conflict between priority grouping and available
emilmont	33:5364839841bd	1210	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont	27:7110ebee3484	1211
emilmont	33:5364839841bd	1212	\param [in] PriorityGroup Priority grouping field.
emilmont	27:7110ebee3484	1213	*/
emilmont	39:737756e0b479	1214	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont	27:7110ebee3484	1215	{
emilmont	27:7110ebee3484	1216	uint32_t reg_value;
emilmont	33:5364839841bd	1217	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
emilmont	33:5364839841bd	1218
emilmont	27:7110ebee3484	1219	reg_value = SCB->AIRCR; /* read old register configuration */
emilmont	27:7110ebee3484	1220	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
emilmont	33:5364839841bd	1221	reg_value = (reg_value \|
emilmont	33:5364839841bd	1222	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
emilmont	27:7110ebee3484	1223	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
emilmont	27:7110ebee3484	1224	SCB->AIRCR = reg_value;
emilmont	27:7110ebee3484	1225	}
emilmont	27:7110ebee3484	1226
emilmont	27:7110ebee3484	1227
emilmont	27:7110ebee3484	1228	/** \brief Get Priority Grouping
emilmont	27:7110ebee3484	1229
emilmont	33:5364839841bd	1230	The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont	27:7110ebee3484	1231
emilmont	33:5364839841bd	1232	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont	27:7110ebee3484	1233	*/
emilmont	39:737756e0b479	1234	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
emilmont	27:7110ebee3484	1235	{
emilmont	27:7110ebee3484	1236	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
emilmont	27:7110ebee3484	1237	}
emilmont	27:7110ebee3484	1238
emilmont	27:7110ebee3484	1239
emilmont	27:7110ebee3484	1240	/** \brief Enable External Interrupt
emilmont	27:7110ebee3484	1241
emilmont	33:5364839841bd	1242	The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont	27:7110ebee3484	1243
emilmont	33:5364839841bd	1244	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	27:7110ebee3484	1245	*/
emilmont	39:737756e0b479	1246	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1247	{
emilmont	27:7110ebee3484	1248	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
emilmont	27:7110ebee3484	1249	}
emilmont	27:7110ebee3484	1250
emilmont	27:7110ebee3484	1251
emilmont	27:7110ebee3484	1252	/** \brief Disable External Interrupt
emilmont	27:7110ebee3484	1253
emilmont	33:5364839841bd	1254	The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont	27:7110ebee3484	1255
emilmont	33:5364839841bd	1256	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	27:7110ebee3484	1257	*/
emilmont	39:737756e0b479	1258	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1259	{
emilmont	27:7110ebee3484	1260	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
emilmont	27:7110ebee3484	1261	}
emilmont	27:7110ebee3484	1262
emilmont	27:7110ebee3484	1263
emilmont	27:7110ebee3484	1264	/** \brief Get Pending Interrupt
emilmont	27:7110ebee3484	1265
emilmont	33:5364839841bd	1266	The function reads the pending register in the NVIC and returns the pending bit
emilmont	33:5364839841bd	1267	for the specified interrupt.
emilmont	27:7110ebee3484	1268
emilmont	33:5364839841bd	1269	\param [in] IRQn Interrupt number.
emilmont	39:737756e0b479	1270
emilmont	33:5364839841bd	1271	\return 0 Interrupt status is not pending.
emilmont	33:5364839841bd	1272	\return 1 Interrupt status is pending.
emilmont	27:7110ebee3484	1273	*/
emilmont	39:737756e0b479	1274	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1275	{
emilmont	27:7110ebee3484	1276	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
emilmont	27:7110ebee3484	1277	}
emilmont	27:7110ebee3484	1278
emilmont	27:7110ebee3484	1279
emilmont	27:7110ebee3484	1280	/** \brief Set Pending Interrupt
emilmont	27:7110ebee3484	1281
emilmont	33:5364839841bd	1282	The function sets the pending bit of an external interrupt.
emilmont	27:7110ebee3484	1283
emilmont	33:5364839841bd	1284	\param [in] IRQn Interrupt number. Value cannot be negative.
emilmont	27:7110ebee3484	1285	*/
emilmont	39:737756e0b479	1286	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1287	{
emilmont	27:7110ebee3484	1288	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
emilmont	27:7110ebee3484	1289	}
emilmont	27:7110ebee3484	1290
emilmont	27:7110ebee3484	1291
emilmont	27:7110ebee3484	1292	/** \brief Clear Pending Interrupt
emilmont	27:7110ebee3484	1293
emilmont	33:5364839841bd	1294	The function clears the pending bit of an external interrupt.
emilmont	27:7110ebee3484	1295
emilmont	33:5364839841bd	1296	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	27:7110ebee3484	1297	*/
emilmont	39:737756e0b479	1298	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1299	{
emilmont	27:7110ebee3484	1300	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont	27:7110ebee3484	1301	}
emilmont	27:7110ebee3484	1302
emilmont	27:7110ebee3484	1303
emilmont	27:7110ebee3484	1304	/** \brief Get Active Interrupt
emilmont	27:7110ebee3484	1305
emilmont	33:5364839841bd	1306	The function reads the active register in NVIC and returns the active bit.
emilmont	39:737756e0b479	1307
emilmont	33:5364839841bd	1308	\param [in] IRQn Interrupt number.
emilmont	39:737756e0b479	1309
emilmont	33:5364839841bd	1310	\return 0 Interrupt status is not active.
emilmont	33:5364839841bd	1311	\return 1 Interrupt status is active.
emilmont	27:7110ebee3484	1312	*/
emilmont	39:737756e0b479	1313	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1314	{
emilmont	27:7110ebee3484	1315	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
emilmont	27:7110ebee3484	1316	}
emilmont	27:7110ebee3484	1317
emilmont	27:7110ebee3484	1318
emilmont	27:7110ebee3484	1319	/** \brief Set Interrupt Priority
emilmont	27:7110ebee3484	1320
emilmont	39:737756e0b479	1321	The function sets the priority of an interrupt.
emilmont	27:7110ebee3484	1322
emilmont	33:5364839841bd	1323	\note The priority cannot be set for every core interrupt.
emilmont	27:7110ebee3484	1324
emilmont	39:737756e0b479	1325	\param [in] IRQn Interrupt number.
emilmont	33:5364839841bd	1326	\param [in] priority Priority to set.
emilmont	27:7110ebee3484	1327	*/
emilmont	39:737756e0b479	1328	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont	27:7110ebee3484	1329	{
emilmont	27:7110ebee3484	1330	if(IRQn < 0) {
emilmont	27:7110ebee3484	1331	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
emilmont	27:7110ebee3484	1332	else {
emilmont	27:7110ebee3484	1333	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
emilmont	27:7110ebee3484	1334	}
emilmont	27:7110ebee3484	1335
emilmont	27:7110ebee3484	1336
emilmont	27:7110ebee3484	1337	/** \brief Get Interrupt Priority
emilmont	27:7110ebee3484	1338
emilmont	33:5364839841bd	1339	The function reads the priority of an interrupt. The interrupt
emilmont	33:5364839841bd	1340	number can be positive to specify an external (device specific)
emilmont	27:7110ebee3484	1341	interrupt, or negative to specify an internal (core) interrupt.
emilmont	27:7110ebee3484	1342
emilmont	27:7110ebee3484	1343
emilmont	33:5364839841bd	1344	\param [in] IRQn Interrupt number.
emilmont	33:5364839841bd	1345	\return Interrupt Priority. Value is aligned automatically to the implemented
emilmont	33:5364839841bd	1346	priority bits of the microcontroller.
emilmont	27:7110ebee3484	1347	*/
emilmont	39:737756e0b479	1348	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1349	{
emilmont	27:7110ebee3484	1350
emilmont	27:7110ebee3484	1351	if(IRQn < 0) {
emilmont	27:7110ebee3484	1352	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
emilmont	27:7110ebee3484	1353	else {
emilmont	27:7110ebee3484	1354	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont	27:7110ebee3484	1355	}
emilmont	27:7110ebee3484	1356
emilmont	27:7110ebee3484	1357
emilmont	27:7110ebee3484	1358	/** \brief Encode Priority
emilmont	27:7110ebee3484	1359
emilmont	33:5364839841bd	1360	The function encodes the priority for an interrupt with the given priority group,
emilmont	33:5364839841bd	1361	preemptive priority value, and subpriority value.
emilmont	27:7110ebee3484	1362	In case of a conflict between priority grouping and available
emilmont	33:5364839841bd	1363	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
emilmont	27:7110ebee3484	1364
emilmont	33:5364839841bd	1365	\param [in] PriorityGroup Used priority group.
emilmont	33:5364839841bd	1366	\param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont	33:5364839841bd	1367	\param [in] SubPriority Subpriority value (starting from 0).
emilmont	33:5364839841bd	1368	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont	27:7110ebee3484	1369	*/
emilmont	39:737756e0b479	1370	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont	27:7110ebee3484	1371	{
emilmont	27:7110ebee3484	1372	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	27:7110ebee3484	1373	uint32_t PreemptPriorityBits;
emilmont	27:7110ebee3484	1374	uint32_t SubPriorityBits;
emilmont	27:7110ebee3484	1375
emilmont	27:7110ebee3484	1376	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont	27:7110ebee3484	1377	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont	33:5364839841bd	1378
emilmont	27:7110ebee3484	1379	return (
emilmont	27:7110ebee3484	1380	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
emilmont	27:7110ebee3484	1381	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
emilmont	27:7110ebee3484	1382	);
emilmont	27:7110ebee3484	1383	}
emilmont	27:7110ebee3484	1384
emilmont	27:7110ebee3484	1385
emilmont	27:7110ebee3484	1386	/** \brief Decode Priority
emilmont	27:7110ebee3484	1387
emilmont	33:5364839841bd	1388	The function decodes an interrupt priority value with a given priority group to
emilmont	33:5364839841bd	1389	preemptive priority value and subpriority value.
emilmont	27:7110ebee3484	1390	In case of a conflict between priority grouping and available
emilmont	27:7110ebee3484	1391	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
emilmont	33:5364839841bd	1392
emilmont	33:5364839841bd	1393	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont	33:5364839841bd	1394	\param [in] PriorityGroup Used priority group.
emilmont	33:5364839841bd	1395	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont	33:5364839841bd	1396	\param [out] pSubPriority Subpriority value (starting from 0).
emilmont	27:7110ebee3484	1397	*/
emilmont	39:737756e0b479	1398	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont	27:7110ebee3484	1399	{
emilmont	27:7110ebee3484	1400	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	27:7110ebee3484	1401	uint32_t PreemptPriorityBits;
emilmont	27:7110ebee3484	1402	uint32_t SubPriorityBits;
emilmont	27:7110ebee3484	1403
emilmont	27:7110ebee3484	1404	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont	27:7110ebee3484	1405	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont	33:5364839841bd	1406
emilmont	27:7110ebee3484	1407	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
emilmont	27:7110ebee3484	1408	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
emilmont	27:7110ebee3484	1409	}
emilmont	27:7110ebee3484	1410
emilmont	27:7110ebee3484	1411
emilmont	27:7110ebee3484	1412	/** \brief System Reset
emilmont	27:7110ebee3484	1413
emilmont	33:5364839841bd	1414	The function initiates a system reset request to reset the MCU.
emilmont	27:7110ebee3484	1415	*/
emilmont	39:737756e0b479	1416	__STATIC_INLINE void NVIC_SystemReset(void)
emilmont	27:7110ebee3484	1417	{
emilmont	27:7110ebee3484	1418	__DSB(); /* Ensure all outstanding memory accesses included
emilmont	33:5364839841bd	1419	buffered write are completed before reset */
emilmont	33:5364839841bd	1420	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
emilmont	33:5364839841bd	1421	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
emilmont	27:7110ebee3484	1422	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
emilmont	33:5364839841bd	1423	__DSB(); /* Ensure completion of memory access */
emilmont	27:7110ebee3484	1424	while(1); /* wait until reset */
emilmont	27:7110ebee3484	1425	}
emilmont	27:7110ebee3484	1426
emilmont	27:7110ebee3484	1427	/@} end of CMSIS_Core_NVICFunctions /
emilmont	27:7110ebee3484	1428
emilmont	27:7110ebee3484	1429
emilmont	27:7110ebee3484	1430
emilmont	27:7110ebee3484	1431	/* ################################## SysTick function ############################################ */
emilmont	33:5364839841bd	1432	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	33:5364839841bd	1433	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont	33:5364839841bd	1434	\brief Functions that configure the System.
emilmont	27:7110ebee3484	1435	@{
emilmont	27:7110ebee3484	1436	*/
emilmont	27:7110ebee3484	1437
emilmont	27:7110ebee3484	1438	#if (__Vendor_SysTickConfig == 0)
emilmont	27:7110ebee3484	1439
emilmont	27:7110ebee3484	1440	/** \brief System Tick Configuration
emilmont	27:7110ebee3484	1441
emilmont	33:5364839841bd	1442	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont	39:737756e0b479	1443	Counter is in free running mode to generate periodic interrupts.
emilmont	27:7110ebee3484	1444
emilmont	33:5364839841bd	1445	\param [in] ticks Number of ticks between two interrupts.
emilmont	39:737756e0b479	1446
emilmont	33:5364839841bd	1447	\return 0 Function succeeded.
emilmont	33:5364839841bd	1448	\return 1 Function failed.
emilmont	39:737756e0b479	1449
emilmont	39:737756e0b479	1450	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont	39:737756e0b479	1451	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont	33:5364839841bd	1452	must contain a vendor-specific implementation of this function.
emilmont	33:5364839841bd	1453
emilmont	27:7110ebee3484	1454	*/
emilmont	39:737756e0b479	1455	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont	33:5364839841bd	1456	{
emilmont	27:7110ebee3484	1457	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont	33:5364839841bd	1458
emilmont	27:7110ebee3484	1459	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
emilmont	33:5364839841bd	1460	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont	27:7110ebee3484	1461	SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont	33:5364839841bd	1462	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
emilmont	33:5364839841bd	1463	SysTick_CTRL_TICKINT_Msk \|
emilmont	27:7110ebee3484	1464	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont	27:7110ebee3484	1465	return (0); /* Function successful */
emilmont	27:7110ebee3484	1466	}
emilmont	27:7110ebee3484	1467
emilmont	27:7110ebee3484	1468	#endif
emilmont	27:7110ebee3484	1469
emilmont	27:7110ebee3484	1470	/@} end of CMSIS_Core_SysTickFunctions /
emilmont	27:7110ebee3484	1471
emilmont	27:7110ebee3484	1472
emilmont	27:7110ebee3484	1473
emilmont	27:7110ebee3484	1474	/* ##################################### Debug In/Output function ########################################### */
emilmont	33:5364839841bd	1475	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	33:5364839841bd	1476	\defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont	33:5364839841bd	1477	\brief Functions that access the ITM debug interface.
emilmont	27:7110ebee3484	1478	@{
emilmont	27:7110ebee3484	1479	*/
emilmont	27:7110ebee3484	1480
emilmont	33:5364839841bd	1481	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
emilmont	33:5364839841bd	1482	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
emilmont	27:7110ebee3484	1483
emilmont	27:7110ebee3484	1484
emilmont	27:7110ebee3484	1485	/** \brief ITM Send Character
emilmont	27:7110ebee3484	1486
emilmont	33:5364839841bd	1487	The function transmits a character via the ITM channel 0, and
emilmont	33:5364839841bd	1488	\li Just returns when no debugger is connected that has booked the output.
emilmont	33:5364839841bd	1489	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont	27:7110ebee3484	1490
emilmont	33:5364839841bd	1491	\param [in] ch Character to transmit.
emilmont	39:737756e0b479	1492
emilmont	33:5364839841bd	1493	\returns Character to transmit.
emilmont	27:7110ebee3484	1494	*/
emilmont	39:737756e0b479	1495	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont	27:7110ebee3484	1496	{
emilmont	33:5364839841bd	1497	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
emilmont	27:7110ebee3484	1498	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
emilmont	27:7110ebee3484	1499	{
emilmont	27:7110ebee3484	1500	while (ITM->PORT[0].u32 == 0);
emilmont	27:7110ebee3484	1501	ITM->PORT[0].u8 = (uint8_t) ch;
emilmont	33:5364839841bd	1502	}
emilmont	27:7110ebee3484	1503	return (ch);
emilmont	27:7110ebee3484	1504	}
emilmont	27:7110ebee3484	1505
emilmont	27:7110ebee3484	1506
emilmont	27:7110ebee3484	1507	/** \brief ITM Receive Character
emilmont	27:7110ebee3484	1508
emilmont	33:5364839841bd	1509	The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont	27:7110ebee3484	1510
emilmont	33:5364839841bd	1511	\return Received character.
emilmont	33:5364839841bd	1512	\return -1 No character pending.
emilmont	27:7110ebee3484	1513	*/
emilmont	39:737756e0b479	1514	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
emilmont	27:7110ebee3484	1515	int32_t ch = -1; /* no character available */
emilmont	27:7110ebee3484	1516
emilmont	27:7110ebee3484	1517	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont	27:7110ebee3484	1518	ch = ITM_RxBuffer;
emilmont	27:7110ebee3484	1519	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont	27:7110ebee3484	1520	}
emilmont	33:5364839841bd	1521
emilmont	33:5364839841bd	1522	return (ch);
emilmont	27:7110ebee3484	1523	}
emilmont	27:7110ebee3484	1524
emilmont	27:7110ebee3484	1525
emilmont	27:7110ebee3484	1526	/** \brief ITM Check Character
emilmont	27:7110ebee3484	1527
emilmont	33:5364839841bd	1528	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont	27:7110ebee3484	1529
emilmont	33:5364839841bd	1530	\return 0 No character available.
emilmont	33:5364839841bd	1531	\return 1 Character available.
emilmont	27:7110ebee3484	1532	*/
emilmont	39:737756e0b479	1533	__STATIC_INLINE int32_t ITM_CheckChar (void) {
emilmont	27:7110ebee3484	1534
emilmont	27:7110ebee3484	1535	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont	27:7110ebee3484	1536	return (0); /* no character available */
emilmont	27:7110ebee3484	1537	} else {
emilmont	27:7110ebee3484	1538	return (1); /* character available */
emilmont	27:7110ebee3484	1539	}
emilmont	27:7110ebee3484	1540	}
emilmont	27:7110ebee3484	1541
emilmont	27:7110ebee3484	1542	/@} end of CMSIS_core_DebugFunctions /
emilmont	27:7110ebee3484	1543
emilmont	27:7110ebee3484	1544	#endif /* __CORE_CM3_H_DEPENDANT */
emilmont	27:7110ebee3484	1545
emilmont	27:7110ebee3484	1546	#endif /* __CMSIS_GENERIC */
emilmont	27:7110ebee3484	1547
emilmont	27:7110ebee3484	1548	#ifdef __cplusplus
emilmont	27:7110ebee3484	1549	}
emilmont	27:7110ebee3484	1550	#endif

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