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TARGET_KL46Z/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@82:6473597d706e, 2014-04-07 (annotated)
- Committer:
- bogdanm
- Date:
- Mon Apr 07 18:28:36 2014 +0100
- Revision:
- 82:6473597d706e
- Parent:
- TARGET_KL25Z/clk_freqs.h@77:869cf507173a
- Child:
- 90:cb3d968589d8
Release 82 of the mbed library
Main changes:
- support for K64F
- Revisited Nordic code structure
- Test infrastructure improvements
- various bug fixes
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 76:824293ae5e43 | 1 | /* mbed Microcontroller Library |
bogdanm | 76:824293ae5e43 | 2 | * Copyright (c) 2006-2013 ARM Limited |
bogdanm | 76:824293ae5e43 | 3 | * |
bogdanm | 76:824293ae5e43 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
bogdanm | 76:824293ae5e43 | 5 | * you may not use this file except in compliance with the License. |
bogdanm | 76:824293ae5e43 | 6 | * You may obtain a copy of the License at |
bogdanm | 76:824293ae5e43 | 7 | * |
bogdanm | 76:824293ae5e43 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
bogdanm | 76:824293ae5e43 | 9 | * |
bogdanm | 76:824293ae5e43 | 10 | * Unless required by applicable law or agreed to in writing, software |
bogdanm | 76:824293ae5e43 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
bogdanm | 76:824293ae5e43 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
bogdanm | 76:824293ae5e43 | 13 | * See the License for the specific language governing permissions and |
bogdanm | 76:824293ae5e43 | 14 | * limitations under the License. |
bogdanm | 76:824293ae5e43 | 15 | */ |
bogdanm | 76:824293ae5e43 | 16 | #ifndef MBED_CLK_FREQS_H |
bogdanm | 76:824293ae5e43 | 17 | #define MBED_CLK_FREQS_H |
bogdanm | 76:824293ae5e43 | 18 | |
bogdanm | 76:824293ae5e43 | 19 | #ifdef __cplusplus |
bogdanm | 76:824293ae5e43 | 20 | extern "C" { |
bogdanm | 76:824293ae5e43 | 21 | #endif |
bogdanm | 76:824293ae5e43 | 22 | |
emilmont | 77:869cf507173a | 23 | #include "PeripheralPins.h" |
emilmont | 77:869cf507173a | 24 | |
bogdanm | 76:824293ae5e43 | 25 | //Get the peripheral bus clock frequency |
bogdanm | 76:824293ae5e43 | 26 | static inline uint32_t bus_frequency(void) { |
bogdanm | 76:824293ae5e43 | 27 | return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1); |
bogdanm | 76:824293ae5e43 | 28 | } |
bogdanm | 76:824293ae5e43 | 29 | |
bogdanm | 76:824293ae5e43 | 30 | //Get external oscillator (crystal) frequency |
bogdanm | 76:824293ae5e43 | 31 | static uint32_t extosc_frequency(void) { |
bogdanm | 76:824293ae5e43 | 32 | uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)); |
bogdanm | 76:824293ae5e43 | 33 | |
bogdanm | 76:824293ae5e43 | 34 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock |
bogdanm | 76:824293ae5e43 | 35 | return MCGClock; |
bogdanm | 76:824293ae5e43 | 36 | |
emilmont | 77:869cf507173a | 37 | uint32_t divider, multiplier; |
emilmont | 77:869cf507173a | 38 | #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available |
bogdanm | 76:824293ae5e43 | 39 | if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected |
bogdanm | 76:824293ae5e43 | 40 | if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected |
emilmont | 77:869cf507173a | 41 | #endif |
bogdanm | 76:824293ae5e43 | 42 | if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference |
bogdanm | 76:824293ae5e43 | 43 | divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); |
bogdanm | 76:824293ae5e43 | 44 | if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) |
bogdanm | 76:824293ae5e43 | 45 | divider <<= 5u; |
bogdanm | 76:824293ae5e43 | 46 | /* Select correct multiplier to calculate the MCG output clock */ |
bogdanm | 76:824293ae5e43 | 47 | switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { |
bogdanm | 76:824293ae5e43 | 48 | case 0x0u: |
bogdanm | 76:824293ae5e43 | 49 | multiplier = 640u; |
bogdanm | 76:824293ae5e43 | 50 | break; |
bogdanm | 76:824293ae5e43 | 51 | case 0x20u: |
bogdanm | 76:824293ae5e43 | 52 | multiplier = 1280u; |
bogdanm | 76:824293ae5e43 | 53 | break; |
bogdanm | 76:824293ae5e43 | 54 | case 0x40u: |
bogdanm | 76:824293ae5e43 | 55 | multiplier = 1920u; |
bogdanm | 76:824293ae5e43 | 56 | break; |
bogdanm | 76:824293ae5e43 | 57 | case 0x60u: |
bogdanm | 76:824293ae5e43 | 58 | multiplier = 2560u; |
bogdanm | 76:824293ae5e43 | 59 | break; |
bogdanm | 76:824293ae5e43 | 60 | case 0x80u: |
bogdanm | 76:824293ae5e43 | 61 | multiplier = 732u; |
bogdanm | 76:824293ae5e43 | 62 | break; |
bogdanm | 76:824293ae5e43 | 63 | case 0xA0u: |
bogdanm | 76:824293ae5e43 | 64 | multiplier = 1464u; |
bogdanm | 76:824293ae5e43 | 65 | break; |
bogdanm | 76:824293ae5e43 | 66 | case 0xC0u: |
bogdanm | 76:824293ae5e43 | 67 | multiplier = 2197u; |
bogdanm | 76:824293ae5e43 | 68 | break; |
bogdanm | 76:824293ae5e43 | 69 | case 0xE0u: |
bogdanm | 76:824293ae5e43 | 70 | default: |
bogdanm | 76:824293ae5e43 | 71 | multiplier = 2929u; |
bogdanm | 76:824293ae5e43 | 72 | break; |
bogdanm | 76:824293ae5e43 | 73 | } |
bogdanm | 76:824293ae5e43 | 74 | |
bogdanm | 76:824293ae5e43 | 75 | return MCGClock * divider / multiplier; |
bogdanm | 76:824293ae5e43 | 76 | } |
emilmont | 77:869cf507173a | 77 | #ifdef MCG_C5_PLLCLKEN0_MASK |
bogdanm | 76:824293ae5e43 | 78 | } else { //PLL is selected |
bogdanm | 76:824293ae5e43 | 79 | divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK)); |
emilmont | 77:869cf507173a | 80 | multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u); |
emilmont | 77:869cf507173a | 81 | return MCGClock * divider / multiplier; |
bogdanm | 76:824293ae5e43 | 82 | } |
bogdanm | 76:824293ae5e43 | 83 | } |
emilmont | 77:869cf507173a | 84 | #endif |
bogdanm | 76:824293ae5e43 | 85 | |
bogdanm | 76:824293ae5e43 | 86 | //In all other cases either there is no crystal or we cannot determine it |
bogdanm | 76:824293ae5e43 | 87 | //For example when the FLL is running on the internal reference, and there is also an |
bogdanm | 76:824293ae5e43 | 88 | //external crystal. However these are unlikely situations |
bogdanm | 76:824293ae5e43 | 89 | return 0; |
bogdanm | 76:824293ae5e43 | 90 | } |
bogdanm | 76:824293ae5e43 | 91 | |
emilmont | 77:869cf507173a | 92 | //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit |
emilmont | 77:869cf507173a | 93 | static uint32_t mcgpllfll_frequency(void) { |
emilmont | 77:869cf507173a | 94 | if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected |
emilmont | 77:869cf507173a | 95 | return 0; |
emilmont | 77:869cf507173a | 96 | |
emilmont | 77:869cf507173a | 97 | uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)); |
emilmont | 77:869cf507173a | 98 | #ifdef MCG_C5_PLLCLKEN0_MASK |
emilmont | 77:869cf507173a | 99 | if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected |
emilmont | 77:869cf507173a | 100 | SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output |
emilmont | 77:869cf507173a | 101 | #endif |
emilmont | 77:869cf507173a | 102 | return MCGClock; |
emilmont | 77:869cf507173a | 103 | #ifdef MCG_C5_PLLCLKEN0_MASK |
emilmont | 77:869cf507173a | 104 | } else { //PLL is selected |
emilmont | 77:869cf507173a | 105 | SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output |
emilmont | 77:869cf507173a | 106 | return (MCGClock >> 1); |
emilmont | 77:869cf507173a | 107 | } |
emilmont | 77:869cf507173a | 108 | #endif |
emilmont | 77:869cf507173a | 109 | |
emilmont | 77:869cf507173a | 110 | //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active |
emilmont | 77:869cf507173a | 111 | //for the peripherals, this is however an unlikely setup |
emilmont | 77:869cf507173a | 112 | } |
bogdanm | 76:824293ae5e43 | 113 | |
bogdanm | 76:824293ae5e43 | 114 | #ifdef __cplusplus |
bogdanm | 76:824293ae5e43 | 115 | } |
bogdanm | 76:824293ae5e43 | 116 | #endif |
bogdanm | 76:824293ae5e43 | 117 | |
bogdanm | 76:824293ae5e43 | 118 | #endif |