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Diff: TARGET_NUCLEO_F746ZG/stm32f7xx_hal_tim.h
- Revision:
- 122:f9eeca106725
- Parent:
- 116:c0f6e94411f5
--- a/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_tim.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_NUCLEO_F746ZG/stm32f7xx_hal_tim.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_tim.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 09-December-2015
+ * @version V1.1.0
+ * @date 22-April-2016
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -77,7 +77,7 @@
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_ClockDivision */
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR down-counter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
@@ -264,11 +264,11 @@
*/
typedef enum
{
- HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_TIM_StateTypeDef;
/**
@@ -276,11 +276,11 @@
*/
typedef enum
{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
}HAL_TIM_ActiveChannel;
/**
@@ -308,7 +308,7 @@
/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
* @{
*/
-#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
@@ -319,7 +319,7 @@
* @{
*/
#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */
/**
* @}
*/
@@ -327,7 +327,7 @@
/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
-#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */
#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
@@ -338,7 +338,7 @@
/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
-#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
@@ -350,7 +350,7 @@
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
-#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
/**
@@ -360,7 +360,7 @@
/** @defgroup TIM_Output_Compare_State TIM Output Compare State
* @{
*/
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
/**
@@ -370,7 +370,7 @@
/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
-#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
/**
* @}
@@ -379,7 +379,7 @@
/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
* @{
*/
-#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U)
#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
/**
* @}
@@ -388,7 +388,7 @@
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
/**
* @}
@@ -397,7 +397,7 @@
/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
*/
-#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)
#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
/**
* @}
@@ -407,7 +407,7 @@
* @{
*/
#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
+#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)
/**
* @}
*/
@@ -416,7 +416,7 @@
* @{
*/
#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
+#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)
/**
* @}
*/
@@ -447,7 +447,7 @@
/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
-#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
@@ -459,7 +459,7 @@
* @{
*/
#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
+#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
/**
* @}
*/
@@ -494,7 +494,7 @@
* @{
*/
#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)
/**
* @}
*/
@@ -554,7 +554,7 @@
*/
#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
-#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
+#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
@@ -613,7 +613,7 @@
* @{
*/
#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+#define TIM_OSSR_DISABLE ((uint32_t)0x0000U)
/**
* @}
*/
@@ -622,7 +622,7 @@
* @{
*/
#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+#define TIM_OSSI_DISABLE ((uint32_t)0x0000U)
/**
* @}
*/
@@ -630,7 +630,7 @@
/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
-#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)
#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
@@ -641,7 +641,7 @@
* @{
*/
#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+#define TIM_BREAK_DISABLE ((uint32_t)0x0000U)
/**
* @}
*/
@@ -649,7 +649,7 @@
/** @defgroup TIM_Break_Polarity TIM Break Polarity
* @{
*/
-#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)
#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
/**
* @}
@@ -659,7 +659,7 @@
* @{
*/
#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)
/**
* @}
*/
@@ -667,7 +667,7 @@
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
-#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_RESET ((uint32_t)0x0000U)
#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
@@ -683,7 +683,7 @@
* @{
*/
#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
/**
* @}
*/
@@ -691,15 +691,15 @@
/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
-#define TIM_TS_ITR0 ((uint32_t)0x0000)
-#define TIM_TS_ITR1 ((uint32_t)0x0010)
-#define TIM_TS_ITR2 ((uint32_t)0x0020)
-#define TIM_TS_ITR3 ((uint32_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
-#define TIM_TS_ETRF ((uint32_t)0x0070)
-#define TIM_TS_NONE ((uint32_t)0xFFFF)
+#define TIM_TS_ITR0 ((uint32_t)0x0000U)
+#define TIM_TS_ITR1 ((uint32_t)0x0010U)
+#define TIM_TS_ITR2 ((uint32_t)0x0020U)
+#define TIM_TS_ITR3 ((uint32_t)0x0030U)
+#define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
+#define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
+#define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
+#define TIM_TS_ETRF ((uint32_t)0x0070U)
+#define TIM_TS_NONE ((uint32_t)0xFFFFU)
/**
* @}
*/
@@ -731,7 +731,7 @@
/** @defgroup TIM_TI1_Selection TIM TI1 Selection
* @{
*/
-#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
/**
* @}
@@ -740,26 +740,26 @@
/** @defgroup TIM_DMA_Base_address TIM DMA Base address
* @{
*/
-#define TIM_DMABASE_CR1 (0x00000000)
-#define TIM_DMABASE_CR2 (0x00000001)
-#define TIM_DMABASE_SMCR (0x00000002)
-#define TIM_DMABASE_DIER (0x00000003)
-#define TIM_DMABASE_SR (0x00000004)
-#define TIM_DMABASE_EGR (0x00000005)
-#define TIM_DMABASE_CCMR1 (0x00000006)
-#define TIM_DMABASE_CCMR2 (0x00000007)
-#define TIM_DMABASE_CCER (0x00000008)
-#define TIM_DMABASE_CNT (0x00000009)
-#define TIM_DMABASE_PSC (0x0000000A)
-#define TIM_DMABASE_ARR (0x0000000B)
-#define TIM_DMABASE_RCR (0x0000000C)
-#define TIM_DMABASE_CCR1 (0x0000000D)
-#define TIM_DMABASE_CCR2 (0x0000000E)
-#define TIM_DMABASE_CCR3 (0x0000000F)
-#define TIM_DMABASE_CCR4 (0x00000010)
-#define TIM_DMABASE_BDTR (0x00000011)
-#define TIM_DMABASE_DCR (0x00000012)
-#define TIM_DMABASE_OR (0x00000013)
+#define TIM_DMABASE_CR1 (0x00000000U)
+#define TIM_DMABASE_CR2 (0x00000001U)
+#define TIM_DMABASE_SMCR (0x00000002U)
+#define TIM_DMABASE_DIER (0x00000003U)
+#define TIM_DMABASE_SR (0x00000004U)
+#define TIM_DMABASE_EGR (0x00000005U)
+#define TIM_DMABASE_CCMR1 (0x00000006U)
+#define TIM_DMABASE_CCMR2 (0x00000007U)
+#define TIM_DMABASE_CCER (0x00000008U)
+#define TIM_DMABASE_CNT (0x00000009U)
+#define TIM_DMABASE_PSC (0x0000000AU)
+#define TIM_DMABASE_ARR (0x0000000BU)
+#define TIM_DMABASE_RCR (0x0000000CU)
+#define TIM_DMABASE_CCR1 (0x0000000DU)
+#define TIM_DMABASE_CCR2 (0x0000000EU)
+#define TIM_DMABASE_CCR3 (0x0000000FU)
+#define TIM_DMABASE_CCR4 (0x00000010U)
+#define TIM_DMABASE_BDTR (0x00000011U)
+#define TIM_DMABASE_DCR (0x00000012U)
+#define TIM_DMABASE_OR (0x00000013U)
/**
* @}
*/
@@ -767,24 +767,24 @@
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
-#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
-#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
-#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
-#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
-#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
-#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
-#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
-#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
-#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
-#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
-#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
-#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
-#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
-#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
-#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
-#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
-#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
+#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
+#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
+#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
+#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
+#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
+#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
+#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
+#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
+#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
+#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
+#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
+#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
+#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
+#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
+#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
+#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
+#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
+#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
/**
* @}
*/
@@ -792,13 +792,13 @@
/** @defgroup DMA_Handle_index DMA Handle index
* @{
*/
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/
@@ -806,10 +806,10 @@
/** @defgroup Channel_CC_State Channel CC State
* @{
*/
-#define TIM_CCx_ENABLE ((uint32_t)0x0001)
-#define TIM_CCx_DISABLE ((uint32_t)0x0000)
-#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
-#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
+#define TIM_CCx_ENABLE ((uint32_t)0x0001U)
+#define TIM_CCx_DISABLE ((uint32_t)0x0000U)
+#define TIM_CCxN_ENABLE ((uint32_t)0x0004U)
+#define TIM_CCxN_DISABLE ((uint32_t)0x0000U)
/**
* @}
*/
@@ -1326,7 +1326,7 @@
((__MODE__) == TIM_ENCODERMODE_TI2) || \
((__MODE__) == TIM_ENCODERMODE_TI12))
-#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00) == 0x00000000) && ((__IT__) != 0x00000000))
+#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U))
#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \
@@ -1338,9 +1338,9 @@
((__IT__) == TIM_IT_TRIGGER) || \
((__IT__) == TIM_IT_BREAK))
-#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
-#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00) == 0x00000000) && ((__SOURCE__) != 0x00000000))
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
((__FLAG__) == TIM_FLAG_CC1) || \