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Diff: TARGET_EFM32LG_STK3600/efm32lg_prs.h
- Revision:
- 113:f141b2784e32
- Parent:
- 98:8ab26030e058
--- a/TARGET_EFM32LG_STK3600/efm32lg_prs.h Wed Jan 13 09:48:29 2016 +0000
+++ b/TARGET_EFM32LG_STK3600/efm32lg_prs.h Tue Feb 02 14:43:35 2016 +0000
@@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32lg_prs.h
* @brief EFM32LG_PRS register and bit field definitions
- * @version 3.20.6
+ * @version 4.2.0
******************************************************************************
* @section License
- * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
*
*****************************************************************************/
/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
* @defgroup EFM32LG_PRS
* @{
* @brief EFM32LG_PRS Register Declaration
@@ -41,7 +45,6 @@
__IO uint32_t ROUTE; /**< I/O Routing Register */
uint32_t RESERVED0[1]; /**< Reserved registers */
-
PRS_CH_TypeDef CH[12]; /**< Channel registers */
} PRS_TypeDef; /** @} */
@@ -448,5 +451,5 @@
#define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
/** @} End of group EFM32LG_PRS */
+/** @} End of group Parts */
-