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Diff: TARGET_EFM32HG_STK3400/efm32hg_cmu.h
- Revision:
- 113:f141b2784e32
- Parent:
- 98:8ab26030e058
--- a/TARGET_EFM32HG_STK3400/efm32hg_cmu.h Wed Jan 13 09:48:29 2016 +0000
+++ b/TARGET_EFM32HG_STK3400/efm32hg_cmu.h Tue Feb 02 14:43:35 2016 +0000
@@ -1,10 +1,10 @@
/**************************************************************************//**
* @file efm32hg_cmu.h
* @brief EFM32HG_CMU register and bit field definitions
- * @version 3.20.12
+ * @version 4.2.0
******************************************************************************
* @section License
- * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
+ * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@@ -30,6 +30,10 @@
*
*****************************************************************************/
/**************************************************************************//**
+* @addtogroup Parts
+* @{
+******************************************************************************/
+/**************************************************************************//**
* @defgroup EFM32HG_CMU
* @{
* @brief EFM32HG_CMU Register Declaration
@@ -84,7 +88,7 @@
*****************************************************************************/
/* Bit fields for CMU CTRL */
-#define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */
+#define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
#define _CMU_CTRL_MASK 0x07FFFEEFUL /**< Mask for CMU_CTRL */
#define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
#define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
@@ -1198,5 +1202,5 @@
#define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */
/** @} End of group EFM32HG_CMU */
+/** @} End of group Parts */
-