Diff: TARGET_K64F/system_MK64F12.h

Revision:

120:7c328cabac7e

Parent:

90:cb3d968589d8

--- a/TARGET_K64F/system_MK64F12.h	Wed Apr 27 12:10:56 2016 -0500
+++ b/TARGET_K64F/system_MK64F12.h	Tue May 10 12:23:43 2016 -0500
@@ -1,22 +1,29 @@
 /*
 ** ###################################################################
-**     Processor:           MK64FN1M0VMD12
+**     Processors:          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**                          MK64FX512VDC12
+**                          MK64FX512VLL12
+**                          MK64FX512VLQ12
+**                          MK64FX512VMD12
+**
 **     Compilers:           Keil ARM C/C++ Compiler
 **                          Freescale C/C++ for Embedded ARM
 **                          GNU C Compiler
-**                          GNU C Compiler - CodeSourcery Sourcery G++
 **                          IAR ANSI C/C++ Compiler for ARM
 **
 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
-**     Version:             rev. 2.5, 2014-02-10
-**     Build:               b140611
+**     Version:             rev. 2.8, 2015-02-19
+**     Build:               b151216
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
 **         contains the system frequency. It configures the device and initializes
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
-**     Copyright (c) 2014 Freescale Semiconductor, Inc.
+**     Copyright (c) 2015 Freescale Semiconductor, Inc.
 **     All rights reserved.
 **
 **     Redistribution and use in source and binary forms, with or without modification,
@@ -72,14 +79,21 @@
 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
 **         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
 **
 ** ###################################################################
 */
 
 /*!
  * @file MK64F12
- * @version 2.5
- * @date 2014-02-10
+ * @version 2.8
+ * @date 2015-02-19
  * @brief Device specific configuration file for MK64F12 (header file)
  *
  * Provides a system configuration function and a global variable that contains
@@ -87,8 +101,8 @@
  * (PLL) that is part of the microcontroller device.
  */
 
-#ifndef SYSTEM_MK64F12_H_
-#define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
+#ifndef _SYSTEM_MK64F12_H_
+#define _SYSTEM_MK64F12_H_                       /**< Symbol preventing repeated inclusion */
 
 #ifdef __cplusplus
 extern "C" {
@@ -97,53 +111,10 @@
 #include <stdint.h>
 
 
-#define DISABLE_WDOG                   1
-
-#ifndef CLOCK_SETUP
-  #define CLOCK_SETUP                  4
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
 #endif
 
-/* MCG mode constants */
-
-#define MCG_MODE_FEI                   0U
-#define MCG_MODE_FBI                   1U
-#define MCG_MODE_BLPI                  2U
-#define MCG_MODE_FEE                   3U
-#define MCG_MODE_FBE                   4U
-#define MCG_MODE_BLPE                  5U
-#define MCG_MODE_PBE                   6U
-#define MCG_MODE_PEE                   7U
-
-/* Predefined clock setups
-   0 ... Default  part configuration
-         Multipurpose Clock Generator (MCG) in FEI mode.
-         Reference clock source for MCG module: Slow internal reference clock
-         Core clock = 20.97152MHz
-         Bus clock  = 20.97152MHz
-   1 ... Maximum achievable clock frequency configuration
-         Multipurpose Clock Generator (MCG) in PEE mode.
-         Reference clock source for MCG module: System oscillator 0 reference clock
-         Core clock = 120MHz
-         Bus clock  = 60MHz
-   2 ... Chip internaly clocked, ready for Very Low Power Run mode.
-         Multipurpose Clock Generator (MCG) in BLPI mode.
-         Reference clock source for MCG module: Fast internal reference clock
-         Core clock = 4MHz
-         Bus clock  = 4MHz
-   3 ... Chip externally clocked, ready for Very Low Power Run mode.
-         Multipurpose Clock Generator (MCG) in BLPE mode.
-         Reference clock source for MCG module: RTC oscillator reference clock
-         Core clock = 0.032768MHz
-         Bus clock  = 0.032768MHz
-   4 ... USB clock setup
-         Multipurpose Clock Generator (MCG) in PEE mode.
-         Reference clock source for MCG module: System oscillator 0 reference clock
-         Core clock = 120MHz
-         Bus clock  = 60MHz
- */
-
-/* Define clock source values */
-
 #define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
 #define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
 #define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
@@ -158,150 +129,8 @@
 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
 #define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
 
-/* Internal reference clock trim */
-/* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
-/* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
-/* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
-/* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+#define DEFAULT_SYSTEM_CLOCK           20971520u           /* Default System clock value */
 
-#if (CLOCK_SETUP == 0)
-  #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
-  #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
-  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
-  #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
-  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
-  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
-  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
-  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
-  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
-  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
-  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
-  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
-/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
-/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
-  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
-  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
-  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
-/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
-  #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 1)
-  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
-  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
-  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
-  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
-  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
-  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
-  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
-  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
-  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
-  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
-  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
-  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
-/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
-/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
-  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
-  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
-  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
-/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
-  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 2)
-  #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
-  #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
-  /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
-  #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
-  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
-  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
-  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
-  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
-  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
-  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
-  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
-  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
-/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
-/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
-  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
-  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
-  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
-/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
-  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 3)
-  #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
-  #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
-  /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
-  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
-  #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
-  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
-  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
-  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
-  #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
-  #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
-  #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
-/* MCG_C7: OSCSEL=1 */
-  #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
-/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
-/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
-  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
-  #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
-  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
-/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
-  #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
-#elif (CLOCK_SETUP == 4)
-  #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
-  #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
-  /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
-  #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
-  /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
-  #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
-  /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
-  #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
-  /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
-  #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
-/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
-  #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
-/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
-  #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
-/* MCG_C7: OSCSEL=0 */
-  #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
-/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
-  #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
-/* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
-  #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
-/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
-  #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
-/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
-  #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
-/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
-  #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
-/* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
-  #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
-#endif
 
 /**
  * @brief System clock frequency (core clock)
@@ -336,4 +165,4 @@
 }
 #endif
 
-#endif  /* #if !defined(SYSTEM_MK64F12_H_) */
+#endif  /* _SYSTEM_MK64F12_H_ */