cc y
/
mbed
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
mbed
by 
mbed official
Diff: TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h
- Revision:
- 92:4fc01daae5a5
- Parent:
- 85:024bf7f99721
- Child:
- 93:e188a91d3eaa
--- a/TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h Wed Oct 29 11:02:04 2014 +0000
+++ b/TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h Thu Nov 27 13:33:22 2014 +0000
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.0.0
- * @date 28-May-2014
+ * @version V1.1.0
+ * @date 03-Oct-2014
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@@ -56,6 +56,10 @@
/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+ * @{
+ */
+
/**
* @brief RCC extended clocks structure definition
*/
@@ -146,7 +150,7 @@
}RCC_PeriphCLKInitTypeDef;
#endif /* STM32F071xB */
-#if defined(STM32F072xB)
+#if defined(STM32F072xB) || defined(STM32F078xx)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
@@ -171,9 +175,10 @@
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F072xB */
+#endif /* STM32F072xB || STM32F078xx */
-#if defined(STM32F078xx)
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
@@ -188,6 +193,9 @@
uint32_t Usart2ClockSelection; /*!< USART2 clock source
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
+ uint32_t Usart3ClockSelection; /*!< USART3 clock source
+ This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
+
uint32_t I2c1ClockSelection; /*!< I2C1 clock source
This parameter can be a value of @ref RCC_I2C1_Clock_Source */
@@ -195,11 +203,12 @@
This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F078xx */
+#endif /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief RCC CRS Status structures definition
*/
@@ -263,14 +272,20 @@
}RCC_CRSSynchroInfoTypeDef;
#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants
+
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
* @{
*/
-/** @defgroup RCCEx_Periph_Clock_Selection
+/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
* @{
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx)
@@ -280,7 +295,19 @@
#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_RTC))
-#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 */
+#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx */
+
+#if defined(STM32F042x6) || defined(STM32F048xx)
+#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
+#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
+#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
+
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+ RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
+ RCC_PERIPHCLK_USB))
+#endif /* STM32F042x6 || STM32F048xx */
#if defined(STM32F051x8) || defined(STM32F058xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
@@ -288,7 +315,7 @@
#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
+#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
#endif /* STM32F051x8 || STM32F058xx */
@@ -304,19 +331,7 @@
RCC_PERIPHCLK_RTC))
#endif /* STM32F071xB */
-#if defined(STM32F042x6) || defined(STM32F048xx)
-#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
-#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
-#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
-
-#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
- RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
- RCC_PERIPHCLK_USB))
-#endif /* STM32F042x6 || STM32F048xx */
-
-#if defined(STM32F072xB)
+#if defined(STM32F072xB) || defined(STM32F078xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
@@ -327,29 +342,31 @@
#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
-#endif /* STM32F072xB */
+#endif /* STM32F072xB || STM32F078xx */
-#if defined(STM32F078xx)
+#if defined(STM32F091xC) || defined(STM32F098xx)
#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
+#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
- RCC_PERIPHCLK_RTC))
-#endif /* STM32F078xx */
+ RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
+#endif /* STM32F091xC || STM32F098xx */
/**
* @}
*/
+/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
+ * @{
+ */
+
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
-/** @defgroup RCCEx_MCO_Clock_Source
- * @{
- */
#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
@@ -361,17 +378,11 @@
((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCOSOURCE_HSI14))
-/**
- * @}
- */
#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx */
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
-/** @defgroup RCCEx_MCO_Clock_Source
- * @{
- */
#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
((SOURCE) == RCC_MCOSOURCE_LSI) || \
((SOURCE) == RCC_MCOSOURCE_LSE) || \
@@ -380,17 +391,13 @@
((SOURCE) == RCC_MCOSOURCE_HSE) || \
((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCOSOURCE_HSI14))
-/**
- * @}
- */
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-/** @defgroup RCCEx_MCO_Clock_Source
- * @{
- */
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
@@ -404,29 +411,24 @@
((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
((SOURCE) == RCC_MCOSOURCE_HSI14) || \
((SOURCE) == RCC_MCOSOURCE_HSI48))
-/**
- * @}
- */
-/** @defgroup RCCEx_Interrupt
- * @{
- */
#define RCC_IT_HSI48 ((uint8_t)0x40)
-/**
- * @}
- */
/* Flags in the CR2 register */
#define RCC_CR2_HSI48RDY_BitNumber 16
#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
-#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/**
+ * @}
+ */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
-/** @defgroup RCCEx_USB_Clock_Source
+/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
* @{
*/
#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
@@ -438,11 +440,12 @@
* @}
*/
-#endif /* STM32F042x6 || STM32F072xB */
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
-/** @defgroup RCCEx_USART2_Clock_Source
+/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
* @{
*/
#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
@@ -458,13 +461,36 @@
* @}
*/
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
+ * @{
+ */
+#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
+#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
+#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
+#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
+
+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
+ ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
+/**
+ * @}
+ */
+
+#endif /* STM32F091xC || STM32F098xx */
+
#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
-/** @defgroup RCCEx_CEC_Clock_Source
+/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
* @{
*/
#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
@@ -476,13 +502,16 @@
* @}
*/
-#endif /* STM32F042x6 || */
+#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-/** @addtogroup RCC_PLL_Clock_Source
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
* @{
*/
#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
@@ -495,7 +524,7 @@
* @}
*/
-/** @addtogroup RCC_System_Clock_Source
+/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
* @{
*/
#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
@@ -504,13 +533,7 @@
((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
-/**
- * @}
- */
-/** @addtogroup RCC_System_Clock_Source_Status
- * @{
- */
#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
@@ -521,7 +544,7 @@
* @}
*/
-/** @defgroup RCCEx_HSI48_Config
+/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00)
@@ -533,35 +556,24 @@
*/
#else
-/** @addtogroup RCC_PLL_Clock_Source
+/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
* @{
*/
#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
- /**
- * @}
- */
-/** @addtogroup RCC_PLL_Clock_Source
- * @{
- */
#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
((SOURCE) == RCC_PLLSOURCE_HSE))
/**
* @}
*/
-/** @addtogroup RCC_System_Clock_Source
+
+/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
* @{
*/
#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
-/**
- * @}
- */
-/** @addtogroup RCC_System_Clock_Source_Status
- * @{
- */
#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
@@ -569,7 +581,7 @@
* @}
*/
-/** @defgroup RCCEx_HSI48_Config
+/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00)
@@ -579,31 +591,28 @@
* @}
*/
-#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
+ * @{
+ */
+
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
-/** @defgroup RCCEx_MCOx_Clock_Prescaler
- * @{
- */
#define RCC_MCO_NODIV ((uint32_t)0x00000000)
#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
-/**
- * @}
- */
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || \
- defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
-/** @defgroup RCCEx_MCOx_Clock_Prescaler
- * @{
- */
#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
@@ -617,16 +626,20 @@
((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
+
+#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
/**
* @}
*/
-#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-/** @defgroup RCCEx_CRS_SynchroSource
+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
* @{
*/
#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
@@ -634,13 +647,13 @@
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
- ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) ||\
- ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
+ ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
+ ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_SynchroDivider
+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
* @{
*/
#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
@@ -652,38 +665,38 @@
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) ||\
- ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
- ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
+#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
+ ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_SynchroPolarity
+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
* @{
*/
#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
- ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
+ ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_ReloadValueDefault
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
* @{
*/
#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
- to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
-
+ to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
+
#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_ErrorLimitDefault
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
* @{
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
@@ -693,31 +706,31 @@
* @}
*/
-/** @defgroup RCCEx_CRS_HSI48CalibrationDefault
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
* @{
*/
-#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
- The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
- corresponds to a higher output frequency */
+#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
+ The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
+ corresponds to a higher output frequency */
#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_FreqErrorDirection
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
* @{
*/
#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
- ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
+ ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
/**
* @}
*/
-/** @defgroup RCCEx_CRS_Interrupt_Sources
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
* @{
*/
#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
@@ -732,7 +745,7 @@
* @}
*/
-/** @defgroup RCCEx_CRS_Flags
+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
* @{
*/
#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
@@ -747,26 +760,30 @@
* @}
*/
-#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
-
/**
* @}
*/
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
* @{
*/
-/** @brief Enable or disable the AHB peripheral clock.
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
+ * @brief Enables or disables the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
+ * @{
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
@@ -774,37 +791,51 @@
#endif /* STM32F030x6 || STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx |[ */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
-#endif /* STM32F042x6 || */
+#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+#define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
+
+#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
+
+#endif /* STM32F091xC || STM32F098xx */
+
/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
#if defined(STM32F030x8) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
@@ -812,25 +843,31 @@
#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#endif /* STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F031x6 || STM32F038xx || */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
#if defined(STM32F030x8) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
@@ -840,31 +877,37 @@
#endif /* STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
-#endif /* STM32F042x6 || */
+#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
#define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
@@ -874,55 +917,95 @@
#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F072xB) || defined(STM32F078xx)
#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#endif /* STM32F042x6 || STM32F072xB */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F072xB || STM32F078xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
-#endif /* STM32F042x6 || STM32F072xB */
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
-#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
+
+#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
+
+#endif /* STM32F091xC || STM32F098xx */
/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
*/
-#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
-#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
+#define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
+#define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
+
+#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
+#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
+
+#endif /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
+ * @brief Forces or releases peripheral reset.
+ * @{
+ */
/** @brief Force or release AHB peripheral reset.
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
@@ -930,34 +1013,40 @@
#endif /* STM32F030x6 || STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
-#endif /* STM32F042x6 || */
+#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
/** @brief Force or release APB1 peripheral reset.
*/
#if defined(STM32F030x8) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
@@ -965,25 +1054,31 @@
#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#endif /* STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F031x6 || STM32F038xx || */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F051x8 || STM32F058xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
#if defined(STM32F030x8) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
@@ -993,31 +1088,37 @@
#endif /* STM32F030x8 || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
-#endif /* STM32F042x6 || */
+#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
#define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
@@ -1027,53 +1128,84 @@
#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F072xB) || defined(STM32F078xx)
#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#endif /* STM32F042x6 || STM32F072xB */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F072xB || STM32F078xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)
+#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
-#endif /* STM32F042x6 || STM32F072xB */
+#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
-#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
+
+#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
+
+#endif /* STM32F091xC || STM32F098xx */
/** @brief Force or release APB2 peripheral reset.
*/
-#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
#define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
-#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
+#endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+
+#define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
+#define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
-
-/** @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
+#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
+#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
+
+#endif /* STM32F091xC || STM32F098xx */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
+ * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
* @note HSI48 can not be stopped if it is used as system clock source. In this case,
* you have to select another source of the system clock then stop the HSI14.
@@ -1082,7 +1214,12 @@
* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
* clock cycles.
+ * @{
*/
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
@@ -1102,10 +1239,19 @@
*/
#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
-#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
+ * @{
+ */
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F072xB) || defined(STM32F078xx)
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSource__: specifies the USB clock source.
@@ -1123,11 +1269,13 @@
*/
#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
-#endif /* STM32F042x6 || STM32F072xB */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F072xB || STM32F078xx */
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
/** @brief Macro to configure the CEC clock.
* @param __CECCLKSource__: specifies the CEC clock source.
@@ -1145,13 +1293,15 @@
*/
#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
-#endif /* STM32F042x6 || */
+#endif /* STM32F042x6 || STM32F048xx || */
/* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || defined(STM32F098xx) */
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || \
- defined(STM32F072xB) || defined(STM32F078xx)
+ defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSource__: specifies the MCO clock source.
@@ -1199,11 +1349,43 @@
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
#endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || */
- /* STM32F042x6 || STM32F071xB || */
- /* STM32F072xB || STM32F078xx */
+ /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
+#if defined(STM32F091xC) || defined(STM32F098xx)
+/** @brief Macro to configure the USART3 clock (USART3CLK).
+ * @param __USART3CLKSource__: specifies the USART3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+ */
+#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
+ MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+/** @brief Macro to get the USART3 clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
+ * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
+ */
+#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
+
+#endif /*STM32F091xC || STM32F098xx*/
+/**
+ * @}
+ */
+
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
+
+/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
+ * @{
+ */
/* Interrupt & Flag management */
/**
@@ -1256,8 +1438,8 @@
/* CRS IT Error Mask */
#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
-#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
- (CRS->ICR |= (__INTERRUPT__)))
+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
+ (CRS->ICR |= (__INTERRUPT__)))
/**
* @brief Checks whether the specified CRS flag is set or not.
@@ -1292,20 +1474,24 @@
#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
- (CRS->ICR |= (__FLAG__)))
+ (CRS->ICR |= (__FLAG__)))
+/**
+ * @}
+ */
+/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+ * @{
+ */
/**
* @brief Enables the oscillator clock for frequency error counter.
* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
- * @param None
* @retval None
*/
#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
/**
* @brief Disables the oscillator clock for frequency error counter.
- * @param None
* @retval None
*/
#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
@@ -1313,14 +1499,12 @@
/**
* @brief Enables the automatic hardware adjustement of TRIM bits.
* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
- * @param None
* @retval None
*/
#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
/**
* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
- * @param None
* @retval None
*/
#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
@@ -1337,25 +1521,40 @@
*/
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
-#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
-
+/**
+ * @}
+ */
+
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
+
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+ * @{
+ */
+
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-#if defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F042x6) || defined(STM32F048xx) || \
+ defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
+ defined(STM32F091xC) || defined(STM32F098xx)
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
-#endif /* STM32F042x6 || */
- /* STM32F071xB || STM32F072xB || STM32F078xx */
+#endif /* STM32F042x6 || STM32F048xx || */
+ /* STM32F071xB || STM32F072xB || STM32F078xx || */
+ /* STM32F091xC || STM32F098xx */
/**
@@ -1365,6 +1564,14 @@
/**
* @}
*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
#ifdef __cplusplus
}