cc y / mbed

ads1115 only

Fork of mbed by mbed official

hal/i2c_api.h@135:fce8a9387ed1, 2017-01-17 (annotated)

Committer:
kaoshen
Date:
Tue Jan 17 23:27:32 2017 +0000
Revision:
135:fce8a9387ed1
Parent:
132:9baf128c2fab 
333 ADS1115 ADC1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1
<> 128:9bcdf88f62b0 2 /** \addtogroup hal */
<> 128:9bcdf88f62b0 3 /** @{*/
<> 128:9bcdf88f62b0 4 /* mbed Microcontroller Library
<> 128:9bcdf88f62b0 5 * Copyright (c) 2006-2015 ARM Limited
<> 128:9bcdf88f62b0 6 *
<> 128:9bcdf88f62b0 7 * Licensed under the Apache License, Version 2.0 (the "License");
<> 128:9bcdf88f62b0 8 * you may not use this file except in compliance with the License.
<> 128:9bcdf88f62b0 9 * You may obtain a copy of the License at
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * http://www.apache.org/licenses/LICENSE-2.0
<> 128:9bcdf88f62b0 12 *
<> 128:9bcdf88f62b0 13 * Unless required by applicable law or agreed to in writing, software
<> 128:9bcdf88f62b0 14 * distributed under the License is distributed on an "AS IS" BASIS,
<> 128:9bcdf88f62b0 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 128:9bcdf88f62b0 16 * See the License for the specific language governing permissions and
<> 128:9bcdf88f62b0 17 * limitations under the License.
<> 128:9bcdf88f62b0 18 */
<> 128:9bcdf88f62b0 19 #ifndef MBED_I2C_API_H
<> 128:9bcdf88f62b0 20 #define MBED_I2C_API_H
<> 128:9bcdf88f62b0 21
<> 128:9bcdf88f62b0 22 #include "device.h"
<> 128:9bcdf88f62b0 23 #include "hal/buffer.h"
<> 128:9bcdf88f62b0 24
<> 128:9bcdf88f62b0 25 #if DEVICE_I2C_ASYNCH
<> 128:9bcdf88f62b0 26 #include "hal/dma_api.h"
<> 128:9bcdf88f62b0 27 #endif
<> 128:9bcdf88f62b0 28
<> 128:9bcdf88f62b0 29 #if DEVICE_I2C
<> 128:9bcdf88f62b0 30
<> 128:9bcdf88f62b0 31 /**
<> 128:9bcdf88f62b0 32 * @defgroup hal_I2CEvents I2C Events Macros
<> 128:9bcdf88f62b0 33 *
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 */
<> 128:9bcdf88f62b0 36 #define I2C_EVENT_ERROR (1 << 1)
<> 128:9bcdf88f62b0 37 #define I2C_EVENT_ERROR_NO_SLAVE (1 << 2)
<> 128:9bcdf88f62b0 38 #define I2C_EVENT_TRANSFER_COMPLETE (1 << 3)
<> 128:9bcdf88f62b0 39 #define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
<> 128:9bcdf88f62b0 40 #define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
<> 128:9bcdf88f62b0 41
<> 128:9bcdf88f62b0 42 /**@}*/
<> 128:9bcdf88f62b0 43
<> 128:9bcdf88f62b0 44 #if DEVICE_I2C_ASYNCH
<> 128:9bcdf88f62b0 45 /** Asynch I2C HAL structure
<> 128:9bcdf88f62b0 46 */
<> 128:9bcdf88f62b0 47 typedef struct {
<> 128:9bcdf88f62b0 48 struct i2c_s i2c; /**< Target specific I2C structure */
<> 128:9bcdf88f62b0 49 struct buffer_s tx_buff; /**< Tx buffer */
<> 128:9bcdf88f62b0 50 struct buffer_s rx_buff; /**< Rx buffer */
<> 128:9bcdf88f62b0 51 } i2c_t;
<> 128:9bcdf88f62b0 52
<> 128:9bcdf88f62b0 53 #else
<> 128:9bcdf88f62b0 54 /** Non-asynch I2C HAL structure
<> 128:9bcdf88f62b0 55 */
<> 128:9bcdf88f62b0 56 typedef struct i2c_s i2c_t;
<> 128:9bcdf88f62b0 57
<> 128:9bcdf88f62b0 58 #endif
<> 128:9bcdf88f62b0 59
<> 128:9bcdf88f62b0 60 enum {
<> 128:9bcdf88f62b0 61 I2C_ERROR_NO_SLAVE = -1,
<> 128:9bcdf88f62b0 62 I2C_ERROR_BUS_BUSY = -2
<> 128:9bcdf88f62b0 63 };
<> 128:9bcdf88f62b0 64
<> 128:9bcdf88f62b0 65 #ifdef __cplusplus
<> 128:9bcdf88f62b0 66 extern "C" {
<> 128:9bcdf88f62b0 67 #endif
<> 128:9bcdf88f62b0 68
<> 128:9bcdf88f62b0 69 /**
<> 128:9bcdf88f62b0 70 * \defgroup hal_GeneralI2C I2C Configuration Functions
<> 128:9bcdf88f62b0 71 * @{
<> 128:9bcdf88f62b0 72 */
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 /** Initialize the I2C peripheral. It sets the default parameters for I2C
<> 128:9bcdf88f62b0 75 * peripheral, and configures its specifieds pins.
<> 128:9bcdf88f62b0 76 *
<> 128:9bcdf88f62b0 77 * @param obj The I2C object
<> 128:9bcdf88f62b0 78 * @param sda The sda pin
<> 128:9bcdf88f62b0 79 * @param scl The scl pin
<> 128:9bcdf88f62b0 80 */
<> 128:9bcdf88f62b0 81 void i2c_init(i2c_t *obj, PinName sda, PinName scl);
<> 128:9bcdf88f62b0 82
<> 128:9bcdf88f62b0 83 /** Configure the I2C frequency
<> 128:9bcdf88f62b0 84 *
<> 128:9bcdf88f62b0 85 * @param obj The I2C object
<> 128:9bcdf88f62b0 86 * @param hz Frequency in Hz
<> 128:9bcdf88f62b0 87 */
<> 128:9bcdf88f62b0 88 void i2c_frequency(i2c_t *obj, int hz);
<> 128:9bcdf88f62b0 89
<> 128:9bcdf88f62b0 90 /** Send START command
<> 128:9bcdf88f62b0 91 *
<> 128:9bcdf88f62b0 92 * @param obj The I2C object
<> 128:9bcdf88f62b0 93 */
<> 128:9bcdf88f62b0 94 int i2c_start(i2c_t *obj);
<> 128:9bcdf88f62b0 95
<> 128:9bcdf88f62b0 96 /** Send STOP command
<> 128:9bcdf88f62b0 97 *
<> 128:9bcdf88f62b0 98 * @param obj The I2C object
<> 128:9bcdf88f62b0 99 */
<> 128:9bcdf88f62b0 100 int i2c_stop(i2c_t *obj);
<> 128:9bcdf88f62b0 101
<> 128:9bcdf88f62b0 102 /** Blocking reading data
<> 128:9bcdf88f62b0 103 *
<> 128:9bcdf88f62b0 104 * @param obj The I2C object
<> 128:9bcdf88f62b0 105 * @param address 7-bit address (last bit is 1)
<> 128:9bcdf88f62b0 106 * @param data The buffer for receiving
<> 128:9bcdf88f62b0 107 * @param length Number of bytes to read
<> 128:9bcdf88f62b0 108 * @param stop Stop to be generated after the transfer is done
<> 128:9bcdf88f62b0 109 * @return Number of read bytes
<> 128:9bcdf88f62b0 110 */
<> 128:9bcdf88f62b0 111 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 /** Blocking sending data
<> 128:9bcdf88f62b0 114 *
<> 128:9bcdf88f62b0 115 * @param obj The I2C object
<> 128:9bcdf88f62b0 116 * @param address 7-bit address (last bit is 0)
<> 128:9bcdf88f62b0 117 * @param data The buffer for sending
<> 128:9bcdf88f62b0 118 * @param length Number of bytes to write
<> 128:9bcdf88f62b0 119 * @param stop Stop to be generated after the transfer is done
<> 132:9baf128c2fab 120 * @return
<> 132:9baf128c2fab 121 * zero or non-zero - Number of written bytes
<> 132:9baf128c2fab 122 * negative - I2C_ERROR_XXX status
<> 128:9bcdf88f62b0 123 */
<> 128:9bcdf88f62b0 124 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
<> 128:9bcdf88f62b0 125
<> 128:9bcdf88f62b0 126 /** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop()
<> 128:9bcdf88f62b0 127 *
<> 128:9bcdf88f62b0 128 * @param obj The I2C object
<> 128:9bcdf88f62b0 129 */
<> 128:9bcdf88f62b0 130 void i2c_reset(i2c_t *obj);
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132 /** Read one byte
<> 128:9bcdf88f62b0 133 *
<> 128:9bcdf88f62b0 134 * @param obj The I2C object
<> 128:9bcdf88f62b0 135 * @param last Acknoledge
<> 128:9bcdf88f62b0 136 * @return The read byte
<> 128:9bcdf88f62b0 137 */
<> 128:9bcdf88f62b0 138 int i2c_byte_read(i2c_t *obj, int last);
<> 128:9bcdf88f62b0 139
<> 128:9bcdf88f62b0 140 /** Write one byte
<> 128:9bcdf88f62b0 141 *
<> 128:9bcdf88f62b0 142 * @param obj The I2C object
<> 128:9bcdf88f62b0 143 * @param data Byte to be written
<> 128:9bcdf88f62b0 144 * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout.
<> 128:9bcdf88f62b0 145 */
<> 128:9bcdf88f62b0 146 int i2c_byte_write(i2c_t *obj, int data);
<> 128:9bcdf88f62b0 147
<> 128:9bcdf88f62b0 148 /**@}*/
<> 128:9bcdf88f62b0 149
<> 128:9bcdf88f62b0 150 #if DEVICE_I2CSLAVE
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 /**
<> 128:9bcdf88f62b0 153 * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
<> 128:9bcdf88f62b0 154 * @{
<> 128:9bcdf88f62b0 155 */
<> 128:9bcdf88f62b0 156
<> 128:9bcdf88f62b0 157 /** Configure I2C as slave or master.
<> 128:9bcdf88f62b0 158 * @param obj The I2C object
<> 128:9bcdf88f62b0 159 * @return non-zero if a value is available
<> 128:9bcdf88f62b0 160 */
<> 128:9bcdf88f62b0 161 void i2c_slave_mode(i2c_t *obj, int enable_slave);
<> 128:9bcdf88f62b0 162
<> 128:9bcdf88f62b0 163 /** Check to see if the I2C slave has been addressed.
<> 128:9bcdf88f62b0 164 * @param obj The I2C object
<> 128:9bcdf88f62b0 165 * @return The status - 1 - read addresses, 2 - write to all slaves,
<> 128:9bcdf88f62b0 166 * 3 write addressed, 0 - the slave has not been addressed
<> 128:9bcdf88f62b0 167 */
<> 128:9bcdf88f62b0 168 int i2c_slave_receive(i2c_t *obj);
<> 128:9bcdf88f62b0 169
<> 128:9bcdf88f62b0 170 /** Configure I2C as slave or master.
<> 128:9bcdf88f62b0 171 * @param obj The I2C object
<> 128:9bcdf88f62b0 172 * @return non-zero if a value is available
<> 128:9bcdf88f62b0 173 */
<> 128:9bcdf88f62b0 174 int i2c_slave_read(i2c_t *obj, char *data, int length);
<> 128:9bcdf88f62b0 175
<> 128:9bcdf88f62b0 176 /** Configure I2C as slave or master.
<> 128:9bcdf88f62b0 177 * @param obj The I2C object
<> 128:9bcdf88f62b0 178 * @return non-zero if a value is available
<> 128:9bcdf88f62b0 179 */
<> 128:9bcdf88f62b0 180 int i2c_slave_write(i2c_t *obj, const char *data, int length);
<> 128:9bcdf88f62b0 181
<> 128:9bcdf88f62b0 182 /** Configure I2C address.
<> 128:9bcdf88f62b0 183 * @param obj The I2C object
<> 128:9bcdf88f62b0 184 * @param idx Currently not used
<> 128:9bcdf88f62b0 185 * @param address The address to be set
<> 128:9bcdf88f62b0 186 * @param mask Currently not used
<> 128:9bcdf88f62b0 187 */
<> 128:9bcdf88f62b0 188 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
<> 128:9bcdf88f62b0 189
<> 128:9bcdf88f62b0 190 #endif
<> 128:9bcdf88f62b0 191
<> 128:9bcdf88f62b0 192 /**@}*/
<> 128:9bcdf88f62b0 193
<> 128:9bcdf88f62b0 194 #if DEVICE_I2C_ASYNCH
<> 128:9bcdf88f62b0 195
<> 128:9bcdf88f62b0 196 /**
<> 128:9bcdf88f62b0 197 * \defgroup hal_AsynchI2C Asynchronous I2C Hardware Abstraction Layer
<> 128:9bcdf88f62b0 198 * @{
<> 128:9bcdf88f62b0 199 */
<> 128:9bcdf88f62b0 200
<> 128:9bcdf88f62b0 201 /** Start I2C asynchronous transfer
<> 128:9bcdf88f62b0 202 *
<> 128:9bcdf88f62b0 203 * @param obj The I2C object
<> 128:9bcdf88f62b0 204 * @param tx The transmit buffer
<> 128:9bcdf88f62b0 205 * @param tx_length The number of bytes to transmit
<> 128:9bcdf88f62b0 206 * @param rx The receive buffer
<> 128:9bcdf88f62b0 207 * @param rx_length The number of bytes to receive
<> 128:9bcdf88f62b0 208 * @param address The address to be set - 7bit or 9bit
<> 128:9bcdf88f62b0 209 * @param stop If true, stop will be generated after the transfer is done
<> 128:9bcdf88f62b0 210 * @param handler The I2C IRQ handler to be set
<> 128:9bcdf88f62b0 211 * @param hint DMA hint usage
<> 128:9bcdf88f62b0 212 */
<> 128:9bcdf88f62b0 213 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
<> 128:9bcdf88f62b0 214
<> 128:9bcdf88f62b0 215 /** The asynchronous IRQ handler
<> 128:9bcdf88f62b0 216 *
<> 128:9bcdf88f62b0 217 * @param obj The I2C object which holds the transfer information
<> 128:9bcdf88f62b0 218 * @return Event flags if a transfer termination condition was met, otherwise return 0.
<> 128:9bcdf88f62b0 219 */
<> 128:9bcdf88f62b0 220 uint32_t i2c_irq_handler_asynch(i2c_t *obj);
<> 128:9bcdf88f62b0 221
<> 128:9bcdf88f62b0 222 /** Attempts to determine if the I2C peripheral is already in use
<> 128:9bcdf88f62b0 223 *
<> 128:9bcdf88f62b0 224 * @param obj The I2C object
<> 128:9bcdf88f62b0 225 * @return Non-zero if the I2C module is active or zero if it is not
<> 128:9bcdf88f62b0 226 */
<> 128:9bcdf88f62b0 227 uint8_t i2c_active(i2c_t *obj);
<> 128:9bcdf88f62b0 228
<> 128:9bcdf88f62b0 229 /** Abort asynchronous transfer
<> 128:9bcdf88f62b0 230 *
<> 128:9bcdf88f62b0 231 * This function does not perform any check - that should happen in upper layers.
<> 128:9bcdf88f62b0 232 * @param obj The I2C object
<> 128:9bcdf88f62b0 233 */
<> 128:9bcdf88f62b0 234 void i2c_abort_asynch(i2c_t *obj);
<> 128:9bcdf88f62b0 235
<> 128:9bcdf88f62b0 236 #endif
<> 128:9bcdf88f62b0 237
<> 128:9bcdf88f62b0 238 /**@}*/
<> 128:9bcdf88f62b0 239
<> 128:9bcdf88f62b0 240 #ifdef __cplusplus
<> 128:9bcdf88f62b0 241 }
<> 128:9bcdf88f62b0 242 #endif
<> 128:9bcdf88f62b0 243
<> 128:9bcdf88f62b0 244 #endif
<> 128:9bcdf88f62b0 245
<> 128:9bcdf88f62b0 246 #endif
<> 128:9bcdf88f62b0 247
<> 128:9bcdf88f62b0 248 /** @}*/