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TARGET_NUCLEO_L486RG/TOOLCHAIN_IAR/stm32l476xx.icf@135:fce8a9387ed1, 2017-01-17 (annotated)

Committer:
kaoshen
Date:
Tue Jan 17 23:27:32 2017 +0000
Revision:
135:fce8a9387ed1
Parent:
128:9bcdf88f62b0 
333 ADS1115 ADC1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /* [ROM = 1024kb = 0x100000] */
<> 128:9bcdf88f62b0 2 define symbol __intvec_start__ = 0x08000000;
<> 128:9bcdf88f62b0 3 define symbol __region_ROM_start__ = 0x08000000;
<> 128:9bcdf88f62b0 4 define symbol __region_ROM_end__ = 0x080FFFFF;
<> 128:9bcdf88f62b0 5
<> 128:9bcdf88f62b0 6 /* [RAM = 96kb + 32kb = 0x20000] */
<> 128:9bcdf88f62b0 7 /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
<> 128:9bcdf88f62b0 8 define symbol __NVIC_start__ = 0x10000000;
<> 128:9bcdf88f62b0 9 define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */
<> 128:9bcdf88f62b0 10 define symbol __region_SRAM2_start__ = 0x10000188;
<> 128:9bcdf88f62b0 11 define symbol __region_SRAM2_end__ = 0x10007FFF;
<> 128:9bcdf88f62b0 12 define symbol __region_SRAM1_start__ = 0x20000000;
<> 128:9bcdf88f62b0 13 define symbol __region_SRAM1_end__ = 0x20017FFF;
<> 128:9bcdf88f62b0 14
<> 128:9bcdf88f62b0 15 /* Memory regions */
<> 128:9bcdf88f62b0 16 define memory mem with size = 4G;
<> 128:9bcdf88f62b0 17 define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
<> 128:9bcdf88f62b0 18 define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_end__];
<> 128:9bcdf88f62b0 19 define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
<> 128:9bcdf88f62b0 20
<> 128:9bcdf88f62b0 21 /* Stack 1/8 and Heap 1/4 of RAM */
<> 128:9bcdf88f62b0 22 define symbol __size_cstack__ = 0x4000;
<> 128:9bcdf88f62b0 23 define symbol __size_heap__ = 0x8000;
<> 128:9bcdf88f62b0 24 define block CSTACK with alignment = 8, size = __size_cstack__ { };
<> 128:9bcdf88f62b0 25 define block HEAP with alignment = 8, size = __size_heap__ { };
<> 128:9bcdf88f62b0 26 define block STACKHEAP with fixed order { block HEAP, block CSTACK };
<> 128:9bcdf88f62b0 27
<> 128:9bcdf88f62b0 28 initialize by copy with packing = zeros { readwrite };
<> 128:9bcdf88f62b0 29 do not initialize { section .noinit };
<> 128:9bcdf88f62b0 30
<> 128:9bcdf88f62b0 31 place at address mem:__intvec_start__ { readonly section .intvec };
<> 128:9bcdf88f62b0 32
<> 128:9bcdf88f62b0 33 place in ROM_region { readonly };
<> 128:9bcdf88f62b0 34 place in SRAM1_region { readwrite, block STACKHEAP };
<> 128:9bcdf88f62b0 35 place in SRAM2_region { };