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TARGET_KW24D/TOOLCHAIN_IAR/MKW24D512xxx5.icf@135:fce8a9387ed1, 2017-01-17 (annotated)

Committer:
kaoshen
Date:
Tue Jan 17 23:27:32 2017 +0000
Revision:
135:fce8a9387ed1
Parent:
128:9bcdf88f62b0 
333 ADS1115 ADC1

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<> 128:9bcdf88f62b0 1 /*
<> 128:9bcdf88f62b0 2 ** ###################################################################
<> 128:9bcdf88f62b0 3 ** Processor: MKW24D512VHA5
<> 128:9bcdf88f62b0 4 ** Compiler: IAR ANSI C/C++ Compiler for ARM
<> 128:9bcdf88f62b0 5 ** Reference manual: MKW2xDRM Rev.2 July 2014
<> 128:9bcdf88f62b0 6 ** Version: rev. 2.0, 2014-11-26
<> 128:9bcdf88f62b0 7 ** Build: b160512
<> 128:9bcdf88f62b0 8 **
<> 128:9bcdf88f62b0 9 ** Abstract:
<> 128:9bcdf88f62b0 10 ** Linker file for the IAR ANSI C/C++ Compiler for ARM
<> 128:9bcdf88f62b0 11 **
<> 128:9bcdf88f62b0 12 ** Copyright (c) 2016 Freescale Semiconductor, Inc.
<> 128:9bcdf88f62b0 13 ** All rights reserved.
<> 128:9bcdf88f62b0 14 **
<> 128:9bcdf88f62b0 15 ** Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 16 ** are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 17 **
<> 128:9bcdf88f62b0 18 ** o Redistributions of source code must retain the above copyright notice, this list
<> 128:9bcdf88f62b0 19 ** of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 20 **
<> 128:9bcdf88f62b0 21 ** o Redistributions in binary form must reproduce the above copyright notice, this
<> 128:9bcdf88f62b0 22 ** list of conditions and the following disclaimer in the documentation and/or
<> 128:9bcdf88f62b0 23 ** other materials provided with the distribution.
<> 128:9bcdf88f62b0 24 **
<> 128:9bcdf88f62b0 25 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 128:9bcdf88f62b0 26 ** contributors may be used to endorse or promote products derived from this
<> 128:9bcdf88f62b0 27 ** software without specific prior written permission.
<> 128:9bcdf88f62b0 28 **
<> 128:9bcdf88f62b0 29 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 128:9bcdf88f62b0 30 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 128:9bcdf88f62b0 31 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 32 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 128:9bcdf88f62b0 33 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 128:9bcdf88f62b0 34 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 128:9bcdf88f62b0 35 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 128:9bcdf88f62b0 36 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 128:9bcdf88f62b0 37 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 128:9bcdf88f62b0 38 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 39 **
<> 128:9bcdf88f62b0 40 ** http: www.freescale.com
<> 128:9bcdf88f62b0 41 ** mail: support@freescale.com
<> 128:9bcdf88f62b0 42 **
<> 128:9bcdf88f62b0 43 ** ###################################################################
<> 128:9bcdf88f62b0 44 */
<> 128:9bcdf88f62b0 45 define symbol __ram_vector_table__ = 1;
<> 128:9bcdf88f62b0 46
<> 128:9bcdf88f62b0 47 /* Heap 1/4 of ram and stack 1/8 */
<> 128:9bcdf88f62b0 48 define symbol __stack_size__=0x2000;
<> 128:9bcdf88f62b0 49 define symbol __heap_size__=0x4000;
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
<> 128:9bcdf88f62b0 52 define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
<> 128:9bcdf88f62b0 53
<> 128:9bcdf88f62b0 54 define symbol m_interrupts_start = 0x00000000;
<> 128:9bcdf88f62b0 55 define symbol m_interrupts_end = 0x000003FF;
<> 128:9bcdf88f62b0 56
<> 128:9bcdf88f62b0 57 define symbol m_flash_config_start = 0x00000400;
<> 128:9bcdf88f62b0 58 define symbol m_flash_config_end = 0x0000040F;
<> 128:9bcdf88f62b0 59
<> 128:9bcdf88f62b0 60 define symbol m_text_start = 0x00000410;
<> 128:9bcdf88f62b0 61 define symbol m_text_end = 0x0007FFFF;
<> 128:9bcdf88f62b0 62
<> 128:9bcdf88f62b0 63 define symbol m_interrupts_ram_start = 0x1FFF8000;
<> 128:9bcdf88f62b0 64 define symbol m_interrupts_ram_end = 0x1FFF8000 + __ram_vector_table_offset__;
<> 128:9bcdf88f62b0 65
<> 128:9bcdf88f62b0 66 define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
<> 128:9bcdf88f62b0 67 define symbol m_data_end = 0x1FFFFFFF;
<> 128:9bcdf88f62b0 68
<> 128:9bcdf88f62b0 69 define symbol m_data_2_start = 0x20000000;
<> 128:9bcdf88f62b0 70 define symbol m_data_2_end = 0x20007FFF;
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 /* Sizes */
<> 128:9bcdf88f62b0 73 if (isdefinedsymbol(__stack_size__)) {
<> 128:9bcdf88f62b0 74 define symbol __size_cstack__ = __stack_size__;
<> 128:9bcdf88f62b0 75 } else {
<> 128:9bcdf88f62b0 76 define symbol __size_cstack__ = 0x0400;
<> 128:9bcdf88f62b0 77 }
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 if (isdefinedsymbol(__heap_size__)) {
<> 128:9bcdf88f62b0 80 define symbol __size_heap__ = __heap_size__;
<> 128:9bcdf88f62b0 81 } else {
<> 128:9bcdf88f62b0 82 define symbol __size_heap__ = 0x0400;
<> 128:9bcdf88f62b0 83 }
<> 128:9bcdf88f62b0 84
<> 128:9bcdf88f62b0 85 define exported symbol __VECTOR_TABLE = m_interrupts_start;
<> 128:9bcdf88f62b0 86 define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
<> 128:9bcdf88f62b0 87 define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
<> 128:9bcdf88f62b0 88
<> 128:9bcdf88f62b0 89 define memory mem with size = 4G;
<> 128:9bcdf88f62b0 90 define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
<> 128:9bcdf88f62b0 91 define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
<> 128:9bcdf88f62b0 92 | mem:[from m_text_start to m_text_end];
<> 128:9bcdf88f62b0 93 define region DATA_region = mem:[from m_data_start to m_data_end]
<> 128:9bcdf88f62b0 94 | mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
<> 128:9bcdf88f62b0 95 define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
<> 128:9bcdf88f62b0 96 define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 define block CSTACK with alignment = 8, size = __size_cstack__ { };
<> 128:9bcdf88f62b0 99 define block HEAP with alignment = 8, size = __size_heap__ { };
<> 128:9bcdf88f62b0 100 define block RW { readwrite };
<> 128:9bcdf88f62b0 101 define block ZI { zi };
<> 128:9bcdf88f62b0 102
<> 128:9bcdf88f62b0 103 initialize by copy { readwrite, section .textrw };
<> 128:9bcdf88f62b0 104 do not initialize { section .noinit };
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 place at address mem: m_interrupts_start { readonly section .intvec };
<> 128:9bcdf88f62b0 107 place in m_flash_config_region { section FlashConfig };
<> 128:9bcdf88f62b0 108 place in TEXT_region { readonly };
<> 128:9bcdf88f62b0 109 place in DATA_region { block RW };
<> 128:9bcdf88f62b0 110 place in DATA_region { block ZI };
<> 128:9bcdf88f62b0 111 place in DATA_region { last block HEAP };
<> 128:9bcdf88f62b0 112 place in CSTACK_region { block CSTACK };
<> 128:9bcdf88f62b0 113 place in m_interrupts_ram_region { section m_interrupts_ram };
<> 128:9bcdf88f62b0 114