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TARGET_KL05Z/core_cm0.h@135:fce8a9387ed1, 2017-01-17 (annotated)

Committer:
kaoshen
Date:
Tue Jan 17 23:27:32 2017 +0000
Revision:
135:fce8a9387ed1
Parent:
131:faff56e089b2 
333 ADS1115 ADC1

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emilmont 78:ed8466a608b4 1 /**************************************************************************//**
emilmont 78:ed8466a608b4 2 * @file core_cm0.h
emilmont 78:ed8466a608b4 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
emilmont 78:ed8466a608b4 6 *
emilmont 78:ed8466a608b4 7 * @note
emilmont 78:ed8466a608b4 8 *
emilmont 78:ed8466a608b4 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont 78:ed8466a608b4 11
emilmont 78:ed8466a608b4 12 All rights reserved.
emilmont 78:ed8466a608b4 13 Redistribution and use in source and binary forms, with or without
emilmont 78:ed8466a608b4 14 modification, are permitted provided that the following conditions are met:
emilmont 78:ed8466a608b4 15 - Redistributions of source code must retain the above copyright
emilmont 78:ed8466a608b4 16 notice, this list of conditions and the following disclaimer.
emilmont 78:ed8466a608b4 17 - Redistributions in binary form must reproduce the above copyright
emilmont 78:ed8466a608b4 18 notice, this list of conditions and the following disclaimer in the
emilmont 78:ed8466a608b4 19 documentation and/or other materials provided with the distribution.
emilmont 78:ed8466a608b4 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 78:ed8466a608b4 21 to endorse or promote products derived from this software without
emilmont 78:ed8466a608b4 22 specific prior written permission.
emilmont 78:ed8466a608b4 23 *
emilmont 78:ed8466a608b4 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 78:ed8466a608b4 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 78:ed8466a608b4 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 78:ed8466a608b4 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 78:ed8466a608b4 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 78:ed8466a608b4 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 78:ed8466a608b4 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 78:ed8466a608b4 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 78:ed8466a608b4 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 78:ed8466a608b4 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 78:ed8466a608b4 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 78:ed8466a608b4 35 ---------------------------------------------------------------------------*/
emilmont 78:ed8466a608b4 36
emilmont 78:ed8466a608b4 37
emilmont 78:ed8466a608b4 38 #if defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 78:ed8466a608b4 40 #endif
emilmont 78:ed8466a608b4 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
emilmont 78:ed8466a608b4 45 #ifdef __cplusplus
emilmont 78:ed8466a608b4 46 extern "C" {
emilmont 78:ed8466a608b4 47 #endif
emilmont 78:ed8466a608b4 48
emilmont 78:ed8466a608b4 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 78:ed8466a608b4 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 78:ed8466a608b4 51
emilmont 78:ed8466a608b4 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 78:ed8466a608b4 53 Function definitions in header files are used to allow 'inlining'.
emilmont 78:ed8466a608b4 54
emilmont 78:ed8466a608b4 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 78:ed8466a608b4 56 Unions are used for effective representation of core registers.
emilmont 78:ed8466a608b4 57
emilmont 78:ed8466a608b4 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 78:ed8466a608b4 59 Function-like macros are used to allow more efficient code.
emilmont 78:ed8466a608b4 60 */
emilmont 78:ed8466a608b4 61
emilmont 78:ed8466a608b4 62
emilmont 78:ed8466a608b4 63 /*******************************************************************************
emilmont 78:ed8466a608b4 64 * CMSIS definitions
emilmont 78:ed8466a608b4 65 ******************************************************************************/
emilmont 78:ed8466a608b4 66 /** \ingroup Cortex_M0
emilmont 78:ed8466a608b4 67 @{
emilmont 78:ed8466a608b4 68 */
emilmont 78:ed8466a608b4 69
emilmont 78:ed8466a608b4 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
emilmont 78:ed8466a608b4 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
emilmont 78:ed8466a608b4 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 78:ed8466a608b4 75
emilmont 78:ed8466a608b4 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 78:ed8466a608b4 77
emilmont 78:ed8466a608b4 78
emilmont 78:ed8466a608b4 79 #if defined ( __CC_ARM )
emilmont 78:ed8466a608b4 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 78:ed8466a608b4 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 78:ed8466a608b4 82 #define __STATIC_INLINE static __inline
emilmont 78:ed8466a608b4 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
emilmont 78:ed8466a608b4 89 #elif defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 78:ed8466a608b4 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 78:ed8466a608b4 92 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emilmont 78:ed8466a608b4 96 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 97
emilmont 78:ed8466a608b4 98 #elif defined ( __TASKING__ )
emilmont 78:ed8466a608b4 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 78:ed8466a608b4 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 78:ed8466a608b4 101 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
emilmont 78:ed8466a608b4 109 #endif
emilmont 78:ed8466a608b4 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
emilmont 78:ed8466a608b4 113 */
emilmont 78:ed8466a608b4 114 #define __FPU_USED 0
emilmont 78:ed8466a608b4 115
emilmont 78:ed8466a608b4 116 #if defined ( __CC_ARM )
emilmont 78:ed8466a608b4 117 #if defined __TARGET_FPU_VFP
emilmont 78:ed8466a608b4 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 119 #endif
emilmont 78:ed8466a608b4 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
emilmont 78:ed8466a608b4 126 #elif defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 127 #if defined __ARMVFP__
emilmont 78:ed8466a608b4 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 129 #endif
emilmont 78:ed8466a608b4 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
emilmont 78:ed8466a608b4 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 134 #endif
emilmont 78:ed8466a608b4 135
emilmont 78:ed8466a608b4 136 #elif defined ( __TASKING__ )
emilmont 78:ed8466a608b4 137 #if defined __FPU_VFP__
emilmont 78:ed8466a608b4 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
emilmont 78:ed8466a608b4 145 #endif
emilmont 78:ed8466a608b4 146
emilmont 78:ed8466a608b4 147 #include <stdint.h> /* standard types definitions */
emilmont 78:ed8466a608b4 148 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 78:ed8466a608b4 149 #include <core_cmFunc.h> /* Core Function Access */
emilmont 78:ed8466a608b4 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
emilmont 78:ed8466a608b4 155 #endif /* __CORE_CM0_H_GENERIC */
emilmont 78:ed8466a608b4 156
emilmont 78:ed8466a608b4 157 #ifndef __CMSIS_GENERIC
emilmont 78:ed8466a608b4 158
emilmont 78:ed8466a608b4 159 #ifndef __CORE_CM0_H_DEPENDANT
emilmont 78:ed8466a608b4 160 #define __CORE_CM0_H_DEPENDANT
emilmont 78:ed8466a608b4 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
emilmont 78:ed8466a608b4 166 /* check device defines and use defaults */
emilmont 78:ed8466a608b4 167 #if defined __CHECK_DEVICE_DEFINES
emilmont 78:ed8466a608b4 168 #ifndef __CM0_REV
emilmont 78:ed8466a608b4 169 #define __CM0_REV 0x0000
emilmont 78:ed8466a608b4 170 #warning "__CM0_REV not defined in device header file; using default!"
emilmont 78:ed8466a608b4 171 #endif
emilmont 78:ed8466a608b4 172
emilmont 78:ed8466a608b4 173 #ifndef __NVIC_PRIO_BITS
emilmont 78:ed8466a608b4 174 #define __NVIC_PRIO_BITS 2
emilmont 78:ed8466a608b4 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 78:ed8466a608b4 176 #endif
emilmont 78:ed8466a608b4 177
emilmont 78:ed8466a608b4 178 #ifndef __Vendor_SysTickConfig
emilmont 78:ed8466a608b4 179 #define __Vendor_SysTickConfig 0
emilmont 78:ed8466a608b4 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 78:ed8466a608b4 181 #endif
emilmont 78:ed8466a608b4 182 #endif
emilmont 78:ed8466a608b4 183
emilmont 78:ed8466a608b4 184 /* IO definitions (access restrictions to peripheral registers) */
emilmont 78:ed8466a608b4 185 /**
emilmont 78:ed8466a608b4 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 78:ed8466a608b4 187
emilmont 78:ed8466a608b4 188 <strong>IO Type Qualifiers</strong> are used
emilmont 78:ed8466a608b4 189 \li to specify the access to peripheral variables.
emilmont 78:ed8466a608b4 190 \li for automatic generation of peripheral register debug information.
emilmont 78:ed8466a608b4 191 */
emilmont 78:ed8466a608b4 192 #ifdef __cplusplus
emilmont 78:ed8466a608b4 193 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 78:ed8466a608b4 194 #else
emilmont 78:ed8466a608b4 195 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 78:ed8466a608b4 196 #endif
emilmont 78:ed8466a608b4 197 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 78:ed8466a608b4 198 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 78:ed8466a608b4 199
<> 128:9bcdf88f62b0 200 #ifdef __cplusplus
<> 128:9bcdf88f62b0 201 #define __IM volatile /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 202 #else
<> 128:9bcdf88f62b0 203 #define __IM volatile const /*!< Defines 'read only' permissions */
<> 128:9bcdf88f62b0 204 #endif
<> 128:9bcdf88f62b0 205 #define __OM volatile /*!< Defines 'write only' permissions */
<> 128:9bcdf88f62b0 206 #define __IOM volatile /*!< Defines 'read / write' permissions */
<> 128:9bcdf88f62b0 207
emilmont 78:ed8466a608b4 208 /*@} end of group Cortex_M0 */
emilmont 78:ed8466a608b4 209
emilmont 78:ed8466a608b4 210
emilmont 78:ed8466a608b4 211
emilmont 78:ed8466a608b4 212 /*******************************************************************************
emilmont 78:ed8466a608b4 213 * Register Abstraction
emilmont 78:ed8466a608b4 214 Core Register contain:
emilmont 78:ed8466a608b4 215 - Core Register
emilmont 78:ed8466a608b4 216 - Core NVIC Register
emilmont 78:ed8466a608b4 217 - Core SCB Register
emilmont 78:ed8466a608b4 218 - Core SysTick Register
emilmont 78:ed8466a608b4 219 ******************************************************************************/
emilmont 78:ed8466a608b4 220 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 78:ed8466a608b4 221 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 78:ed8466a608b4 222 */
emilmont 78:ed8466a608b4 223
emilmont 78:ed8466a608b4 224 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 225 \defgroup CMSIS_CORE Status and Control Registers
emilmont 78:ed8466a608b4 226 \brief Core Register type definitions.
emilmont 78:ed8466a608b4 227 @{
emilmont 78:ed8466a608b4 228 */
emilmont 78:ed8466a608b4 229
emilmont 78:ed8466a608b4 230 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 78:ed8466a608b4 231 */
emilmont 78:ed8466a608b4 232 typedef union
emilmont 78:ed8466a608b4 233 {
emilmont 78:ed8466a608b4 234 struct
emilmont 78:ed8466a608b4 235 {
Kojto 110:165afa46840b 236 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
emilmont 78:ed8466a608b4 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 78:ed8466a608b4 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 78:ed8466a608b4 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 78:ed8466a608b4 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 78:ed8466a608b4 241 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 242 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 243 } APSR_Type;
emilmont 78:ed8466a608b4 244
Kojto 110:165afa46840b 245 /* APSR Register Definitions */
Kojto 110:165afa46840b 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 248
Kojto 110:165afa46840b 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 251
Kojto 110:165afa46840b 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 254
Kojto 110:165afa46840b 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 257
emilmont 78:ed8466a608b4 258
emilmont 78:ed8466a608b4 259 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 78:ed8466a608b4 260 */
emilmont 78:ed8466a608b4 261 typedef union
emilmont 78:ed8466a608b4 262 {
emilmont 78:ed8466a608b4 263 struct
emilmont 78:ed8466a608b4 264 {
emilmont 78:ed8466a608b4 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 78:ed8466a608b4 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 78:ed8466a608b4 267 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 268 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 269 } IPSR_Type;
emilmont 78:ed8466a608b4 270
Kojto 110:165afa46840b 271 /* IPSR Register Definitions */
Kojto 110:165afa46840b 272 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 274
emilmont 78:ed8466a608b4 275
emilmont 78:ed8466a608b4 276 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 78:ed8466a608b4 277 */
emilmont 78:ed8466a608b4 278 typedef union
emilmont 78:ed8466a608b4 279 {
emilmont 78:ed8466a608b4 280 struct
emilmont 78:ed8466a608b4 281 {
emilmont 78:ed8466a608b4 282 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 78:ed8466a608b4 283 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 78:ed8466a608b4 284 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 285 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
emilmont 78:ed8466a608b4 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 78:ed8466a608b4 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 78:ed8466a608b4 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 78:ed8466a608b4 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 78:ed8466a608b4 290 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 291 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 292 } xPSR_Type;
emilmont 78:ed8466a608b4 293
Kojto 110:165afa46840b 294 /* xPSR Register Definitions */
Kojto 110:165afa46840b 295 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 296 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 297
Kojto 110:165afa46840b 298 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 299 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 302 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 305 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 308 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 311 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 312
emilmont 78:ed8466a608b4 313
emilmont 78:ed8466a608b4 314 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 78:ed8466a608b4 315 */
emilmont 78:ed8466a608b4 316 typedef union
emilmont 78:ed8466a608b4 317 {
emilmont 78:ed8466a608b4 318 struct
emilmont 78:ed8466a608b4 319 {
Kojto 110:165afa46840b 320 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
emilmont 78:ed8466a608b4 321 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 322 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
emilmont 78:ed8466a608b4 323 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 324 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 325 } CONTROL_Type;
emilmont 78:ed8466a608b4 326
Kojto 110:165afa46840b 327 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 328 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 329 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 330
emilmont 78:ed8466a608b4 331 /*@} end of group CMSIS_CORE */
emilmont 78:ed8466a608b4 332
emilmont 78:ed8466a608b4 333
emilmont 78:ed8466a608b4 334 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 335 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 78:ed8466a608b4 336 \brief Type definitions for the NVIC Registers
emilmont 78:ed8466a608b4 337 @{
emilmont 78:ed8466a608b4 338 */
emilmont 78:ed8466a608b4 339
emilmont 78:ed8466a608b4 340 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 78:ed8466a608b4 341 */
emilmont 78:ed8466a608b4 342 typedef struct
emilmont 78:ed8466a608b4 343 {
emilmont 78:ed8466a608b4 344 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 78:ed8466a608b4 345 uint32_t RESERVED0[31];
emilmont 78:ed8466a608b4 346 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 78:ed8466a608b4 347 uint32_t RSERVED1[31];
emilmont 78:ed8466a608b4 348 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 78:ed8466a608b4 349 uint32_t RESERVED2[31];
emilmont 78:ed8466a608b4 350 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 78:ed8466a608b4 351 uint32_t RESERVED3[31];
emilmont 78:ed8466a608b4 352 uint32_t RESERVED4[64];
emilmont 78:ed8466a608b4 353 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 78:ed8466a608b4 354 } NVIC_Type;
emilmont 78:ed8466a608b4 355
emilmont 78:ed8466a608b4 356 /*@} end of group CMSIS_NVIC */
emilmont 78:ed8466a608b4 357
emilmont 78:ed8466a608b4 358
emilmont 78:ed8466a608b4 359 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 360 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 78:ed8466a608b4 361 \brief Type definitions for the System Control Block Registers
emilmont 78:ed8466a608b4 362 @{
emilmont 78:ed8466a608b4 363 */
emilmont 78:ed8466a608b4 364
emilmont 78:ed8466a608b4 365 /** \brief Structure type to access the System Control Block (SCB).
emilmont 78:ed8466a608b4 366 */
emilmont 78:ed8466a608b4 367 typedef struct
emilmont 78:ed8466a608b4 368 {
emilmont 78:ed8466a608b4 369 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 78:ed8466a608b4 370 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 78:ed8466a608b4 371 uint32_t RESERVED0;
emilmont 78:ed8466a608b4 372 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 78:ed8466a608b4 373 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 78:ed8466a608b4 374 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 78:ed8466a608b4 375 uint32_t RESERVED1;
emilmont 78:ed8466a608b4 376 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 78:ed8466a608b4 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 78:ed8466a608b4 378 } SCB_Type;
emilmont 78:ed8466a608b4 379
emilmont 78:ed8466a608b4 380 /* SCB CPUID Register Definitions */
emilmont 78:ed8466a608b4 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 78:ed8466a608b4 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 78:ed8466a608b4 383
emilmont 78:ed8466a608b4 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 78:ed8466a608b4 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 78:ed8466a608b4 386
emilmont 78:ed8466a608b4 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 78:ed8466a608b4 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 78:ed8466a608b4 389
emilmont 78:ed8466a608b4 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 78:ed8466a608b4 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 78:ed8466a608b4 392
emilmont 78:ed8466a608b4 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
emilmont 78:ed8466a608b4 395
emilmont 78:ed8466a608b4 396 /* SCB Interrupt Control State Register Definitions */
emilmont 78:ed8466a608b4 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 78:ed8466a608b4 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 78:ed8466a608b4 399
emilmont 78:ed8466a608b4 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 78:ed8466a608b4 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 78:ed8466a608b4 402
emilmont 78:ed8466a608b4 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 78:ed8466a608b4 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 78:ed8466a608b4 405
emilmont 78:ed8466a608b4 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 78:ed8466a608b4 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 78:ed8466a608b4 408
emilmont 78:ed8466a608b4 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 78:ed8466a608b4 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 78:ed8466a608b4 411
emilmont 78:ed8466a608b4 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 78:ed8466a608b4 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 78:ed8466a608b4 414
emilmont 78:ed8466a608b4 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 78:ed8466a608b4 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 78:ed8466a608b4 417
emilmont 78:ed8466a608b4 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 78:ed8466a608b4 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 78:ed8466a608b4 420
emilmont 78:ed8466a608b4 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 78:ed8466a608b4 423
emilmont 78:ed8466a608b4 424 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 78:ed8466a608b4 425 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 78:ed8466a608b4 426 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 78:ed8466a608b4 427
emilmont 78:ed8466a608b4 428 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 78:ed8466a608b4 429 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 78:ed8466a608b4 430
emilmont 78:ed8466a608b4 431 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 78:ed8466a608b4 432 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 78:ed8466a608b4 433
emilmont 78:ed8466a608b4 434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 78:ed8466a608b4 435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 78:ed8466a608b4 436
emilmont 78:ed8466a608b4 437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 78:ed8466a608b4 438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 78:ed8466a608b4 439
emilmont 78:ed8466a608b4 440 /* SCB System Control Register Definitions */
emilmont 78:ed8466a608b4 441 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 78:ed8466a608b4 442 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 78:ed8466a608b4 443
emilmont 78:ed8466a608b4 444 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 78:ed8466a608b4 445 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 78:ed8466a608b4 446
emilmont 78:ed8466a608b4 447 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 78:ed8466a608b4 448 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 78:ed8466a608b4 449
emilmont 78:ed8466a608b4 450 /* SCB Configuration Control Register Definitions */
emilmont 78:ed8466a608b4 451 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 78:ed8466a608b4 452 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 78:ed8466a608b4 453
emilmont 78:ed8466a608b4 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 78:ed8466a608b4 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 78:ed8466a608b4 456
emilmont 78:ed8466a608b4 457 /* SCB System Handler Control and State Register Definitions */
emilmont 78:ed8466a608b4 458 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 78:ed8466a608b4 459 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 78:ed8466a608b4 460
emilmont 78:ed8466a608b4 461 /*@} end of group CMSIS_SCB */
emilmont 78:ed8466a608b4 462
emilmont 78:ed8466a608b4 463
emilmont 78:ed8466a608b4 464 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 465 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 78:ed8466a608b4 466 \brief Type definitions for the System Timer Registers.
emilmont 78:ed8466a608b4 467 @{
emilmont 78:ed8466a608b4 468 */
emilmont 78:ed8466a608b4 469
emilmont 78:ed8466a608b4 470 /** \brief Structure type to access the System Timer (SysTick).
emilmont 78:ed8466a608b4 471 */
emilmont 78:ed8466a608b4 472 typedef struct
emilmont 78:ed8466a608b4 473 {
emilmont 78:ed8466a608b4 474 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 78:ed8466a608b4 475 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 78:ed8466a608b4 476 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 78:ed8466a608b4 477 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 78:ed8466a608b4 478 } SysTick_Type;
emilmont 78:ed8466a608b4 479
emilmont 78:ed8466a608b4 480 /* SysTick Control / Status Register Definitions */
emilmont 78:ed8466a608b4 481 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 78:ed8466a608b4 482 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 78:ed8466a608b4 483
emilmont 78:ed8466a608b4 484 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 78:ed8466a608b4 485 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 78:ed8466a608b4 486
emilmont 78:ed8466a608b4 487 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 78:ed8466a608b4 488 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 78:ed8466a608b4 489
emilmont 78:ed8466a608b4 490 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 491 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
emilmont 78:ed8466a608b4 492
emilmont 78:ed8466a608b4 493 /* SysTick Reload Register Definitions */
emilmont 78:ed8466a608b4 494 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 495 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
emilmont 78:ed8466a608b4 496
emilmont 78:ed8466a608b4 497 /* SysTick Current Register Definitions */
emilmont 78:ed8466a608b4 498 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 499 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
emilmont 78:ed8466a608b4 500
emilmont 78:ed8466a608b4 501 /* SysTick Calibration Register Definitions */
emilmont 78:ed8466a608b4 502 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 78:ed8466a608b4 503 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 78:ed8466a608b4 504
emilmont 78:ed8466a608b4 505 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 78:ed8466a608b4 506 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 78:ed8466a608b4 507
emilmont 78:ed8466a608b4 508 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 509 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
emilmont 78:ed8466a608b4 510
emilmont 78:ed8466a608b4 511 /*@} end of group CMSIS_SysTick */
emilmont 78:ed8466a608b4 512
emilmont 78:ed8466a608b4 513
emilmont 78:ed8466a608b4 514 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 515 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 78:ed8466a608b4 516 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 78:ed8466a608b4 517 are only accessible over DAP and not via processor. Therefore
emilmont 78:ed8466a608b4 518 they are not covered by the Cortex-M0 header file.
emilmont 78:ed8466a608b4 519 @{
emilmont 78:ed8466a608b4 520 */
emilmont 78:ed8466a608b4 521 /*@} end of group CMSIS_CoreDebug */
emilmont 78:ed8466a608b4 522
emilmont 78:ed8466a608b4 523
emilmont 78:ed8466a608b4 524 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 525 \defgroup CMSIS_core_base Core Definitions
emilmont 78:ed8466a608b4 526 \brief Definitions for base addresses, unions, and structures.
emilmont 78:ed8466a608b4 527 @{
emilmont 78:ed8466a608b4 528 */
emilmont 78:ed8466a608b4 529
emilmont 78:ed8466a608b4 530 /* Memory mapping of Cortex-M0 Hardware */
emilmont 78:ed8466a608b4 531 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 78:ed8466a608b4 532 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 78:ed8466a608b4 533 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 78:ed8466a608b4 534 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 78:ed8466a608b4 535
emilmont 78:ed8466a608b4 536 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 78:ed8466a608b4 537 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 78:ed8466a608b4 538 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 78:ed8466a608b4 539
emilmont 78:ed8466a608b4 540
emilmont 78:ed8466a608b4 541 /*@} */
emilmont 78:ed8466a608b4 542
emilmont 78:ed8466a608b4 543
emilmont 78:ed8466a608b4 544
emilmont 78:ed8466a608b4 545 /*******************************************************************************
emilmont 78:ed8466a608b4 546 * Hardware Abstraction Layer
emilmont 78:ed8466a608b4 547 Core Function Interface contains:
emilmont 78:ed8466a608b4 548 - Core NVIC Functions
emilmont 78:ed8466a608b4 549 - Core SysTick Functions
emilmont 78:ed8466a608b4 550 - Core Register Access Functions
emilmont 78:ed8466a608b4 551 ******************************************************************************/
emilmont 78:ed8466a608b4 552 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 78:ed8466a608b4 553 */
emilmont 78:ed8466a608b4 554
emilmont 78:ed8466a608b4 555
emilmont 78:ed8466a608b4 556
emilmont 78:ed8466a608b4 557 /* ########################## NVIC functions #################################### */
emilmont 78:ed8466a608b4 558 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 559 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 78:ed8466a608b4 560 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 78:ed8466a608b4 561 @{
emilmont 78:ed8466a608b4 562 */
emilmont 78:ed8466a608b4 563
emilmont 78:ed8466a608b4 564 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 78:ed8466a608b4 565 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 566 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 567 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 568 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
emilmont 78:ed8466a608b4 569
emilmont 78:ed8466a608b4 570
emilmont 78:ed8466a608b4 571 /** \brief Enable External Interrupt
emilmont 78:ed8466a608b4 572
emilmont 78:ed8466a608b4 573 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 78:ed8466a608b4 574
emilmont 78:ed8466a608b4 575 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 576 */
emilmont 78:ed8466a608b4 577 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 578 {
Kojto 110:165afa46840b 579 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 580 }
emilmont 78:ed8466a608b4 581
emilmont 78:ed8466a608b4 582
emilmont 78:ed8466a608b4 583 /** \brief Disable External Interrupt
emilmont 78:ed8466a608b4 584
emilmont 78:ed8466a608b4 585 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 78:ed8466a608b4 586
emilmont 78:ed8466a608b4 587 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 588 */
emilmont 78:ed8466a608b4 589 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 590 {
Kojto 110:165afa46840b 591 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 131:faff56e089b2 592 __DSB();
<> 131:faff56e089b2 593 __ISB();
emilmont 78:ed8466a608b4 594 }
emilmont 78:ed8466a608b4 595
emilmont 78:ed8466a608b4 596
emilmont 78:ed8466a608b4 597 /** \brief Get Pending Interrupt
emilmont 78:ed8466a608b4 598
emilmont 78:ed8466a608b4 599 The function reads the pending register in the NVIC and returns the pending bit
emilmont 78:ed8466a608b4 600 for the specified interrupt.
emilmont 78:ed8466a608b4 601
emilmont 78:ed8466a608b4 602 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 603
emilmont 78:ed8466a608b4 604 \return 0 Interrupt status is not pending.
emilmont 78:ed8466a608b4 605 \return 1 Interrupt status is pending.
emilmont 78:ed8466a608b4 606 */
emilmont 78:ed8466a608b4 607 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 608 {
Kojto 110:165afa46840b 609 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont 78:ed8466a608b4 610 }
emilmont 78:ed8466a608b4 611
emilmont 78:ed8466a608b4 612
emilmont 78:ed8466a608b4 613 /** \brief Set Pending Interrupt
emilmont 78:ed8466a608b4 614
emilmont 78:ed8466a608b4 615 The function sets the pending bit of an external interrupt.
emilmont 78:ed8466a608b4 616
emilmont 78:ed8466a608b4 617 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 618 */
emilmont 78:ed8466a608b4 619 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 620 {
Kojto 110:165afa46840b 621 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 622 }
emilmont 78:ed8466a608b4 623
emilmont 78:ed8466a608b4 624
emilmont 78:ed8466a608b4 625 /** \brief Clear Pending Interrupt
emilmont 78:ed8466a608b4 626
emilmont 78:ed8466a608b4 627 The function clears the pending bit of an external interrupt.
emilmont 78:ed8466a608b4 628
emilmont 78:ed8466a608b4 629 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 630 */
emilmont 78:ed8466a608b4 631 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 632 {
Kojto 110:165afa46840b 633 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 634 }
emilmont 78:ed8466a608b4 635
emilmont 78:ed8466a608b4 636
emilmont 78:ed8466a608b4 637 /** \brief Set Interrupt Priority
emilmont 78:ed8466a608b4 638
emilmont 78:ed8466a608b4 639 The function sets the priority of an interrupt.
emilmont 78:ed8466a608b4 640
emilmont 78:ed8466a608b4 641 \note The priority cannot be set for every core interrupt.
emilmont 78:ed8466a608b4 642
emilmont 78:ed8466a608b4 643 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 644 \param [in] priority Priority to set.
emilmont 78:ed8466a608b4 645 */
emilmont 78:ed8466a608b4 646 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 78:ed8466a608b4 647 {
Kojto 110:165afa46840b 648 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 649 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 650 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 651 }
emilmont 78:ed8466a608b4 652 else {
Kojto 110:165afa46840b 653 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 654 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 655 }
emilmont 78:ed8466a608b4 656 }
emilmont 78:ed8466a608b4 657
emilmont 78:ed8466a608b4 658
emilmont 78:ed8466a608b4 659 /** \brief Get Interrupt Priority
emilmont 78:ed8466a608b4 660
emilmont 78:ed8466a608b4 661 The function reads the priority of an interrupt. The interrupt
emilmont 78:ed8466a608b4 662 number can be positive to specify an external (device specific)
emilmont 78:ed8466a608b4 663 interrupt, or negative to specify an internal (core) interrupt.
emilmont 78:ed8466a608b4 664
emilmont 78:ed8466a608b4 665
emilmont 78:ed8466a608b4 666 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 667 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 78:ed8466a608b4 668 priority bits of the microcontroller.
emilmont 78:ed8466a608b4 669 */
emilmont 78:ed8466a608b4 670 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 671 {
emilmont 78:ed8466a608b4 672
Kojto 110:165afa46840b 673 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 674 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 675 }
emilmont 78:ed8466a608b4 676 else {
Kojto 110:165afa46840b 677 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 678 }
emilmont 78:ed8466a608b4 679 }
emilmont 78:ed8466a608b4 680
emilmont 78:ed8466a608b4 681
emilmont 78:ed8466a608b4 682 /** \brief System Reset
emilmont 78:ed8466a608b4 683
emilmont 78:ed8466a608b4 684 The function initiates a system reset request to reset the MCU.
emilmont 78:ed8466a608b4 685 */
emilmont 78:ed8466a608b4 686 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 78:ed8466a608b4 687 {
emilmont 78:ed8466a608b4 688 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 78:ed8466a608b4 689 buffered write are completed before reset */
Kojto 110:165afa46840b 690 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
emilmont 78:ed8466a608b4 691 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 78:ed8466a608b4 692 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 693 while(1) { __NOP(); } /* wait until reset */
emilmont 78:ed8466a608b4 694 }
emilmont 78:ed8466a608b4 695
emilmont 78:ed8466a608b4 696 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 78:ed8466a608b4 697
emilmont 78:ed8466a608b4 698
emilmont 78:ed8466a608b4 699
emilmont 78:ed8466a608b4 700 /* ################################## SysTick function ############################################ */
emilmont 78:ed8466a608b4 701 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 702 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 78:ed8466a608b4 703 \brief Functions that configure the System.
emilmont 78:ed8466a608b4 704 @{
emilmont 78:ed8466a608b4 705 */
emilmont 78:ed8466a608b4 706
emilmont 78:ed8466a608b4 707 #if (__Vendor_SysTickConfig == 0)
emilmont 78:ed8466a608b4 708
emilmont 78:ed8466a608b4 709 /** \brief System Tick Configuration
emilmont 78:ed8466a608b4 710
emilmont 78:ed8466a608b4 711 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 78:ed8466a608b4 712 Counter is in free running mode to generate periodic interrupts.
emilmont 78:ed8466a608b4 713
emilmont 78:ed8466a608b4 714 \param [in] ticks Number of ticks between two interrupts.
emilmont 78:ed8466a608b4 715
emilmont 78:ed8466a608b4 716 \return 0 Function succeeded.
emilmont 78:ed8466a608b4 717 \return 1 Function failed.
emilmont 78:ed8466a608b4 718
emilmont 78:ed8466a608b4 719 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 78:ed8466a608b4 720 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 78:ed8466a608b4 721 must contain a vendor-specific implementation of this function.
emilmont 78:ed8466a608b4 722
emilmont 78:ed8466a608b4 723 */
emilmont 78:ed8466a608b4 724 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 78:ed8466a608b4 725 {
Kojto 110:165afa46840b 726 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
emilmont 78:ed8466a608b4 727
Kojto 110:165afa46840b 728 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 729 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 730 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
emilmont 78:ed8466a608b4 731 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 78:ed8466a608b4 732 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 733 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 734 return (0UL); /* Function successful */
emilmont 78:ed8466a608b4 735 }
emilmont 78:ed8466a608b4 736
emilmont 78:ed8466a608b4 737 #endif
emilmont 78:ed8466a608b4 738
emilmont 78:ed8466a608b4 739 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 78:ed8466a608b4 740
emilmont 78:ed8466a608b4 741
emilmont 78:ed8466a608b4 742
emilmont 78:ed8466a608b4 743
Kojto 110:165afa46840b 744 #ifdef __cplusplus
Kojto 110:165afa46840b 745 }
Kojto 110:165afa46840b 746 #endif
Kojto 110:165afa46840b 747
emilmont 78:ed8466a608b4 748 #endif /* __CORE_CM0_H_DEPENDANT */
emilmont 78:ed8466a608b4 749
emilmont 78:ed8466a608b4 750 #endif /* __CMSIS_GENERIC */