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TARGET_NUCLEO_L152RE/stm32l152xe.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
90:cb3d968589d8 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32l152xe.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V2.1.3
Kojto 122:f9eeca106725 6 * @date 04-March-2016
Kojto 90:cb3d968589d8 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
Kojto 90:cb3d968589d8 8 * This file contains all the peripheral register's definitions, bits
Kojto 90:cb3d968589d8 9 * definitions and memory mapping for STM32L1xx devices.
Kojto 90:cb3d968589d8 10 *
Kojto 90:cb3d968589d8 11 * This file contains:
Kojto 90:cb3d968589d8 12 * - Data structures and the address mapping for all peripherals
Kojto 90:cb3d968589d8 13 * - Peripheral's registers declarations and bits definition
Kojto 90:cb3d968589d8 14 * - Macros to access peripheral’s registers hardware
Kojto 90:cb3d968589d8 15 *
Kojto 90:cb3d968589d8 16 ******************************************************************************
Kojto 90:cb3d968589d8 17 * @attention
Kojto 90:cb3d968589d8 18 *
Kojto 122:f9eeca106725 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 20 *
Kojto 90:cb3d968589d8 21 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 22 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 23 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 24 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 26 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 27 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 29 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 30 * without specific prior written permission.
Kojto 122:f9eeca106725 31 *
Kojto 90:cb3d968589d8 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 *
Kojto 90:cb3d968589d8 43 ******************************************************************************
Kojto 90:cb3d968589d8 44 */
Kojto 90:cb3d968589d8 45
Kojto 90:cb3d968589d8 46 /** @addtogroup CMSIS
Kojto 90:cb3d968589d8 47 * @{
Kojto 90:cb3d968589d8 48 */
Kojto 90:cb3d968589d8 49
Kojto 90:cb3d968589d8 50 /** @addtogroup stm32l152xe
Kojto 90:cb3d968589d8 51 * @{
Kojto 90:cb3d968589d8 52 */
Kojto 90:cb3d968589d8 53
Kojto 90:cb3d968589d8 54 #ifndef __STM32L152xE_H
Kojto 90:cb3d968589d8 55 #define __STM32L152xE_H
Kojto 90:cb3d968589d8 56
Kojto 90:cb3d968589d8 57 #ifdef __cplusplus
Kojto 90:cb3d968589d8 58 extern "C" {
Kojto 90:cb3d968589d8 59 #endif
Kojto 90:cb3d968589d8 60
Kojto 90:cb3d968589d8 61
Kojto 90:cb3d968589d8 62 /** @addtogroup Configuration_section_for_CMSIS
Kojto 90:cb3d968589d8 63 * @{
Kojto 90:cb3d968589d8 64 */
Kojto 90:cb3d968589d8 65 /**
Kojto 90:cb3d968589d8 66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
Kojto 90:cb3d968589d8 67 */
Kojto 122:f9eeca106725 68 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */
Kojto 122:f9eeca106725 69 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */
Kojto 122:f9eeca106725 70 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */
Kojto 122:f9eeca106725 71 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
Kojto 90:cb3d968589d8 72
Kojto 90:cb3d968589d8 73 /**
Kojto 90:cb3d968589d8 74 * @}
Kojto 90:cb3d968589d8 75 */
Kojto 90:cb3d968589d8 76
Kojto 90:cb3d968589d8 77 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 90:cb3d968589d8 78 * @{
Kojto 90:cb3d968589d8 79 */
Kojto 90:cb3d968589d8 80
Kojto 90:cb3d968589d8 81 /**
Kojto 90:cb3d968589d8 82 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
Kojto 90:cb3d968589d8 83 * in @ref Library_configuration_section
Kojto 90:cb3d968589d8 84 */
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 /*!< Interrupt Number Definition */
Kojto 90:cb3d968589d8 87 typedef enum
Kojto 90:cb3d968589d8 88 {
Kojto 90:cb3d968589d8 89 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
Kojto 90:cb3d968589d8 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 122:f9eeca106725 91 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
Kojto 90:cb3d968589d8 92 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
Kojto 90:cb3d968589d8 93 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
Kojto 90:cb3d968589d8 94 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
Kojto 90:cb3d968589d8 95 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
Kojto 90:cb3d968589d8 96 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
Kojto 90:cb3d968589d8 97 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
Kojto 90:cb3d968589d8 98 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
Kojto 90:cb3d968589d8 99
Kojto 90:cb3d968589d8 100 /****** STM32L specific Interrupt Numbers ***********************************************************/
Kojto 90:cb3d968589d8 101 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 90:cb3d968589d8 102 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 90:cb3d968589d8 103 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 90:cb3d968589d8 104 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
Kojto 90:cb3d968589d8 105 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 90:cb3d968589d8 106 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 90:cb3d968589d8 107 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 90:cb3d968589d8 108 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 90:cb3d968589d8 109 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 90:cb3d968589d8 110 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 90:cb3d968589d8 111 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 90:cb3d968589d8 112 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
Kojto 90:cb3d968589d8 113 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
Kojto 90:cb3d968589d8 114 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
Kojto 90:cb3d968589d8 115 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
Kojto 90:cb3d968589d8 116 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
Kojto 90:cb3d968589d8 117 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
Kojto 90:cb3d968589d8 118 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
Kojto 90:cb3d968589d8 119 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
Kojto 90:cb3d968589d8 120 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
Kojto 90:cb3d968589d8 121 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
Kojto 90:cb3d968589d8 122 DAC_IRQn = 21, /*!< DAC Interrupt */
Kojto 90:cb3d968589d8 123 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
Kojto 90:cb3d968589d8 124 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 90:cb3d968589d8 125 LCD_IRQn = 24, /*!< LCD Interrupt */
Kojto 90:cb3d968589d8 126 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
Kojto 90:cb3d968589d8 127 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
Kojto 90:cb3d968589d8 128 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
Kojto 90:cb3d968589d8 129 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 90:cb3d968589d8 130 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 90:cb3d968589d8 131 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 90:cb3d968589d8 132 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 90:cb3d968589d8 133 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 90:cb3d968589d8 134 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 90:cb3d968589d8 135 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 90:cb3d968589d8 136 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 90:cb3d968589d8 137 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 90:cb3d968589d8 138 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 90:cb3d968589d8 139 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 90:cb3d968589d8 140 USART3_IRQn = 39, /*!< USART3 global Interrupt */
Kojto 90:cb3d968589d8 141 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 90:cb3d968589d8 142 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
Kojto 90:cb3d968589d8 143 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
Kojto 90:cb3d968589d8 144 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
Kojto 90:cb3d968589d8 145 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
Kojto 90:cb3d968589d8 146 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
Kojto 90:cb3d968589d8 147 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
Kojto 90:cb3d968589d8 148 UART4_IRQn = 48, /*!< UART4 global Interrupt */
Kojto 90:cb3d968589d8 149 UART5_IRQn = 49, /*!< UART5 global Interrupt */
Kojto 90:cb3d968589d8 150 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
Kojto 90:cb3d968589d8 151 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
Kojto 90:cb3d968589d8 152 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
Kojto 90:cb3d968589d8 153 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
Kojto 90:cb3d968589d8 154 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
Kojto 90:cb3d968589d8 155 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
Kojto 90:cb3d968589d8 156 } IRQn_Type;
Kojto 90:cb3d968589d8 157
Kojto 90:cb3d968589d8 158 /**
Kojto 90:cb3d968589d8 159 * @}
Kojto 90:cb3d968589d8 160 */
Kojto 90:cb3d968589d8 161
Kojto 90:cb3d968589d8 162 #include "core_cm3.h"
Kojto 90:cb3d968589d8 163 #include "system_stm32l1xx.h"
Kojto 90:cb3d968589d8 164 #include <stdint.h>
Kojto 90:cb3d968589d8 165
Kojto 90:cb3d968589d8 166 /** @addtogroup Peripheral_registers_structures
Kojto 90:cb3d968589d8 167 * @{
Kojto 90:cb3d968589d8 168 */
Kojto 90:cb3d968589d8 169
Kojto 90:cb3d968589d8 170 /**
Kojto 90:cb3d968589d8 171 * @brief Analog to Digital Converter
Kojto 90:cb3d968589d8 172 */
Kojto 90:cb3d968589d8 173
Kojto 90:cb3d968589d8 174 typedef struct
Kojto 90:cb3d968589d8 175 {
Kojto 90:cb3d968589d8 176 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 177 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 90:cb3d968589d8 178 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 90:cb3d968589d8 179 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 90:cb3d968589d8 180 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 90:cb3d968589d8 181 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
Kojto 90:cb3d968589d8 182 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
Kojto 90:cb3d968589d8 183 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
Kojto 90:cb3d968589d8 184 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
Kojto 90:cb3d968589d8 185 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
Kojto 90:cb3d968589d8 186 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 187 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 188 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
Kojto 90:cb3d968589d8 189 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
Kojto 90:cb3d968589d8 190 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
Kojto 90:cb3d968589d8 191 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
Kojto 90:cb3d968589d8 192 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
Kojto 90:cb3d968589d8 193 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
Kojto 90:cb3d968589d8 194 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
Kojto 90:cb3d968589d8 195 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
Kojto 90:cb3d968589d8 196 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
Kojto 90:cb3d968589d8 197 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
Kojto 90:cb3d968589d8 198 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
Kojto 90:cb3d968589d8 199 __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
Kojto 90:cb3d968589d8 200 } ADC_TypeDef;
Kojto 90:cb3d968589d8 201
Kojto 90:cb3d968589d8 202 typedef struct
Kojto 90:cb3d968589d8 203 {
Kojto 90:cb3d968589d8 204 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
Kojto 90:cb3d968589d8 205 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 90:cb3d968589d8 206 } ADC_Common_TypeDef;
Kojto 90:cb3d968589d8 207
Kojto 90:cb3d968589d8 208 /**
Kojto 90:cb3d968589d8 209 * @brief Comparator
Kojto 90:cb3d968589d8 210 */
Kojto 90:cb3d968589d8 211
Kojto 90:cb3d968589d8 212 typedef struct
Kojto 90:cb3d968589d8 213 {
Kojto 90:cb3d968589d8 214 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 215 } COMP_TypeDef;
Kojto 90:cb3d968589d8 216
Kojto 90:cb3d968589d8 217 /**
Kojto 90:cb3d968589d8 218 * @brief CRC calculation unit
Kojto 90:cb3d968589d8 219 */
Kojto 90:cb3d968589d8 220
Kojto 90:cb3d968589d8 221 typedef struct
Kojto 90:cb3d968589d8 222 {
Kojto 90:cb3d968589d8 223 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 122:f9eeca106725 224 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 122:f9eeca106725 225 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
Kojto 122:f9eeca106725 226 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
Kojto 90:cb3d968589d8 227 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 228 } CRC_TypeDef;
Kojto 90:cb3d968589d8 229
Kojto 90:cb3d968589d8 230 /**
Kojto 90:cb3d968589d8 231 * @brief Digital to Analog Converter
Kojto 90:cb3d968589d8 232 */
Kojto 90:cb3d968589d8 233
Kojto 90:cb3d968589d8 234 typedef struct
Kojto 90:cb3d968589d8 235 {
Kojto 90:cb3d968589d8 236 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 237 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 238 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 239 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 240 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 241 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 242 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 243 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 244 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 245 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 246 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 247 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 248 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 90:cb3d968589d8 249 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 90:cb3d968589d8 250 } DAC_TypeDef;
Kojto 90:cb3d968589d8 251
Kojto 90:cb3d968589d8 252 /**
Kojto 90:cb3d968589d8 253 * @brief Debug MCU
Kojto 90:cb3d968589d8 254 */
Kojto 90:cb3d968589d8 255
Kojto 90:cb3d968589d8 256 typedef struct
Kojto 90:cb3d968589d8 257 {
Kojto 90:cb3d968589d8 258 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 90:cb3d968589d8 259 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 260 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 261 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 262 }DBGMCU_TypeDef;
Kojto 90:cb3d968589d8 263
Kojto 90:cb3d968589d8 264 /**
Kojto 90:cb3d968589d8 265 * @brief DMA Controller
Kojto 90:cb3d968589d8 266 */
Kojto 90:cb3d968589d8 267
Kojto 90:cb3d968589d8 268 typedef struct
Kojto 90:cb3d968589d8 269 {
Kojto 90:cb3d968589d8 270 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 90:cb3d968589d8 271 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 90:cb3d968589d8 272 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 90:cb3d968589d8 273 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 90:cb3d968589d8 274 } DMA_Channel_TypeDef;
Kojto 90:cb3d968589d8 275
Kojto 90:cb3d968589d8 276 typedef struct
Kojto 90:cb3d968589d8 277 {
Kojto 90:cb3d968589d8 278 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 279 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 280 } DMA_TypeDef;
Kojto 90:cb3d968589d8 281
Kojto 90:cb3d968589d8 282 /**
Kojto 90:cb3d968589d8 283 * @brief External Interrupt/Event Controller
Kojto 90:cb3d968589d8 284 */
Kojto 90:cb3d968589d8 285
Kojto 90:cb3d968589d8 286 typedef struct
Kojto 90:cb3d968589d8 287 {
Kojto 90:cb3d968589d8 288 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 289 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 290 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 90:cb3d968589d8 291 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 292 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 293 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 294 } EXTI_TypeDef;
Kojto 90:cb3d968589d8 295
Kojto 90:cb3d968589d8 296 /**
Kojto 90:cb3d968589d8 297 * @brief FLASH Registers
Kojto 90:cb3d968589d8 298 */
Kojto 90:cb3d968589d8 299 typedef struct
Kojto 90:cb3d968589d8 300 {
Kojto 90:cb3d968589d8 301 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 302 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 303 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 304 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
Kojto 90:cb3d968589d8 305 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 306 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 307 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 308 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
Kojto 90:cb3d968589d8 309 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
Kojto 90:cb3d968589d8 310 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
Kojto 90:cb3d968589d8 311 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
Kojto 90:cb3d968589d8 312 __IO uint32_t WRPR3; /*!< Write protection register 3, Address offset: 0x84 */
Kojto 90:cb3d968589d8 313 __IO uint32_t WRPR4; /*!< Write protection register 4, Address offset: 0x88 */
Kojto 90:cb3d968589d8 314 } FLASH_TypeDef;
Kojto 90:cb3d968589d8 315
Kojto 90:cb3d968589d8 316 /**
Kojto 90:cb3d968589d8 317 * @brief Option Bytes Registers
Kojto 90:cb3d968589d8 318 */
Kojto 90:cb3d968589d8 319 typedef struct
Kojto 90:cb3d968589d8 320 {
Kojto 90:cb3d968589d8 321 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 322 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 323 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
Kojto 90:cb3d968589d8 324 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
Kojto 90:cb3d968589d8 325 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
Kojto 90:cb3d968589d8 326 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
Kojto 90:cb3d968589d8 327 __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
Kojto 90:cb3d968589d8 328 __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
Kojto 90:cb3d968589d8 329 uint32_t RESERVED[24]; /*!< Reserved, 0x20 -> 0x7C */
Kojto 90:cb3d968589d8 330 __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */
Kojto 90:cb3d968589d8 331 __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */
Kojto 90:cb3d968589d8 332 } OB_TypeDef;
Kojto 90:cb3d968589d8 333
Kojto 90:cb3d968589d8 334 /**
Kojto 90:cb3d968589d8 335 * @brief Operational Amplifier (OPAMP)
Kojto 90:cb3d968589d8 336 */
Kojto 90:cb3d968589d8 337 typedef struct
Kojto 90:cb3d968589d8 338 {
Kojto 90:cb3d968589d8 339 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 340 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
Kojto 90:cb3d968589d8 341 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
Kojto 90:cb3d968589d8 342 } OPAMP_TypeDef;
Kojto 90:cb3d968589d8 343
Kojto 90:cb3d968589d8 344 /**
Kojto 90:cb3d968589d8 345 * @brief General Purpose IO
Kojto 90:cb3d968589d8 346 */
Kojto 90:cb3d968589d8 347
Kojto 90:cb3d968589d8 348 typedef struct
Kojto 90:cb3d968589d8 349 {
Kojto 90:cb3d968589d8 350 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 351 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 352 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 353 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 354 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 355 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 356 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
Kojto 90:cb3d968589d8 357 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 358 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
Kojto 90:cb3d968589d8 359 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 360 } GPIO_TypeDef;
Kojto 90:cb3d968589d8 361
Kojto 90:cb3d968589d8 362 /**
Kojto 90:cb3d968589d8 363 * @brief SysTem Configuration
Kojto 90:cb3d968589d8 364 */
Kojto 90:cb3d968589d8 365
Kojto 90:cb3d968589d8 366 typedef struct
Kojto 90:cb3d968589d8 367 {
Kojto 90:cb3d968589d8 368 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 369 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 370 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 90:cb3d968589d8 371 } SYSCFG_TypeDef;
Kojto 90:cb3d968589d8 372
Kojto 90:cb3d968589d8 373 /**
Kojto 90:cb3d968589d8 374 * @brief Inter-integrated Circuit Interface
Kojto 90:cb3d968589d8 375 */
Kojto 90:cb3d968589d8 376
Kojto 90:cb3d968589d8 377 typedef struct
Kojto 90:cb3d968589d8 378 {
Kojto 90:cb3d968589d8 379 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 380 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 381 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
Kojto 90:cb3d968589d8 382 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
Kojto 90:cb3d968589d8 383 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 384 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
Kojto 90:cb3d968589d8 385 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
Kojto 90:cb3d968589d8 386 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 387 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 388 } I2C_TypeDef;
Kojto 90:cb3d968589d8 389
Kojto 90:cb3d968589d8 390 /**
Kojto 90:cb3d968589d8 391 * @brief Independent WATCHDOG
Kojto 90:cb3d968589d8 392 */
Kojto 90:cb3d968589d8 393
Kojto 90:cb3d968589d8 394 typedef struct
Kojto 90:cb3d968589d8 395 {
Kojto 90:cb3d968589d8 396 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 397 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 398 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 399 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 400 } IWDG_TypeDef;
Kojto 90:cb3d968589d8 401
Kojto 90:cb3d968589d8 402 /**
Kojto 90:cb3d968589d8 403 * @brief LCD
Kojto 90:cb3d968589d8 404 */
Kojto 90:cb3d968589d8 405
Kojto 90:cb3d968589d8 406 typedef struct
Kojto 90:cb3d968589d8 407 {
Kojto 90:cb3d968589d8 408 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 409 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 410 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 411 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 412 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
Kojto 90:cb3d968589d8 413 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
Kojto 90:cb3d968589d8 414 } LCD_TypeDef;
Kojto 90:cb3d968589d8 415
Kojto 90:cb3d968589d8 416 /**
Kojto 90:cb3d968589d8 417 * @brief Power Control
Kojto 90:cb3d968589d8 418 */
Kojto 90:cb3d968589d8 419
Kojto 90:cb3d968589d8 420 typedef struct
Kojto 90:cb3d968589d8 421 {
Kojto 90:cb3d968589d8 422 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 423 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 424 } PWR_TypeDef;
Kojto 90:cb3d968589d8 425
Kojto 90:cb3d968589d8 426 /**
Kojto 90:cb3d968589d8 427 * @brief Reset and Clock Control
Kojto 90:cb3d968589d8 428 */
Kojto 90:cb3d968589d8 429
Kojto 90:cb3d968589d8 430 typedef struct
Kojto 90:cb3d968589d8 431 {
Kojto 90:cb3d968589d8 432 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 433 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 434 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 435 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 436 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 437 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 438 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 439 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 440 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 441 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 442 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 443 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 444 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
Kojto 90:cb3d968589d8 445 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
Kojto 90:cb3d968589d8 446 } RCC_TypeDef;
Kojto 90:cb3d968589d8 447
Kojto 90:cb3d968589d8 448 /**
Kojto 90:cb3d968589d8 449 * @brief Routing Interface
Kojto 90:cb3d968589d8 450 */
Kojto 90:cb3d968589d8 451
Kojto 90:cb3d968589d8 452 typedef struct
Kojto 90:cb3d968589d8 453 {
Kojto 90:cb3d968589d8 454 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 455 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 456 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
Kojto 90:cb3d968589d8 457 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 458 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 459 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 460 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 461 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
Kojto 90:cb3d968589d8 462 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
Kojto 90:cb3d968589d8 463 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
Kojto 90:cb3d968589d8 464 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
Kojto 90:cb3d968589d8 465 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
Kojto 90:cb3d968589d8 466 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
Kojto 90:cb3d968589d8 467 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
Kojto 90:cb3d968589d8 468 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
Kojto 90:cb3d968589d8 469 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
Kojto 90:cb3d968589d8 470 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
Kojto 90:cb3d968589d8 471 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
Kojto 90:cb3d968589d8 472 __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
Kojto 90:cb3d968589d8 473 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
Kojto 90:cb3d968589d8 474 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
Kojto 90:cb3d968589d8 475 __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
Kojto 90:cb3d968589d8 476 } RI_TypeDef;
Kojto 90:cb3d968589d8 477
Kojto 90:cb3d968589d8 478 /**
Kojto 90:cb3d968589d8 479 * @brief Real-Time Clock
Kojto 90:cb3d968589d8 480 */
Kojto 90:cb3d968589d8 481 typedef struct
Kojto 90:cb3d968589d8 482 {
Kojto 90:cb3d968589d8 483 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 484 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 485 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 486 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 487 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 488 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 489 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 490 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 491 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 492 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 493 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 494 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 495 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 90:cb3d968589d8 496 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 90:cb3d968589d8 497 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 90:cb3d968589d8 498 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
Kojto 90:cb3d968589d8 499 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 90:cb3d968589d8 500 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 90:cb3d968589d8 501 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 90:cb3d968589d8 502 uint32_t RESERVED7; /*!< Reserved, 0x4C */
Kojto 90:cb3d968589d8 503 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 90:cb3d968589d8 504 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 90:cb3d968589d8 505 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 90:cb3d968589d8 506 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 90:cb3d968589d8 507 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 90:cb3d968589d8 508 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 90:cb3d968589d8 509 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 90:cb3d968589d8 510 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 90:cb3d968589d8 511 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 90:cb3d968589d8 512 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 90:cb3d968589d8 513 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 90:cb3d968589d8 514 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 90:cb3d968589d8 515 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 90:cb3d968589d8 516 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 90:cb3d968589d8 517 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 90:cb3d968589d8 518 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 90:cb3d968589d8 519 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 90:cb3d968589d8 520 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 90:cb3d968589d8 521 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 90:cb3d968589d8 522 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 90:cb3d968589d8 523 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
Kojto 90:cb3d968589d8 524 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
Kojto 90:cb3d968589d8 525 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
Kojto 90:cb3d968589d8 526 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
Kojto 90:cb3d968589d8 527 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
Kojto 90:cb3d968589d8 528 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
Kojto 90:cb3d968589d8 529 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
Kojto 90:cb3d968589d8 530 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
Kojto 90:cb3d968589d8 531 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
Kojto 90:cb3d968589d8 532 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
Kojto 90:cb3d968589d8 533 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
Kojto 90:cb3d968589d8 534 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
Kojto 90:cb3d968589d8 535 } RTC_TypeDef;
Kojto 90:cb3d968589d8 536
Kojto 90:cb3d968589d8 537 /**
Kojto 90:cb3d968589d8 538 * @brief Serial Peripheral Interface
Kojto 90:cb3d968589d8 539 */
Kojto 90:cb3d968589d8 540
Kojto 90:cb3d968589d8 541 typedef struct
Kojto 90:cb3d968589d8 542 {
Kojto 90:cb3d968589d8 543 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 90:cb3d968589d8 544 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 545 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 546 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 547 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 90:cb3d968589d8 548 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 90:cb3d968589d8 549 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 90:cb3d968589d8 550 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 551 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 552 } SPI_TypeDef;
Kojto 90:cb3d968589d8 553
Kojto 90:cb3d968589d8 554 /**
Kojto 90:cb3d968589d8 555 * @brief TIM
Kojto 90:cb3d968589d8 556 */
Kojto 90:cb3d968589d8 557 typedef struct
Kojto 90:cb3d968589d8 558 {
Kojto 90:cb3d968589d8 559 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 560 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 561 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 562 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 563 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 564 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 565 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 90:cb3d968589d8 566 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 90:cb3d968589d8 567 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 568 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 569 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 570 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 571 uint32_t RESERVED12; /*!< Reserved, 0x30 */
Kojto 90:cb3d968589d8 572 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 90:cb3d968589d8 573 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 90:cb3d968589d8 574 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 90:cb3d968589d8 575 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 90:cb3d968589d8 576 uint32_t RESERVED17; /*!< Reserved, 0x44 */
Kojto 90:cb3d968589d8 577 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 90:cb3d968589d8 578 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 90:cb3d968589d8 579 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 90:cb3d968589d8 580 } TIM_TypeDef;
Kojto 90:cb3d968589d8 581 /**
Kojto 90:cb3d968589d8 582 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 90:cb3d968589d8 583 */
Kojto 90:cb3d968589d8 584
Kojto 90:cb3d968589d8 585 typedef struct
Kojto 90:cb3d968589d8 586 {
Kojto 90:cb3d968589d8 587 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 588 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 589 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 590 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
Kojto 90:cb3d968589d8 591 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
Kojto 90:cb3d968589d8 592 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
Kojto 90:cb3d968589d8 593 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 594 } USART_TypeDef;
Kojto 90:cb3d968589d8 595
Kojto 90:cb3d968589d8 596 /**
Kojto 90:cb3d968589d8 597 * @brief Universal Serial Bus Full Speed Device
Kojto 90:cb3d968589d8 598 */
Kojto 90:cb3d968589d8 599
Kojto 90:cb3d968589d8 600 typedef struct
Kojto 90:cb3d968589d8 601 {
Kojto 90:cb3d968589d8 602 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 603 __IO uint16_t RESERVED0; /*!< Reserved */
Kojto 90:cb3d968589d8 604 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 605 __IO uint16_t RESERVED1; /*!< Reserved */
Kojto 90:cb3d968589d8 606 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 607 __IO uint16_t RESERVED2; /*!< Reserved */
Kojto 90:cb3d968589d8 608 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 609 __IO uint16_t RESERVED3; /*!< Reserved */
Kojto 90:cb3d968589d8 610 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 611 __IO uint16_t RESERVED4; /*!< Reserved */
Kojto 90:cb3d968589d8 612 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 613 __IO uint16_t RESERVED5; /*!< Reserved */
Kojto 90:cb3d968589d8 614 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 615 __IO uint16_t RESERVED6; /*!< Reserved */
Kojto 90:cb3d968589d8 616 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 617 __IO uint16_t RESERVED7[17]; /*!< Reserved */
Kojto 90:cb3d968589d8 618 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
Kojto 90:cb3d968589d8 619 __IO uint16_t RESERVED8; /*!< Reserved */
Kojto 90:cb3d968589d8 620 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
Kojto 90:cb3d968589d8 621 __IO uint16_t RESERVED9; /*!< Reserved */
Kojto 90:cb3d968589d8 622 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
Kojto 90:cb3d968589d8 623 __IO uint16_t RESERVEDA; /*!< Reserved */
Kojto 90:cb3d968589d8 624 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
Kojto 90:cb3d968589d8 625 __IO uint16_t RESERVEDB; /*!< Reserved */
Kojto 90:cb3d968589d8 626 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
Kojto 90:cb3d968589d8 627 __IO uint16_t RESERVEDC; /*!< Reserved */
Kojto 90:cb3d968589d8 628 } USB_TypeDef;
Kojto 90:cb3d968589d8 629
Kojto 90:cb3d968589d8 630 /**
Kojto 90:cb3d968589d8 631 * @brief Window WATCHDOG
Kojto 90:cb3d968589d8 632 */
Kojto 90:cb3d968589d8 633 typedef struct
Kojto 90:cb3d968589d8 634 {
Kojto 90:cb3d968589d8 635 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 636 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 637 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 638 } WWDG_TypeDef;
Kojto 90:cb3d968589d8 639
Kojto 90:cb3d968589d8 640 /**
Kojto 90:cb3d968589d8 641 * @brief Universal Serial Bus Full Speed Device
Kojto 90:cb3d968589d8 642 */
Kojto 90:cb3d968589d8 643 /**
Kojto 90:cb3d968589d8 644 * @}
Kojto 90:cb3d968589d8 645 */
Kojto 90:cb3d968589d8 646
Kojto 90:cb3d968589d8 647 /** @addtogroup Peripheral_memory_map
Kojto 90:cb3d968589d8 648 * @{
Kojto 90:cb3d968589d8 649 */
Kojto 90:cb3d968589d8 650
Kojto 122:f9eeca106725 651 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
Kojto 122:f9eeca106725 652 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */
Kojto 122:f9eeca106725 653 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
Kojto 122:f9eeca106725 654 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
Kojto 122:f9eeca106725 655 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
Kojto 122:f9eeca106725 656 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
Kojto 122:f9eeca106725 657 #define FLASH_BANK2_BASE ((uint32_t)0x08040000U) /*!< FLASH BANK2 base address in the alias region */
Kojto 122:f9eeca106725 658 #define FLASH_BANK1_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH BANK1 address */
Kojto 122:f9eeca106725 659 #define FLASH_BANK2_END ((uint32_t)0x0807FFFFU) /*!< Program end FLASH BANK2 address */
Kojto 122:f9eeca106725 660 #define FLASH_EEPROM_END ((uint32_t)0x08083FFFU) /*!< FLASH EEPROM end address (16KB) */
Kojto 90:cb3d968589d8 661
Kojto 90:cb3d968589d8 662 /*!< Peripheral memory map */
Kojto 90:cb3d968589d8 663 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 122:f9eeca106725 664 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto 122:f9eeca106725 665 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto 90:cb3d968589d8 666
Kojto 90:cb3d968589d8 667 /*!< APB1 peripherals */
Kojto 122:f9eeca106725 668 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
Kojto 122:f9eeca106725 669 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
Kojto 122:f9eeca106725 670 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
Kojto 122:f9eeca106725 671 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
Kojto 122:f9eeca106725 672 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
Kojto 122:f9eeca106725 673 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
Kojto 122:f9eeca106725 674 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400U)
Kojto 122:f9eeca106725 675 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
Kojto 122:f9eeca106725 676 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
Kojto 122:f9eeca106725 677 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
Kojto 122:f9eeca106725 678 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
Kojto 122:f9eeca106725 679 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
Kojto 122:f9eeca106725 680 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
Kojto 122:f9eeca106725 681 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
Kojto 122:f9eeca106725 682 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
Kojto 122:f9eeca106725 683 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
Kojto 122:f9eeca106725 684 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
Kojto 122:f9eeca106725 685 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
Kojto 90:cb3d968589d8 686
Kojto 90:cb3d968589d8 687 /* USB device FS */
Kojto 122:f9eeca106725 688 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
Kojto 122:f9eeca106725 689 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
Kojto 90:cb3d968589d8 690
Kojto 90:cb3d968589d8 691 /* USB device FS SRAM */
Kojto 122:f9eeca106725 692 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
Kojto 122:f9eeca106725 693 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
Kojto 122:f9eeca106725 694 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U)
Kojto 122:f9eeca106725 695 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U)
Kojto 122:f9eeca106725 696 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU)
Kojto 90:cb3d968589d8 697
Kojto 90:cb3d968589d8 698 /*!< APB2 peripherals */
Kojto 122:f9eeca106725 699 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
Kojto 122:f9eeca106725 700 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
Kojto 122:f9eeca106725 701 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U)
Kojto 122:f9eeca106725 702 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U)
Kojto 122:f9eeca106725 703 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U)
Kojto 122:f9eeca106725 704 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
Kojto 122:f9eeca106725 705 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700U)
Kojto 122:f9eeca106725 706 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
Kojto 122:f9eeca106725 707 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
Kojto 90:cb3d968589d8 708
Kojto 90:cb3d968589d8 709 /*!< AHB peripherals */
Kojto 122:f9eeca106725 710 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U)
Kojto 122:f9eeca106725 711 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U)
Kojto 122:f9eeca106725 712 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U)
Kojto 122:f9eeca106725 713 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U)
Kojto 122:f9eeca106725 714 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U)
Kojto 122:f9eeca106725 715 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U)
Kojto 122:f9eeca106725 716 #define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800U)
Kojto 122:f9eeca106725 717 #define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00U)
Kojto 122:f9eeca106725 718 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
Kojto 122:f9eeca106725 719 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800U)
Kojto 122:f9eeca106725 720 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */
Kojto 122:f9eeca106725 721 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
Kojto 122:f9eeca106725 722 #define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
Kojto 122:f9eeca106725 723 #define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
Kojto 122:f9eeca106725 724 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U)
Kojto 122:f9eeca106725 725 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
Kojto 122:f9eeca106725 726 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
Kojto 122:f9eeca106725 727 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
Kojto 122:f9eeca106725 728 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
Kojto 122:f9eeca106725 729 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
Kojto 122:f9eeca106725 730 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
Kojto 122:f9eeca106725 731 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
Kojto 122:f9eeca106725 732 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U)
Kojto 122:f9eeca106725 733 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U)
Kojto 122:f9eeca106725 734 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU)
Kojto 122:f9eeca106725 735 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U)
Kojto 122:f9eeca106725 736 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U)
Kojto 122:f9eeca106725 737 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U)
Kojto 122:f9eeca106725 738 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
Kojto 90:cb3d968589d8 739
Kojto 90:cb3d968589d8 740 /**
Kojto 90:cb3d968589d8 741 * @}
Kojto 90:cb3d968589d8 742 */
Kojto 90:cb3d968589d8 743
Kojto 90:cb3d968589d8 744 /** @addtogroup Peripheral_declaration
Kojto 90:cb3d968589d8 745 * @{
Kojto 90:cb3d968589d8 746 */
Kojto 90:cb3d968589d8 747
Kojto 90:cb3d968589d8 748 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 90:cb3d968589d8 749 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 90:cb3d968589d8 750 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 90:cb3d968589d8 751 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 90:cb3d968589d8 752 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 90:cb3d968589d8 753 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 90:cb3d968589d8 754 #define LCD ((LCD_TypeDef *) LCD_BASE)
Kojto 90:cb3d968589d8 755 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 90:cb3d968589d8 756 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 90:cb3d968589d8 757 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 90:cb3d968589d8 758 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 90:cb3d968589d8 759 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 90:cb3d968589d8 760 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 90:cb3d968589d8 761 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 90:cb3d968589d8 762 #define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto 90:cb3d968589d8 763 #define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto 90:cb3d968589d8 764 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 90:cb3d968589d8 765 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 90:cb3d968589d8 766 /* USB device FS */
Kojto 90:cb3d968589d8 767 #define USB ((USB_TypeDef *) USB_BASE)
Kojto 90:cb3d968589d8 768 /* USB device FS SRAM */
Kojto 90:cb3d968589d8 769 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 122:f9eeca106725 770
Kojto 122:f9eeca106725 771 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
Kojto 122:f9eeca106725 772 /* Legacy defines */
Kojto 122:f9eeca106725 773 #define DAC DAC1
Kojto 122:f9eeca106725 774
Kojto 90:cb3d968589d8 775 #define COMP ((COMP_TypeDef *) COMP_BASE)
Kojto 90:cb3d968589d8 776 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
Kojto 122:f9eeca106725 777 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U))
Kojto 90:cb3d968589d8 778 #define RI ((RI_TypeDef *) RI_BASE)
Kojto 90:cb3d968589d8 779 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
Kojto 90:cb3d968589d8 780 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
Kojto 122:f9eeca106725 781 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
Kojto 90:cb3d968589d8 782 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 90:cb3d968589d8 783 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 90:cb3d968589d8 784 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 90:cb3d968589d8 785 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 90:cb3d968589d8 786 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 122:f9eeca106725 787
Kojto 90:cb3d968589d8 788 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 122:f9eeca106725 789 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 122:f9eeca106725 790 /* Legacy defines */
Kojto 122:f9eeca106725 791 #define ADC ADC1_COMMON
Kojto 122:f9eeca106725 792
Kojto 90:cb3d968589d8 793 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 90:cb3d968589d8 794 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 90:cb3d968589d8 795 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 90:cb3d968589d8 796 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 90:cb3d968589d8 797 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 90:cb3d968589d8 798 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 90:cb3d968589d8 799 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 90:cb3d968589d8 800 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 90:cb3d968589d8 801 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 90:cb3d968589d8 802 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto 90:cb3d968589d8 803 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 90:cb3d968589d8 804 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 90:cb3d968589d8 805 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 90:cb3d968589d8 806 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 90:cb3d968589d8 807 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 90:cb3d968589d8 808 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 90:cb3d968589d8 809 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 90:cb3d968589d8 810 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 90:cb3d968589d8 811 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 90:cb3d968589d8 812 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 90:cb3d968589d8 813 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto 90:cb3d968589d8 814 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto 90:cb3d968589d8 815 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 90:cb3d968589d8 816 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
Kojto 90:cb3d968589d8 817 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
Kojto 90:cb3d968589d8 818 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
Kojto 90:cb3d968589d8 819 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
Kojto 90:cb3d968589d8 820 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
Kojto 90:cb3d968589d8 821 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 90:cb3d968589d8 822
Kojto 90:cb3d968589d8 823 /**
Kojto 90:cb3d968589d8 824 * @}
Kojto 90:cb3d968589d8 825 */
Kojto 90:cb3d968589d8 826
Kojto 90:cb3d968589d8 827 /** @addtogroup Exported_constants
Kojto 90:cb3d968589d8 828 * @{
Kojto 90:cb3d968589d8 829 */
Kojto 90:cb3d968589d8 830
Kojto 90:cb3d968589d8 831 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 90:cb3d968589d8 832 * @{
Kojto 90:cb3d968589d8 833 */
Kojto 90:cb3d968589d8 834
Kojto 90:cb3d968589d8 835 /******************************************************************************/
Kojto 90:cb3d968589d8 836 /* Peripheral Registers Bits Definition */
Kojto 90:cb3d968589d8 837 /******************************************************************************/
Kojto 90:cb3d968589d8 838 /******************************************************************************/
Kojto 90:cb3d968589d8 839 /* */
Kojto 90:cb3d968589d8 840 /* Analog to Digital Converter (ADC) */
Kojto 90:cb3d968589d8 841 /* */
Kojto 90:cb3d968589d8 842 /******************************************************************************/
Kojto 90:cb3d968589d8 843
Kojto 90:cb3d968589d8 844 /******************** Bit definition for ADC_SR register ********************/
Kojto 122:f9eeca106725 845 #define ADC_SR_AWD ((uint32_t)0x00000001U) /*!< ADC analog watchdog 1 flag */
Kojto 122:f9eeca106725 846 #define ADC_SR_EOCS ((uint32_t)0x00000002U) /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
Kojto 122:f9eeca106725 847 #define ADC_SR_JEOS ((uint32_t)0x00000004U) /*!< ADC group injected end of sequence conversions flag */
Kojto 122:f9eeca106725 848 #define ADC_SR_JSTRT ((uint32_t)0x00000008U) /*!< ADC group injected conversion start flag */
Kojto 122:f9eeca106725 849 #define ADC_SR_STRT ((uint32_t)0x00000010U) /*!< ADC group regular conversion start flag */
Kojto 122:f9eeca106725 850 #define ADC_SR_OVR ((uint32_t)0x00000020U) /*!< ADC group regular overrun flag */
Kojto 122:f9eeca106725 851 #define ADC_SR_ADONS ((uint32_t)0x00000040U) /*!< ADC ready flag */
Kojto 122:f9eeca106725 852 #define ADC_SR_RCNR ((uint32_t)0x00000100U) /*!< ADC group regular not ready flag */
Kojto 122:f9eeca106725 853 #define ADC_SR_JCNR ((uint32_t)0x00000200U) /*!< ADC group injected not ready flag */
Kojto 122:f9eeca106725 854
Kojto 122:f9eeca106725 855 /* Legacy defines */
Kojto 122:f9eeca106725 856 #define ADC_SR_EOC (ADC_SR_EOCS)
Kojto 122:f9eeca106725 857 #define ADC_SR_JEOC (ADC_SR_JEOS)
Kojto 90:cb3d968589d8 858
Kojto 90:cb3d968589d8 859 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 122:f9eeca106725 860 #define ADC_CR1_AWDCH ((uint32_t)0x0000001FU) /*!< ADC analog watchdog 1 monitored channel selection */
Kojto 122:f9eeca106725 861 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 862 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 863 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 864 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 865 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 866
Kojto 122:f9eeca106725 867 #define ADC_CR1_EOCSIE ((uint32_t)0x00000020U) /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
Kojto 122:f9eeca106725 868 #define ADC_CR1_AWDIE ((uint32_t)0x00000040U) /*!< ADC analog watchdog 1 interrupt */
Kojto 122:f9eeca106725 869 #define ADC_CR1_JEOSIE ((uint32_t)0x00000080U) /*!< ADC group injected end of sequence conversions interrupt */
Kojto 122:f9eeca106725 870 #define ADC_CR1_SCAN ((uint32_t)0x00000100U) /*!< ADC scan mode */
Kojto 122:f9eeca106725 871 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200U) /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
Kojto 122:f9eeca106725 872 #define ADC_CR1_JAUTO ((uint32_t)0x00000400U) /*!< ADC group injected automatic trigger mode */
Kojto 122:f9eeca106725 873 #define ADC_CR1_DISCEN ((uint32_t)0x00000800U) /*!< ADC group regular sequencer discontinuous mode */
Kojto 122:f9eeca106725 874 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000U) /*!< ADC group injected sequencer discontinuous mode */
Kojto 122:f9eeca106725 875
Kojto 122:f9eeca106725 876 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000U) /*!< ADC group regular sequencer discontinuous number of ranks */
Kojto 122:f9eeca106725 877 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 878 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 879 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 880
Kojto 122:f9eeca106725 881 #define ADC_CR1_PDD ((uint32_t)0x00010000U) /*!< ADC power down during auto delay phase */
Kojto 122:f9eeca106725 882 #define ADC_CR1_PDI ((uint32_t)0x00020000U) /*!< ADC power down during idle phase */
Kojto 122:f9eeca106725 883
Kojto 122:f9eeca106725 884 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000U) /*!< ADC analog watchdog 1 enable on scope ADC group injected */
Kojto 122:f9eeca106725 885 #define ADC_CR1_AWDEN ((uint32_t)0x00800000U) /*!< ADC analog watchdog 1 enable on scope ADC group regular */
Kojto 122:f9eeca106725 886
Kojto 122:f9eeca106725 887 #define ADC_CR1_RES ((uint32_t)0x03000000U) /*!< ADC resolution */
Kojto 122:f9eeca106725 888 #define ADC_CR1_RES_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 889 #define ADC_CR1_RES_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 890
Kojto 122:f9eeca106725 891 #define ADC_CR1_OVRIE ((uint32_t)0x04000000U) /*!< ADC group regular overrun interrupt */
Kojto 122:f9eeca106725 892
Kojto 122:f9eeca106725 893 /* Legacy defines */
Kojto 122:f9eeca106725 894 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)
Kojto 122:f9eeca106725 895 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
Kojto 122:f9eeca106725 896
Kojto 90:cb3d968589d8 897 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 122:f9eeca106725 898 #define ADC_CR2_ADON ((uint32_t)0x00000001U) /*!< ADC enable */
Kojto 122:f9eeca106725 899 #define ADC_CR2_CONT ((uint32_t)0x00000002U) /*!< ADC group regular continuous conversion mode */
Kojto 122:f9eeca106725 900 #define ADC_CR2_CFG ((uint32_t)0x00000004U) /*!< ADC channels bank selection */
Kojto 122:f9eeca106725 901
Kojto 122:f9eeca106725 902 #define ADC_CR2_DELS ((uint32_t)0x00000070U) /*!< ADC auto delay selection */
Kojto 122:f9eeca106725 903 #define ADC_CR2_DELS_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
Kojto 122:f9eeca106725 904 #define ADC_CR2_DELS_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
Kojto 122:f9eeca106725 905 #define ADC_CR2_DELS_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
Kojto 122:f9eeca106725 906
Kojto 122:f9eeca106725 907 #define ADC_CR2_DMA ((uint32_t)0x00000100U) /*!< ADC DMA transfer enable */
Kojto 122:f9eeca106725 908 #define ADC_CR2_DDS ((uint32_t)0x00000200U) /*!< ADC DMA transfer configuration */
Kojto 122:f9eeca106725 909 #define ADC_CR2_EOCS ((uint32_t)0x00000400U) /*!< ADC end of unitary or end of sequence conversions selection */
Kojto 122:f9eeca106725 910 #define ADC_CR2_ALIGN ((uint32_t)0x00000800U) /*!< ADC data alignement */
Kojto 122:f9eeca106725 911
Kojto 122:f9eeca106725 912 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000U) /*!< ADC group injected external trigger source */
Kojto 122:f9eeca106725 913 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 914 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 915 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 916 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 917
Kojto 122:f9eeca106725 918 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000U) /*!< ADC group injected external trigger polarity */
Kojto 122:f9eeca106725 919 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 920 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 921
Kojto 122:f9eeca106725 922 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000U) /*!< ADC group injected conversion start */
Kojto 122:f9eeca106725 923
Kojto 122:f9eeca106725 924 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000U) /*!< ADC group regular external trigger source */
Kojto 122:f9eeca106725 925 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 926 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 927 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 928 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 929
Kojto 122:f9eeca106725 930 #define ADC_CR2_EXTEN ((uint32_t)0x30000000U) /*!< ADC group regular external trigger polarity */
Kojto 122:f9eeca106725 931 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 932 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 933
Kojto 122:f9eeca106725 934 #define ADC_CR2_SWSTART ((uint32_t)0x40000000U) /*!< ADC group regular conversion start */
Kojto 90:cb3d968589d8 935
Kojto 90:cb3d968589d8 936 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 122:f9eeca106725 937 #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007U) /*!< ADC channel 20 sampling time selection */
Kojto 122:f9eeca106725 938 #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 939 #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 940 #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 941
Kojto 122:f9eeca106725 942 #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038U) /*!< ADC channel 21 sampling time selection */
Kojto 122:f9eeca106725 943 #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 122:f9eeca106725 944 #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 122:f9eeca106725 945 #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
Kojto 122:f9eeca106725 946
Kojto 122:f9eeca106725 947 #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0U) /*!< ADC channel 22 sampling time selection */
Kojto 122:f9eeca106725 948 #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
Kojto 122:f9eeca106725 949 #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
Kojto 122:f9eeca106725 950 #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
Kojto 122:f9eeca106725 951
Kojto 122:f9eeca106725 952 #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00U) /*!< ADC channel 23 sampling time selection */
Kojto 122:f9eeca106725 953 #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
Kojto 122:f9eeca106725 954 #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
Kojto 122:f9eeca106725 955 #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
Kojto 122:f9eeca106725 956
Kojto 122:f9eeca106725 957 #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000U) /*!< ADC channel 24 sampling time selection */
Kojto 122:f9eeca106725 958 #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 959 #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 960 #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 961
Kojto 122:f9eeca106725 962 #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000U) /*!< ADC channel 25 sampling time selection */
Kojto 122:f9eeca106725 963 #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 964 #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 965 #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 966
Kojto 122:f9eeca106725 967 #define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000U) /*!< ADC channel 26 sampling time selection */
Kojto 122:f9eeca106725 968 #define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 969 #define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 970 #define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 971
Kojto 122:f9eeca106725 972 #define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000U) /*!< ADC channel 27 sampling time selection */
Kojto 122:f9eeca106725 973 #define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 974 #define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 975 #define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 976
Kojto 122:f9eeca106725 977 #define ADC_SMPR1_SMP28 ((uint32_t)0x07000000U) /*!< ADC channel 28 sampling time selection */
Kojto 122:f9eeca106725 978 #define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 979 #define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 980 #define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 981
Kojto 122:f9eeca106725 982 #define ADC_SMPR1_SMP29 ((uint32_t)0x38000000U) /*!< ADC channel 29 sampling time selection */
Kojto 122:f9eeca106725 983 #define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 984 #define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 985 #define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 986
Kojto 90:cb3d968589d8 987 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 122:f9eeca106725 988 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007U) /*!< ADC channel 10 sampling time selection */
Kojto 122:f9eeca106725 989 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 990 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 991 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 992
Kojto 122:f9eeca106725 993 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038U) /*!< ADC channel 11 sampling time selection */
Kojto 122:f9eeca106725 994 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 122:f9eeca106725 995 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 122:f9eeca106725 996 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
Kojto 122:f9eeca106725 997
Kojto 122:f9eeca106725 998 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0U) /*!< ADC channel 12 sampling time selection */
Kojto 122:f9eeca106725 999 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1000 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1001 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1002
Kojto 122:f9eeca106725 1003 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00U) /*!< ADC channel 13 sampling time selection */
Kojto 122:f9eeca106725 1004 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1005 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1006 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1007
Kojto 122:f9eeca106725 1008 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000U) /*!< ADC channel 14 sampling time selection */
Kojto 122:f9eeca106725 1009 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1010 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1011 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1012
Kojto 122:f9eeca106725 1013 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */
Kojto 122:f9eeca106725 1014 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1015 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1016 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1017
Kojto 122:f9eeca106725 1018 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000U) /*!< ADC channel 16 sampling time selection */
Kojto 122:f9eeca106725 1019 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1020 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1021 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1022
Kojto 122:f9eeca106725 1023 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000U) /*!< ADC channel 17 sampling time selection */
Kojto 122:f9eeca106725 1024 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1025 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1026 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1027
Kojto 122:f9eeca106725 1028 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000U) /*!< ADC channel 18 sampling time selection */
Kojto 122:f9eeca106725 1029 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1030 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1031 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1032
Kojto 122:f9eeca106725 1033 #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000U) /*!< ADC channel 19 sampling time selection */
Kojto 122:f9eeca106725 1034 #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1035 #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1036 #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 1037
Kojto 90:cb3d968589d8 1038 /****************** Bit definition for ADC_SMPR3 register *******************/
Kojto 122:f9eeca106725 1039 #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007U) /*!< ADC channel 0 sampling time selection */
Kojto 122:f9eeca106725 1040 #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1041 #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1042 #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 1043
Kojto 122:f9eeca106725 1044 #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038U) /*!< ADC channel 1 sampling time selection */
Kojto 122:f9eeca106725 1045 #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1046 #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1047 #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1048
Kojto 122:f9eeca106725 1049 #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0U) /*!< ADC channel 2 sampling time selection */
Kojto 122:f9eeca106725 1050 #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1051 #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1052 #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1053
Kojto 122:f9eeca106725 1054 #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00U) /*!< ADC channel 3 sampling time selection */
Kojto 122:f9eeca106725 1055 #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1056 #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1057 #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1058
Kojto 122:f9eeca106725 1059 #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000U) /*!< ADC channel 4 sampling time selection */
Kojto 122:f9eeca106725 1060 #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1061 #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1062 #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1063
Kojto 122:f9eeca106725 1064 #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000U) /*!< ADC channel 5 sampling time selection */
Kojto 122:f9eeca106725 1065 #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1066 #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1067 #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1068
Kojto 122:f9eeca106725 1069 #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000U) /*!< ADC channel 6 sampling time selection */
Kojto 122:f9eeca106725 1070 #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1071 #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1072 #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1073
Kojto 122:f9eeca106725 1074 #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000U) /*!< ADC channel 7 sampling time selection */
Kojto 122:f9eeca106725 1075 #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1076 #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1077 #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1078
Kojto 122:f9eeca106725 1079 #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000U) /*!< ADC channel 8 sampling time selection */
Kojto 122:f9eeca106725 1080 #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1081 #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1082 #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1083
Kojto 122:f9eeca106725 1084 #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000U) /*!< ADC channel 9 sampling time selection */
Kojto 122:f9eeca106725 1085 #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1086 #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1087 #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 1088
Kojto 90:cb3d968589d8 1089 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 122:f9eeca106725 1090 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 1 offset value */
Kojto 90:cb3d968589d8 1091
Kojto 90:cb3d968589d8 1092 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 122:f9eeca106725 1093 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 2 offset value */
Kojto 90:cb3d968589d8 1094
Kojto 90:cb3d968589d8 1095 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 122:f9eeca106725 1096 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 3 offset value */
Kojto 90:cb3d968589d8 1097
Kojto 90:cb3d968589d8 1098 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 122:f9eeca106725 1099 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFFU) /*!< ADC group injected sequencer rank 4 offset value */
Kojto 90:cb3d968589d8 1100
Kojto 90:cb3d968589d8 1101 /******************* Bit definition for ADC_HTR register ********************/
Kojto 122:f9eeca106725 1102 #define ADC_HTR_HT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold high */
Kojto 90:cb3d968589d8 1103
Kojto 90:cb3d968589d8 1104 /******************* Bit definition for ADC_LTR register ********************/
Kojto 122:f9eeca106725 1105 #define ADC_LTR_LT ((uint32_t)0x00000FFFU) /*!< ADC analog watchdog 1 threshold low */
Kojto 90:cb3d968589d8 1106
Kojto 90:cb3d968589d8 1107 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 122:f9eeca106725 1108 #define ADC_SQR1_L ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer scan length */
Kojto 122:f9eeca106725 1109 #define ADC_SQR1_L_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1110 #define ADC_SQR1_L_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1111 #define ADC_SQR1_L_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1112 #define ADC_SQR1_L_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1113 #define ADC_SQR1_L_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1114
Kojto 122:f9eeca106725 1115 #define ADC_SQR1_SQ28 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 28 */
Kojto 122:f9eeca106725 1116 #define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1117 #define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1118 #define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1119 #define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1120 #define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1121
Kojto 122:f9eeca106725 1122 #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 27 */
Kojto 122:f9eeca106725 1123 #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1124 #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1125 #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1126 #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1127 #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1128
Kojto 122:f9eeca106725 1129 #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 26 */
Kojto 122:f9eeca106725 1130 #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1131 #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1132 #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1133 #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1134 #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1135
Kojto 122:f9eeca106725 1136 #define ADC_SQR1_SQ25 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 25 */
Kojto 122:f9eeca106725 1137 #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1138 #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1139 #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1140 #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1141 #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 90:cb3d968589d8 1142
Kojto 90:cb3d968589d8 1143 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 122:f9eeca106725 1144 #define ADC_SQR2_SQ19 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 19 */
Kojto 122:f9eeca106725 1145 #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1146 #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1147 #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1148 #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1149 #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1150
Kojto 122:f9eeca106725 1151 #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 20 */
Kojto 122:f9eeca106725 1152 #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1153 #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1154 #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1155 #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1156 #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1157
Kojto 122:f9eeca106725 1158 #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 21 */
Kojto 122:f9eeca106725 1159 #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1160 #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1161 #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1162 #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1163 #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1164
Kojto 122:f9eeca106725 1165 #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 22 */
Kojto 122:f9eeca106725 1166 #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1167 #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1168 #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1169 #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1170 #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1171
Kojto 122:f9eeca106725 1172 #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 23 */
Kojto 122:f9eeca106725 1173 #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1174 #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1175 #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1176 #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1177 #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1178
Kojto 122:f9eeca106725 1179 #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 24 */
Kojto 122:f9eeca106725 1180 #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1181 #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1182 #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1183 #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1184 #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000U) /*!< Bit 4 */
Kojto 90:cb3d968589d8 1185
Kojto 90:cb3d968589d8 1186 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 122:f9eeca106725 1187 #define ADC_SQR3_SQ13 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 13 */
Kojto 122:f9eeca106725 1188 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1189 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1190 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1191 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1192 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1193
Kojto 122:f9eeca106725 1194 #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 14 */
Kojto 122:f9eeca106725 1195 #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1196 #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1197 #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1198 #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1199 #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1200
Kojto 122:f9eeca106725 1201 #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 15 */
Kojto 122:f9eeca106725 1202 #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1203 #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1204 #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1205 #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1206 #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1207
Kojto 122:f9eeca106725 1208 #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 16 */
Kojto 122:f9eeca106725 1209 #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1210 #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1211 #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1212 #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1213 #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1214
Kojto 122:f9eeca106725 1215 #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 17 */
Kojto 122:f9eeca106725 1216 #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1217 #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1218 #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1219 #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1220 #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1221
Kojto 122:f9eeca106725 1222 #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 18 */
Kojto 122:f9eeca106725 1223 #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1224 #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1225 #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1226 #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1227 #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000U) /*!< Bit 4 */
Kojto 90:cb3d968589d8 1228
Kojto 90:cb3d968589d8 1229 /******************* Bit definition for ADC_SQR4 register *******************/
Kojto 122:f9eeca106725 1230 #define ADC_SQR4_SQ7 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 7 */
Kojto 122:f9eeca106725 1231 #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1232 #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1233 #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1234 #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1235 #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1236
Kojto 122:f9eeca106725 1237 #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 8 */
Kojto 122:f9eeca106725 1238 #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1239 #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1240 #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1241 #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1242 #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1243
Kojto 122:f9eeca106725 1244 #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 9 */
Kojto 122:f9eeca106725 1245 #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1246 #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1247 #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1248 #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1249 #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1250
Kojto 122:f9eeca106725 1251 #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 10 */
Kojto 122:f9eeca106725 1252 #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1253 #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1254 #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1255 #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1256 #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1257
Kojto 122:f9eeca106725 1258 #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 11 */
Kojto 122:f9eeca106725 1259 #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1260 #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1261 #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1262 #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1263 #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1264
Kojto 122:f9eeca106725 1265 #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 12 */
Kojto 122:f9eeca106725 1266 #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1267 #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1268 #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1269 #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1270 #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000U) /*!< Bit 4 */
Kojto 90:cb3d968589d8 1271
Kojto 90:cb3d968589d8 1272 /******************* Bit definition for ADC_SQR5 register *******************/
Kojto 122:f9eeca106725 1273 #define ADC_SQR5_SQ1 ((uint32_t)0x0000001FU) /*!< ADC group regular sequencer rank 1 */
Kojto 122:f9eeca106725 1274 #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1275 #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1276 #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1277 #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1278 #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1279
Kojto 122:f9eeca106725 1280 #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0U) /*!< ADC group regular sequencer rank 2 */
Kojto 122:f9eeca106725 1281 #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1282 #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1283 #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1284 #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1285 #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1286
Kojto 122:f9eeca106725 1287 #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00U) /*!< ADC group regular sequencer rank 3 */
Kojto 122:f9eeca106725 1288 #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1289 #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1290 #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1291 #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1292 #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1293
Kojto 122:f9eeca106725 1294 #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000U) /*!< ADC group regular sequencer rank 4 */
Kojto 122:f9eeca106725 1295 #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1296 #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1297 #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1298 #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1299 #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1300
Kojto 122:f9eeca106725 1301 #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000U) /*!< ADC group regular sequencer rank 5 */
Kojto 122:f9eeca106725 1302 #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1303 #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1304 #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1305 #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1306 #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1307
Kojto 122:f9eeca106725 1308 #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000U) /*!< ADC group regular sequencer rank 6 */
Kojto 122:f9eeca106725 1309 #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1310 #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1311 #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1312 #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1313 #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000U) /*!< Bit 4 */
Kojto 90:cb3d968589d8 1314
Kojto 90:cb3d968589d8 1315
Kojto 90:cb3d968589d8 1316 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 122:f9eeca106725 1317 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001FU) /*!< ADC group injected sequencer rank 1 */
Kojto 122:f9eeca106725 1318 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1319 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1320 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1321 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1322 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1323
Kojto 122:f9eeca106725 1324 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0U) /*!< ADC group injected sequencer rank 2 */
Kojto 122:f9eeca106725 1325 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1326 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1327 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1328 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1329 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1330
Kojto 122:f9eeca106725 1331 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00U) /*!< ADC group injected sequencer rank 3 */
Kojto 122:f9eeca106725 1332 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1333 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1334 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1335 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1336 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1337
Kojto 122:f9eeca106725 1338 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000U) /*!< ADC group injected sequencer rank 4 */
Kojto 122:f9eeca106725 1339 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1340 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1341 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1342 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1343 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1344
Kojto 122:f9eeca106725 1345 #define ADC_JSQR_JL ((uint32_t)0x00300000U) /*!< ADC group injected sequencer scan length */
Kojto 122:f9eeca106725 1346 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1347 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
Kojto 90:cb3d968589d8 1348
Kojto 90:cb3d968589d8 1349 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 122:f9eeca106725 1350 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 1 conversion data */
Kojto 90:cb3d968589d8 1351
Kojto 90:cb3d968589d8 1352 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 122:f9eeca106725 1353 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 2 conversion data */
Kojto 90:cb3d968589d8 1354
Kojto 90:cb3d968589d8 1355 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 122:f9eeca106725 1356 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 3 conversion data */
Kojto 90:cb3d968589d8 1357
Kojto 90:cb3d968589d8 1358 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 122:f9eeca106725 1359 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFFU) /*!< ADC group injected sequencer rank 4 conversion data */
Kojto 90:cb3d968589d8 1360
Kojto 90:cb3d968589d8 1361 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 1362 #define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< ADC group regular conversion data */
Kojto 90:cb3d968589d8 1363
Kojto 90:cb3d968589d8 1364 /****************** Bit definition for ADC_SMPR0 register *******************/
Kojto 122:f9eeca106725 1365 #define ADC_SMPR0_SMP30 ((uint32_t)0x00000007U) /*!< ADC channel 30 sampling time selection */
Kojto 122:f9eeca106725 1366 #define ADC_SMPR0_SMP30_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1367 #define ADC_SMPR0_SMP30_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1368 #define ADC_SMPR0_SMP30_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 1369
Kojto 122:f9eeca106725 1370 #define ADC_SMPR0_SMP31 ((uint32_t)0x00000038U) /*!< ADC channel 31 sampling time selection */
Kojto 122:f9eeca106725 1371 #define ADC_SMPR0_SMP31_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1372 #define ADC_SMPR0_SMP31_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1373 #define ADC_SMPR0_SMP31_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 1374
Kojto 90:cb3d968589d8 1375 /******************* Bit definition for ADC_CSR register ********************/
Kojto 122:f9eeca106725 1376 #define ADC_CSR_AWD1 ((uint32_t)0x00000001U) /*!< ADC multimode master analog watchdog 1 flag */
Kojto 122:f9eeca106725 1377 #define ADC_CSR_EOCS1 ((uint32_t)0x00000002U) /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
Kojto 122:f9eeca106725 1378 #define ADC_CSR_JEOS1 ((uint32_t)0x00000004U) /*!< ADC multimode master group injected end of sequence conversions flag */
Kojto 122:f9eeca106725 1379 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008U) /*!< ADC multimode master group injected conversion start flag */
Kojto 122:f9eeca106725 1380 #define ADC_CSR_STRT1 ((uint32_t)0x00000010U) /*!< ADC multimode master group regular conversion start flag */
Kojto 122:f9eeca106725 1381 #define ADC_CSR_OVR1 ((uint32_t)0x00000020U) /*!< ADC multimode master group regular overrun flag */
Kojto 122:f9eeca106725 1382 #define ADC_CSR_ADONS1 ((uint32_t)0x00000040U) /*!< ADC multimode master ready flag */
Kojto 122:f9eeca106725 1383
Kojto 122:f9eeca106725 1384 /* Legacy defines */
Kojto 122:f9eeca106725 1385 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1)
Kojto 122:f9eeca106725 1386 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)
Kojto 90:cb3d968589d8 1387
Kojto 90:cb3d968589d8 1388 /******************* Bit definition for ADC_CCR register ********************/
Kojto 122:f9eeca106725 1389 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000U) /*!< ADC clock source asynchronous prescaler */
Kojto 122:f9eeca106725 1390 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1391 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1392 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000U) /*!< ADC internal path to VrefInt and temperature sensor enable */
Kojto 90:cb3d968589d8 1393
Kojto 90:cb3d968589d8 1394 /******************************************************************************/
Kojto 90:cb3d968589d8 1395 /* */
Kojto 90:cb3d968589d8 1396 /* Analog Comparators (COMP) */
Kojto 90:cb3d968589d8 1397 /* */
Kojto 90:cb3d968589d8 1398 /******************************************************************************/
Kojto 90:cb3d968589d8 1399
Kojto 90:cb3d968589d8 1400 /****************** Bit definition for COMP_CSR register ********************/
Kojto 122:f9eeca106725 1401 #define COMP_CSR_10KPU ((uint32_t)0x00000001U) /*!< 10K pull-up resistor */
Kojto 122:f9eeca106725 1402 #define COMP_CSR_400KPU ((uint32_t)0x00000002U) /*!< 400K pull-up resistor */
Kojto 122:f9eeca106725 1403 #define COMP_CSR_10KPD ((uint32_t)0x00000004U) /*!< 10K pull-down resistor */
Kojto 122:f9eeca106725 1404 #define COMP_CSR_400KPD ((uint32_t)0x00000008U) /*!< 400K pull-down resistor */
Kojto 122:f9eeca106725 1405 #define COMP_CSR_CMP1EN ((uint32_t)0x00000010U) /*!< Comparator 1 enable */
Kojto 122:f9eeca106725 1406 #define COMP_CSR_SW1 ((uint32_t)0x00000020U) /*!< SW1 analog switch enable */
Kojto 122:f9eeca106725 1407 #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080U) /*!< Comparator 1 output */
Kojto 122:f9eeca106725 1408
Kojto 122:f9eeca106725 1409 #define COMP_CSR_SPEED ((uint32_t)0x00001000U) /*!< Comparator 2 speed */
Kojto 122:f9eeca106725 1410 #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000U) /*!< Comparator 2 ouput */
Kojto 122:f9eeca106725 1411 #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000U) /*!< Comparator Vref Enable */
Kojto 122:f9eeca106725 1412 #define COMP_CSR_WNDWE ((uint32_t)0x00020000U) /*!< Window mode enable */
Kojto 122:f9eeca106725 1413 #define COMP_CSR_INSEL ((uint32_t)0x001C0000U) /*!< INSEL[2:0] Inversion input Selection */
Kojto 122:f9eeca106725 1414 #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1415 #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1416 #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1417 #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000U) /*!< OUTSEL[2:0] comparator 2 output redirection */
Kojto 122:f9eeca106725 1418 #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1419 #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1420 #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1421
Kojto 122:f9eeca106725 1422 #define COMP_CSR_FCH3 ((uint32_t)0x04000000U) /*!< Bit 26 */
Kojto 122:f9eeca106725 1423 #define COMP_CSR_FCH8 ((uint32_t)0x08000000U) /*!< Bit 27 */
Kojto 122:f9eeca106725 1424 #define COMP_CSR_RCH13 ((uint32_t)0x10000000U) /*!< Bit 28 */
Kojto 122:f9eeca106725 1425
Kojto 122:f9eeca106725 1426 #define COMP_CSR_CAIE ((uint32_t)0x20000000U) /*!< Bit 29 */
Kojto 122:f9eeca106725 1427 #define COMP_CSR_CAIF ((uint32_t)0x40000000U) /*!< Bit 30 */
Kojto 122:f9eeca106725 1428 #define COMP_CSR_TSUSP ((uint32_t)0x80000000U) /*!< Bit 31 */
Kojto 90:cb3d968589d8 1429
Kojto 90:cb3d968589d8 1430 /******************************************************************************/
Kojto 90:cb3d968589d8 1431 /* */
Kojto 90:cb3d968589d8 1432 /* Operational Amplifier (OPAMP) */
Kojto 90:cb3d968589d8 1433 /* */
Kojto 90:cb3d968589d8 1434 /******************************************************************************/
Kojto 90:cb3d968589d8 1435 /******************* Bit definition for OPAMP_CSR register ******************/
Kojto 122:f9eeca106725 1436 #define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001U) /*!< OPAMP1 disable */
Kojto 122:f9eeca106725 1437 #define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002U) /*!< Switch 3 for OPAMP1 Enable */
Kojto 122:f9eeca106725 1438 #define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004U) /*!< Switch 4 for OPAMP1 Enable */
Kojto 122:f9eeca106725 1439 #define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008U) /*!< Switch 5 for OPAMP1 Enable */
Kojto 122:f9eeca106725 1440 #define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010U) /*!< Switch 6 for OPAMP1 Enable */
Kojto 122:f9eeca106725 1441 #define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020U) /*!< OPAMP1 Offset calibration for P differential pair */
Kojto 122:f9eeca106725 1442 #define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040U) /*!< OPAMP1 Offset calibration for N differential pair */
Kojto 122:f9eeca106725 1443 #define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080U) /*!< OPAMP1 Low power enable */
Kojto 122:f9eeca106725 1444 #define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100U) /*!< OPAMP2 disable */
Kojto 122:f9eeca106725 1445 #define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200U) /*!< Switch 3 for OPAMP2 Enable */
Kojto 122:f9eeca106725 1446 #define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400U) /*!< Switch 4 for OPAMP2 Enable */
Kojto 122:f9eeca106725 1447 #define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800U) /*!< Switch 5 for OPAMP2 Enable */
Kojto 122:f9eeca106725 1448 #define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000U) /*!< Switch 6 for OPAMP2 Enable */
Kojto 122:f9eeca106725 1449 #define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000U) /*!< OPAMP2 Offset calibration for P differential pair */
Kojto 122:f9eeca106725 1450 #define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000U) /*!< OPAMP2 Offset calibration for N differential pair */
Kojto 122:f9eeca106725 1451 #define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000U) /*!< OPAMP2 Low power enable */
Kojto 122:f9eeca106725 1452 #define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000U) /*!< Switch ANA Enable for OPAMP1 */
Kojto 122:f9eeca106725 1453 #define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000U) /*!< Switch ANA Enable for OPAMP2 */
Kojto 122:f9eeca106725 1454 #define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000U) /*!< Switch 7 for OPAMP2 Enable */
Kojto 122:f9eeca106725 1455 #define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000U) /*!< Power range selection */
Kojto 122:f9eeca106725 1456 #define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000U) /*!< OPAMP1 calibration output */
Kojto 122:f9eeca106725 1457 #define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000U) /*!< OPAMP2 calibration output */
Kojto 90:cb3d968589d8 1458
Kojto 90:cb3d968589d8 1459 /******************* Bit definition for OPAMP_OTR register ******************/
Kojto 122:f9eeca106725 1460 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
Kojto 122:f9eeca106725 1461 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
Kojto 122:f9eeca106725 1462 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
Kojto 122:f9eeca106725 1463 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
Kojto 122:f9eeca106725 1464 #define OPAMP_OTR_OT_USER ((uint32_t)0x80000000U) /*!< Switch to OPAMP offset user trimmed values */
Kojto 90:cb3d968589d8 1465
Kojto 90:cb3d968589d8 1466 /******************* Bit definition for OPAMP_LPOTR register ****************/
Kojto 122:f9eeca106725 1467 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001FU) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
Kojto 122:f9eeca106725 1468 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0U) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
Kojto 122:f9eeca106725 1469 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00U) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
Kojto 122:f9eeca106725 1470 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000U) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
Kojto 90:cb3d968589d8 1471
Kojto 90:cb3d968589d8 1472 /******************************************************************************/
Kojto 90:cb3d968589d8 1473 /* */
Kojto 90:cb3d968589d8 1474 /* CRC calculation unit (CRC) */
Kojto 90:cb3d968589d8 1475 /* */
Kojto 90:cb3d968589d8 1476 /******************************************************************************/
Kojto 90:cb3d968589d8 1477
Kojto 90:cb3d968589d8 1478 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 1479 #define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
Kojto 90:cb3d968589d8 1480
Kojto 90:cb3d968589d8 1481 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 1482 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 90:cb3d968589d8 1483
Kojto 90:cb3d968589d8 1484 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 1485 #define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET bit */
Kojto 90:cb3d968589d8 1486
Kojto 90:cb3d968589d8 1487 /******************************************************************************/
Kojto 90:cb3d968589d8 1488 /* */
Kojto 90:cb3d968589d8 1489 /* Digital to Analog Converter (DAC) */
Kojto 90:cb3d968589d8 1490 /* */
Kojto 90:cb3d968589d8 1491 /******************************************************************************/
Kojto 90:cb3d968589d8 1492
Kojto 90:cb3d968589d8 1493 /******************** Bit definition for DAC_CR register ********************/
Kojto 122:f9eeca106725 1494 #define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!<DAC channel1 enable */
Kojto 122:f9eeca106725 1495 #define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!<DAC channel1 output buffer disable */
Kojto 122:f9eeca106725 1496 #define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!<DAC channel1 Trigger enable */
Kojto 122:f9eeca106725 1497
Kojto 122:f9eeca106725 1498 #define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 122:f9eeca106725 1499 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
Kojto 122:f9eeca106725 1500 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
Kojto 122:f9eeca106725 1501 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!<Bit 2 */
Kojto 122:f9eeca106725 1502
Kojto 122:f9eeca106725 1503 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 1504 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!<Bit 0 */
Kojto 122:f9eeca106725 1505 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!<Bit 1 */
Kojto 122:f9eeca106725 1506
Kojto 122:f9eeca106725 1507 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 1508 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 122:f9eeca106725 1509 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 122:f9eeca106725 1510 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
Kojto 122:f9eeca106725 1511 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
Kojto 122:f9eeca106725 1512
Kojto 122:f9eeca106725 1513 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!<DAC channel1 DMA enable */
Kojto 122:f9eeca106725 1514 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!<DAC channel1 DMA Interrupt enable */
Kojto 122:f9eeca106725 1515 #define DAC_CR_EN2 ((uint32_t)0x00010000U) /*!<DAC channel2 enable */
Kojto 122:f9eeca106725 1516 #define DAC_CR_BOFF2 ((uint32_t)0x00020000U) /*!<DAC channel2 output buffer disable */
Kojto 122:f9eeca106725 1517 #define DAC_CR_TEN2 ((uint32_t)0x00040000U) /*!<DAC channel2 Trigger enable */
Kojto 122:f9eeca106725 1518
Kojto 122:f9eeca106725 1519 #define DAC_CR_TSEL2 ((uint32_t)0x00380000U) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 122:f9eeca106725 1520 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 1521 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 1522 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 1523
Kojto 122:f9eeca106725 1524 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000U) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 1525 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 1526 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 1527
Kojto 122:f9eeca106725 1528 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000U) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 1529 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 1530 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 1531 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 1532 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
Kojto 122:f9eeca106725 1533
Kojto 122:f9eeca106725 1534 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000U) /*!<DAC channel2 DMA enabled */
Kojto 122:f9eeca106725 1535 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun interrupt enable */
Kojto 90:cb3d968589d8 1536 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 122:f9eeca106725 1537 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!<DAC channel1 software trigger */
Kojto 122:f9eeca106725 1538 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002U) /*!<DAC channel2 software trigger */
Kojto 90:cb3d968589d8 1539
Kojto 90:cb3d968589d8 1540 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 122:f9eeca106725 1541 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
Kojto 90:cb3d968589d8 1542
Kojto 90:cb3d968589d8 1543 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 122:f9eeca106725 1544 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
Kojto 90:cb3d968589d8 1545
Kojto 90:cb3d968589d8 1546 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 122:f9eeca106725 1547 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
Kojto 90:cb3d968589d8 1548
Kojto 90:cb3d968589d8 1549 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 122:f9eeca106725 1550 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFFU) /*!<DAC channel2 12-bit Right aligned data */
Kojto 90:cb3d968589d8 1551
Kojto 90:cb3d968589d8 1552 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 122:f9eeca106725 1553 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel2 12-bit Left aligned data */
Kojto 90:cb3d968589d8 1554
Kojto 90:cb3d968589d8 1555 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 122:f9eeca106725 1556 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FFU) /*!<DAC channel2 8-bit Right aligned data */
Kojto 90:cb3d968589d8 1557
Kojto 90:cb3d968589d8 1558 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 122:f9eeca106725 1559 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFFU) /*!<DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 1560 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000U) /*!<DAC channel2 12-bit Right aligned data */
Kojto 90:cb3d968589d8 1561
Kojto 90:cb3d968589d8 1562 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 122:f9eeca106725 1563 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0U) /*!<DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 1564 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000U) /*!<DAC channel2 12-bit Left aligned data */
Kojto 90:cb3d968589d8 1565
Kojto 90:cb3d968589d8 1566 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 122:f9eeca106725 1567 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FFU) /*!<DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 1568 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00U) /*!<DAC channel2 8-bit Right aligned data */
Kojto 90:cb3d968589d8 1569
Kojto 90:cb3d968589d8 1570 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 122:f9eeca106725 1571 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFFU) /*!<DAC channel1 data output */
Kojto 90:cb3d968589d8 1572
Kojto 90:cb3d968589d8 1573 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 122:f9eeca106725 1574 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!<DAC channel2 data output */
Kojto 90:cb3d968589d8 1575
Kojto 90:cb3d968589d8 1576 /******************** Bit definition for DAC_SR register ********************/
Kojto 122:f9eeca106725 1577 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!<DAC channel1 DMA underrun flag */
Kojto 122:f9eeca106725 1578 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000U) /*!<DAC channel2 DMA underrun flag */
Kojto 90:cb3d968589d8 1579
Kojto 90:cb3d968589d8 1580 /******************************************************************************/
Kojto 90:cb3d968589d8 1581 /* */
Kojto 90:cb3d968589d8 1582 /* Debug MCU (DBGMCU) */
Kojto 90:cb3d968589d8 1583 /* */
Kojto 90:cb3d968589d8 1584 /******************************************************************************/
Kojto 90:cb3d968589d8 1585
Kojto 90:cb3d968589d8 1586 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 122:f9eeca106725 1587 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */
Kojto 122:f9eeca106725 1588
Kojto 122:f9eeca106725 1589 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 122:f9eeca106725 1590 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1591 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1592 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 1593 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 1594 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 1595 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
Kojto 122:f9eeca106725 1596 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
Kojto 122:f9eeca106725 1597 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
Kojto 122:f9eeca106725 1598 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
Kojto 122:f9eeca106725 1599 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
Kojto 122:f9eeca106725 1600 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
Kojto 122:f9eeca106725 1601 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
Kojto 122:f9eeca106725 1602 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 1603 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 1604 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 1605 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 1606
Kojto 90:cb3d968589d8 1607 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 122:f9eeca106725 1608 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */
Kojto 122:f9eeca106725 1609 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */
Kojto 122:f9eeca106725 1610 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */
Kojto 122:f9eeca106725 1611 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020U) /*!< Trace Pin Assignment Control */
Kojto 122:f9eeca106725 1612
Kojto 122:f9eeca106725 1613 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0U) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
Kojto 122:f9eeca106725 1614 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1615 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
Kojto 90:cb3d968589d8 1616
Kojto 90:cb3d968589d8 1617 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Kojto 90:cb3d968589d8 1618
Kojto 122:f9eeca106725 1619 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */
Kojto 122:f9eeca106725 1620 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002U) /*!< TIM3 counter stopped when core is halted */
Kojto 122:f9eeca106725 1621 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004U) /*!< TIM4 counter stopped when core is halted */
Kojto 122:f9eeca106725 1622 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008U) /*!< TIM5 counter stopped when core is halted */
Kojto 122:f9eeca106725 1623 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */
Kojto 122:f9eeca106725 1624 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020U) /*!< TIM7 counter stopped when core is halted */
Kojto 122:f9eeca106725 1625 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Counter stopped when Core is halted */
Kojto 122:f9eeca106725 1626 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 122:f9eeca106725 1627 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 122:f9eeca106725 1628 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000U) /*!< SMBUS timeout mode stopped when Core is halted */
Kojto 122:f9eeca106725 1629 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000U) /*!< SMBUS timeout mode stopped when Core is halted */
Kojto 90:cb3d968589d8 1630
Kojto 90:cb3d968589d8 1631 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Kojto 90:cb3d968589d8 1632
Kojto 122:f9eeca106725 1633 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004U) /*!< TIM9 counter stopped when core is halted */
Kojto 122:f9eeca106725 1634 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008U) /*!< TIM10 counter stopped when core is halted */
Kojto 122:f9eeca106725 1635 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010U) /*!< TIM11 counter stopped when core is halted */
Kojto 90:cb3d968589d8 1636
Kojto 90:cb3d968589d8 1637 /******************************************************************************/
Kojto 90:cb3d968589d8 1638 /* */
Kojto 90:cb3d968589d8 1639 /* DMA Controller (DMA) */
Kojto 90:cb3d968589d8 1640 /* */
Kojto 90:cb3d968589d8 1641 /******************************************************************************/
Kojto 90:cb3d968589d8 1642
Kojto 90:cb3d968589d8 1643 /******************* Bit definition for DMA_ISR register ********************/
Kojto 122:f9eeca106725 1644 #define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
Kojto 122:f9eeca106725 1645 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
Kojto 122:f9eeca106725 1646 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
Kojto 122:f9eeca106725 1647 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
Kojto 122:f9eeca106725 1648 #define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
Kojto 122:f9eeca106725 1649 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
Kojto 122:f9eeca106725 1650 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
Kojto 122:f9eeca106725 1651 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
Kojto 122:f9eeca106725 1652 #define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
Kojto 122:f9eeca106725 1653 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
Kojto 122:f9eeca106725 1654 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
Kojto 122:f9eeca106725 1655 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
Kojto 122:f9eeca106725 1656 #define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
Kojto 122:f9eeca106725 1657 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
Kojto 122:f9eeca106725 1658 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
Kojto 122:f9eeca106725 1659 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
Kojto 122:f9eeca106725 1660 #define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
Kojto 122:f9eeca106725 1661 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
Kojto 122:f9eeca106725 1662 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
Kojto 122:f9eeca106725 1663 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
Kojto 122:f9eeca106725 1664 #define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
Kojto 122:f9eeca106725 1665 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
Kojto 122:f9eeca106725 1666 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
Kojto 122:f9eeca106725 1667 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
Kojto 122:f9eeca106725 1668 #define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
Kojto 122:f9eeca106725 1669 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
Kojto 122:f9eeca106725 1670 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
Kojto 122:f9eeca106725 1671 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
Kojto 90:cb3d968589d8 1672
Kojto 90:cb3d968589d8 1673 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 122:f9eeca106725 1674 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */
Kojto 122:f9eeca106725 1675 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
Kojto 122:f9eeca106725 1676 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
Kojto 122:f9eeca106725 1677 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
Kojto 122:f9eeca106725 1678 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
Kojto 122:f9eeca106725 1679 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
Kojto 122:f9eeca106725 1680 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
Kojto 122:f9eeca106725 1681 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
Kojto 122:f9eeca106725 1682 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
Kojto 122:f9eeca106725 1683 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
Kojto 122:f9eeca106725 1684 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
Kojto 122:f9eeca106725 1685 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
Kojto 122:f9eeca106725 1686 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
Kojto 122:f9eeca106725 1687 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
Kojto 122:f9eeca106725 1688 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
Kojto 122:f9eeca106725 1689 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
Kojto 122:f9eeca106725 1690 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
Kojto 122:f9eeca106725 1691 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
Kojto 122:f9eeca106725 1692 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
Kojto 122:f9eeca106725 1693 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
Kojto 122:f9eeca106725 1694 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
Kojto 122:f9eeca106725 1695 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
Kojto 122:f9eeca106725 1696 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
Kojto 122:f9eeca106725 1697 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
Kojto 122:f9eeca106725 1698 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
Kojto 122:f9eeca106725 1699 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
Kojto 122:f9eeca106725 1700 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
Kojto 122:f9eeca106725 1701 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
Kojto 90:cb3d968589d8 1702
Kojto 90:cb3d968589d8 1703 /******************* Bit definition for DMA_CCR register *******************/
Kojto 122:f9eeca106725 1704 #define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable*/
Kojto 122:f9eeca106725 1705 #define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 1706 #define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
Kojto 122:f9eeca106725 1707 #define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
Kojto 122:f9eeca106725 1708 #define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
Kojto 122:f9eeca106725 1709 #define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
Kojto 122:f9eeca106725 1710 #define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
Kojto 122:f9eeca106725 1711 #define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
Kojto 122:f9eeca106725 1712
Kojto 122:f9eeca106725 1713 #define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 122:f9eeca106725 1714 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1715 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1716
Kojto 122:f9eeca106725 1717 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
Kojto 122:f9eeca106725 1718 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1719 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1720
Kojto 122:f9eeca106725 1721 #define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level) */
Kojto 122:f9eeca106725 1722 #define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 1723 #define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 1724
Kojto 122:f9eeca106725 1725 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
Kojto 122:f9eeca106725 1726
Kojto 122:f9eeca106725 1727 /****************** Bit definition generic for DMA_CNDTR register *******************/
Kojto 122:f9eeca106725 1728 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 1729
Kojto 90:cb3d968589d8 1730 /****************** Bit definition for DMA_CNDTR1 register ******************/
Kojto 122:f9eeca106725 1731 #define DMA_CNDTR1_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 1732
Kojto 90:cb3d968589d8 1733 /****************** Bit definition for DMA_CNDTR2 register ******************/
Kojto 122:f9eeca106725 1734 #define DMA_CNDTR2_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 1735
Kojto 90:cb3d968589d8 1736 /****************** Bit definition for DMA_CNDTR3 register ******************/
Kojto 122:f9eeca106725 1737 #define DMA_CNDTR3_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 1738
Kojto 90:cb3d968589d8 1739 /****************** Bit definition for DMA_CNDTR4 register ******************/
Kojto 122:f9eeca106725 1740 #define DMA_CNDTR4_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 1741
Kojto 90:cb3d968589d8 1742 /****************** Bit definition for DMA_CNDTR5 register ******************/
Kojto 122:f9eeca106725 1743 #define DMA_CNDTR5_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 1744
Kojto 90:cb3d968589d8 1745 /****************** Bit definition for DMA_CNDTR6 register ******************/
Kojto 122:f9eeca106725 1746 #define DMA_CNDTR6_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 1747
Kojto 90:cb3d968589d8 1748 /****************** Bit definition for DMA_CNDTR7 register ******************/
Kojto 122:f9eeca106725 1749 #define DMA_CNDTR7_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 122:f9eeca106725 1750
Kojto 122:f9eeca106725 1751 /****************** Bit definition generic for DMA_CPAR register ********************/
Kojto 122:f9eeca106725 1752 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 90:cb3d968589d8 1753
Kojto 90:cb3d968589d8 1754 /****************** Bit definition for DMA_CPAR1 register *******************/
Kojto 122:f9eeca106725 1755 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 90:cb3d968589d8 1756
Kojto 90:cb3d968589d8 1757 /****************** Bit definition for DMA_CPAR2 register *******************/
Kojto 122:f9eeca106725 1758 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 90:cb3d968589d8 1759
Kojto 90:cb3d968589d8 1760 /****************** Bit definition for DMA_CPAR3 register *******************/
Kojto 122:f9eeca106725 1761 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 90:cb3d968589d8 1762
Kojto 90:cb3d968589d8 1763
Kojto 90:cb3d968589d8 1764 /****************** Bit definition for DMA_CPAR4 register *******************/
Kojto 122:f9eeca106725 1765 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 90:cb3d968589d8 1766
Kojto 90:cb3d968589d8 1767 /****************** Bit definition for DMA_CPAR5 register *******************/
Kojto 122:f9eeca106725 1768 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 90:cb3d968589d8 1769
Kojto 90:cb3d968589d8 1770 /****************** Bit definition for DMA_CPAR6 register *******************/
Kojto 122:f9eeca106725 1771 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 90:cb3d968589d8 1772
Kojto 90:cb3d968589d8 1773
Kojto 90:cb3d968589d8 1774 /****************** Bit definition for DMA_CPAR7 register *******************/
Kojto 122:f9eeca106725 1775 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 122:f9eeca106725 1776
Kojto 122:f9eeca106725 1777 /****************** Bit definition generic for DMA_CMAR register ********************/
Kojto 122:f9eeca106725 1778 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 90:cb3d968589d8 1779
Kojto 90:cb3d968589d8 1780 /****************** Bit definition for DMA_CMAR1 register *******************/
Kojto 122:f9eeca106725 1781 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 90:cb3d968589d8 1782
Kojto 90:cb3d968589d8 1783 /****************** Bit definition for DMA_CMAR2 register *******************/
Kojto 122:f9eeca106725 1784 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 90:cb3d968589d8 1785
Kojto 90:cb3d968589d8 1786 /****************** Bit definition for DMA_CMAR3 register *******************/
Kojto 122:f9eeca106725 1787 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 90:cb3d968589d8 1788
Kojto 90:cb3d968589d8 1789
Kojto 90:cb3d968589d8 1790 /****************** Bit definition for DMA_CMAR4 register *******************/
Kojto 122:f9eeca106725 1791 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 90:cb3d968589d8 1792
Kojto 90:cb3d968589d8 1793 /****************** Bit definition for DMA_CMAR5 register *******************/
Kojto 122:f9eeca106725 1794 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 90:cb3d968589d8 1795
Kojto 90:cb3d968589d8 1796 /****************** Bit definition for DMA_CMAR6 register *******************/
Kojto 122:f9eeca106725 1797 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 90:cb3d968589d8 1798
Kojto 90:cb3d968589d8 1799 /****************** Bit definition for DMA_CMAR7 register *******************/
Kojto 122:f9eeca106725 1800 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 90:cb3d968589d8 1801
Kojto 90:cb3d968589d8 1802 /******************************************************************************/
Kojto 90:cb3d968589d8 1803 /* */
Kojto 90:cb3d968589d8 1804 /* External Interrupt/Event Controller (EXTI) */
Kojto 90:cb3d968589d8 1805 /* */
Kojto 90:cb3d968589d8 1806 /******************************************************************************/
Kojto 90:cb3d968589d8 1807
Kojto 90:cb3d968589d8 1808 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 122:f9eeca106725 1809 #define EXTI_IMR_MR0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 1810 #define EXTI_IMR_MR1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 1811 #define EXTI_IMR_MR2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 1812 #define EXTI_IMR_MR3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 1813 #define EXTI_IMR_MR4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 1814 #define EXTI_IMR_MR5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 1815 #define EXTI_IMR_MR6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 1816 #define EXTI_IMR_MR7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 1817 #define EXTI_IMR_MR8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 1818 #define EXTI_IMR_MR9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 1819 #define EXTI_IMR_MR10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 1820 #define EXTI_IMR_MR11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 1821 #define EXTI_IMR_MR12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 1822 #define EXTI_IMR_MR13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 1823 #define EXTI_IMR_MR14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 1824 #define EXTI_IMR_MR15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 1825 #define EXTI_IMR_MR16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
Kojto 122:f9eeca106725 1826 #define EXTI_IMR_MR17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 1827 #define EXTI_IMR_MR18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 1828 #define EXTI_IMR_MR19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 1829 #define EXTI_IMR_MR20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
Kojto 122:f9eeca106725 1830 #define EXTI_IMR_MR21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
Kojto 122:f9eeca106725 1831 #define EXTI_IMR_MR22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
Kojto 122:f9eeca106725 1832 #define EXTI_IMR_MR23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
Kojto 122:f9eeca106725 1833
Kojto 122:f9eeca106725 1834 /* References Defines */
Kojto 122:f9eeca106725 1835 #define EXTI_IMR_IM0 EXTI_IMR_MR0
Kojto 122:f9eeca106725 1836 #define EXTI_IMR_IM1 EXTI_IMR_MR1
Kojto 122:f9eeca106725 1837 #define EXTI_IMR_IM2 EXTI_IMR_MR2
Kojto 122:f9eeca106725 1838 #define EXTI_IMR_IM3 EXTI_IMR_MR3
Kojto 122:f9eeca106725 1839 #define EXTI_IMR_IM4 EXTI_IMR_MR4
Kojto 122:f9eeca106725 1840 #define EXTI_IMR_IM5 EXTI_IMR_MR5
Kojto 122:f9eeca106725 1841 #define EXTI_IMR_IM6 EXTI_IMR_MR6
Kojto 122:f9eeca106725 1842 #define EXTI_IMR_IM7 EXTI_IMR_MR7
Kojto 122:f9eeca106725 1843 #define EXTI_IMR_IM8 EXTI_IMR_MR8
Kojto 122:f9eeca106725 1844 #define EXTI_IMR_IM9 EXTI_IMR_MR9
Kojto 122:f9eeca106725 1845 #define EXTI_IMR_IM10 EXTI_IMR_MR10
Kojto 122:f9eeca106725 1846 #define EXTI_IMR_IM11 EXTI_IMR_MR11
Kojto 122:f9eeca106725 1847 #define EXTI_IMR_IM12 EXTI_IMR_MR12
Kojto 122:f9eeca106725 1848 #define EXTI_IMR_IM13 EXTI_IMR_MR13
Kojto 122:f9eeca106725 1849 #define EXTI_IMR_IM14 EXTI_IMR_MR14
Kojto 122:f9eeca106725 1850 #define EXTI_IMR_IM15 EXTI_IMR_MR15
Kojto 122:f9eeca106725 1851 #define EXTI_IMR_IM16 EXTI_IMR_MR16
Kojto 122:f9eeca106725 1852 #define EXTI_IMR_IM17 EXTI_IMR_MR17
Kojto 122:f9eeca106725 1853 #define EXTI_IMR_IM18 EXTI_IMR_MR18
Kojto 122:f9eeca106725 1854 #define EXTI_IMR_IM19 EXTI_IMR_MR19
Kojto 122:f9eeca106725 1855 #define EXTI_IMR_IM20 EXTI_IMR_MR20
Kojto 122:f9eeca106725 1856 #define EXTI_IMR_IM21 EXTI_IMR_MR21
Kojto 122:f9eeca106725 1857 #define EXTI_IMR_IM22 EXTI_IMR_MR22
Kojto 122:f9eeca106725 1858 /* Category 3, 4 & 5 */
Kojto 122:f9eeca106725 1859 #define EXTI_IMR_IM23 EXTI_IMR_MR23
Kojto 122:f9eeca106725 1860 #define EXTI_IMR_IM ((uint32_t)0x00FFFFFFU) /*!< Interrupt Mask All */
Kojto 90:cb3d968589d8 1861
Kojto 90:cb3d968589d8 1862 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 122:f9eeca106725 1863 #define EXTI_EMR_MR0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 1864 #define EXTI_EMR_MR1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 1865 #define EXTI_EMR_MR2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 1866 #define EXTI_EMR_MR3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 1867 #define EXTI_EMR_MR4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 1868 #define EXTI_EMR_MR5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 1869 #define EXTI_EMR_MR6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 1870 #define EXTI_EMR_MR7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 1871 #define EXTI_EMR_MR8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 1872 #define EXTI_EMR_MR9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 1873 #define EXTI_EMR_MR10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 1874 #define EXTI_EMR_MR11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 1875 #define EXTI_EMR_MR12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 1876 #define EXTI_EMR_MR13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 1877 #define EXTI_EMR_MR14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 1878 #define EXTI_EMR_MR15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 1879 #define EXTI_EMR_MR16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
Kojto 122:f9eeca106725 1880 #define EXTI_EMR_MR17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 1881 #define EXTI_EMR_MR18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 1882 #define EXTI_EMR_MR19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 1883 #define EXTI_EMR_MR20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
Kojto 122:f9eeca106725 1884 #define EXTI_EMR_MR21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
Kojto 122:f9eeca106725 1885 #define EXTI_EMR_MR22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
Kojto 122:f9eeca106725 1886 #define EXTI_EMR_MR23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
Kojto 122:f9eeca106725 1887
Kojto 122:f9eeca106725 1888 /* References Defines */
Kojto 122:f9eeca106725 1889 #define EXTI_EMR_EM0 EXTI_EMR_MR0
Kojto 122:f9eeca106725 1890 #define EXTI_EMR_EM1 EXTI_EMR_MR1
Kojto 122:f9eeca106725 1891 #define EXTI_EMR_EM2 EXTI_EMR_MR2
Kojto 122:f9eeca106725 1892 #define EXTI_EMR_EM3 EXTI_EMR_MR3
Kojto 122:f9eeca106725 1893 #define EXTI_EMR_EM4 EXTI_EMR_MR4
Kojto 122:f9eeca106725 1894 #define EXTI_EMR_EM5 EXTI_EMR_MR5
Kojto 122:f9eeca106725 1895 #define EXTI_EMR_EM6 EXTI_EMR_MR6
Kojto 122:f9eeca106725 1896 #define EXTI_EMR_EM7 EXTI_EMR_MR7
Kojto 122:f9eeca106725 1897 #define EXTI_EMR_EM8 EXTI_EMR_MR8
Kojto 122:f9eeca106725 1898 #define EXTI_EMR_EM9 EXTI_EMR_MR9
Kojto 122:f9eeca106725 1899 #define EXTI_EMR_EM10 EXTI_EMR_MR10
Kojto 122:f9eeca106725 1900 #define EXTI_EMR_EM11 EXTI_EMR_MR11
Kojto 122:f9eeca106725 1901 #define EXTI_EMR_EM12 EXTI_EMR_MR12
Kojto 122:f9eeca106725 1902 #define EXTI_EMR_EM13 EXTI_EMR_MR13
Kojto 122:f9eeca106725 1903 #define EXTI_EMR_EM14 EXTI_EMR_MR14
Kojto 122:f9eeca106725 1904 #define EXTI_EMR_EM15 EXTI_EMR_MR15
Kojto 122:f9eeca106725 1905 #define EXTI_EMR_EM16 EXTI_EMR_MR16
Kojto 122:f9eeca106725 1906 #define EXTI_EMR_EM17 EXTI_EMR_MR17
Kojto 122:f9eeca106725 1907 #define EXTI_EMR_EM18 EXTI_EMR_MR18
Kojto 122:f9eeca106725 1908 #define EXTI_EMR_EM19 EXTI_EMR_MR19
Kojto 122:f9eeca106725 1909 #define EXTI_EMR_EM20 EXTI_EMR_MR20
Kojto 122:f9eeca106725 1910 #define EXTI_EMR_EM21 EXTI_EMR_MR21
Kojto 122:f9eeca106725 1911 #define EXTI_EMR_EM22 EXTI_EMR_MR22
Kojto 122:f9eeca106725 1912 #define EXTI_EMR_EM23 EXTI_EMR_MR23
Kojto 90:cb3d968589d8 1913
Kojto 90:cb3d968589d8 1914 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 122:f9eeca106725 1915 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 1916 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 1917 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 1918 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 1919 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 1920 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 1921 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 1922 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 1923 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 1924 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 1925 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 1926 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 1927 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 1928 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 1929 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 1930 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 1931 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 1932 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 1933 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000U) /*!< Rising trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 1934 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 1935 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 1936 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 1937 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 1938 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000U) /*!< Rising trigger event configuration bit of line 23 */
Kojto 122:f9eeca106725 1939
Kojto 122:f9eeca106725 1940 /* References Defines */
Kojto 122:f9eeca106725 1941 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
Kojto 122:f9eeca106725 1942 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
Kojto 122:f9eeca106725 1943 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
Kojto 122:f9eeca106725 1944 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
Kojto 122:f9eeca106725 1945 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
Kojto 122:f9eeca106725 1946 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
Kojto 122:f9eeca106725 1947 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
Kojto 122:f9eeca106725 1948 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
Kojto 122:f9eeca106725 1949 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
Kojto 122:f9eeca106725 1950 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
Kojto 122:f9eeca106725 1951 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
Kojto 122:f9eeca106725 1952 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
Kojto 122:f9eeca106725 1953 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
Kojto 122:f9eeca106725 1954 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
Kojto 122:f9eeca106725 1955 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
Kojto 122:f9eeca106725 1956 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
Kojto 122:f9eeca106725 1957 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
Kojto 122:f9eeca106725 1958 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
Kojto 122:f9eeca106725 1959 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
Kojto 122:f9eeca106725 1960 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
Kojto 122:f9eeca106725 1961 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
Kojto 122:f9eeca106725 1962 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
Kojto 122:f9eeca106725 1963 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
Kojto 122:f9eeca106725 1964 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
Kojto 90:cb3d968589d8 1965
Kojto 90:cb3d968589d8 1966 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 122:f9eeca106725 1967 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 1968 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 1969 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 1970 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 1971 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 1972 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 1973 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 1974 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 1975 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 1976 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 1977 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 1978 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 1979 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 1980 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 1981 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 1982 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 1983 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 1984 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 1985 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000U) /*!< Falling trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 1986 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 1987 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 1988 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 1989 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 1990 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000U) /*!< Falling trigger event configuration bit of line 23 */
Kojto 122:f9eeca106725 1991
Kojto 122:f9eeca106725 1992 /* References Defines */
Kojto 122:f9eeca106725 1993 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
Kojto 122:f9eeca106725 1994 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
Kojto 122:f9eeca106725 1995 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
Kojto 122:f9eeca106725 1996 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
Kojto 122:f9eeca106725 1997 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
Kojto 122:f9eeca106725 1998 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
Kojto 122:f9eeca106725 1999 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
Kojto 122:f9eeca106725 2000 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
Kojto 122:f9eeca106725 2001 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
Kojto 122:f9eeca106725 2002 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
Kojto 122:f9eeca106725 2003 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
Kojto 122:f9eeca106725 2004 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
Kojto 122:f9eeca106725 2005 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
Kojto 122:f9eeca106725 2006 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
Kojto 122:f9eeca106725 2007 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
Kojto 122:f9eeca106725 2008 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
Kojto 122:f9eeca106725 2009 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
Kojto 122:f9eeca106725 2010 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
Kojto 122:f9eeca106725 2011 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
Kojto 122:f9eeca106725 2012 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
Kojto 122:f9eeca106725 2013 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
Kojto 122:f9eeca106725 2014 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
Kojto 122:f9eeca106725 2015 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
Kojto 122:f9eeca106725 2016 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
Kojto 90:cb3d968589d8 2017
Kojto 90:cb3d968589d8 2018 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 122:f9eeca106725 2019 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 2020 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 2021 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 2022 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 2023 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 2024 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 2025 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 2026 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 2027 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 2028 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 2029 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 2030 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 2031 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 2032 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 2033 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 2034 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 2035 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 2036 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */
Kojto 122:f9eeca106725 2037 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000U) /*!< Software Interrupt on line 18 */
Kojto 122:f9eeca106725 2038 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 2039 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
Kojto 122:f9eeca106725 2040 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
Kojto 122:f9eeca106725 2041 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
Kojto 122:f9eeca106725 2042 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000U) /*!< Software Interrupt on line 23 */
Kojto 122:f9eeca106725 2043
Kojto 122:f9eeca106725 2044 /* References Defines */
Kojto 122:f9eeca106725 2045 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
Kojto 122:f9eeca106725 2046 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
Kojto 122:f9eeca106725 2047 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
Kojto 122:f9eeca106725 2048 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
Kojto 122:f9eeca106725 2049 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
Kojto 122:f9eeca106725 2050 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
Kojto 122:f9eeca106725 2051 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
Kojto 122:f9eeca106725 2052 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
Kojto 122:f9eeca106725 2053 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
Kojto 122:f9eeca106725 2054 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
Kojto 122:f9eeca106725 2055 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
Kojto 122:f9eeca106725 2056 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
Kojto 122:f9eeca106725 2057 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
Kojto 122:f9eeca106725 2058 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
Kojto 122:f9eeca106725 2059 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
Kojto 122:f9eeca106725 2060 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
Kojto 122:f9eeca106725 2061 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
Kojto 122:f9eeca106725 2062 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
Kojto 122:f9eeca106725 2063 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
Kojto 122:f9eeca106725 2064 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
Kojto 122:f9eeca106725 2065 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
Kojto 122:f9eeca106725 2066 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
Kojto 122:f9eeca106725 2067 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
Kojto 122:f9eeca106725 2068 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
Kojto 90:cb3d968589d8 2069
Kojto 90:cb3d968589d8 2070 /******************* Bit definition for EXTI_PR register ********************/
Kojto 122:f9eeca106725 2071 #define EXTI_PR_PR0 ((uint32_t)0x00000001U) /*!< Pending bit for line 0 */
Kojto 122:f9eeca106725 2072 #define EXTI_PR_PR1 ((uint32_t)0x00000002U) /*!< Pending bit for line 1 */
Kojto 122:f9eeca106725 2073 #define EXTI_PR_PR2 ((uint32_t)0x00000004U) /*!< Pending bit for line 2 */
Kojto 122:f9eeca106725 2074 #define EXTI_PR_PR3 ((uint32_t)0x00000008U) /*!< Pending bit for line 3 */
Kojto 122:f9eeca106725 2075 #define EXTI_PR_PR4 ((uint32_t)0x00000010U) /*!< Pending bit for line 4 */
Kojto 122:f9eeca106725 2076 #define EXTI_PR_PR5 ((uint32_t)0x00000020U) /*!< Pending bit for line 5 */
Kojto 122:f9eeca106725 2077 #define EXTI_PR_PR6 ((uint32_t)0x00000040U) /*!< Pending bit for line 6 */
Kojto 122:f9eeca106725 2078 #define EXTI_PR_PR7 ((uint32_t)0x00000080U) /*!< Pending bit for line 7 */
Kojto 122:f9eeca106725 2079 #define EXTI_PR_PR8 ((uint32_t)0x00000100U) /*!< Pending bit for line 8 */
Kojto 122:f9eeca106725 2080 #define EXTI_PR_PR9 ((uint32_t)0x00000200U) /*!< Pending bit for line 9 */
Kojto 122:f9eeca106725 2081 #define EXTI_PR_PR10 ((uint32_t)0x00000400U) /*!< Pending bit for line 10 */
Kojto 122:f9eeca106725 2082 #define EXTI_PR_PR11 ((uint32_t)0x00000800U) /*!< Pending bit for line 11 */
Kojto 122:f9eeca106725 2083 #define EXTI_PR_PR12 ((uint32_t)0x00001000U) /*!< Pending bit for line 12 */
Kojto 122:f9eeca106725 2084 #define EXTI_PR_PR13 ((uint32_t)0x00002000U) /*!< Pending bit for line 13 */
Kojto 122:f9eeca106725 2085 #define EXTI_PR_PR14 ((uint32_t)0x00004000U) /*!< Pending bit for line 14 */
Kojto 122:f9eeca106725 2086 #define EXTI_PR_PR15 ((uint32_t)0x00008000U) /*!< Pending bit for line 15 */
Kojto 122:f9eeca106725 2087 #define EXTI_PR_PR16 ((uint32_t)0x00010000U) /*!< Pending bit for line 16 */
Kojto 122:f9eeca106725 2088 #define EXTI_PR_PR17 ((uint32_t)0x00020000U) /*!< Pending bit for line 17 */
Kojto 122:f9eeca106725 2089 #define EXTI_PR_PR18 ((uint32_t)0x00040000U) /*!< Pending bit for line 18 */
Kojto 122:f9eeca106725 2090 #define EXTI_PR_PR19 ((uint32_t)0x00080000U) /*!< Pending bit for line 19 */
Kojto 122:f9eeca106725 2091 #define EXTI_PR_PR20 ((uint32_t)0x00100000U) /*!< Pending bit for line 20 */
Kojto 122:f9eeca106725 2092 #define EXTI_PR_PR21 ((uint32_t)0x00200000U) /*!< Pending bit for line 21 */
Kojto 122:f9eeca106725 2093 #define EXTI_PR_PR22 ((uint32_t)0x00400000U) /*!< Pending bit for line 22 */
Kojto 122:f9eeca106725 2094 #define EXTI_PR_PR23 ((uint32_t)0x00800000U) /*!< Pending bit for line 23 */
Kojto 122:f9eeca106725 2095
Kojto 122:f9eeca106725 2096 /* References Defines */
Kojto 122:f9eeca106725 2097 #define EXTI_PR_PIF0 EXTI_PR_PR0
Kojto 122:f9eeca106725 2098 #define EXTI_PR_PIF1 EXTI_PR_PR1
Kojto 122:f9eeca106725 2099 #define EXTI_PR_PIF2 EXTI_PR_PR2
Kojto 122:f9eeca106725 2100 #define EXTI_PR_PIF3 EXTI_PR_PR3
Kojto 122:f9eeca106725 2101 #define EXTI_PR_PIF4 EXTI_PR_PR4
Kojto 122:f9eeca106725 2102 #define EXTI_PR_PIF5 EXTI_PR_PR5
Kojto 122:f9eeca106725 2103 #define EXTI_PR_PIF6 EXTI_PR_PR6
Kojto 122:f9eeca106725 2104 #define EXTI_PR_PIF7 EXTI_PR_PR7
Kojto 122:f9eeca106725 2105 #define EXTI_PR_PIF8 EXTI_PR_PR8
Kojto 122:f9eeca106725 2106 #define EXTI_PR_PIF9 EXTI_PR_PR9
Kojto 122:f9eeca106725 2107 #define EXTI_PR_PIF10 EXTI_PR_PR10
Kojto 122:f9eeca106725 2108 #define EXTI_PR_PIF11 EXTI_PR_PR11
Kojto 122:f9eeca106725 2109 #define EXTI_PR_PIF12 EXTI_PR_PR12
Kojto 122:f9eeca106725 2110 #define EXTI_PR_PIF13 EXTI_PR_PR13
Kojto 122:f9eeca106725 2111 #define EXTI_PR_PIF14 EXTI_PR_PR14
Kojto 122:f9eeca106725 2112 #define EXTI_PR_PIF15 EXTI_PR_PR15
Kojto 122:f9eeca106725 2113 #define EXTI_PR_PIF16 EXTI_PR_PR16
Kojto 122:f9eeca106725 2114 #define EXTI_PR_PIF17 EXTI_PR_PR17
Kojto 122:f9eeca106725 2115 #define EXTI_PR_PIF18 EXTI_PR_PR18
Kojto 122:f9eeca106725 2116 #define EXTI_PR_PIF19 EXTI_PR_PR19
Kojto 122:f9eeca106725 2117 #define EXTI_PR_PIF20 EXTI_PR_PR20
Kojto 122:f9eeca106725 2118 #define EXTI_PR_PIF21 EXTI_PR_PR21
Kojto 122:f9eeca106725 2119 #define EXTI_PR_PIF22 EXTI_PR_PR22
Kojto 122:f9eeca106725 2120 #define EXTI_PR_PIF23 EXTI_PR_PR23
Kojto 90:cb3d968589d8 2121
Kojto 90:cb3d968589d8 2122 /******************************************************************************/
Kojto 90:cb3d968589d8 2123 /* */
Kojto 90:cb3d968589d8 2124 /* FLASH, DATA EEPROM and Option Bytes Registers */
Kojto 90:cb3d968589d8 2125 /* (FLASH, DATA_EEPROM, OB) */
Kojto 90:cb3d968589d8 2126 /* */
Kojto 90:cb3d968589d8 2127 /******************************************************************************/
Kojto 90:cb3d968589d8 2128
Kojto 90:cb3d968589d8 2129 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 122:f9eeca106725 2130 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< Latency */
Kojto 122:f9eeca106725 2131 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */
Kojto 122:f9eeca106725 2132 #define FLASH_ACR_ACC64 ((uint32_t)0x00000004U) /*!< Access 64 bits */
Kojto 122:f9eeca106725 2133 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */
Kojto 122:f9eeca106725 2134 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */
Kojto 90:cb3d968589d8 2135
Kojto 90:cb3d968589d8 2136 /******************* Bit definition for FLASH_PECR register ******************/
Kojto 122:f9eeca106725 2137 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */
Kojto 122:f9eeca106725 2138 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */
Kojto 122:f9eeca106725 2139 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */
Kojto 122:f9eeca106725 2140 #define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */
Kojto 122:f9eeca106725 2141 #define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */
Kojto 122:f9eeca106725 2142 #define FLASH_PECR_FTDW ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
Kojto 122:f9eeca106725 2143 #define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */
Kojto 122:f9eeca106725 2144 #define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */
Kojto 122:f9eeca106725 2145 #define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000U) /*!< Parallel Bank mode */
Kojto 122:f9eeca106725 2146 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */
Kojto 122:f9eeca106725 2147 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */
Kojto 122:f9eeca106725 2148 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */
Kojto 90:cb3d968589d8 2149
Kojto 90:cb3d968589d8 2150 /****************** Bit definition for FLASH_PDKEYR register ******************/
Kojto 122:f9eeca106725 2151 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
Kojto 90:cb3d968589d8 2152
Kojto 90:cb3d968589d8 2153 /****************** Bit definition for FLASH_PEKEYR register ******************/
Kojto 122:f9eeca106725 2154 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
Kojto 90:cb3d968589d8 2155
Kojto 90:cb3d968589d8 2156 /****************** Bit definition for FLASH_PRGKEYR register ******************/
Kojto 122:f9eeca106725 2157 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */
Kojto 90:cb3d968589d8 2158
Kojto 90:cb3d968589d8 2159 /****************** Bit definition for FLASH_OPTKEYR register ******************/
Kojto 122:f9eeca106725 2160 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */
Kojto 90:cb3d968589d8 2161
Kojto 90:cb3d968589d8 2162 /****************** Bit definition for FLASH_SR register *******************/
Kojto 122:f9eeca106725 2163 #define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */
Kojto 122:f9eeca106725 2164 #define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/
Kojto 122:f9eeca106725 2165 #define FLASH_SR_ENDHV ((uint32_t)0x00000004U) /*!< End of high voltage */
Kojto 122:f9eeca106725 2166 #define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */
Kojto 122:f9eeca106725 2167
Kojto 122:f9eeca106725 2168 #define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protected error */
Kojto 122:f9eeca106725 2169 #define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */
Kojto 122:f9eeca106725 2170 #define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */
Kojto 122:f9eeca106725 2171 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option validity error */
Kojto 122:f9eeca106725 2172 #define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000U) /*!< Option User validity error */
Kojto 90:cb3d968589d8 2173
Kojto 90:cb3d968589d8 2174 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 122:f9eeca106725 2175 #define FLASH_OBR_RDPRT ((uint32_t)0x000000FFU) /*!< Read Protection */
Kojto 122:f9eeca106725 2176 #define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
Kojto 122:f9eeca106725 2177 #define FLASH_OBR_USER ((uint32_t)0x00F00000U) /*!< User Option Bytes */
Kojto 122:f9eeca106725 2178 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */
Kojto 122:f9eeca106725 2179 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */
Kojto 122:f9eeca106725 2180 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */
Kojto 122:f9eeca106725 2181 #define FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000U) /*!< BFB2 */
Kojto 90:cb3d968589d8 2182
Kojto 90:cb3d968589d8 2183 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 122:f9eeca106725 2184 #define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFFU) /*!< Write Protect sectors 0 to 31 */
Kojto 122:f9eeca106725 2185 #define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFFU) /*!< Write Protect sectors 32 to 63 */
Kojto 122:f9eeca106725 2186 #define FLASH_WRPR3_WRP ((uint32_t)0xFFFFFFFFU) /*!< Write Protect sectors 64 to 95 */
Kojto 122:f9eeca106725 2187 #define FLASH_WRPR4_WRP ((uint32_t)0xFFFFFFFFU) /*!< Write Protect sectors 96 to 127 */
Kojto 90:cb3d968589d8 2188
Kojto 90:cb3d968589d8 2189 /******************************************************************************/
Kojto 90:cb3d968589d8 2190 /* */
Kojto 90:cb3d968589d8 2191 /* General Purpose I/O */
Kojto 90:cb3d968589d8 2192 /* */
Kojto 90:cb3d968589d8 2193 /******************************************************************************/
Kojto 90:cb3d968589d8 2194 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 2195 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003U)
Kojto 122:f9eeca106725 2196 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2197 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2198
Kojto 122:f9eeca106725 2199 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000CU)
Kojto 122:f9eeca106725 2200 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2201 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2202
Kojto 122:f9eeca106725 2203 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030U)
Kojto 122:f9eeca106725 2204 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2205 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2206
Kojto 122:f9eeca106725 2207 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0U)
Kojto 122:f9eeca106725 2208 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2209 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2210
Kojto 122:f9eeca106725 2211 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300U)
Kojto 122:f9eeca106725 2212 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2213 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2214
Kojto 122:f9eeca106725 2215 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00U)
Kojto 122:f9eeca106725 2216 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2217 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2218
Kojto 122:f9eeca106725 2219 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000U)
Kojto 122:f9eeca106725 2220 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2221 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2222
Kojto 122:f9eeca106725 2223 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000U)
Kojto 122:f9eeca106725 2224 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2225 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 2226
Kojto 122:f9eeca106725 2227 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000U)
Kojto 122:f9eeca106725 2228 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 2229 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 2230
Kojto 122:f9eeca106725 2231 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000U)
Kojto 122:f9eeca106725 2232 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 2233 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 2234
Kojto 122:f9eeca106725 2235 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000U)
Kojto 122:f9eeca106725 2236 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 2237 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 2238
Kojto 122:f9eeca106725 2239 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000U)
Kojto 122:f9eeca106725 2240 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 2241 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 2242
Kojto 122:f9eeca106725 2243 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000U)
Kojto 122:f9eeca106725 2244 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 2245 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 2246
Kojto 122:f9eeca106725 2247 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000U)
Kojto 122:f9eeca106725 2248 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 2249 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 2250
Kojto 122:f9eeca106725 2251 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000U)
Kojto 122:f9eeca106725 2252 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 2253 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000U)
Kojto 122:f9eeca106725 2254
Kojto 122:f9eeca106725 2255 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000U)
Kojto 122:f9eeca106725 2256 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000U)
Kojto 122:f9eeca106725 2257 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000U)
Kojto 90:cb3d968589d8 2258
Kojto 90:cb3d968589d8 2259 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 122:f9eeca106725 2260 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2261 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2262 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2263 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2264 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2265 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2266 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2267 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2268 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2269 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2270 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2271 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2272 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2273 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2274 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2275 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
Kojto 90:cb3d968589d8 2276
Kojto 90:cb3d968589d8 2277 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 122:f9eeca106725 2278 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003U)
Kojto 122:f9eeca106725 2279 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2280 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2281
Kojto 122:f9eeca106725 2282 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000CU)
Kojto 122:f9eeca106725 2283 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2284 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2285
Kojto 122:f9eeca106725 2286 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030U)
Kojto 122:f9eeca106725 2287 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2288 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2289
Kojto 122:f9eeca106725 2290 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0U)
Kojto 122:f9eeca106725 2291 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2292 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2293
Kojto 122:f9eeca106725 2294 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300U)
Kojto 122:f9eeca106725 2295 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2296 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2297
Kojto 122:f9eeca106725 2298 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00U)
Kojto 122:f9eeca106725 2299 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2300 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2301
Kojto 122:f9eeca106725 2302 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000U)
Kojto 122:f9eeca106725 2303 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2304 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2305
Kojto 122:f9eeca106725 2306 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000U)
Kojto 122:f9eeca106725 2307 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2308 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 2309
Kojto 122:f9eeca106725 2310 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000U)
Kojto 122:f9eeca106725 2311 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 2312 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 2313
Kojto 122:f9eeca106725 2314 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000U)
Kojto 122:f9eeca106725 2315 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 2316 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 2317
Kojto 122:f9eeca106725 2318 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000U)
Kojto 122:f9eeca106725 2319 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 2320 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 2321
Kojto 122:f9eeca106725 2322 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000U)
Kojto 122:f9eeca106725 2323 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 2324 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 2325
Kojto 122:f9eeca106725 2326 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000U)
Kojto 122:f9eeca106725 2327 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 2328 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 2329
Kojto 122:f9eeca106725 2330 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000U)
Kojto 122:f9eeca106725 2331 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 2332 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 2333
Kojto 122:f9eeca106725 2334 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000U)
Kojto 122:f9eeca106725 2335 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 2336 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000U)
Kojto 122:f9eeca106725 2337
Kojto 122:f9eeca106725 2338 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000U)
Kojto 122:f9eeca106725 2339 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000U)
Kojto 122:f9eeca106725 2340 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000U)
Kojto 90:cb3d968589d8 2341
Kojto 90:cb3d968589d8 2342 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 122:f9eeca106725 2343 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003U)
Kojto 122:f9eeca106725 2344 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2345 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2346
Kojto 122:f9eeca106725 2347 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000CU)
Kojto 122:f9eeca106725 2348 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2349 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2350
Kojto 122:f9eeca106725 2351 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030U)
Kojto 122:f9eeca106725 2352 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2353 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2354
Kojto 122:f9eeca106725 2355 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0U)
Kojto 122:f9eeca106725 2356 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2357 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2358
Kojto 122:f9eeca106725 2359 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300U)
Kojto 122:f9eeca106725 2360 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2361 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2362
Kojto 122:f9eeca106725 2363 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00U)
Kojto 122:f9eeca106725 2364 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2365 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2366
Kojto 122:f9eeca106725 2367 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000U)
Kojto 122:f9eeca106725 2368 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2369 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2370
Kojto 122:f9eeca106725 2371 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000U)
Kojto 122:f9eeca106725 2372 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2373 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 2374
Kojto 122:f9eeca106725 2375 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000U)
Kojto 122:f9eeca106725 2376 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 2377 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 2378
Kojto 122:f9eeca106725 2379 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000U)
Kojto 122:f9eeca106725 2380 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 2381 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 2382
Kojto 122:f9eeca106725 2383 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000U)
Kojto 122:f9eeca106725 2384 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 2385 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 2386
Kojto 122:f9eeca106725 2387 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000U)
Kojto 122:f9eeca106725 2388 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 2389 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 2390
Kojto 122:f9eeca106725 2391 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000U)
Kojto 122:f9eeca106725 2392 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 2393 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 2394
Kojto 122:f9eeca106725 2395 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000U)
Kojto 122:f9eeca106725 2396 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 2397 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 2398
Kojto 122:f9eeca106725 2399 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000U)
Kojto 122:f9eeca106725 2400 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 2401 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000U)
Kojto 122:f9eeca106725 2402 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000U)
Kojto 122:f9eeca106725 2403 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000U)
Kojto 122:f9eeca106725 2404 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000U)
Kojto 90:cb3d968589d8 2405
Kojto 90:cb3d968589d8 2406 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 2407 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2408 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2409 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2410 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2411 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2412 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2413 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2414 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2415 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2416 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2417 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2418 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2419 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2420 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2421 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2422 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000U)
Kojto 90:cb3d968589d8 2423
Kojto 90:cb3d968589d8 2424 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 122:f9eeca106725 2425 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2426 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2427 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2428 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2429 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2430 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2431 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2432 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2433 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2434 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2435 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2436 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2437 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2438 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2439 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2440 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000U)
Kojto 90:cb3d968589d8 2441
Kojto 90:cb3d968589d8 2442 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 122:f9eeca106725 2443 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2444 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2445 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2446 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2447 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2448 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2449 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2450 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2451 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2452 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2453 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2454 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2455 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2456 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2457 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2458 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 2459 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 2460 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 2461 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 2462 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 2463 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 2464 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 2465 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 2466 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 2467 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 2468 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 2469 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 2470 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 2471 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 2472 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
Kojto 122:f9eeca106725 2473 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
Kojto 122:f9eeca106725 2474 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
Kojto 90:cb3d968589d8 2475
Kojto 90:cb3d968589d8 2476 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 122:f9eeca106725 2477 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2478 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2479 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2480 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2481 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2482 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2483 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2484 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2485 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2486 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2487 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2488 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2489 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2490 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2491 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2492 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 2493 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
Kojto 90:cb3d968589d8 2494
Kojto 90:cb3d968589d8 2495 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 122:f9eeca106725 2496 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
Kojto 122:f9eeca106725 2497 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
Kojto 122:f9eeca106725 2498 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
Kojto 122:f9eeca106725 2499 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
Kojto 122:f9eeca106725 2500 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
Kojto 122:f9eeca106725 2501 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
Kojto 122:f9eeca106725 2502 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
Kojto 122:f9eeca106725 2503 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
Kojto 90:cb3d968589d8 2504
Kojto 90:cb3d968589d8 2505 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 122:f9eeca106725 2506 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
Kojto 122:f9eeca106725 2507 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
Kojto 122:f9eeca106725 2508 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
Kojto 122:f9eeca106725 2509 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
Kojto 122:f9eeca106725 2510 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
Kojto 122:f9eeca106725 2511 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
Kojto 122:f9eeca106725 2512 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
Kojto 122:f9eeca106725 2513 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
Kojto 90:cb3d968589d8 2514
Kojto 90:cb3d968589d8 2515 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 122:f9eeca106725 2516 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 2517 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 2518 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 2519 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 2520 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 2521 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 2522 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 2523 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 2524 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 2525 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 2526 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 2527 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 2528 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 2529 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 2530 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 2531 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
Kojto 90:cb3d968589d8 2532
Kojto 90:cb3d968589d8 2533 /******************************************************************************/
Kojto 90:cb3d968589d8 2534 /* */
Kojto 90:cb3d968589d8 2535 /* Inter-integrated Circuit Interface (I2C) */
Kojto 90:cb3d968589d8 2536 /* */
Kojto 90:cb3d968589d8 2537 /******************************************************************************/
Kojto 90:cb3d968589d8 2538
Kojto 90:cb3d968589d8 2539 /******************* Bit definition for I2C_CR1 register ********************/
Kojto 122:f9eeca106725 2540 #define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral Enable */
Kojto 122:f9eeca106725 2541 #define I2C_CR1_SMBUS ((uint32_t)0x00000002U) /*!< SMBus Mode */
Kojto 122:f9eeca106725 2542 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008U) /*!< SMBus Type */
Kojto 122:f9eeca106725 2543 #define I2C_CR1_ENARP ((uint32_t)0x00000010U) /*!< ARP Enable */
Kojto 122:f9eeca106725 2544 #define I2C_CR1_ENPEC ((uint32_t)0x00000020U) /*!< PEC Enable */
Kojto 122:f9eeca106725 2545 #define I2C_CR1_ENGC ((uint32_t)0x00000040U) /*!< General Call Enable */
Kojto 122:f9eeca106725 2546 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080U) /*!< Clock Stretching Disable (Slave mode) */
Kojto 122:f9eeca106725 2547 #define I2C_CR1_START ((uint32_t)0x00000100U) /*!< Start Generation */
Kojto 122:f9eeca106725 2548 #define I2C_CR1_STOP ((uint32_t)0x00000200U) /*!< Stop Generation */
Kojto 122:f9eeca106725 2549 #define I2C_CR1_ACK ((uint32_t)0x00000400U) /*!< Acknowledge Enable */
Kojto 122:f9eeca106725 2550 #define I2C_CR1_POS ((uint32_t)0x00000800U) /*!< Acknowledge/PEC Position (for data reception) */
Kojto 122:f9eeca106725 2551 #define I2C_CR1_PEC ((uint32_t)0x00001000U) /*!< Packet Error Checking */
Kojto 122:f9eeca106725 2552 #define I2C_CR1_ALERT ((uint32_t)0x00002000U) /*!< SMBus Alert */
Kojto 122:f9eeca106725 2553 #define I2C_CR1_SWRST ((uint32_t)0x00008000U) /*!< Software Reset */
Kojto 90:cb3d968589d8 2554
Kojto 90:cb3d968589d8 2555 /******************* Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 2556 #define I2C_CR2_FREQ ((uint32_t)0x0000003FU) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
Kojto 122:f9eeca106725 2557 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2558 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2559 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 2560 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 2561 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 2562 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 2563
Kojto 122:f9eeca106725 2564 #define I2C_CR2_ITERREN ((uint32_t)0x00000100U) /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 2565 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200U) /*!< Event Interrupt Enable */
Kojto 122:f9eeca106725 2566 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400U) /*!< Buffer Interrupt Enable */
Kojto 122:f9eeca106725 2567 #define I2C_CR2_DMAEN ((uint32_t)0x00000800U) /*!< DMA Requests Enable */
Kojto 122:f9eeca106725 2568 #define I2C_CR2_LAST ((uint32_t)0x00001000U) /*!< DMA Last Transfer */
Kojto 90:cb3d968589d8 2569
Kojto 90:cb3d968589d8 2570 /******************* Bit definition for I2C_OAR1 register *******************/
Kojto 122:f9eeca106725 2571 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FEU) /*!< Interface Address */
Kojto 122:f9eeca106725 2572 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300U) /*!< Interface Address */
Kojto 122:f9eeca106725 2573
Kojto 122:f9eeca106725 2574 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2575 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2576 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 2577 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 2578 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 2579 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 2580 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 2581 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 2582 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 2583 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 2584
Kojto 122:f9eeca106725 2585 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000U) /*!< Addressing Mode (Slave mode) */
Kojto 90:cb3d968589d8 2586
Kojto 90:cb3d968589d8 2587 /******************* Bit definition for I2C_OAR2 register *******************/
Kojto 122:f9eeca106725 2588 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001U) /*!< Dual addressing mode enable */
Kojto 122:f9eeca106725 2589 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FEU) /*!< Interface address */
Kojto 90:cb3d968589d8 2590
Kojto 90:cb3d968589d8 2591 /******************** Bit definition for I2C_DR register ********************/
Kojto 122:f9eeca106725 2592 #define I2C_DR_DR ((uint32_t)0x000000FFU) /*!< 8-bit Data Register */
Kojto 90:cb3d968589d8 2593
Kojto 90:cb3d968589d8 2594 /******************* Bit definition for I2C_SR1 register ********************/
Kojto 122:f9eeca106725 2595 #define I2C_SR1_SB ((uint32_t)0x00000001U) /*!< Start Bit (Master mode) */
Kojto 122:f9eeca106725 2596 #define I2C_SR1_ADDR ((uint32_t)0x00000002U) /*!< Address sent (master mode)/matched (slave mode) */
Kojto 122:f9eeca106725 2597 #define I2C_SR1_BTF ((uint32_t)0x00000004U) /*!< Byte Transfer Finished */
Kojto 122:f9eeca106725 2598 #define I2C_SR1_ADD10 ((uint32_t)0x00000008U) /*!< 10-bit header sent (Master mode) */
Kojto 122:f9eeca106725 2599 #define I2C_SR1_STOPF ((uint32_t)0x00000010U) /*!< Stop detection (Slave mode) */
Kojto 122:f9eeca106725 2600 #define I2C_SR1_RXNE ((uint32_t)0x00000040U) /*!< Data Register not Empty (receivers) */
Kojto 122:f9eeca106725 2601 #define I2C_SR1_TXE ((uint32_t)0x00000080U) /*!< Data Register Empty (transmitters) */
Kojto 122:f9eeca106725 2602 #define I2C_SR1_BERR ((uint32_t)0x00000100U) /*!< Bus Error */
Kojto 122:f9eeca106725 2603 #define I2C_SR1_ARLO ((uint32_t)0x00000200U) /*!< Arbitration Lost (master mode) */
Kojto 122:f9eeca106725 2604 #define I2C_SR1_AF ((uint32_t)0x00000400U) /*!< Acknowledge Failure */
Kojto 122:f9eeca106725 2605 #define I2C_SR1_OVR ((uint32_t)0x00000800U) /*!< Overrun/Underrun */
Kojto 122:f9eeca106725 2606 #define I2C_SR1_PECERR ((uint32_t)0x00001000U) /*!< PEC Error in reception */
Kojto 122:f9eeca106725 2607 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000U) /*!< Timeout or Tlow Error */
Kojto 122:f9eeca106725 2608 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000U) /*!< SMBus Alert */
Kojto 90:cb3d968589d8 2609
Kojto 90:cb3d968589d8 2610 /******************* Bit definition for I2C_SR2 register ********************/
Kojto 122:f9eeca106725 2611 #define I2C_SR2_MSL ((uint32_t)0x00000001U) /*!< Master/Slave */
Kojto 122:f9eeca106725 2612 #define I2C_SR2_BUSY ((uint32_t)0x00000002U) /*!< Bus Busy */
Kojto 122:f9eeca106725 2613 #define I2C_SR2_TRA ((uint32_t)0x00000004U) /*!< Transmitter/Receiver */
Kojto 122:f9eeca106725 2614 #define I2C_SR2_GENCALL ((uint32_t)0x00000010U) /*!< General Call Address (Slave mode) */
Kojto 122:f9eeca106725 2615 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020U) /*!< SMBus Device Default Address (Slave mode) */
Kojto 122:f9eeca106725 2616 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040U) /*!< SMBus Host Header (Slave mode) */
Kojto 122:f9eeca106725 2617 #define I2C_SR2_DUALF ((uint32_t)0x00000080U) /*!< Dual Flag (Slave mode) */
Kojto 122:f9eeca106725 2618 #define I2C_SR2_PEC ((uint32_t)0x0000FF00U) /*!< Packet Error Checking Register */
Kojto 90:cb3d968589d8 2619
Kojto 90:cb3d968589d8 2620 /******************* Bit definition for I2C_CCR register ********************/
Kojto 122:f9eeca106725 2621 #define I2C_CCR_CCR ((uint32_t)0x00000FFFU) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
Kojto 122:f9eeca106725 2622 #define I2C_CCR_DUTY ((uint32_t)0x00004000U) /*!< Fast Mode Duty Cycle */
Kojto 122:f9eeca106725 2623 #define I2C_CCR_FS ((uint32_t)0x00008000U) /*!< I2C Master Mode Selection */
Kojto 90:cb3d968589d8 2624
Kojto 90:cb3d968589d8 2625 /****************** Bit definition for I2C_TRISE register *******************/
Kojto 122:f9eeca106725 2626 #define I2C_TRISE_TRISE ((uint32_t)0x0000003FU) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
Kojto 90:cb3d968589d8 2627
Kojto 90:cb3d968589d8 2628 /******************************************************************************/
Kojto 90:cb3d968589d8 2629 /* */
Kojto 90:cb3d968589d8 2630 /* Independent WATCHDOG (IWDG) */
Kojto 90:cb3d968589d8 2631 /* */
Kojto 90:cb3d968589d8 2632 /******************************************************************************/
Kojto 90:cb3d968589d8 2633
Kojto 90:cb3d968589d8 2634 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 2635 #define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */
Kojto 90:cb3d968589d8 2636
Kojto 90:cb3d968589d8 2637 /******************* Bit definition for IWDG_PR register ********************/
Kojto 122:f9eeca106725 2638 #define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 2639 #define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2640 #define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2641 #define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2642
Kojto 90:cb3d968589d8 2643 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 122:f9eeca106725 2644 #define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */
Kojto 90:cb3d968589d8 2645
Kojto 90:cb3d968589d8 2646 /******************* Bit definition for IWDG_SR register ********************/
Kojto 122:f9eeca106725 2647 #define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
Kojto 122:f9eeca106725 2648 #define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
Kojto 90:cb3d968589d8 2649
Kojto 90:cb3d968589d8 2650 /******************************************************************************/
Kojto 90:cb3d968589d8 2651 /* */
Kojto 90:cb3d968589d8 2652 /* LCD Controller (LCD) */
Kojto 90:cb3d968589d8 2653 /* */
Kojto 90:cb3d968589d8 2654 /******************************************************************************/
Kojto 90:cb3d968589d8 2655
Kojto 90:cb3d968589d8 2656 /******************* Bit definition for LCD_CR register *********************/
Kojto 122:f9eeca106725 2657 #define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */
Kojto 122:f9eeca106725 2658 #define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */
Kojto 122:f9eeca106725 2659
Kojto 122:f9eeca106725 2660 #define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */
Kojto 122:f9eeca106725 2661 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */
Kojto 122:f9eeca106725 2662 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */
Kojto 122:f9eeca106725 2663 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */
Kojto 122:f9eeca106725 2664
Kojto 122:f9eeca106725 2665 #define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */
Kojto 122:f9eeca106725 2666 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */
Kojto 122:f9eeca106725 2667 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */
Kojto 122:f9eeca106725 2668
Kojto 122:f9eeca106725 2669 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */
Kojto 90:cb3d968589d8 2670
Kojto 90:cb3d968589d8 2671 /******************* Bit definition for LCD_FCR register ********************/
Kojto 122:f9eeca106725 2672 #define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */
Kojto 122:f9eeca106725 2673 #define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */
Kojto 122:f9eeca106725 2674 #define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */
Kojto 122:f9eeca106725 2675
Kojto 122:f9eeca106725 2676 #define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */
Kojto 122:f9eeca106725 2677 #define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2678 #define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2679 #define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
Kojto 122:f9eeca106725 2680
Kojto 122:f9eeca106725 2681 #define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */
Kojto 122:f9eeca106725 2682 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2683 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2684 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */
Kojto 122:f9eeca106725 2685
Kojto 122:f9eeca106725 2686 #define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */
Kojto 122:f9eeca106725 2687 #define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2688 #define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2689 #define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 2690
Kojto 122:f9eeca106725 2691 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */
Kojto 122:f9eeca106725 2692 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2693 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2694 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 2695
Kojto 122:f9eeca106725 2696 #define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */
Kojto 122:f9eeca106725 2697 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2698 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2699
Kojto 122:f9eeca106725 2700 #define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */
Kojto 122:f9eeca106725 2701 #define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */
Kojto 90:cb3d968589d8 2702
Kojto 90:cb3d968589d8 2703 /******************* Bit definition for LCD_SR register *********************/
Kojto 122:f9eeca106725 2704 #define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */
Kojto 122:f9eeca106725 2705 #define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */
Kojto 122:f9eeca106725 2706 #define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */
Kojto 122:f9eeca106725 2707 #define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */
Kojto 122:f9eeca106725 2708 #define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */
Kojto 122:f9eeca106725 2709 #define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */
Kojto 90:cb3d968589d8 2710
Kojto 90:cb3d968589d8 2711 /******************* Bit definition for LCD_CLR register ********************/
Kojto 122:f9eeca106725 2712 #define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */
Kojto 122:f9eeca106725 2713 #define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */
Kojto 90:cb3d968589d8 2714
Kojto 90:cb3d968589d8 2715 /******************* Bit definition for LCD_RAM register ********************/
Kojto 122:f9eeca106725 2716 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */
Kojto 90:cb3d968589d8 2717
Kojto 90:cb3d968589d8 2718 /******************************************************************************/
Kojto 90:cb3d968589d8 2719 /* */
Kojto 90:cb3d968589d8 2720 /* Power Control (PWR) */
Kojto 90:cb3d968589d8 2721 /* */
Kojto 90:cb3d968589d8 2722 /******************************************************************************/
Kojto 90:cb3d968589d8 2723
Kojto 122:f9eeca106725 2724 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
Kojto 122:f9eeca106725 2725
Kojto 90:cb3d968589d8 2726 /******************** Bit definition for PWR_CR register ********************/
Kojto 122:f9eeca106725 2727 #define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */
Kojto 122:f9eeca106725 2728 #define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */
Kojto 122:f9eeca106725 2729 #define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */
Kojto 122:f9eeca106725 2730 #define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */
Kojto 122:f9eeca106725 2731 #define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */
Kojto 122:f9eeca106725 2732
Kojto 122:f9eeca106725 2733 #define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 122:f9eeca106725 2734 #define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2735 #define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2736 #define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2737
Kojto 90:cb3d968589d8 2738 /*!< PVD level configuration */
Kojto 122:f9eeca106725 2739 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
Kojto 122:f9eeca106725 2740 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */
Kojto 122:f9eeca106725 2741 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */
Kojto 122:f9eeca106725 2742 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */
Kojto 122:f9eeca106725 2743 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */
Kojto 122:f9eeca106725 2744 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */
Kojto 122:f9eeca106725 2745 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */
Kojto 122:f9eeca106725 2746 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */
Kojto 122:f9eeca106725 2747
Kojto 122:f9eeca106725 2748 #define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */
Kojto 122:f9eeca106725 2749 #define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */
Kojto 122:f9eeca106725 2750 #define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */
Kojto 122:f9eeca106725 2751
Kojto 122:f9eeca106725 2752 #define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */
Kojto 122:f9eeca106725 2753 #define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2754 #define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2755 #define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */
Kojto 90:cb3d968589d8 2756
Kojto 90:cb3d968589d8 2757 /******************* Bit definition for PWR_CSR register ********************/
Kojto 122:f9eeca106725 2758 #define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */
Kojto 122:f9eeca106725 2759 #define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */
Kojto 122:f9eeca106725 2760 #define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */
Kojto 122:f9eeca106725 2761 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */
Kojto 122:f9eeca106725 2762 #define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */
Kojto 122:f9eeca106725 2763 #define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */
Kojto 122:f9eeca106725 2764
Kojto 122:f9eeca106725 2765 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */
Kojto 122:f9eeca106725 2766 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */
Kojto 122:f9eeca106725 2767 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /*!< Enable WKUP pin 3 */
Kojto 90:cb3d968589d8 2768
Kojto 90:cb3d968589d8 2769 /******************************************************************************/
Kojto 90:cb3d968589d8 2770 /* */
Kojto 90:cb3d968589d8 2771 /* Reset and Clock Control (RCC) */
Kojto 90:cb3d968589d8 2772 /* */
Kojto 90:cb3d968589d8 2773 /******************************************************************************/
Kojto 122:f9eeca106725 2774 /*
Kojto 122:f9eeca106725 2775 * @brief Specific device feature definitions (not present on all devices in the STM32F0 family)
Kojto 122:f9eeca106725 2776 */
Kojto 122:f9eeca106725 2777 #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
Kojto 122:f9eeca106725 2778
Kojto 90:cb3d968589d8 2779 /******************** Bit definition for RCC_CR register ********************/
Kojto 122:f9eeca106725 2780 #define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */
Kojto 122:f9eeca106725 2781 #define RCC_CR_HSIRDY ((uint32_t)0x00000002U) /*!< Internal High Speed clock ready flag */
Kojto 122:f9eeca106725 2782
Kojto 122:f9eeca106725 2783 #define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */
Kojto 122:f9eeca106725 2784 #define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */
Kojto 122:f9eeca106725 2785
Kojto 122:f9eeca106725 2786 #define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */
Kojto 122:f9eeca106725 2787 #define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */
Kojto 122:f9eeca106725 2788 #define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */
Kojto 122:f9eeca106725 2789
Kojto 122:f9eeca106725 2790 #define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */
Kojto 122:f9eeca106725 2791 #define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */
Kojto 122:f9eeca106725 2792 #define RCC_CR_CSSON ((uint32_t)0x10000000U) /*!< Clock Security System enable */
Kojto 122:f9eeca106725 2793
Kojto 122:f9eeca106725 2794 #define RCC_CR_RTCPRE ((uint32_t)0x60000000U) /*!< RTC/LCD Prescaler */
Kojto 122:f9eeca106725 2795 #define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000U) /*!< Bit0 */
Kojto 122:f9eeca106725 2796 #define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000U) /*!< Bit1 */
Kojto 90:cb3d968589d8 2797
Kojto 90:cb3d968589d8 2798 /******************** Bit definition for RCC_ICSCR register *****************/
Kojto 122:f9eeca106725 2799 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */
Kojto 122:f9eeca106725 2800 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */
Kojto 122:f9eeca106725 2801
Kojto 122:f9eeca106725 2802 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */
Kojto 122:f9eeca106725 2803 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */
Kojto 122:f9eeca106725 2804 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */
Kojto 122:f9eeca106725 2805 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */
Kojto 122:f9eeca106725 2806 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */
Kojto 122:f9eeca106725 2807 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */
Kojto 122:f9eeca106725 2808 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */
Kojto 122:f9eeca106725 2809 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */
Kojto 122:f9eeca106725 2810 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */
Kojto 122:f9eeca106725 2811 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */
Kojto 90:cb3d968589d8 2812
Kojto 90:cb3d968589d8 2813 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 122:f9eeca106725 2814 #define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 2815 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2816 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2817
Kojto 90:cb3d968589d8 2818 /*!< SW configuration */
Kojto 122:f9eeca106725 2819 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */
Kojto 122:f9eeca106725 2820 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 2821 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 2822 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */
Kojto 122:f9eeca106725 2823
Kojto 122:f9eeca106725 2824 #define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 2825 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2826 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
Kojto 90:cb3d968589d8 2827
Kojto 90:cb3d968589d8 2828 /*!< SWS configuration */
Kojto 122:f9eeca106725 2829 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
Kojto 122:f9eeca106725 2830 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */
Kojto 122:f9eeca106725 2831 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 2832 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
Kojto 122:f9eeca106725 2833
Kojto 122:f9eeca106725 2834 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 2835 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2836 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2837 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
Kojto 122:f9eeca106725 2838 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
Kojto 90:cb3d968589d8 2839
Kojto 90:cb3d968589d8 2840 /*!< HPRE configuration */
Kojto 122:f9eeca106725 2841 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 2842 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 2843 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 2844 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 2845 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 2846 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 2847 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 2848 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 2849 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
Kojto 122:f9eeca106725 2850
Kojto 122:f9eeca106725 2851 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 122:f9eeca106725 2852 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2853 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2854 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2855
Kojto 90:cb3d968589d8 2856 /*!< PPRE1 configuration */
Kojto 122:f9eeca106725 2857 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
Kojto 122:f9eeca106725 2858 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 2859 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 2860 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 2861 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 2862
Kojto 122:f9eeca106725 2863 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 122:f9eeca106725 2864 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2865 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2866 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2867
Kojto 90:cb3d968589d8 2868 /*!< PPRE2 configuration */
Kojto 122:f9eeca106725 2869 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
Kojto 122:f9eeca106725 2870 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 2871 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 2872 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 2873 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
Kojto 90:cb3d968589d8 2874
Kojto 90:cb3d968589d8 2875 /*!< PLL entry clock source*/
Kojto 122:f9eeca106725 2876 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */
Kojto 122:f9eeca106725 2877
Kojto 122:f9eeca106725 2878 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */
Kojto 122:f9eeca106725 2879 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */
Kojto 90:cb3d968589d8 2880
Kojto 90:cb3d968589d8 2881
Kojto 90:cb3d968589d8 2882 /*!< PLLMUL configuration */
Kojto 122:f9eeca106725 2883 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 122:f9eeca106725 2884 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2885 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2886 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 2887 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
Kojto 90:cb3d968589d8 2888
Kojto 90:cb3d968589d8 2889 /*!< PLLMUL configuration */
Kojto 122:f9eeca106725 2890 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */
Kojto 122:f9eeca106725 2891 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */
Kojto 122:f9eeca106725 2892 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */
Kojto 122:f9eeca106725 2893 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */
Kojto 122:f9eeca106725 2894 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */
Kojto 122:f9eeca106725 2895 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */
Kojto 122:f9eeca106725 2896 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */
Kojto 122:f9eeca106725 2897 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */
Kojto 122:f9eeca106725 2898 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */
Kojto 90:cb3d968589d8 2899
Kojto 90:cb3d968589d8 2900 /*!< PLLDIV configuration */
Kojto 122:f9eeca106725 2901 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */
Kojto 122:f9eeca106725 2902 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */
Kojto 122:f9eeca106725 2903 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */
Kojto 90:cb3d968589d8 2904
Kojto 90:cb3d968589d8 2905
Kojto 90:cb3d968589d8 2906 /*!< PLLDIV configuration */
Kojto 122:f9eeca106725 2907 #define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000U) /*!< PLL clock output = CKVCO / 1 */
Kojto 122:f9eeca106725 2908 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */
Kojto 122:f9eeca106725 2909 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */
Kojto 122:f9eeca106725 2910 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */
Kojto 122:f9eeca106725 2911
Kojto 122:f9eeca106725 2912
Kojto 122:f9eeca106725 2913 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000U) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
Kojto 122:f9eeca106725 2914 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 2915 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 2916 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 2917
Kojto 90:cb3d968589d8 2918 /*!< MCO configuration */
Kojto 122:f9eeca106725 2919 #define RCC_CFGR_MCOSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 2920 #define RCC_CFGR_MCOSEL_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected */
Kojto 122:f9eeca106725 2921 #define RCC_CFGR_MCOSEL_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */
Kojto 122:f9eeca106725 2922 #define RCC_CFGR_MCOSEL_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */
Kojto 122:f9eeca106725 2923 #define RCC_CFGR_MCOSEL_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */
Kojto 122:f9eeca106725 2924 #define RCC_CFGR_MCOSEL_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */
Kojto 122:f9eeca106725 2925 #define RCC_CFGR_MCOSEL_LSI ((uint32_t)0x06000000U) /*!< LSI selected */
Kojto 122:f9eeca106725 2926 #define RCC_CFGR_MCOSEL_LSE ((uint32_t)0x07000000U) /*!< LSE selected */
Kojto 122:f9eeca106725 2927
Kojto 122:f9eeca106725 2928 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
Kojto 122:f9eeca106725 2929 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 2930 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 2931 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 2932
Kojto 122:f9eeca106725 2933 /*!< MCO Prescaler configuration */
Kojto 122:f9eeca106725 2934 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
Kojto 122:f9eeca106725 2935 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
Kojto 122:f9eeca106725 2936 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
Kojto 122:f9eeca106725 2937 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
Kojto 122:f9eeca106725 2938 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
Kojto 122:f9eeca106725 2939
Kojto 122:f9eeca106725 2940 /* Legacy aliases */
Kojto 122:f9eeca106725 2941 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1
Kojto 122:f9eeca106725 2942 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
Kojto 122:f9eeca106725 2943 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4
Kojto 122:f9eeca106725 2944 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8
Kojto 122:f9eeca106725 2945 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16
Kojto 122:f9eeca106725 2946 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
Kojto 122:f9eeca106725 2947 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
Kojto 122:f9eeca106725 2948 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
Kojto 122:f9eeca106725 2949 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
Kojto 122:f9eeca106725 2950 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
Kojto 122:f9eeca106725 2951 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
Kojto 122:f9eeca106725 2952 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
Kojto 122:f9eeca106725 2953 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
Kojto 90:cb3d968589d8 2954
Kojto 90:cb3d968589d8 2955 /*!<****************** Bit definition for RCC_CIR register ********************/
Kojto 122:f9eeca106725 2956 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */
Kojto 122:f9eeca106725 2957 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */
Kojto 122:f9eeca106725 2958 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */
Kojto 122:f9eeca106725 2959 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */
Kojto 122:f9eeca106725 2960 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */
Kojto 122:f9eeca106725 2961 #define RCC_CIR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */
Kojto 122:f9eeca106725 2962 #define RCC_CIR_LSECSSF ((uint32_t)0x00000040U) /*!< LSE CSS Interrupt flag */
Kojto 122:f9eeca106725 2963 #define RCC_CIR_CSSF ((uint32_t)0x00000080U) /*!< Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 2964
Kojto 122:f9eeca106725 2965 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100U) /*!< LSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 2966 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200U) /*!< LSE Ready Interrupt Enable */
Kojto 122:f9eeca106725 2967 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400U) /*!< HSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 2968 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800U) /*!< HSE Ready Interrupt Enable */
Kojto 122:f9eeca106725 2969 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000U) /*!< PLL Ready Interrupt Enable */
Kojto 122:f9eeca106725 2970 #define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000U) /*!< MSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 2971 #define RCC_CIR_LSECSSIE ((uint32_t)0x00004000U) /*!< LSE CSS Interrupt Enable */
Kojto 122:f9eeca106725 2972
Kojto 122:f9eeca106725 2973 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000U) /*!< LSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 2974 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000U) /*!< LSE Ready Interrupt Clear */
Kojto 122:f9eeca106725 2975 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000U) /*!< HSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 2976 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000U) /*!< HSE Ready Interrupt Clear */
Kojto 122:f9eeca106725 2977 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000U) /*!< PLL Ready Interrupt Clear */
Kojto 122:f9eeca106725 2978 #define RCC_CIR_MSIRDYC ((uint32_t)0x00200000U) /*!< MSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 2979 #define RCC_CIR_LSECSSC ((uint32_t)0x00400000U) /*!< LSE CSS Interrupt Clear */
Kojto 122:f9eeca106725 2980 #define RCC_CIR_CSSC ((uint32_t)0x00800000U) /*!< Clock Security System Interrupt Clear */
Kojto 90:cb3d968589d8 2981
Kojto 90:cb3d968589d8 2982 /***************** Bit definition for RCC_AHBRSTR register ******************/
Kojto 122:f9eeca106725 2983 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */
Kojto 122:f9eeca106725 2984 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */
Kojto 122:f9eeca106725 2985 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */
Kojto 122:f9eeca106725 2986 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */
Kojto 122:f9eeca106725 2987 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010U) /*!< GPIO port E reset */
Kojto 122:f9eeca106725 2988 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020U) /*!< GPIO port H reset */
Kojto 122:f9eeca106725 2989 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040U) /*!< GPIO port F reset */
Kojto 122:f9eeca106725 2990 #define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080U) /*!< GPIO port G reset */
Kojto 122:f9eeca106725 2991 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */
Kojto 122:f9eeca106725 2992 #define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000U) /*!< FLITF reset */
Kojto 122:f9eeca106725 2993 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000U) /*!< DMA1 reset */
Kojto 122:f9eeca106725 2994 #define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000U) /*!< DMA2 reset */
Kojto 90:cb3d968589d8 2995
Kojto 90:cb3d968589d8 2996 /***************** Bit definition for RCC_APB2RSTR register *****************/
Kojto 122:f9eeca106725 2997 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< System Configuration SYSCFG reset */
Kojto 122:f9eeca106725 2998 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004U) /*!< TIM9 reset */
Kojto 122:f9eeca106725 2999 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008U) /*!< TIM10 reset */
Kojto 122:f9eeca106725 3000 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010U) /*!< TIM11 reset */
Kojto 122:f9eeca106725 3001 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200U) /*!< ADC1 reset */
Kojto 122:f9eeca106725 3002 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 reset */
Kojto 122:f9eeca106725 3003 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 reset */
Kojto 90:cb3d968589d8 3004
Kojto 90:cb3d968589d8 3005 /***************** Bit definition for RCC_APB1RSTR register *****************/
Kojto 122:f9eeca106725 3006 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 reset */
Kojto 122:f9eeca106725 3007 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002U) /*!< Timer 3 reset */
Kojto 122:f9eeca106725 3008 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004U) /*!< Timer 4 reset */
Kojto 122:f9eeca106725 3009 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008U) /*!< Timer 5 reset */
Kojto 122:f9eeca106725 3010 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 reset */
Kojto 122:f9eeca106725 3011 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020U) /*!< Timer 7 reset */
Kojto 122:f9eeca106725 3012 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD reset */
Kojto 122:f9eeca106725 3013 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog reset */
Kojto 122:f9eeca106725 3014 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI 2 reset */
Kojto 122:f9eeca106725 3015 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000U) /*!< SPI 3 reset */
Kojto 122:f9eeca106725 3016 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 reset */
Kojto 122:f9eeca106725 3017 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000U) /*!< USART 3 reset */
Kojto 122:f9eeca106725 3018 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000U) /*!< UART 4 reset */
Kojto 122:f9eeca106725 3019 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000U) /*!< UART 5 reset */
Kojto 122:f9eeca106725 3020 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 reset */
Kojto 122:f9eeca106725 3021 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 reset */
Kojto 122:f9eeca106725 3022 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB reset */
Kojto 122:f9eeca106725 3023 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< Power interface reset */
Kojto 122:f9eeca106725 3024 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC interface reset */
Kojto 122:f9eeca106725 3025 #define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000U) /*!< Comparator interface reset */
Kojto 90:cb3d968589d8 3026
Kojto 90:cb3d968589d8 3027 /****************** Bit definition for RCC_AHBENR register ******************/
Kojto 122:f9eeca106725 3028 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */
Kojto 122:f9eeca106725 3029 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */
Kojto 122:f9eeca106725 3030 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */
Kojto 122:f9eeca106725 3031 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */
Kojto 122:f9eeca106725 3032 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enable */
Kojto 122:f9eeca106725 3033 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020U) /*!< GPIO port H clock enable */
Kojto 122:f9eeca106725 3034 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040U) /*!< GPIO port F clock enable */
Kojto 122:f9eeca106725 3035 #define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080U) /*!< GPIO port G clock enable */
Kojto 122:f9eeca106725 3036 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */
Kojto 122:f9eeca106725 3037 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000U) /*!< FLITF clock enable (has effect only when
Kojto 90:cb3d968589d8 3038 the Flash memory is in power down mode) */
Kojto 122:f9eeca106725 3039 #define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000U) /*!< DMA1 clock enable */
Kojto 122:f9eeca106725 3040 #define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000U) /*!< DMA2 clock enable */
Kojto 90:cb3d968589d8 3041
Kojto 90:cb3d968589d8 3042 /****************** Bit definition for RCC_APB2ENR register *****************/
Kojto 122:f9eeca106725 3043 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< System Configuration SYSCFG clock enable */
Kojto 122:f9eeca106725 3044 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004U) /*!< TIM9 interface clock enable */
Kojto 122:f9eeca106725 3045 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008U) /*!< TIM10 interface clock enable */
Kojto 122:f9eeca106725 3046 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010U) /*!< TIM11 Timer clock enable */
Kojto 122:f9eeca106725 3047 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */
Kojto 122:f9eeca106725 3048 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */
Kojto 122:f9eeca106725 3049 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */
Kojto 90:cb3d968589d8 3050
Kojto 90:cb3d968589d8 3051 /***************** Bit definition for RCC_APB1ENR register ******************/
Kojto 122:f9eeca106725 3052 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled*/
Kojto 122:f9eeca106725 3053 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002U) /*!< Timer 3 clock enable */
Kojto 122:f9eeca106725 3054 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004U) /*!< Timer 4 clock enable */
Kojto 122:f9eeca106725 3055 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008U) /*!< Timer 5 clock enable */
Kojto 122:f9eeca106725 3056 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */
Kojto 122:f9eeca106725 3057 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020U) /*!< Timer 7 clock enable */
Kojto 122:f9eeca106725 3058 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */
Kojto 122:f9eeca106725 3059 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */
Kojto 122:f9eeca106725 3060 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI 2 clock enable */
Kojto 122:f9eeca106725 3061 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000U) /*!< SPI 3 clock enable */
Kojto 122:f9eeca106725 3062 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART 2 clock enable */
Kojto 122:f9eeca106725 3063 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000U) /*!< USART 3 clock enable */
Kojto 122:f9eeca106725 3064 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000U) /*!< UART 4 clock enable */
Kojto 122:f9eeca106725 3065 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000U) /*!< UART 5 clock enable */
Kojto 122:f9eeca106725 3066 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C 1 clock enable */
Kojto 122:f9eeca106725 3067 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C 2 clock enable */
Kojto 122:f9eeca106725 3068 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */
Kojto 122:f9eeca106725 3069 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< Power interface clock enable */
Kojto 122:f9eeca106725 3070 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC interface clock enable */
Kojto 122:f9eeca106725 3071 #define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000U) /*!< Comparator interface clock enable */
Kojto 90:cb3d968589d8 3072
Kojto 90:cb3d968589d8 3073 /****************** Bit definition for RCC_AHBLPENR register ****************/
Kojto 122:f9eeca106725 3074 #define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */
Kojto 122:f9eeca106725 3075 #define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */
Kojto 122:f9eeca106725 3076 #define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */
Kojto 122:f9eeca106725 3077 #define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */
Kojto 122:f9eeca106725 3078 #define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010U) /*!< GPIO port E clock enabled in sleep mode */
Kojto 122:f9eeca106725 3079 #define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020U) /*!< GPIO port H clock enabled in sleep mode */
Kojto 122:f9eeca106725 3080 #define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040U) /*!< GPIO port F clock enabled in sleep mode */
Kojto 122:f9eeca106725 3081 #define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080U) /*!< GPIO port G clock enabled in sleep mode */
Kojto 122:f9eeca106725 3082 #define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */
Kojto 122:f9eeca106725 3083 #define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000U) /*!< Flash Interface clock enabled in sleep mode
Kojto 90:cb3d968589d8 3084 (has effect only when the Flash memory is
Kojto 90:cb3d968589d8 3085 in power down mode) */
Kojto 122:f9eeca106725 3086 #define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000U) /*!< SRAM clock enabled in sleep mode */
Kojto 122:f9eeca106725 3087 #define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000U) /*!< DMA1 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3088 #define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000U) /*!< DMA2 clock enabled in sleep mode */
Kojto 90:cb3d968589d8 3089
Kojto 90:cb3d968589d8 3090 /****************** Bit definition for RCC_APB2LPENR register ***************/
Kojto 122:f9eeca106725 3091 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001U) /*!< System Configuration SYSCFG clock enabled in sleep mode */
Kojto 122:f9eeca106725 3092 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004U) /*!< TIM9 interface clock enabled in sleep mode */
Kojto 122:f9eeca106725 3093 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008U) /*!< TIM10 interface clock enabled in sleep mode */
Kojto 122:f9eeca106725 3094 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010U) /*!< TIM11 Timer clock enabled in sleep mode */
Kojto 122:f9eeca106725 3095 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3096 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3097 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */
Kojto 90:cb3d968589d8 3098
Kojto 90:cb3d968589d8 3099 /***************** Bit definition for RCC_APB1LPENR register ****************/
Kojto 122:f9eeca106725 3100 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3101 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002U) /*!< Timer 3 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3102 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004U) /*!< Timer 4 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3103 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008U) /*!< Timer 5 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3104 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3105 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020U) /*!< Timer 7 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3106 #define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */
Kojto 122:f9eeca106725 3107 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */
Kojto 122:f9eeca106725 3108 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000U) /*!< SPI 2 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3109 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000U) /*!< SPI 3 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3110 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000U) /*!< USART 2 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3111 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000U) /*!< USART 3 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3112 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000U) /*!< UART 4 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3113 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000U) /*!< UART 5 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3114 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000U) /*!< I2C 1 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3115 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000U) /*!< I2C 2 clock enabled in sleep mode */
Kojto 122:f9eeca106725 3116 #define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */
Kojto 122:f9eeca106725 3117 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000U) /*!< Power interface clock enabled in sleep mode */
Kojto 122:f9eeca106725 3118 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000U) /*!< DAC interface clock enabled in sleep mode */
Kojto 122:f9eeca106725 3119 #define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000U) /*!< Comparator interface clock enabled in sleep mode*/
Kojto 90:cb3d968589d8 3120
Kojto 90:cb3d968589d8 3121 /******************* Bit definition for RCC_CSR register ********************/
Kojto 122:f9eeca106725 3122 #define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */
Kojto 122:f9eeca106725 3123 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */
Kojto 122:f9eeca106725 3124
Kojto 122:f9eeca106725 3125 #define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */
Kojto 122:f9eeca106725 3126 #define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */
Kojto 122:f9eeca106725 3127 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */
Kojto 122:f9eeca106725 3128
Kojto 122:f9eeca106725 3129 #define RCC_CSR_LSECSSON ((uint32_t)0x00000800U) /*!< External Low Speed oscillator CSS Enable */
Kojto 122:f9eeca106725 3130 #define RCC_CSR_LSECSSD ((uint32_t)0x00001000U) /*!< External Low Speed oscillator CSS Detected */
Kojto 122:f9eeca106725 3131
Kojto 122:f9eeca106725 3132 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 122:f9eeca106725 3133 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3134 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3135
Kojto 90:cb3d968589d8 3136 /*!< RTC congiguration */
Kojto 122:f9eeca106725 3137 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 3138 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 3139 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 3140 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
Kojto 122:f9eeca106725 3141
Kojto 122:f9eeca106725 3142 #define RCC_CSR_RTCEN ((uint32_t)0x00400000U) /*!< RTC clock enable */
Kojto 122:f9eeca106725 3143 #define RCC_CSR_RTCRST ((uint32_t)0x00800000U) /*!< RTC reset */
Kojto 90:cb3d968589d8 3144
Kojto 122:f9eeca106725 3145 #define RCC_CSR_RMVF ((uint32_t)0x01000000U) /*!< Remove reset flag */
Kojto 122:f9eeca106725 3146 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< Option Bytes Loader reset flag */
Kojto 122:f9eeca106725 3147 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */
Kojto 122:f9eeca106725 3148 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */
Kojto 122:f9eeca106725 3149 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */
Kojto 122:f9eeca106725 3150 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */
Kojto 122:f9eeca106725 3151 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */
Kojto 122:f9eeca106725 3152 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */
Kojto 90:cb3d968589d8 3153
Kojto 90:cb3d968589d8 3154 /******************************************************************************/
Kojto 90:cb3d968589d8 3155 /* */
Kojto 90:cb3d968589d8 3156 /* Real-Time Clock (RTC) */
Kojto 90:cb3d968589d8 3157 /* */
Kojto 90:cb3d968589d8 3158 /******************************************************************************/
Kojto 122:f9eeca106725 3159 /*
Kojto 122:f9eeca106725 3160 * @brief Specific device feature definitions (not present on all devices in the STM32F0 family)
Kojto 122:f9eeca106725 3161 */
Kojto 122:f9eeca106725 3162 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
Kojto 122:f9eeca106725 3163 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
Kojto 122:f9eeca106725 3164 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
Kojto 122:f9eeca106725 3165 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
Kojto 122:f9eeca106725 3166 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
Kojto 122:f9eeca106725 3167 #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */
Kojto 122:f9eeca106725 3168 #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */
Kojto 122:f9eeca106725 3169
Kojto 90:cb3d968589d8 3170 /******************** Bits definition for RTC_TR register *******************/
Kojto 122:f9eeca106725 3171 #define RTC_TR_PM ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 3172 #define RTC_TR_HT ((uint32_t)0x00300000U)
Kojto 122:f9eeca106725 3173 #define RTC_TR_HT_0 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 3174 #define RTC_TR_HT_1 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 3175 #define RTC_TR_HU ((uint32_t)0x000F0000U)
Kojto 122:f9eeca106725 3176 #define RTC_TR_HU_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 3177 #define RTC_TR_HU_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 3178 #define RTC_TR_HU_2 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 3179 #define RTC_TR_HU_3 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 3180 #define RTC_TR_MNT ((uint32_t)0x00007000U)
Kojto 122:f9eeca106725 3181 #define RTC_TR_MNT_0 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3182 #define RTC_TR_MNT_1 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3183 #define RTC_TR_MNT_2 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3184 #define RTC_TR_MNU ((uint32_t)0x00000F00U)
Kojto 122:f9eeca106725 3185 #define RTC_TR_MNU_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3186 #define RTC_TR_MNU_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3187 #define RTC_TR_MNU_2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3188 #define RTC_TR_MNU_3 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3189 #define RTC_TR_ST ((uint32_t)0x00000070U)
Kojto 122:f9eeca106725 3190 #define RTC_TR_ST_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3191 #define RTC_TR_ST_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3192 #define RTC_TR_ST_2 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 3193 #define RTC_TR_SU ((uint32_t)0x0000000FU)
Kojto 122:f9eeca106725 3194 #define RTC_TR_SU_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 3195 #define RTC_TR_SU_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3196 #define RTC_TR_SU_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3197 #define RTC_TR_SU_3 ((uint32_t)0x00000008U)
Kojto 90:cb3d968589d8 3198
Kojto 90:cb3d968589d8 3199 /******************** Bits definition for RTC_DR register *******************/
Kojto 122:f9eeca106725 3200 #define RTC_DR_YT ((uint32_t)0x00F00000U)
Kojto 122:f9eeca106725 3201 #define RTC_DR_YT_0 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 3202 #define RTC_DR_YT_1 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 3203 #define RTC_DR_YT_2 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 3204 #define RTC_DR_YT_3 ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 3205 #define RTC_DR_YU ((uint32_t)0x000F0000U)
Kojto 122:f9eeca106725 3206 #define RTC_DR_YU_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 3207 #define RTC_DR_YU_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 3208 #define RTC_DR_YU_2 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 3209 #define RTC_DR_YU_3 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 3210 #define RTC_DR_WDU ((uint32_t)0x0000E000U)
Kojto 122:f9eeca106725 3211 #define RTC_DR_WDU_0 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3212 #define RTC_DR_WDU_1 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3213 #define RTC_DR_WDU_2 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 3214 #define RTC_DR_MT ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3215 #define RTC_DR_MU ((uint32_t)0x00000F00U)
Kojto 122:f9eeca106725 3216 #define RTC_DR_MU_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3217 #define RTC_DR_MU_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3218 #define RTC_DR_MU_2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3219 #define RTC_DR_MU_3 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3220 #define RTC_DR_DT ((uint32_t)0x00000030U)
Kojto 122:f9eeca106725 3221 #define RTC_DR_DT_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3222 #define RTC_DR_DT_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3223 #define RTC_DR_DU ((uint32_t)0x0000000FU)
Kojto 122:f9eeca106725 3224 #define RTC_DR_DU_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 3225 #define RTC_DR_DU_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3226 #define RTC_DR_DU_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3227 #define RTC_DR_DU_3 ((uint32_t)0x00000008U)
Kojto 90:cb3d968589d8 3228
Kojto 90:cb3d968589d8 3229 /******************** Bits definition for RTC_CR register *******************/
Kojto 122:f9eeca106725 3230 #define RTC_CR_COE ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 3231 #define RTC_CR_OSEL ((uint32_t)0x00600000U)
Kojto 122:f9eeca106725 3232 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 3233 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 3234 #define RTC_CR_POL ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 3235 #define RTC_CR_COSEL ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 3236 #define RTC_CR_BCK ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 3237 #define RTC_CR_SUB1H ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 3238 #define RTC_CR_ADD1H ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 3239 #define RTC_CR_TSIE ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 3240 #define RTC_CR_WUTIE ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3241 #define RTC_CR_ALRBIE ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3242 #define RTC_CR_ALRAIE ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3243 #define RTC_CR_TSE ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3244 #define RTC_CR_WUTE ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3245 #define RTC_CR_ALRBE ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3246 #define RTC_CR_ALRAE ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3247 #define RTC_CR_DCE ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 3248 #define RTC_CR_FMT ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 3249 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3250 #define RTC_CR_REFCKON ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3251 #define RTC_CR_TSEDGE ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 3252 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007U)
Kojto 122:f9eeca106725 3253 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 3254 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3255 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U)
Kojto 90:cb3d968589d8 3256
Kojto 90:cb3d968589d8 3257 /******************** Bits definition for RTC_ISR register ******************/
Kojto 122:f9eeca106725 3258 #define RTC_ISR_RECALPF ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 3259 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 3260 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3261 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3262 #define RTC_ISR_TSOVF ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3263 #define RTC_ISR_TSF ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3264 #define RTC_ISR_WUTF ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3265 #define RTC_ISR_ALRBF ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3266 #define RTC_ISR_ALRAF ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3267 #define RTC_ISR_INIT ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 3268 #define RTC_ISR_INITF ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 3269 #define RTC_ISR_RSF ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3270 #define RTC_ISR_INITS ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3271 #define RTC_ISR_SHPF ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 3272 #define RTC_ISR_WUTWF ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3273 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3274 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001U)
Kojto 90:cb3d968589d8 3275
Kojto 90:cb3d968589d8 3276 /******************** Bits definition for RTC_PRER register *****************/
Kojto 122:f9eeca106725 3277 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U)
Kojto 122:f9eeca106725 3278 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU)
Kojto 90:cb3d968589d8 3279
Kojto 90:cb3d968589d8 3280 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 122:f9eeca106725 3281 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
Kojto 90:cb3d968589d8 3282
Kojto 90:cb3d968589d8 3283 /******************** Bits definition for RTC_CALIBR register ***************/
Kojto 122:f9eeca106725 3284 #define RTC_CALIBR_DCS ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 3285 #define RTC_CALIBR_DC ((uint32_t)0x0000001FU)
Kojto 90:cb3d968589d8 3286
Kojto 90:cb3d968589d8 3287 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 122:f9eeca106725 3288 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U)
Kojto 122:f9eeca106725 3289 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U)
Kojto 122:f9eeca106725 3290 #define RTC_ALRMAR_DT ((uint32_t)0x30000000U)
Kojto 122:f9eeca106725 3291 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 3292 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U)
Kojto 122:f9eeca106725 3293 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000U)
Kojto 122:f9eeca106725 3294 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 3295 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 3296 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 3297 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 3298 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 3299 #define RTC_ALRMAR_PM ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 3300 #define RTC_ALRMAR_HT ((uint32_t)0x00300000U)
Kojto 122:f9eeca106725 3301 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 3302 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 3303 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000U)
Kojto 122:f9eeca106725 3304 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 3305 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 3306 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 3307 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 3308 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 3309 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000U)
Kojto 122:f9eeca106725 3310 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3311 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3312 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3313 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U)
Kojto 122:f9eeca106725 3314 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3315 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3316 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3317 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3318 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 3319 #define RTC_ALRMAR_ST ((uint32_t)0x00000070U)
Kojto 122:f9eeca106725 3320 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3321 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3322 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 3323 #define RTC_ALRMAR_SU ((uint32_t)0x0000000FU)
Kojto 122:f9eeca106725 3324 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 3325 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3326 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3327 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U)
Kojto 90:cb3d968589d8 3328
Kojto 90:cb3d968589d8 3329 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 122:f9eeca106725 3330 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U)
Kojto 122:f9eeca106725 3331 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U)
Kojto 122:f9eeca106725 3332 #define RTC_ALRMBR_DT ((uint32_t)0x30000000U)
Kojto 122:f9eeca106725 3333 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 3334 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U)
Kojto 122:f9eeca106725 3335 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000U)
Kojto 122:f9eeca106725 3336 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 3337 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 3338 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 3339 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 3340 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 3341 #define RTC_ALRMBR_PM ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 3342 #define RTC_ALRMBR_HT ((uint32_t)0x00300000U)
Kojto 122:f9eeca106725 3343 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 3344 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 3345 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000U)
Kojto 122:f9eeca106725 3346 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 3347 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 3348 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 3349 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 3350 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 3351 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000U)
Kojto 122:f9eeca106725 3352 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3353 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3354 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3355 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U)
Kojto 122:f9eeca106725 3356 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3357 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3358 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3359 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3360 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 3361 #define RTC_ALRMBR_ST ((uint32_t)0x00000070U)
Kojto 122:f9eeca106725 3362 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3363 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3364 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 3365 #define RTC_ALRMBR_SU ((uint32_t)0x0000000FU)
Kojto 122:f9eeca106725 3366 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 3367 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3368 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3369 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U)
Kojto 90:cb3d968589d8 3370
Kojto 90:cb3d968589d8 3371 /******************** Bits definition for RTC_WPR register ******************/
Kojto 122:f9eeca106725 3372 #define RTC_WPR_KEY ((uint32_t)0x000000FFU)
Kojto 90:cb3d968589d8 3373
Kojto 90:cb3d968589d8 3374 /******************** Bits definition for RTC_SSR register ******************/
Kojto 122:f9eeca106725 3375 #define RTC_SSR_SS ((uint32_t)0x0000FFFFU)
Kojto 90:cb3d968589d8 3376
Kojto 90:cb3d968589d8 3377 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 122:f9eeca106725 3378 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU)
Kojto 122:f9eeca106725 3379 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U)
Kojto 90:cb3d968589d8 3380
Kojto 90:cb3d968589d8 3381 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 122:f9eeca106725 3382 #define RTC_TSTR_PM ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 3383 #define RTC_TSTR_HT ((uint32_t)0x00300000U)
Kojto 122:f9eeca106725 3384 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 3385 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 3386 #define RTC_TSTR_HU ((uint32_t)0x000F0000U)
Kojto 122:f9eeca106725 3387 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 3388 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 3389 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 3390 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 3391 #define RTC_TSTR_MNT ((uint32_t)0x00007000U)
Kojto 122:f9eeca106725 3392 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3393 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3394 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3395 #define RTC_TSTR_MNU ((uint32_t)0x00000F00U)
Kojto 122:f9eeca106725 3396 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3397 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3398 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3399 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3400 #define RTC_TSTR_ST ((uint32_t)0x00000070U)
Kojto 122:f9eeca106725 3401 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3402 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3403 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 3404 #define RTC_TSTR_SU ((uint32_t)0x0000000FU)
Kojto 122:f9eeca106725 3405 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 3406 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3407 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3408 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008U)
Kojto 90:cb3d968589d8 3409
Kojto 90:cb3d968589d8 3410 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 122:f9eeca106725 3411 #define RTC_TSDR_WDU ((uint32_t)0x0000E000U)
Kojto 122:f9eeca106725 3412 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3413 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3414 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 3415 #define RTC_TSDR_MT ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3416 #define RTC_TSDR_MU ((uint32_t)0x00000F00U)
Kojto 122:f9eeca106725 3417 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3418 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3419 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3420 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3421 #define RTC_TSDR_DT ((uint32_t)0x00000030U)
Kojto 122:f9eeca106725 3422 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3423 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3424 #define RTC_TSDR_DU ((uint32_t)0x0000000FU)
Kojto 122:f9eeca106725 3425 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 3426 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3427 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3428 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008U)
Kojto 90:cb3d968589d8 3429
Kojto 90:cb3d968589d8 3430 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 122:f9eeca106725 3431 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
Kojto 90:cb3d968589d8 3432
Kojto 90:cb3d968589d8 3433 /******************** Bits definition for RTC_CAL register *****************/
Kojto 122:f9eeca106725 3434 #define RTC_CALR_CALP ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 3435 #define RTC_CALR_CALW8 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3436 #define RTC_CALR_CALW16 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3437 #define RTC_CALR_CALM ((uint32_t)0x000001FFU)
Kojto 122:f9eeca106725 3438 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 3439 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3440 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3441 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 3442 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3443 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3444 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 3445 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 3446 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100U)
Kojto 90:cb3d968589d8 3447
Kojto 90:cb3d968589d8 3448 /******************** Bits definition for RTC_TAFCR register ****************/
Kojto 122:f9eeca106725 3449 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 3450 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 3451 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000U)
Kojto 122:f9eeca106725 3452 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 3453 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 3454 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800U)
Kojto 122:f9eeca106725 3455 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 3456 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 3457 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700U)
Kojto 122:f9eeca106725 3458 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 3459 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 3460 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 3461 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 3462 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 3463 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 3464 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 3465 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 3466 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 3467 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 3468 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001U)
Kojto 90:cb3d968589d8 3469
Kojto 90:cb3d968589d8 3470 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 122:f9eeca106725 3471 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
Kojto 122:f9eeca106725 3472 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 3473 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 3474 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 3475 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 3476 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
Kojto 90:cb3d968589d8 3477
Kojto 90:cb3d968589d8 3478 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 122:f9eeca106725 3479 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
Kojto 122:f9eeca106725 3480 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 3481 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 3482 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 3483 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 3484 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
Kojto 90:cb3d968589d8 3485
Kojto 90:cb3d968589d8 3486 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 122:f9eeca106725 3487 #define RTC_BKP0R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3488
Kojto 90:cb3d968589d8 3489 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 122:f9eeca106725 3490 #define RTC_BKP1R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3491
Kojto 90:cb3d968589d8 3492 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 122:f9eeca106725 3493 #define RTC_BKP2R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3494
Kojto 90:cb3d968589d8 3495 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 122:f9eeca106725 3496 #define RTC_BKP3R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3497
Kojto 90:cb3d968589d8 3498 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 122:f9eeca106725 3499 #define RTC_BKP4R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3500
Kojto 90:cb3d968589d8 3501 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 122:f9eeca106725 3502 #define RTC_BKP5R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3503
Kojto 90:cb3d968589d8 3504 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 122:f9eeca106725 3505 #define RTC_BKP6R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3506
Kojto 90:cb3d968589d8 3507 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 122:f9eeca106725 3508 #define RTC_BKP7R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3509
Kojto 90:cb3d968589d8 3510 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 122:f9eeca106725 3511 #define RTC_BKP8R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3512
Kojto 90:cb3d968589d8 3513 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 122:f9eeca106725 3514 #define RTC_BKP9R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3515
Kojto 90:cb3d968589d8 3516 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 122:f9eeca106725 3517 #define RTC_BKP10R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3518
Kojto 90:cb3d968589d8 3519 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 122:f9eeca106725 3520 #define RTC_BKP11R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3521
Kojto 90:cb3d968589d8 3522 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 122:f9eeca106725 3523 #define RTC_BKP12R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3524
Kojto 90:cb3d968589d8 3525 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 122:f9eeca106725 3526 #define RTC_BKP13R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3527
Kojto 90:cb3d968589d8 3528 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 122:f9eeca106725 3529 #define RTC_BKP14R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3530
Kojto 90:cb3d968589d8 3531 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 122:f9eeca106725 3532 #define RTC_BKP15R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3533
Kojto 90:cb3d968589d8 3534 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 122:f9eeca106725 3535 #define RTC_BKP16R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3536
Kojto 90:cb3d968589d8 3537 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 122:f9eeca106725 3538 #define RTC_BKP17R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3539
Kojto 90:cb3d968589d8 3540 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 122:f9eeca106725 3541 #define RTC_BKP18R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3542
Kojto 90:cb3d968589d8 3543 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 122:f9eeca106725 3544 #define RTC_BKP19R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3545
Kojto 90:cb3d968589d8 3546 /******************** Bits definition for RTC_BKP20R register ***************/
Kojto 122:f9eeca106725 3547 #define RTC_BKP20R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3548
Kojto 90:cb3d968589d8 3549 /******************** Bits definition for RTC_BKP21R register ***************/
Kojto 122:f9eeca106725 3550 #define RTC_BKP21R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3551
Kojto 90:cb3d968589d8 3552 /******************** Bits definition for RTC_BKP22R register ***************/
Kojto 122:f9eeca106725 3553 #define RTC_BKP22R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3554
Kojto 90:cb3d968589d8 3555 /******************** Bits definition for RTC_BKP23R register ***************/
Kojto 122:f9eeca106725 3556 #define RTC_BKP23R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3557
Kojto 90:cb3d968589d8 3558 /******************** Bits definition for RTC_BKP24R register ***************/
Kojto 122:f9eeca106725 3559 #define RTC_BKP24R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3560
Kojto 90:cb3d968589d8 3561 /******************** Bits definition for RTC_BKP25R register ***************/
Kojto 122:f9eeca106725 3562 #define RTC_BKP25R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3563
Kojto 90:cb3d968589d8 3564 /******************** Bits definition for RTC_BKP26R register ***************/
Kojto 122:f9eeca106725 3565 #define RTC_BKP26R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3566
Kojto 90:cb3d968589d8 3567 /******************** Bits definition for RTC_BKP27R register ***************/
Kojto 122:f9eeca106725 3568 #define RTC_BKP27R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3569
Kojto 90:cb3d968589d8 3570 /******************** Bits definition for RTC_BKP28R register ***************/
Kojto 122:f9eeca106725 3571 #define RTC_BKP28R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3572
Kojto 90:cb3d968589d8 3573 /******************** Bits definition for RTC_BKP29R register ***************/
Kojto 122:f9eeca106725 3574 #define RTC_BKP29R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3575
Kojto 90:cb3d968589d8 3576 /******************** Bits definition for RTC_BKP30R register ***************/
Kojto 122:f9eeca106725 3577 #define RTC_BKP30R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3578
Kojto 90:cb3d968589d8 3579 /******************** Bits definition for RTC_BKP31R register ***************/
Kojto 122:f9eeca106725 3580 #define RTC_BKP31R ((uint32_t)0xFFFFFFFFU)
Kojto 90:cb3d968589d8 3581
Kojto 90:cb3d968589d8 3582 /******************** Number of backup registers ******************************/
Kojto 90:cb3d968589d8 3583 #define RTC_BKP_NUMBER 32
Kojto 90:cb3d968589d8 3584
Kojto 90:cb3d968589d8 3585 /******************************************************************************/
Kojto 90:cb3d968589d8 3586 /* */
Kojto 90:cb3d968589d8 3587 /* Serial Peripheral Interface (SPI) */
Kojto 90:cb3d968589d8 3588 /* */
Kojto 90:cb3d968589d8 3589 /******************************************************************************/
Kojto 90:cb3d968589d8 3590
Kojto 122:f9eeca106725 3591 /*
Kojto 122:f9eeca106725 3592 * @brief Specific device feature definitions (not present on all devices in the STM32F3 family)
Kojto 122:f9eeca106725 3593 */
Kojto 122:f9eeca106725 3594 #define SPI_I2S_SUPPORT
Kojto 122:f9eeca106725 3595
Kojto 90:cb3d968589d8 3596 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 122:f9eeca106725 3597 #define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */
Kojto 122:f9eeca106725 3598 #define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */
Kojto 122:f9eeca106725 3599 #define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */
Kojto 122:f9eeca106725 3600
Kojto 122:f9eeca106725 3601 #define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 3602 #define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3603 #define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3604 #define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
Kojto 122:f9eeca106725 3605
Kojto 122:f9eeca106725 3606 #define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */
Kojto 122:f9eeca106725 3607 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */
Kojto 122:f9eeca106725 3608 #define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */
Kojto 122:f9eeca106725 3609 #define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */
Kojto 122:f9eeca106725 3610 #define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */
Kojto 122:f9eeca106725 3611 #define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */
Kojto 122:f9eeca106725 3612 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */
Kojto 122:f9eeca106725 3613 #define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */
Kojto 122:f9eeca106725 3614 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */
Kojto 122:f9eeca106725 3615 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */
Kojto 90:cb3d968589d8 3616
Kojto 90:cb3d968589d8 3617 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 122:f9eeca106725 3618 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 3619 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 3620 #define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
Kojto 122:f9eeca106725 3621 #define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame format */
Kojto 122:f9eeca106725 3622 #define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 3623 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 3624 #define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
Kojto 90:cb3d968589d8 3625
Kojto 90:cb3d968589d8 3626 /******************** Bit definition for SPI_SR register ********************/
Kojto 122:f9eeca106725 3627 #define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
Kojto 122:f9eeca106725 3628 #define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
Kojto 122:f9eeca106725 3629 #define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
Kojto 122:f9eeca106725 3630 #define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
Kojto 122:f9eeca106725 3631 #define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
Kojto 122:f9eeca106725 3632 #define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
Kojto 122:f9eeca106725 3633 #define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
Kojto 122:f9eeca106725 3634 #define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
Kojto 122:f9eeca106725 3635 #define SPI_SR_FRE ((uint32_t)0x00000100U) /*!<Frame format error flag */
Kojto 90:cb3d968589d8 3636
Kojto 90:cb3d968589d8 3637 /******************** Bit definition for SPI_DR register ********************/
Kojto 122:f9eeca106725 3638 #define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */
Kojto 90:cb3d968589d8 3639
Kojto 90:cb3d968589d8 3640 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 122:f9eeca106725 3641 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */
Kojto 90:cb3d968589d8 3642
Kojto 90:cb3d968589d8 3643 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 122:f9eeca106725 3644 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */
Kojto 90:cb3d968589d8 3645
Kojto 90:cb3d968589d8 3646 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 122:f9eeca106725 3647 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */
Kojto 90:cb3d968589d8 3648
Kojto 90:cb3d968589d8 3649 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 122:f9eeca106725 3650 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!<Channel length (number of bits per audio channel) */
Kojto 122:f9eeca106725 3651
Kojto 122:f9eeca106725 3652 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006U) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 122:f9eeca106725 3653 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
Kojto 122:f9eeca106725 3654 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
Kojto 122:f9eeca106725 3655
Kojto 122:f9eeca106725 3656 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008U) /*!<steady state clock polarity */
Kojto 122:f9eeca106725 3657
Kojto 122:f9eeca106725 3658 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030U) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 122:f9eeca106725 3659 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 3660 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 3661
Kojto 122:f9eeca106725 3662 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080U) /*!<PCM frame synchronization */
Kojto 122:f9eeca106725 3663
Kojto 122:f9eeca106725 3664 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300U) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 122:f9eeca106725 3665 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 122:f9eeca106725 3666 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 122:f9eeca106725 3667
Kojto 122:f9eeca106725 3668 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400U) /*!<I2S Enable */
Kojto 122:f9eeca106725 3669 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800U) /*!<I2S mode selection */
Kojto 90:cb3d968589d8 3670
Kojto 90:cb3d968589d8 3671 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 122:f9eeca106725 3672 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FFU) /*!<I2S Linear prescaler */
Kojto 122:f9eeca106725 3673 #define SPI_I2SPR_ODD ((uint32_t)0x00000100U) /*!<Odd factor for the prescaler */
Kojto 122:f9eeca106725 3674 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200U) /*!<Master Clock Output Enable */
Kojto 90:cb3d968589d8 3675
Kojto 90:cb3d968589d8 3676 /******************************************************************************/
Kojto 90:cb3d968589d8 3677 /* */
Kojto 90:cb3d968589d8 3678 /* System Configuration (SYSCFG) */
Kojto 90:cb3d968589d8 3679 /* */
Kojto 90:cb3d968589d8 3680 /******************************************************************************/
Kojto 90:cb3d968589d8 3681 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
Kojto 122:f9eeca106725 3682 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */
Kojto 122:f9eeca106725 3683 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3684 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3685 #define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300U) /*!< Boot mode Config */
Kojto 122:f9eeca106725 3686 #define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3687 #define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
Kojto 90:cb3d968589d8 3688
Kojto 90:cb3d968589d8 3689 /***************** Bit definition for SYSCFG_PMC register *******************/
Kojto 122:f9eeca106725 3690 #define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001U) /*!< SYSCFG PMC */
Kojto 122:f9eeca106725 3691 #define SYSCFG_PMC_LCD_CAPA ((uint32_t)0x0000003EU) /*!< LCD_CAPA decoupling capacitance connection */
Kojto 122:f9eeca106725 3692 #define SYSCFG_PMC_LCD_CAPA_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3693 #define SYSCFG_PMC_LCD_CAPA_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3694 #define SYSCFG_PMC_LCD_CAPA_2 ((uint32_t)0x00000008U) /*!< Bit 2 */
Kojto 122:f9eeca106725 3695 #define SYSCFG_PMC_LCD_CAPA_3 ((uint32_t)0x00000010U) /*!< Bit 3 */
Kojto 122:f9eeca106725 3696 #define SYSCFG_PMC_LCD_CAPA_4 ((uint32_t)0x00000020U) /*!< Bit 4 */
Kojto 90:cb3d968589d8 3697
Kojto 90:cb3d968589d8 3698 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 122:f9eeca106725 3699 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */
Kojto 122:f9eeca106725 3700 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */
Kojto 122:f9eeca106725 3701 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */
Kojto 122:f9eeca106725 3702 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */
Kojto 90:cb3d968589d8 3703
Kojto 90:cb3d968589d8 3704 /**
Kojto 90:cb3d968589d8 3705 * @brief EXTI0 configuration
Kojto 90:cb3d968589d8 3706 */
Kojto 122:f9eeca106725 3707 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */
Kojto 122:f9eeca106725 3708 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */
Kojto 122:f9eeca106725 3709 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */
Kojto 122:f9eeca106725 3710 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003U) /*!< PD[0] pin */
Kojto 122:f9eeca106725 3711 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004U) /*!< PE[0] pin */
Kojto 122:f9eeca106725 3712 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */
Kojto 122:f9eeca106725 3713 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000006U) /*!< PF[0] pin */
Kojto 122:f9eeca106725 3714 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000007U) /*!< PG[0] pin */
Kojto 90:cb3d968589d8 3715
Kojto 90:cb3d968589d8 3716 /**
Kojto 90:cb3d968589d8 3717 * @brief EXTI1 configuration
Kojto 90:cb3d968589d8 3718 */
Kojto 122:f9eeca106725 3719 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */
Kojto 122:f9eeca106725 3720 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */
Kojto 122:f9eeca106725 3721 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */
Kojto 122:f9eeca106725 3722 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030U) /*!< PD[1] pin */
Kojto 122:f9eeca106725 3723 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040U) /*!< PE[1] pin */
Kojto 122:f9eeca106725 3724 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */
Kojto 122:f9eeca106725 3725 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000060U) /*!< PF[1] pin */
Kojto 122:f9eeca106725 3726 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000070U) /*!< PG[1] pin */
Kojto 90:cb3d968589d8 3727
Kojto 90:cb3d968589d8 3728 /**
Kojto 90:cb3d968589d8 3729 * @brief EXTI2 configuration
Kojto 90:cb3d968589d8 3730 */
Kojto 122:f9eeca106725 3731 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */
Kojto 122:f9eeca106725 3732 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */
Kojto 122:f9eeca106725 3733 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */
Kojto 122:f9eeca106725 3734 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */
Kojto 122:f9eeca106725 3735 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400U) /*!< PE[2] pin */
Kojto 122:f9eeca106725 3736 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000500U) /*!< PH[2] pin */
Kojto 122:f9eeca106725 3737 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000600U) /*!< PF[2] pin */
Kojto 122:f9eeca106725 3738 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000700U) /*!< PG[2] pin */
Kojto 90:cb3d968589d8 3739
Kojto 90:cb3d968589d8 3740 /**
Kojto 90:cb3d968589d8 3741 * @brief EXTI3 configuration
Kojto 90:cb3d968589d8 3742 */
Kojto 122:f9eeca106725 3743 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */
Kojto 122:f9eeca106725 3744 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */
Kojto 122:f9eeca106725 3745 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */
Kojto 122:f9eeca106725 3746 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000U) /*!< PD[3] pin */
Kojto 122:f9eeca106725 3747 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000U) /*!< PE[3] pin */
Kojto 122:f9eeca106725 3748 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00003000U) /*!< PF[3] pin */
Kojto 122:f9eeca106725 3749 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00004000U) /*!< PG[3] pin */
Kojto 90:cb3d968589d8 3750
Kojto 90:cb3d968589d8 3751 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
Kojto 122:f9eeca106725 3752 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */
Kojto 122:f9eeca106725 3753 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */
Kojto 122:f9eeca106725 3754 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */
Kojto 122:f9eeca106725 3755 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */
Kojto 90:cb3d968589d8 3756
Kojto 90:cb3d968589d8 3757 /**
Kojto 90:cb3d968589d8 3758 * @brief EXTI4 configuration
Kojto 90:cb3d968589d8 3759 */
Kojto 122:f9eeca106725 3760 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */
Kojto 122:f9eeca106725 3761 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */
Kojto 122:f9eeca106725 3762 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */
Kojto 122:f9eeca106725 3763 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003U) /*!< PD[4] pin */
Kojto 122:f9eeca106725 3764 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004U) /*!< PE[4] pin */
Kojto 122:f9eeca106725 3765 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000006U) /*!< PF[4] pin */
Kojto 122:f9eeca106725 3766 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000007U) /*!< PG[4] pin */
Kojto 90:cb3d968589d8 3767
Kojto 90:cb3d968589d8 3768 /**
Kojto 90:cb3d968589d8 3769 * @brief EXTI5 configuration
Kojto 90:cb3d968589d8 3770 */
Kojto 122:f9eeca106725 3771 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */
Kojto 122:f9eeca106725 3772 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */
Kojto 122:f9eeca106725 3773 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */
Kojto 122:f9eeca106725 3774 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030U) /*!< PD[5] pin */
Kojto 122:f9eeca106725 3775 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040U) /*!< PE[5] pin */
Kojto 122:f9eeca106725 3776 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000060U) /*!< PF[5] pin */
Kojto 122:f9eeca106725 3777 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000070U) /*!< PG[5] pin */
Kojto 90:cb3d968589d8 3778
Kojto 90:cb3d968589d8 3779 /**
Kojto 90:cb3d968589d8 3780 * @brief EXTI6 configuration
Kojto 90:cb3d968589d8 3781 */
Kojto 122:f9eeca106725 3782 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */
Kojto 122:f9eeca106725 3783 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */
Kojto 122:f9eeca106725 3784 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */
Kojto 122:f9eeca106725 3785 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300U) /*!< PD[6] pin */
Kojto 122:f9eeca106725 3786 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400U) /*!< PE[6] pin */
Kojto 122:f9eeca106725 3787 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000600U) /*!< PF[6] pin */
Kojto 122:f9eeca106725 3788 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000700U) /*!< PG[6] pin */
Kojto 90:cb3d968589d8 3789
Kojto 90:cb3d968589d8 3790 /**
Kojto 90:cb3d968589d8 3791 * @brief EXTI7 configuration
Kojto 90:cb3d968589d8 3792 */
Kojto 122:f9eeca106725 3793 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */
Kojto 122:f9eeca106725 3794 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */
Kojto 122:f9eeca106725 3795 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */
Kojto 122:f9eeca106725 3796 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000U) /*!< PD[7] pin */
Kojto 122:f9eeca106725 3797 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000U) /*!< PE[7] pin */
Kojto 122:f9eeca106725 3798 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00006000U) /*!< PF[7] pin */
Kojto 122:f9eeca106725 3799 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00007000U) /*!< PG[7] pin */
Kojto 90:cb3d968589d8 3800
Kojto 90:cb3d968589d8 3801 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
Kojto 122:f9eeca106725 3802 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */
Kojto 122:f9eeca106725 3803 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */
Kojto 122:f9eeca106725 3804 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */
Kojto 122:f9eeca106725 3805 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */
Kojto 90:cb3d968589d8 3806
Kojto 90:cb3d968589d8 3807 /**
Kojto 90:cb3d968589d8 3808 * @brief EXTI8 configuration
Kojto 90:cb3d968589d8 3809 */
Kojto 122:f9eeca106725 3810 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */
Kojto 122:f9eeca106725 3811 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */
Kojto 122:f9eeca106725 3812 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */
Kojto 122:f9eeca106725 3813 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003U) /*!< PD[8] pin */
Kojto 122:f9eeca106725 3814 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004U) /*!< PE[8] pin */
Kojto 122:f9eeca106725 3815 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000006U) /*!< PF[8] pin */
Kojto 122:f9eeca106725 3816 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000007U) /*!< PG[8] pin */
Kojto 90:cb3d968589d8 3817
Kojto 90:cb3d968589d8 3818 /**
Kojto 90:cb3d968589d8 3819 * @brief EXTI9 configuration
Kojto 90:cb3d968589d8 3820 */
Kojto 122:f9eeca106725 3821 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */
Kojto 122:f9eeca106725 3822 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */
Kojto 122:f9eeca106725 3823 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */
Kojto 122:f9eeca106725 3824 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030U) /*!< PD[9] pin */
Kojto 122:f9eeca106725 3825 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040U) /*!< PE[9] pin */
Kojto 122:f9eeca106725 3826 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000060U) /*!< PF[9] pin */
Kojto 122:f9eeca106725 3827 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000070U) /*!< PG[9] pin */
Kojto 90:cb3d968589d8 3828
Kojto 90:cb3d968589d8 3829 /**
Kojto 90:cb3d968589d8 3830 * @brief EXTI10 configuration
Kojto 90:cb3d968589d8 3831 */
Kojto 122:f9eeca106725 3832 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */
Kojto 122:f9eeca106725 3833 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */
Kojto 122:f9eeca106725 3834 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */
Kojto 122:f9eeca106725 3835 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300U) /*!< PD[10] pin */
Kojto 122:f9eeca106725 3836 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400U) /*!< PE[10] pin */
Kojto 122:f9eeca106725 3837 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000600U) /*!< PF[10] pin */
Kojto 122:f9eeca106725 3838 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000700U) /*!< PG[10] pin */
Kojto 90:cb3d968589d8 3839
Kojto 90:cb3d968589d8 3840 /**
Kojto 90:cb3d968589d8 3841 * @brief EXTI11 configuration
Kojto 90:cb3d968589d8 3842 */
Kojto 122:f9eeca106725 3843 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */
Kojto 122:f9eeca106725 3844 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */
Kojto 122:f9eeca106725 3845 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */
Kojto 122:f9eeca106725 3846 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000U) /*!< PD[11] pin */
Kojto 122:f9eeca106725 3847 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000U) /*!< PE[11] pin */
Kojto 122:f9eeca106725 3848 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00006000U) /*!< PF[11] pin */
Kojto 122:f9eeca106725 3849 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00007000U) /*!< PG[11] pin */
Kojto 90:cb3d968589d8 3850
Kojto 90:cb3d968589d8 3851 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
Kojto 122:f9eeca106725 3852 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */
Kojto 122:f9eeca106725 3853 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */
Kojto 122:f9eeca106725 3854 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */
Kojto 122:f9eeca106725 3855 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */
Kojto 90:cb3d968589d8 3856
Kojto 90:cb3d968589d8 3857 /**
Kojto 90:cb3d968589d8 3858 * @brief EXTI12 configuration
Kojto 90:cb3d968589d8 3859 */
Kojto 122:f9eeca106725 3860 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */
Kojto 122:f9eeca106725 3861 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */
Kojto 122:f9eeca106725 3862 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */
Kojto 122:f9eeca106725 3863 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003U) /*!< PD[12] pin */
Kojto 122:f9eeca106725 3864 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004U) /*!< PE[12] pin */
Kojto 122:f9eeca106725 3865 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000006U) /*!< PF[12] pin */
Kojto 122:f9eeca106725 3866 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000007U) /*!< PG[12] pin */
Kojto 90:cb3d968589d8 3867
Kojto 90:cb3d968589d8 3868 /**
Kojto 90:cb3d968589d8 3869 * @brief EXTI13 configuration
Kojto 90:cb3d968589d8 3870 */
Kojto 122:f9eeca106725 3871 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */
Kojto 122:f9eeca106725 3872 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */
Kojto 122:f9eeca106725 3873 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */
Kojto 122:f9eeca106725 3874 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030U) /*!< PD[13] pin */
Kojto 122:f9eeca106725 3875 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040U) /*!< PE[13] pin */
Kojto 122:f9eeca106725 3876 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000060U) /*!< PF[13] pin */
Kojto 122:f9eeca106725 3877 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000070U) /*!< PG[13] pin */
Kojto 90:cb3d968589d8 3878
Kojto 90:cb3d968589d8 3879 /**
Kojto 90:cb3d968589d8 3880 * @brief EXTI14 configuration
Kojto 90:cb3d968589d8 3881 */
Kojto 122:f9eeca106725 3882 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */
Kojto 122:f9eeca106725 3883 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */
Kojto 122:f9eeca106725 3884 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */
Kojto 122:f9eeca106725 3885 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300U) /*!< PD[14] pin */
Kojto 122:f9eeca106725 3886 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400U) /*!< PE[14] pin */
Kojto 122:f9eeca106725 3887 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000600U) /*!< PF[14] pin */
Kojto 122:f9eeca106725 3888 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000700U) /*!< PG[14] pin */
Kojto 90:cb3d968589d8 3889
Kojto 90:cb3d968589d8 3890 /**
Kojto 90:cb3d968589d8 3891 * @brief EXTI15 configuration
Kojto 90:cb3d968589d8 3892 */
Kojto 122:f9eeca106725 3893 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */
Kojto 122:f9eeca106725 3894 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */
Kojto 122:f9eeca106725 3895 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */
Kojto 122:f9eeca106725 3896 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000U) /*!< PD[15] pin */
Kojto 122:f9eeca106725 3897 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000U) /*!< PE[15] pin */
Kojto 122:f9eeca106725 3898 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00006000U) /*!< PF[15] pin */
Kojto 122:f9eeca106725 3899 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00007000U) /*!< PG[15] pin */
Kojto 90:cb3d968589d8 3900
Kojto 90:cb3d968589d8 3901 /******************************************************************************/
Kojto 90:cb3d968589d8 3902 /* */
Kojto 90:cb3d968589d8 3903 /* Routing Interface (RI) */
Kojto 90:cb3d968589d8 3904 /* */
Kojto 90:cb3d968589d8 3905 /******************************************************************************/
Kojto 90:cb3d968589d8 3906
Kojto 90:cb3d968589d8 3907 /******************** Bit definition for RI_ICR register ********************/
Kojto 122:f9eeca106725 3908 #define RI_ICR_IC1OS ((uint32_t)0x0000000FU) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
Kojto 122:f9eeca106725 3909 #define RI_ICR_IC1OS_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3910 #define RI_ICR_IC1OS_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3911 #define RI_ICR_IC1OS_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 3912 #define RI_ICR_IC1OS_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 3913
Kojto 122:f9eeca106725 3914 #define RI_ICR_IC2OS ((uint32_t)0x000000F0U) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
Kojto 122:f9eeca106725 3915 #define RI_ICR_IC2OS_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3916 #define RI_ICR_IC2OS_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3917 #define RI_ICR_IC2OS_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
Kojto 122:f9eeca106725 3918 #define RI_ICR_IC2OS_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
Kojto 122:f9eeca106725 3919
Kojto 122:f9eeca106725 3920 #define RI_ICR_IC3OS ((uint32_t)0x00000F00U) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
Kojto 122:f9eeca106725 3921 #define RI_ICR_IC3OS_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3922 #define RI_ICR_IC3OS_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3923 #define RI_ICR_IC3OS_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
Kojto 122:f9eeca106725 3924 #define RI_ICR_IC3OS_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
Kojto 122:f9eeca106725 3925
Kojto 122:f9eeca106725 3926 #define RI_ICR_IC4OS ((uint32_t)0x0000F000U) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
Kojto 122:f9eeca106725 3927 #define RI_ICR_IC4OS_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3928 #define RI_ICR_IC4OS_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3929 #define RI_ICR_IC4OS_2 ((uint32_t)0x00004000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 3930 #define RI_ICR_IC4OS_3 ((uint32_t)0x00008000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 3931
Kojto 122:f9eeca106725 3932 #define RI_ICR_TIM ((uint32_t)0x00030000U) /*!< TIM[3:0] bits (Timers select bits) */
Kojto 122:f9eeca106725 3933 #define RI_ICR_TIM_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3934 #define RI_ICR_TIM_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3935
Kojto 122:f9eeca106725 3936 #define RI_ICR_IC1 ((uint32_t)0x00040000U) /*!< Input capture 1 */
Kojto 122:f9eeca106725 3937 #define RI_ICR_IC2 ((uint32_t)0x00080000U) /*!< Input capture 2 */
Kojto 122:f9eeca106725 3938 #define RI_ICR_IC3 ((uint32_t)0x00100000U) /*!< Input capture 3 */
Kojto 122:f9eeca106725 3939 #define RI_ICR_IC4 ((uint32_t)0x00200000U) /*!< Input capture 4 */
Kojto 90:cb3d968589d8 3940
Kojto 90:cb3d968589d8 3941 /******************** Bit definition for RI_ASCR1 register ********************/
Kojto 122:f9eeca106725 3942 #define RI_ASCR1_CH ((uint32_t)0x7BFDFFFFU) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
Kojto 122:f9eeca106725 3943 #define RI_ASCR1_CH_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 3944 #define RI_ASCR1_CH_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 3945 #define RI_ASCR1_CH_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 3946 #define RI_ASCR1_CH_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 3947 #define RI_ASCR1_CH_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 3948 #define RI_ASCR1_CH_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 3949 #define RI_ASCR1_CH_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 3950 #define RI_ASCR1_CH_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 3951 #define RI_ASCR1_CH_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 3952 #define RI_ASCR1_CH_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 3953 #define RI_ASCR1_CH_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 3954 #define RI_ASCR1_CH_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 3955 #define RI_ASCR1_CH_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 3956 #define RI_ASCR1_CH_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 3957 #define RI_ASCR1_CH_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 3958 #define RI_ASCR1_CH_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 122:f9eeca106725 3959 #define RI_ASCR1_CH_31 ((uint32_t)0x00010000U) /*!< Bit 16 */
Kojto 122:f9eeca106725 3960 #define RI_ASCR1_CH_18 ((uint32_t)0x00040000U) /*!< Bit 18 */
Kojto 122:f9eeca106725 3961 #define RI_ASCR1_CH_19 ((uint32_t)0x00080000U) /*!< Bit 19 */
Kojto 122:f9eeca106725 3962 #define RI_ASCR1_CH_20 ((uint32_t)0x00100000U) /*!< Bit 20 */
Kojto 122:f9eeca106725 3963 #define RI_ASCR1_CH_21 ((uint32_t)0x00200000U) /*!< Bit 21 */
Kojto 122:f9eeca106725 3964 #define RI_ASCR1_CH_22 ((uint32_t)0x00400000U) /*!< Bit 22 */
Kojto 122:f9eeca106725 3965 #define RI_ASCR1_CH_23 ((uint32_t)0x00800000U) /*!< Bit 23 */
Kojto 122:f9eeca106725 3966 #define RI_ASCR1_CH_24 ((uint32_t)0x01000000U) /*!< Bit 24 */
Kojto 122:f9eeca106725 3967 #define RI_ASCR1_CH_25 ((uint32_t)0x02000000U) /*!< Bit 25 */
Kojto 122:f9eeca106725 3968 #define RI_ASCR1_VCOMP ((uint32_t)0x04000000U) /*!< ADC analog switch selection for internal node to COMP1 */
Kojto 122:f9eeca106725 3969 #define RI_ASCR1_CH_27 ((uint32_t)0x08000000U) /*!< Bit 27 */
Kojto 122:f9eeca106725 3970 #define RI_ASCR1_CH_28 ((uint32_t)0x10000000U) /*!< Bit 28 */
Kojto 122:f9eeca106725 3971 #define RI_ASCR1_CH_29 ((uint32_t)0x20000000U) /*!< Bit 29 */
Kojto 122:f9eeca106725 3972 #define RI_ASCR1_CH_30 ((uint32_t)0x40000000U) /*!< Bit 30 */
Kojto 122:f9eeca106725 3973 #define RI_ASCR1_SCM ((uint32_t)0x80000000U) /*!< I/O Switch control mode */
Kojto 90:cb3d968589d8 3974
Kojto 90:cb3d968589d8 3975 /******************** Bit definition for RI_ASCR2 register ********************/
Kojto 122:f9eeca106725 3976 #define RI_ASCR2_GR10_1 ((uint32_t)0x00000001U) /*!< GR10-1 selection bit */
Kojto 122:f9eeca106725 3977 #define RI_ASCR2_GR10_2 ((uint32_t)0x00000002U) /*!< GR10-2 selection bit */
Kojto 122:f9eeca106725 3978 #define RI_ASCR2_GR10_3 ((uint32_t)0x00000004U) /*!< GR10-3 selection bit */
Kojto 122:f9eeca106725 3979 #define RI_ASCR2_GR10_4 ((uint32_t)0x00000008U) /*!< GR10-4 selection bit */
Kojto 122:f9eeca106725 3980 #define RI_ASCR2_GR6_1 ((uint32_t)0x00000010U) /*!< GR6-1 selection bit */
Kojto 122:f9eeca106725 3981 #define RI_ASCR2_GR6_2 ((uint32_t)0x00000020U) /*!< GR6-2 selection bit */
Kojto 122:f9eeca106725 3982 #define RI_ASCR2_GR5_1 ((uint32_t)0x00000040U) /*!< GR5-1 selection bit */
Kojto 122:f9eeca106725 3983 #define RI_ASCR2_GR5_2 ((uint32_t)0x00000080U) /*!< GR5-2 selection bit */
Kojto 122:f9eeca106725 3984 #define RI_ASCR2_GR5_3 ((uint32_t)0x00000100U) /*!< GR5-3 selection bit */
Kojto 122:f9eeca106725 3985 #define RI_ASCR2_GR4_1 ((uint32_t)0x00000200U) /*!< GR4-1 selection bit */
Kojto 122:f9eeca106725 3986 #define RI_ASCR2_GR4_2 ((uint32_t)0x00000400U) /*!< GR4-2 selection bit */
Kojto 122:f9eeca106725 3987 #define RI_ASCR2_GR4_3 ((uint32_t)0x00000800U) /*!< GR4-3 selection bit */
Kojto 122:f9eeca106725 3988 #define RI_ASCR2_GR4_4 ((uint32_t)0x00008000U) /*!< GR4-4 selection bit */
Kojto 122:f9eeca106725 3989 #define RI_ASCR2_CH0b ((uint32_t)0x00010000U) /*!< CH0b selection bit */
Kojto 122:f9eeca106725 3990 #define RI_ASCR2_CH1b ((uint32_t)0x00020000U) /*!< CH1b selection bit */
Kojto 122:f9eeca106725 3991 #define RI_ASCR2_CH2b ((uint32_t)0x00040000U) /*!< CH2b selection bit */
Kojto 122:f9eeca106725 3992 #define RI_ASCR2_CH3b ((uint32_t)0x00080000U) /*!< CH3b selection bit */
Kojto 122:f9eeca106725 3993 #define RI_ASCR2_CH6b ((uint32_t)0x00100000U) /*!< CH6b selection bit */
Kojto 122:f9eeca106725 3994 #define RI_ASCR2_CH7b ((uint32_t)0x00200000U) /*!< CH7b selection bit */
Kojto 122:f9eeca106725 3995 #define RI_ASCR2_CH8b ((uint32_t)0x00400000U) /*!< CH8b selection bit */
Kojto 122:f9eeca106725 3996 #define RI_ASCR2_CH9b ((uint32_t)0x00800000U) /*!< CH9b selection bit */
Kojto 122:f9eeca106725 3997 #define RI_ASCR2_CH10b ((uint32_t)0x01000000U) /*!< CH10b selection bit */
Kojto 122:f9eeca106725 3998 #define RI_ASCR2_CH11b ((uint32_t)0x02000000U) /*!< CH11b selection bit */
Kojto 122:f9eeca106725 3999 #define RI_ASCR2_CH12b ((uint32_t)0x04000000U) /*!< CH12b selection bit */
Kojto 122:f9eeca106725 4000 #define RI_ASCR2_GR6_3 ((uint32_t)0x08000000U) /*!< GR6-3 selection bit */
Kojto 122:f9eeca106725 4001 #define RI_ASCR2_GR6_4 ((uint32_t)0x10000000U) /*!< GR6-4 selection bit */
Kojto 90:cb3d968589d8 4002
Kojto 90:cb3d968589d8 4003 /******************** Bit definition for RI_HYSCR1 register ********************/
Kojto 122:f9eeca106725 4004 #define RI_HYSCR1_PA ((uint32_t)0x0000FFFFU) /*!< PA[15:0] Port A Hysteresis selection */
Kojto 122:f9eeca106725 4005 #define RI_HYSCR1_PA_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4006 #define RI_HYSCR1_PA_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4007 #define RI_HYSCR1_PA_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4008 #define RI_HYSCR1_PA_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4009 #define RI_HYSCR1_PA_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4010 #define RI_HYSCR1_PA_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4011 #define RI_HYSCR1_PA_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4012 #define RI_HYSCR1_PA_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4013 #define RI_HYSCR1_PA_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4014 #define RI_HYSCR1_PA_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4015 #define RI_HYSCR1_PA_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4016 #define RI_HYSCR1_PA_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4017 #define RI_HYSCR1_PA_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4018 #define RI_HYSCR1_PA_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4019 #define RI_HYSCR1_PA_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4020 #define RI_HYSCR1_PA_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 122:f9eeca106725 4021
Kojto 122:f9eeca106725 4022 #define RI_HYSCR1_PB ((uint32_t)0xFFFF0000U) /*!< PB[15:0] Port B Hysteresis selection */
Kojto 122:f9eeca106725 4023 #define RI_HYSCR1_PB_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4024 #define RI_HYSCR1_PB_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4025 #define RI_HYSCR1_PB_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4026 #define RI_HYSCR1_PB_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4027 #define RI_HYSCR1_PB_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4028 #define RI_HYSCR1_PB_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4029 #define RI_HYSCR1_PB_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4030 #define RI_HYSCR1_PB_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4031 #define RI_HYSCR1_PB_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4032 #define RI_HYSCR1_PB_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4033 #define RI_HYSCR1_PB_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4034 #define RI_HYSCR1_PB_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4035 #define RI_HYSCR1_PB_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4036 #define RI_HYSCR1_PB_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4037 #define RI_HYSCR1_PB_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4038 #define RI_HYSCR1_PB_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4039
Kojto 90:cb3d968589d8 4040 /******************** Bit definition for RI_HYSCR2 register ********************/
Kojto 122:f9eeca106725 4041 #define RI_HYSCR2_PC ((uint32_t)0x0000FFFFU) /*!< PC[15:0] Port C Hysteresis selection */
Kojto 122:f9eeca106725 4042 #define RI_HYSCR2_PC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4043 #define RI_HYSCR2_PC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4044 #define RI_HYSCR2_PC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4045 #define RI_HYSCR2_PC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4046 #define RI_HYSCR2_PC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4047 #define RI_HYSCR2_PC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4048 #define RI_HYSCR2_PC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4049 #define RI_HYSCR2_PC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4050 #define RI_HYSCR2_PC_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4051 #define RI_HYSCR2_PC_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4052 #define RI_HYSCR2_PC_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4053 #define RI_HYSCR2_PC_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4054 #define RI_HYSCR2_PC_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4055 #define RI_HYSCR2_PC_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4056 #define RI_HYSCR2_PC_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4057 #define RI_HYSCR2_PC_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 122:f9eeca106725 4058
Kojto 122:f9eeca106725 4059 #define RI_HYSCR2_PD ((uint32_t)0xFFFF0000U) /*!< PD[15:0] Port D Hysteresis selection */
Kojto 122:f9eeca106725 4060 #define RI_HYSCR2_PD_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4061 #define RI_HYSCR2_PD_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4062 #define RI_HYSCR2_PD_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4063 #define RI_HYSCR2_PD_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4064 #define RI_HYSCR2_PD_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4065 #define RI_HYSCR2_PD_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4066 #define RI_HYSCR2_PD_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4067 #define RI_HYSCR2_PD_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4068 #define RI_HYSCR2_PD_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4069 #define RI_HYSCR2_PD_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4070 #define RI_HYSCR2_PD_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4071 #define RI_HYSCR2_PD_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4072 #define RI_HYSCR2_PD_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4073 #define RI_HYSCR2_PD_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4074 #define RI_HYSCR2_PD_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4075 #define RI_HYSCR2_PD_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4076
Kojto 90:cb3d968589d8 4077 /******************** Bit definition for RI_HYSCR3 register ********************/
Kojto 122:f9eeca106725 4078 #define RI_HYSCR3_PE ((uint32_t)0x0000FFFFU) /*!< PE[15:0] Port E Hysteresis selection */
Kojto 122:f9eeca106725 4079 #define RI_HYSCR3_PE_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4080 #define RI_HYSCR3_PE_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4081 #define RI_HYSCR3_PE_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4082 #define RI_HYSCR3_PE_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4083 #define RI_HYSCR3_PE_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4084 #define RI_HYSCR3_PE_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4085 #define RI_HYSCR3_PE_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4086 #define RI_HYSCR3_PE_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4087 #define RI_HYSCR3_PE_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4088 #define RI_HYSCR3_PE_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4089 #define RI_HYSCR3_PE_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4090 #define RI_HYSCR3_PE_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4091 #define RI_HYSCR3_PE_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4092 #define RI_HYSCR3_PE_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4093 #define RI_HYSCR3_PE_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4094 #define RI_HYSCR3_PE_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 122:f9eeca106725 4095 #define RI_HYSCR3_PF ((uint32_t)0xFFFF0000U) /*!< PF[15:0] Port F Hysteresis selection */
Kojto 122:f9eeca106725 4096 #define RI_HYSCR3_PF_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4097 #define RI_HYSCR3_PF_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4098 #define RI_HYSCR3_PF_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4099 #define RI_HYSCR3_PF_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4100 #define RI_HYSCR3_PF_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4101 #define RI_HYSCR3_PF_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4102 #define RI_HYSCR3_PF_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4103 #define RI_HYSCR3_PF_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4104 #define RI_HYSCR3_PF_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4105 #define RI_HYSCR3_PF_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4106 #define RI_HYSCR3_PF_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4107 #define RI_HYSCR3_PF_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4108 #define RI_HYSCR3_PF_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4109 #define RI_HYSCR3_PF_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4110 #define RI_HYSCR3_PF_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4111 #define RI_HYSCR3_PF_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4112
Kojto 90:cb3d968589d8 4113 /******************** Bit definition for RI_HYSCR4 register ********************/
Kojto 122:f9eeca106725 4114 #define RI_HYSCR4_PG ((uint32_t)0x0000FFFFU) /*!< PG[15:0] Port G Hysteresis selection */
Kojto 122:f9eeca106725 4115 #define RI_HYSCR4_PG_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4116 #define RI_HYSCR4_PG_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4117 #define RI_HYSCR4_PG_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4118 #define RI_HYSCR4_PG_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4119 #define RI_HYSCR4_PG_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4120 #define RI_HYSCR4_PG_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4121 #define RI_HYSCR4_PG_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4122 #define RI_HYSCR4_PG_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4123 #define RI_HYSCR4_PG_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4124 #define RI_HYSCR4_PG_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4125 #define RI_HYSCR4_PG_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4126 #define RI_HYSCR4_PG_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4127 #define RI_HYSCR4_PG_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4128 #define RI_HYSCR4_PG_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4129 #define RI_HYSCR4_PG_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4130 #define RI_HYSCR4_PG_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4131
Kojto 90:cb3d968589d8 4132 /******************** Bit definition for RI_ASMR1 register ********************/
Kojto 122:f9eeca106725 4133 #define RI_ASMR1_PA ((uint32_t)0x0000FFFFU) /*!< PA[15:0] Port A selection*/
Kojto 122:f9eeca106725 4134 #define RI_ASMR1_PA_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4135 #define RI_ASMR1_PA_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4136 #define RI_ASMR1_PA_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4137 #define RI_ASMR1_PA_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4138 #define RI_ASMR1_PA_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4139 #define RI_ASMR1_PA_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4140 #define RI_ASMR1_PA_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4141 #define RI_ASMR1_PA_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4142 #define RI_ASMR1_PA_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4143 #define RI_ASMR1_PA_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4144 #define RI_ASMR1_PA_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4145 #define RI_ASMR1_PA_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4146 #define RI_ASMR1_PA_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4147 #define RI_ASMR1_PA_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4148 #define RI_ASMR1_PA_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4149 #define RI_ASMR1_PA_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4150
Kojto 90:cb3d968589d8 4151 /******************** Bit definition for RI_CMR1 register ********************/
Kojto 122:f9eeca106725 4152 #define RI_CMR1_PA ((uint32_t)0x0000FFFFU) /*!< PA[15:0] Port A selection*/
Kojto 122:f9eeca106725 4153 #define RI_CMR1_PA_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4154 #define RI_CMR1_PA_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4155 #define RI_CMR1_PA_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4156 #define RI_CMR1_PA_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4157 #define RI_CMR1_PA_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4158 #define RI_CMR1_PA_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4159 #define RI_CMR1_PA_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4160 #define RI_CMR1_PA_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4161 #define RI_CMR1_PA_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4162 #define RI_CMR1_PA_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4163 #define RI_CMR1_PA_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4164 #define RI_CMR1_PA_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4165 #define RI_CMR1_PA_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4166 #define RI_CMR1_PA_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4167 #define RI_CMR1_PA_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4168 #define RI_CMR1_PA_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4169
Kojto 90:cb3d968589d8 4170 /******************** Bit definition for RI_CICR1 register ********************/
Kojto 122:f9eeca106725 4171 #define RI_CICR1_PA ((uint32_t)0x0000FFFFU) /*!< PA[15:0] Port A selection*/
Kojto 122:f9eeca106725 4172 #define RI_CICR1_PA_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4173 #define RI_CICR1_PA_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4174 #define RI_CICR1_PA_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4175 #define RI_CICR1_PA_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4176 #define RI_CICR1_PA_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4177 #define RI_CICR1_PA_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4178 #define RI_CICR1_PA_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4179 #define RI_CICR1_PA_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4180 #define RI_CICR1_PA_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4181 #define RI_CICR1_PA_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4182 #define RI_CICR1_PA_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4183 #define RI_CICR1_PA_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4184 #define RI_CICR1_PA_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4185 #define RI_CICR1_PA_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4186 #define RI_CICR1_PA_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4187 #define RI_CICR1_PA_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4188
Kojto 90:cb3d968589d8 4189 /******************** Bit definition for RI_ASMR2 register ********************/
Kojto 122:f9eeca106725 4190 #define RI_ASMR2_PB ((uint32_t)0x0000FFFFU) /*!< PB[15:0] Port B selection */
Kojto 122:f9eeca106725 4191 #define RI_ASMR2_PB_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4192 #define RI_ASMR2_PB_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4193 #define RI_ASMR2_PB_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4194 #define RI_ASMR2_PB_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4195 #define RI_ASMR2_PB_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4196 #define RI_ASMR2_PB_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4197 #define RI_ASMR2_PB_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4198 #define RI_ASMR2_PB_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4199 #define RI_ASMR2_PB_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4200 #define RI_ASMR2_PB_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4201 #define RI_ASMR2_PB_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4202 #define RI_ASMR2_PB_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4203 #define RI_ASMR2_PB_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4204 #define RI_ASMR2_PB_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4205 #define RI_ASMR2_PB_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4206 #define RI_ASMR2_PB_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4207
Kojto 90:cb3d968589d8 4208 /******************** Bit definition for RI_CMR2 register ********************/
Kojto 122:f9eeca106725 4209 #define RI_CMR2_PB ((uint32_t)0x0000FFFFU) /*!< PB[15:0] Port B selection */
Kojto 122:f9eeca106725 4210 #define RI_CMR2_PB_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4211 #define RI_CMR2_PB_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4212 #define RI_CMR2_PB_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4213 #define RI_CMR2_PB_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4214 #define RI_CMR2_PB_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4215 #define RI_CMR2_PB_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4216 #define RI_CMR2_PB_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4217 #define RI_CMR2_PB_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4218 #define RI_CMR2_PB_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4219 #define RI_CMR2_PB_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4220 #define RI_CMR2_PB_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4221 #define RI_CMR2_PB_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4222 #define RI_CMR2_PB_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4223 #define RI_CMR2_PB_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4224 #define RI_CMR2_PB_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4225 #define RI_CMR2_PB_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4226
Kojto 90:cb3d968589d8 4227 /******************** Bit definition for RI_CICR2 register ********************/
Kojto 122:f9eeca106725 4228 #define RI_CICR2_PB ((uint32_t)0x0000FFFFU) /*!< PB[15:0] Port B selection */
Kojto 122:f9eeca106725 4229 #define RI_CICR2_PB_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4230 #define RI_CICR2_PB_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4231 #define RI_CICR2_PB_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4232 #define RI_CICR2_PB_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4233 #define RI_CICR2_PB_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4234 #define RI_CICR2_PB_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4235 #define RI_CICR2_PB_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4236 #define RI_CICR2_PB_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4237 #define RI_CICR2_PB_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4238 #define RI_CICR2_PB_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4239 #define RI_CICR2_PB_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4240 #define RI_CICR2_PB_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4241 #define RI_CICR2_PB_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4242 #define RI_CICR2_PB_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4243 #define RI_CICR2_PB_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4244 #define RI_CICR2_PB_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4245
Kojto 90:cb3d968589d8 4246 /******************** Bit definition for RI_ASMR3 register ********************/
Kojto 122:f9eeca106725 4247 #define RI_ASMR3_PC ((uint32_t)0x0000FFFFU) /*!< PC[15:0] Port C selection */
Kojto 122:f9eeca106725 4248 #define RI_ASMR3_PC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4249 #define RI_ASMR3_PC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4250 #define RI_ASMR3_PC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4251 #define RI_ASMR3_PC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4252 #define RI_ASMR3_PC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4253 #define RI_ASMR3_PC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4254 #define RI_ASMR3_PC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4255 #define RI_ASMR3_PC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4256 #define RI_ASMR3_PC_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4257 #define RI_ASMR3_PC_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4258 #define RI_ASMR3_PC_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4259 #define RI_ASMR3_PC_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4260 #define RI_ASMR3_PC_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4261 #define RI_ASMR3_PC_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4262 #define RI_ASMR3_PC_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4263 #define RI_ASMR3_PC_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4264
Kojto 90:cb3d968589d8 4265 /******************** Bit definition for RI_CMR3 register ********************/
Kojto 122:f9eeca106725 4266 #define RI_CMR3_PC ((uint32_t)0x0000FFFFU) /*!< PC[15:0] Port C selection */
Kojto 122:f9eeca106725 4267 #define RI_CMR3_PC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4268 #define RI_CMR3_PC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4269 #define RI_CMR3_PC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4270 #define RI_CMR3_PC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4271 #define RI_CMR3_PC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4272 #define RI_CMR3_PC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4273 #define RI_CMR3_PC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4274 #define RI_CMR3_PC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4275 #define RI_CMR3_PC_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4276 #define RI_CMR3_PC_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4277 #define RI_CMR3_PC_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4278 #define RI_CMR3_PC_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4279 #define RI_CMR3_PC_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4280 #define RI_CMR3_PC_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4281 #define RI_CMR3_PC_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4282 #define RI_CMR3_PC_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4283
Kojto 90:cb3d968589d8 4284 /******************** Bit definition for RI_CICR3 register ********************/
Kojto 122:f9eeca106725 4285 #define RI_CICR3_PC ((uint32_t)0x0000FFFFU) /*!< PC[15:0] Port C selection */
Kojto 122:f9eeca106725 4286 #define RI_CICR3_PC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4287 #define RI_CICR3_PC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4288 #define RI_CICR3_PC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4289 #define RI_CICR3_PC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4290 #define RI_CICR3_PC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4291 #define RI_CICR3_PC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4292 #define RI_CICR3_PC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4293 #define RI_CICR3_PC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4294 #define RI_CICR3_PC_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4295 #define RI_CICR3_PC_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4296 #define RI_CICR3_PC_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4297 #define RI_CICR3_PC_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4298 #define RI_CICR3_PC_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4299 #define RI_CICR3_PC_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4300 #define RI_CICR3_PC_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4301 #define RI_CICR3_PC_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4302
Kojto 90:cb3d968589d8 4303 /******************** Bit definition for RI_ASMR4 register ********************/
Kojto 122:f9eeca106725 4304 #define RI_ASMR4_PF ((uint32_t)0x0000FFFFU) /*!< PF[15:0] Port F selection */
Kojto 122:f9eeca106725 4305 #define RI_ASMR4_PF_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4306 #define RI_ASMR4_PF_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4307 #define RI_ASMR4_PF_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4308 #define RI_ASMR4_PF_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4309 #define RI_ASMR4_PF_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4310 #define RI_ASMR4_PF_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4311 #define RI_ASMR4_PF_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4312 #define RI_ASMR4_PF_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4313 #define RI_ASMR4_PF_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4314 #define RI_ASMR4_PF_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4315 #define RI_ASMR4_PF_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4316 #define RI_ASMR4_PF_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4317 #define RI_ASMR4_PF_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4318 #define RI_ASMR4_PF_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4319 #define RI_ASMR4_PF_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4320 #define RI_ASMR4_PF_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4321
Kojto 90:cb3d968589d8 4322 /******************** Bit definition for RI_CMR4 register ********************/
Kojto 122:f9eeca106725 4323 #define RI_CMR4_PF ((uint32_t)0x0000FFFFU) /*!< PF[15:0] Port F selection */
Kojto 122:f9eeca106725 4324 #define RI_CMR4_PF_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4325 #define RI_CMR4_PF_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4326 #define RI_CMR4_PF_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4327 #define RI_CMR4_PF_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4328 #define RI_CMR4_PF_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4329 #define RI_CMR4_PF_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4330 #define RI_CMR4_PF_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4331 #define RI_CMR4_PF_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4332 #define RI_CMR4_PF_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4333 #define RI_CMR4_PF_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4334 #define RI_CMR4_PF_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4335 #define RI_CMR4_PF_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4336 #define RI_CMR4_PF_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4337 #define RI_CMR4_PF_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4338 #define RI_CMR4_PF_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4339 #define RI_CMR4_PF_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4340
Kojto 90:cb3d968589d8 4341 /******************** Bit definition for RI_CICR4 register ********************/
Kojto 122:f9eeca106725 4342 #define RI_CICR4_PF ((uint32_t)0x0000FFFFU) /*!< PF[15:0] Port F selection */
Kojto 122:f9eeca106725 4343 #define RI_CICR4_PF_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4344 #define RI_CICR4_PF_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4345 #define RI_CICR4_PF_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4346 #define RI_CICR4_PF_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4347 #define RI_CICR4_PF_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4348 #define RI_CICR4_PF_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4349 #define RI_CICR4_PF_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4350 #define RI_CICR4_PF_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4351 #define RI_CICR4_PF_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4352 #define RI_CICR4_PF_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4353 #define RI_CICR4_PF_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4354 #define RI_CICR4_PF_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4355 #define RI_CICR4_PF_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4356 #define RI_CICR4_PF_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4357 #define RI_CICR4_PF_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4358 #define RI_CICR4_PF_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4359
Kojto 90:cb3d968589d8 4360 /******************** Bit definition for RI_ASMR5 register ********************/
Kojto 122:f9eeca106725 4361 #define RI_ASMR5_PG ((uint32_t)0x0000FFFFU) /*!< PG[15:0] Port G selection */
Kojto 122:f9eeca106725 4362 #define RI_ASMR5_PG_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4363 #define RI_ASMR5_PG_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4364 #define RI_ASMR5_PG_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4365 #define RI_ASMR5_PG_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4366 #define RI_ASMR5_PG_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4367 #define RI_ASMR5_PG_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4368 #define RI_ASMR5_PG_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4369 #define RI_ASMR5_PG_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4370 #define RI_ASMR5_PG_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4371 #define RI_ASMR5_PG_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4372 #define RI_ASMR5_PG_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4373 #define RI_ASMR5_PG_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4374 #define RI_ASMR5_PG_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4375 #define RI_ASMR5_PG_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4376 #define RI_ASMR5_PG_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4377 #define RI_ASMR5_PG_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4378
Kojto 90:cb3d968589d8 4379 /******************** Bit definition for RI_CMR5 register ********************/
Kojto 122:f9eeca106725 4380 #define RI_CMR5_PG ((uint32_t)0x0000FFFFU) /*!< PG[15:0] Port G selection */
Kojto 122:f9eeca106725 4381 #define RI_CMR5_PG_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4382 #define RI_CMR5_PG_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4383 #define RI_CMR5_PG_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4384 #define RI_CMR5_PG_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4385 #define RI_CMR5_PG_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4386 #define RI_CMR5_PG_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4387 #define RI_CMR5_PG_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4388 #define RI_CMR5_PG_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4389 #define RI_CMR5_PG_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4390 #define RI_CMR5_PG_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4391 #define RI_CMR5_PG_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4392 #define RI_CMR5_PG_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4393 #define RI_CMR5_PG_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4394 #define RI_CMR5_PG_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4395 #define RI_CMR5_PG_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4396 #define RI_CMR5_PG_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4397
Kojto 90:cb3d968589d8 4398 /******************** Bit definition for RI_CICR5 register ********************/
Kojto 122:f9eeca106725 4399 #define RI_CICR5_PG ((uint32_t)0x0000FFFFU) /*!< PG[15:0] Port G selection */
Kojto 122:f9eeca106725 4400 #define RI_CICR5_PG_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4401 #define RI_CICR5_PG_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4402 #define RI_CICR5_PG_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4403 #define RI_CICR5_PG_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4404 #define RI_CICR5_PG_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4405 #define RI_CICR5_PG_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4406 #define RI_CICR5_PG_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4407 #define RI_CICR5_PG_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4408 #define RI_CICR5_PG_8 ((uint32_t)0x00000100U) /*!< Bit 8 */
Kojto 122:f9eeca106725 4409 #define RI_CICR5_PG_9 ((uint32_t)0x00000200U) /*!< Bit 9 */
Kojto 122:f9eeca106725 4410 #define RI_CICR5_PG_10 ((uint32_t)0x00000400U) /*!< Bit 10 */
Kojto 122:f9eeca106725 4411 #define RI_CICR5_PG_11 ((uint32_t)0x00000800U) /*!< Bit 11 */
Kojto 122:f9eeca106725 4412 #define RI_CICR5_PG_12 ((uint32_t)0x00001000U) /*!< Bit 12 */
Kojto 122:f9eeca106725 4413 #define RI_CICR5_PG_13 ((uint32_t)0x00002000U) /*!< Bit 13 */
Kojto 122:f9eeca106725 4414 #define RI_CICR5_PG_14 ((uint32_t)0x00004000U) /*!< Bit 14 */
Kojto 122:f9eeca106725 4415 #define RI_CICR5_PG_15 ((uint32_t)0x00008000U) /*!< Bit 15 */
Kojto 90:cb3d968589d8 4416
Kojto 90:cb3d968589d8 4417 /******************************************************************************/
Kojto 90:cb3d968589d8 4418 /* */
Kojto 90:cb3d968589d8 4419 /* Timers (TIM) */
Kojto 90:cb3d968589d8 4420 /* */
Kojto 90:cb3d968589d8 4421 /******************************************************************************/
Kojto 90:cb3d968589d8 4422
Kojto 90:cb3d968589d8 4423 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 122:f9eeca106725 4424 #define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
Kojto 122:f9eeca106725 4425 #define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
Kojto 122:f9eeca106725 4426 #define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
Kojto 122:f9eeca106725 4427 #define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
Kojto 122:f9eeca106725 4428 #define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
Kojto 122:f9eeca106725 4429
Kojto 122:f9eeca106725 4430 #define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 4431 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4432 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4433
Kojto 122:f9eeca106725 4434 #define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 4435
Kojto 122:f9eeca106725 4436 #define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 4437 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4438 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 90:cb3d968589d8 4439
Kojto 90:cb3d968589d8 4440 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 122:f9eeca106725 4441 #define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 4442
Kojto 122:f9eeca106725 4443 #define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 4444 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4445 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4446 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4447
Kojto 122:f9eeca106725 4448 #define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
Kojto 90:cb3d968589d8 4449
Kojto 90:cb3d968589d8 4450 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 122:f9eeca106725 4451 #define TIM_SMCR_SMS ((uint32_t)0x00000007U) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 4452 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4453 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4454 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4455
Kojto 122:f9eeca106725 4456 #define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
Kojto 122:f9eeca106725 4457
Kojto 122:f9eeca106725 4458 #define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 4459 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4460 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4461 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4462
Kojto 122:f9eeca106725 4463 #define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
Kojto 122:f9eeca106725 4464
Kojto 122:f9eeca106725 4465 #define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 4466 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4467 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4468 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4469 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
Kojto 122:f9eeca106725 4470
Kojto 122:f9eeca106725 4471 #define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 4472 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4473 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4474
Kojto 122:f9eeca106725 4475 #define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
Kojto 122:f9eeca106725 4476 #define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
Kojto 90:cb3d968589d8 4477
Kojto 90:cb3d968589d8 4478 /******************* Bit definition for TIM_DIER register *******************/
Kojto 122:f9eeca106725 4479 #define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
Kojto 122:f9eeca106725 4480 #define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 4481 #define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 4482 #define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 4483 #define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 4484 #define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 4485 #define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
Kojto 122:f9eeca106725 4486 #define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 4487 #define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 4488 #define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 4489 #define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 4490 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */
Kojto 122:f9eeca106725 4491 #define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
Kojto 90:cb3d968589d8 4492
Kojto 90:cb3d968589d8 4493 /******************** Bit definition for TIM_SR register ********************/
Kojto 122:f9eeca106725 4494 #define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 4495 #define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 4496 #define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 4497 #define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 4498 #define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 4499 #define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 4500 #define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 4501 #define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 4502 #define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 4503 #define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 90:cb3d968589d8 4504
Kojto 90:cb3d968589d8 4505 /******************* Bit definition for TIM_EGR register ********************/
Kojto 122:f9eeca106725 4506 #define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
Kojto 122:f9eeca106725 4507 #define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 4508 #define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 4509 #define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 4510 #define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 4511 #define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
Kojto 90:cb3d968589d8 4512
Kojto 90:cb3d968589d8 4513 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 122:f9eeca106725 4514 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 4515 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4516 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4517
Kojto 122:f9eeca106725 4518 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 4519 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 4520
Kojto 122:f9eeca106725 4521 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 4522 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4523 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4524 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4525
Kojto 122:f9eeca106725 4526 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1Clear Enable */
Kojto 122:f9eeca106725 4527
Kojto 122:f9eeca106725 4528 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 4529 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4530 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4531
Kojto 122:f9eeca106725 4532 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 4533 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 4534
Kojto 122:f9eeca106725 4535 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 4536 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4537 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4538 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4539
Kojto 122:f9eeca106725 4540 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
Kojto 90:cb3d968589d8 4541
Kojto 90:cb3d968589d8 4542 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 4543
Kojto 122:f9eeca106725 4544 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 4545 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4546 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4547
Kojto 122:f9eeca106725 4548 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 4549 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4550 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4551 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4552 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
Kojto 122:f9eeca106725 4553
Kojto 122:f9eeca106725 4554 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 4555 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4556 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4557
Kojto 122:f9eeca106725 4558 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 4559 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4560 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4561 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4562 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4563
Kojto 90:cb3d968589d8 4564 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 122:f9eeca106725 4565 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 4566 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4567 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4568
Kojto 122:f9eeca106725 4569 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 4570 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 4571
Kojto 122:f9eeca106725 4572 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 4573 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4574 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4575 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4576
Kojto 122:f9eeca106725 4577 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 4578
Kojto 122:f9eeca106725 4579 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 4580 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4581 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4582
Kojto 122:f9eeca106725 4583 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 4584 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 4585
Kojto 122:f9eeca106725 4586 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 4587 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4588 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4589 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4590
Kojto 122:f9eeca106725 4591 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
Kojto 90:cb3d968589d8 4592
Kojto 90:cb3d968589d8 4593 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 4594
Kojto 122:f9eeca106725 4595 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 4596 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4597 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4598
Kojto 122:f9eeca106725 4599 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 4600 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4601 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4602 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4603 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
Kojto 122:f9eeca106725 4604
Kojto 122:f9eeca106725 4605 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 4606 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4607 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4608
Kojto 122:f9eeca106725 4609 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 4610 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4611 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4612 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4613 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
Kojto 90:cb3d968589d8 4614
Kojto 90:cb3d968589d8 4615 /******************* Bit definition for TIM_CCER register *******************/
Kojto 122:f9eeca106725 4616 #define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 4617 #define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 4618 #define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 4619 #define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 4620 #define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 4621 #define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 4622 #define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 4623 #define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 4624 #define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 4625 #define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 4626 #define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 4627 #define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 90:cb3d968589d8 4628
Kojto 90:cb3d968589d8 4629 /******************* Bit definition for TIM_CNT register ********************/
Kojto 122:f9eeca106725 4630 #define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!<Counter Value */
Kojto 90:cb3d968589d8 4631
Kojto 90:cb3d968589d8 4632 /******************* Bit definition for TIM_PSC register ********************/
Kojto 122:f9eeca106725 4633 #define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
Kojto 90:cb3d968589d8 4634
Kojto 90:cb3d968589d8 4635 /******************* Bit definition for TIM_ARR register ********************/
Kojto 122:f9eeca106725 4636 #define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!<actual auto-reload Value */
Kojto 90:cb3d968589d8 4637
Kojto 90:cb3d968589d8 4638 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 122:f9eeca106725 4639 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
Kojto 90:cb3d968589d8 4640
Kojto 90:cb3d968589d8 4641 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 122:f9eeca106725 4642 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
Kojto 90:cb3d968589d8 4643
Kojto 90:cb3d968589d8 4644 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 122:f9eeca106725 4645 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
Kojto 90:cb3d968589d8 4646
Kojto 90:cb3d968589d8 4647 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 122:f9eeca106725 4648 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
Kojto 90:cb3d968589d8 4649
Kojto 90:cb3d968589d8 4650 /******************* Bit definition for TIM_DCR register ********************/
Kojto 122:f9eeca106725 4651 #define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 4652 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4653 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4654 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4655 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
Kojto 122:f9eeca106725 4656 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
Kojto 122:f9eeca106725 4657
Kojto 122:f9eeca106725 4658 #define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 4659 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4660 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4661 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
Kojto 122:f9eeca106725 4662 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
Kojto 122:f9eeca106725 4663 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
Kojto 90:cb3d968589d8 4664
Kojto 90:cb3d968589d8 4665 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 122:f9eeca106725 4666 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
Kojto 90:cb3d968589d8 4667
Kojto 90:cb3d968589d8 4668 /******************* Bit definition for TIM_OR register *********************/
Kojto 122:f9eeca106725 4669 #define TIM_OR_TI1RMP ((uint32_t)0x00000003U) /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
Kojto 122:f9eeca106725 4670 #define TIM_OR_TI1RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4671 #define TIM_OR_TI1RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4672
Kojto 122:f9eeca106725 4673 #define TIM_OR_ETR_RMP ((uint32_t)0x00000004U) /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
Kojto 122:f9eeca106725 4674 #define TIM_OR_TI1_RMP_RI ((uint32_t)0x00000008U) /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
Kojto 90:cb3d968589d8 4675
Kojto 90:cb3d968589d8 4676 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 4677 #define TIM9_OR_ITR1_RMP ((uint32_t)0x00000004U) /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
Kojto 90:cb3d968589d8 4678
Kojto 90:cb3d968589d8 4679 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 4680 #define TIM2_OR_ITR1_RMP ((uint32_t)0x00000001U) /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
Kojto 90:cb3d968589d8 4681
Kojto 90:cb3d968589d8 4682 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 4683 #define TIM3_OR_ITR2_RMP ((uint32_t)0x00000001U) /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
Kojto 90:cb3d968589d8 4684
Kojto 90:cb3d968589d8 4685 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 4686
Kojto 90:cb3d968589d8 4687
Kojto 90:cb3d968589d8 4688 /******************************************************************************/
Kojto 90:cb3d968589d8 4689 /* */
Kojto 90:cb3d968589d8 4690 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 90:cb3d968589d8 4691 /* */
Kojto 90:cb3d968589d8 4692 /******************************************************************************/
Kojto 90:cb3d968589d8 4693
Kojto 90:cb3d968589d8 4694 /******************* Bit definition for USART_SR register *******************/
Kojto 122:f9eeca106725 4695 #define USART_SR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
Kojto 122:f9eeca106725 4696 #define USART_SR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
Kojto 122:f9eeca106725 4697 #define USART_SR_NE ((uint32_t)0x00000004U) /*!< Noise Error Flag */
Kojto 122:f9eeca106725 4698 #define USART_SR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
Kojto 122:f9eeca106725 4699 #define USART_SR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
Kojto 122:f9eeca106725 4700 #define USART_SR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
Kojto 122:f9eeca106725 4701 #define USART_SR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
Kojto 122:f9eeca106725 4702 #define USART_SR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
Kojto 122:f9eeca106725 4703 #define USART_SR_LBD ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
Kojto 122:f9eeca106725 4704 #define USART_SR_CTS ((uint32_t)0x00000200U) /*!< CTS Flag */
Kojto 90:cb3d968589d8 4705
Kojto 90:cb3d968589d8 4706 /******************* Bit definition for USART_DR register *******************/
Kojto 122:f9eeca106725 4707 #define USART_DR_DR ((uint32_t)0x000001FFU) /*!< Data value */
Kojto 90:cb3d968589d8 4708
Kojto 90:cb3d968589d8 4709 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 4710 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /*!< Fraction of USARTDIV */
Kojto 122:f9eeca106725 4711 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /*!< Mantissa of USARTDIV */
Kojto 90:cb3d968589d8 4712
Kojto 90:cb3d968589d8 4713 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 4714 #define USART_CR1_SBK ((uint32_t)0x00000001U) /*!< Send Break */
Kojto 122:f9eeca106725 4715 #define USART_CR1_RWU ((uint32_t)0x00000002U) /*!< Receiver wakeup */
Kojto 122:f9eeca106725 4716 #define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
Kojto 122:f9eeca106725 4717 #define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
Kojto 122:f9eeca106725 4718 #define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
Kojto 122:f9eeca106725 4719 #define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
Kojto 122:f9eeca106725 4720 #define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 4721 #define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< PE Interrupt Enable */
Kojto 122:f9eeca106725 4722 #define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
Kojto 122:f9eeca106725 4723 #define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
Kojto 122:f9eeca106725 4724 #define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
Kojto 122:f9eeca106725 4725 #define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Wakeup method */
Kojto 122:f9eeca106725 4726 #define USART_CR1_M ((uint32_t)0x00001000U) /*!< Word length */
Kojto 122:f9eeca106725 4727 #define USART_CR1_UE ((uint32_t)0x00002000U) /*!< USART Enable */
Kojto 122:f9eeca106725 4728 #define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit mode */
Kojto 90:cb3d968589d8 4729
Kojto 90:cb3d968589d8 4730 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 4731 #define USART_CR2_ADD ((uint32_t)0x0000000FU) /*!< Address of the USART node */
Kojto 122:f9eeca106725 4732 #define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
Kojto 122:f9eeca106725 4733 #define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
Kojto 122:f9eeca106725 4734 #define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
Kojto 122:f9eeca106725 4735 #define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
Kojto 122:f9eeca106725 4736 #define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
Kojto 122:f9eeca106725 4737 #define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
Kojto 122:f9eeca106725 4738
Kojto 122:f9eeca106725 4739 #define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 4740 #define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4741 #define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4742
Kojto 122:f9eeca106725 4743 #define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
Kojto 90:cb3d968589d8 4744
Kojto 90:cb3d968589d8 4745 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 4746 #define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 4747 #define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
Kojto 122:f9eeca106725 4748 #define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
Kojto 122:f9eeca106725 4749 #define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
Kojto 122:f9eeca106725 4750 #define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< Smartcard NACK enable */
Kojto 122:f9eeca106725 4751 #define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< Smartcard mode enable */
Kojto 122:f9eeca106725 4752 #define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
Kojto 122:f9eeca106725 4753 #define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
Kojto 122:f9eeca106725 4754 #define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
Kojto 122:f9eeca106725 4755 #define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
Kojto 122:f9eeca106725 4756 #define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
Kojto 122:f9eeca106725 4757 #define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
Kojto 90:cb3d968589d8 4758
Kojto 90:cb3d968589d8 4759 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 4760 #define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 4761 #define USART_GTPR_PSC_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 4762 #define USART_GTPR_PSC_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 4763 #define USART_GTPR_PSC_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 4764 #define USART_GTPR_PSC_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 4765 #define USART_GTPR_PSC_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 4766 #define USART_GTPR_PSC_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 4767 #define USART_GTPR_PSC_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 4768 #define USART_GTPR_PSC_7 ((uint32_t)0x00000080U) /*!< Bit 7 */
Kojto 122:f9eeca106725 4769
Kojto 122:f9eeca106725 4770 #define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< Guard time value */
Kojto 90:cb3d968589d8 4771
Kojto 90:cb3d968589d8 4772 /******************************************************************************/
Kojto 90:cb3d968589d8 4773 /* */
Kojto 90:cb3d968589d8 4774 /* Universal Serial Bus (USB) */
Kojto 90:cb3d968589d8 4775 /* */
Kojto 90:cb3d968589d8 4776 /******************************************************************************/
Kojto 90:cb3d968589d8 4777
Kojto 90:cb3d968589d8 4778 /*!<Endpoint-specific registers */
Kojto 90:cb3d968589d8 4779
Kojto 90:cb3d968589d8 4780 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
Kojto 122:f9eeca106725 4781 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */
Kojto 122:f9eeca106725 4782 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */
Kojto 122:f9eeca106725 4783 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */
Kojto 122:f9eeca106725 4784 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */
Kojto 122:f9eeca106725 4785 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */
Kojto 122:f9eeca106725 4786 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */
Kojto 122:f9eeca106725 4787 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */
Kojto 90:cb3d968589d8 4788
Kojto 90:cb3d968589d8 4789 /* bit positions */
Kojto 122:f9eeca106725 4790 #define USB_EP_CTR_RX ((uint32_t)0x00008000U) /*!< EndPoint Correct TRansfer RX */
Kojto 122:f9eeca106725 4791 #define USB_EP_DTOG_RX ((uint32_t)0x00004000U) /*!< EndPoint Data TOGGLE RX */
Kojto 122:f9eeca106725 4792 #define USB_EPRX_STAT ((uint32_t)0x00003000U) /*!< EndPoint RX STATus bit field */
Kojto 122:f9eeca106725 4793 #define USB_EP_SETUP ((uint32_t)0x00000800U) /*!< EndPoint SETUP */
Kojto 122:f9eeca106725 4794 #define USB_EP_T_FIELD ((uint32_t)0x00000600U) /*!< EndPoint TYPE */
Kojto 122:f9eeca106725 4795 #define USB_EP_KIND ((uint32_t)0x00000100U) /*!< EndPoint KIND */
Kojto 122:f9eeca106725 4796 #define USB_EP_CTR_TX ((uint32_t)0x00000080U) /*!< EndPoint Correct TRansfer TX */
Kojto 122:f9eeca106725 4797 #define USB_EP_DTOG_TX ((uint32_t)0x00000040U) /*!< EndPoint Data TOGGLE TX */
Kojto 122:f9eeca106725 4798 #define USB_EPTX_STAT ((uint32_t)0x00000030U) /*!< EndPoint TX STATus bit field */
Kojto 122:f9eeca106725 4799 #define USB_EPADDR_FIELD ((uint32_t)0x0000000FU) /*!< EndPoint ADDRess FIELD */
Kojto 90:cb3d968589d8 4800
Kojto 90:cb3d968589d8 4801 /* EndPoint REGister MASK (no toggle fields) */
Kojto 90:cb3d968589d8 4802 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
Kojto 90:cb3d968589d8 4803 /*!< EP_TYPE[1:0] EndPoint TYPE */
Kojto 122:f9eeca106725 4804 #define USB_EP_TYPE_MASK ((uint32_t)0x00000600U) /*!< EndPoint TYPE Mask */
Kojto 122:f9eeca106725 4805 #define USB_EP_BULK ((uint32_t)0x00000000U) /*!< EndPoint BULK */
Kojto 122:f9eeca106725 4806 #define USB_EP_CONTROL ((uint32_t)0x00000200U) /*!< EndPoint CONTROL */
Kojto 122:f9eeca106725 4807 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400U) /*!< EndPoint ISOCHRONOUS */
Kojto 122:f9eeca106725 4808 #define USB_EP_INTERRUPT ((uint32_t)0x00000600U) /*!< EndPoint INTERRUPT */
Kojto 90:cb3d968589d8 4809 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
Kojto 90:cb3d968589d8 4810
Kojto 90:cb3d968589d8 4811 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
Kojto 90:cb3d968589d8 4812 /*!< STAT_TX[1:0] STATus for TX transfer */
Kojto 122:f9eeca106725 4813 #define USB_EP_TX_DIS ((uint32_t)0x00000000U) /*!< EndPoint TX DISabled */
Kojto 122:f9eeca106725 4814 #define USB_EP_TX_STALL ((uint32_t)0x00000010U) /*!< EndPoint TX STALLed */
Kojto 122:f9eeca106725 4815 #define USB_EP_TX_NAK ((uint32_t)0x00000020U) /*!< EndPoint TX NAKed */
Kojto 122:f9eeca106725 4816 #define USB_EP_TX_VALID ((uint32_t)0x00000030U) /*!< EndPoint TX VALID */
Kojto 122:f9eeca106725 4817 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */
Kojto 122:f9eeca106725 4818 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */
Kojto 90:cb3d968589d8 4819 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
Kojto 90:cb3d968589d8 4820 /*!< STAT_RX[1:0] STATus for RX transfer */
Kojto 122:f9eeca106725 4821 #define USB_EP_RX_DIS ((uint32_t)0x00000000U) /*!< EndPoint RX DISabled */
Kojto 122:f9eeca106725 4822 #define USB_EP_RX_STALL ((uint32_t)0x00001000U) /*!< EndPoint RX STALLed */
Kojto 122:f9eeca106725 4823 #define USB_EP_RX_NAK ((uint32_t)0x00002000U) /*!< EndPoint RX NAKed */
Kojto 122:f9eeca106725 4824 #define USB_EP_RX_VALID ((uint32_t)0x00003000U) /*!< EndPoint RX VALID */
Kojto 122:f9eeca106725 4825 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 122:f9eeca106725 4826 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 90:cb3d968589d8 4827 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
Kojto 90:cb3d968589d8 4828
Kojto 90:cb3d968589d8 4829 /******************* Bit definition for USB_EP0R register *******************/
Kojto 122:f9eeca106725 4830 #define USB_EP0R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
Kojto 122:f9eeca106725 4831
Kojto 122:f9eeca106725 4832 #define USB_EP0R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 122:f9eeca106725 4833 #define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4834 #define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4835
Kojto 122:f9eeca106725 4836 #define USB_EP0R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
Kojto 122:f9eeca106725 4837 #define USB_EP0R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
Kojto 122:f9eeca106725 4838 #define USB_EP0R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
Kojto 122:f9eeca106725 4839
Kojto 122:f9eeca106725 4840 #define USB_EP0R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
Kojto 122:f9eeca106725 4841 #define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4842 #define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4843
Kojto 122:f9eeca106725 4844 #define USB_EP0R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
Kojto 122:f9eeca106725 4845
Kojto 122:f9eeca106725 4846 #define USB_EP0R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 122:f9eeca106725 4847 #define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4848 #define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4849
Kojto 122:f9eeca106725 4850 #define USB_EP0R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
Kojto 122:f9eeca106725 4851 #define USB_EP0R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
Kojto 90:cb3d968589d8 4852
Kojto 90:cb3d968589d8 4853 /******************* Bit definition for USB_EP1R register *******************/
Kojto 122:f9eeca106725 4854 #define USB_EP1R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
Kojto 122:f9eeca106725 4855
Kojto 122:f9eeca106725 4856 #define USB_EP1R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 122:f9eeca106725 4857 #define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4858 #define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4859
Kojto 122:f9eeca106725 4860 #define USB_EP1R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
Kojto 122:f9eeca106725 4861 #define USB_EP1R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
Kojto 122:f9eeca106725 4862 #define USB_EP1R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
Kojto 122:f9eeca106725 4863
Kojto 122:f9eeca106725 4864 #define USB_EP1R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
Kojto 122:f9eeca106725 4865 #define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4866 #define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4867
Kojto 122:f9eeca106725 4868 #define USB_EP1R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
Kojto 122:f9eeca106725 4869
Kojto 122:f9eeca106725 4870 #define USB_EP1R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 122:f9eeca106725 4871 #define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4872 #define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4873
Kojto 122:f9eeca106725 4874 #define USB_EP1R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
Kojto 122:f9eeca106725 4875 #define USB_EP1R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
Kojto 90:cb3d968589d8 4876
Kojto 90:cb3d968589d8 4877 /******************* Bit definition for USB_EP2R register *******************/
Kojto 122:f9eeca106725 4878 #define USB_EP2R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
Kojto 122:f9eeca106725 4879
Kojto 122:f9eeca106725 4880 #define USB_EP2R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 122:f9eeca106725 4881 #define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4882 #define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4883
Kojto 122:f9eeca106725 4884 #define USB_EP2R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
Kojto 122:f9eeca106725 4885 #define USB_EP2R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
Kojto 122:f9eeca106725 4886 #define USB_EP2R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
Kojto 122:f9eeca106725 4887
Kojto 122:f9eeca106725 4888 #define USB_EP2R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
Kojto 122:f9eeca106725 4889 #define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4890 #define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4891
Kojto 122:f9eeca106725 4892 #define USB_EP2R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
Kojto 122:f9eeca106725 4893
Kojto 122:f9eeca106725 4894 #define USB_EP2R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 122:f9eeca106725 4895 #define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4896 #define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4897
Kojto 122:f9eeca106725 4898 #define USB_EP2R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
Kojto 122:f9eeca106725 4899 #define USB_EP2R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
Kojto 90:cb3d968589d8 4900
Kojto 90:cb3d968589d8 4901 /******************* Bit definition for USB_EP3R register *******************/
Kojto 122:f9eeca106725 4902 #define USB_EP3R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
Kojto 122:f9eeca106725 4903
Kojto 122:f9eeca106725 4904 #define USB_EP3R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 122:f9eeca106725 4905 #define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4906 #define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4907
Kojto 122:f9eeca106725 4908 #define USB_EP3R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
Kojto 122:f9eeca106725 4909 #define USB_EP3R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
Kojto 122:f9eeca106725 4910 #define USB_EP3R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
Kojto 122:f9eeca106725 4911
Kojto 122:f9eeca106725 4912 #define USB_EP3R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
Kojto 122:f9eeca106725 4913 #define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4914 #define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4915
Kojto 122:f9eeca106725 4916 #define USB_EP3R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
Kojto 122:f9eeca106725 4917
Kojto 122:f9eeca106725 4918 #define USB_EP3R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 122:f9eeca106725 4919 #define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4920 #define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4921
Kojto 122:f9eeca106725 4922 #define USB_EP3R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
Kojto 122:f9eeca106725 4923 #define USB_EP3R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
Kojto 90:cb3d968589d8 4924
Kojto 90:cb3d968589d8 4925 /******************* Bit definition for USB_EP4R register *******************/
Kojto 122:f9eeca106725 4926 #define USB_EP4R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
Kojto 122:f9eeca106725 4927
Kojto 122:f9eeca106725 4928 #define USB_EP4R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 122:f9eeca106725 4929 #define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4930 #define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4931
Kojto 122:f9eeca106725 4932 #define USB_EP4R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
Kojto 122:f9eeca106725 4933 #define USB_EP4R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
Kojto 122:f9eeca106725 4934 #define USB_EP4R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
Kojto 122:f9eeca106725 4935
Kojto 122:f9eeca106725 4936 #define USB_EP4R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
Kojto 122:f9eeca106725 4937 #define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4938 #define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4939
Kojto 122:f9eeca106725 4940 #define USB_EP4R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
Kojto 122:f9eeca106725 4941
Kojto 122:f9eeca106725 4942 #define USB_EP4R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 122:f9eeca106725 4943 #define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4944 #define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4945
Kojto 122:f9eeca106725 4946 #define USB_EP4R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
Kojto 122:f9eeca106725 4947 #define USB_EP4R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
Kojto 90:cb3d968589d8 4948
Kojto 90:cb3d968589d8 4949 /******************* Bit definition for USB_EP5R register *******************/
Kojto 122:f9eeca106725 4950 #define USB_EP5R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
Kojto 122:f9eeca106725 4951
Kojto 122:f9eeca106725 4952 #define USB_EP5R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 122:f9eeca106725 4953 #define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4954 #define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4955
Kojto 122:f9eeca106725 4956 #define USB_EP5R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
Kojto 122:f9eeca106725 4957 #define USB_EP5R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
Kojto 122:f9eeca106725 4958 #define USB_EP5R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
Kojto 122:f9eeca106725 4959
Kojto 122:f9eeca106725 4960 #define USB_EP5R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
Kojto 122:f9eeca106725 4961 #define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4962 #define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4963
Kojto 122:f9eeca106725 4964 #define USB_EP5R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
Kojto 122:f9eeca106725 4965
Kojto 122:f9eeca106725 4966 #define USB_EP5R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 122:f9eeca106725 4967 #define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4968 #define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4969
Kojto 122:f9eeca106725 4970 #define USB_EP5R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
Kojto 122:f9eeca106725 4971 #define USB_EP5R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
Kojto 90:cb3d968589d8 4972
Kojto 90:cb3d968589d8 4973 /******************* Bit definition for USB_EP6R register *******************/
Kojto 122:f9eeca106725 4974 #define USB_EP6R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
Kojto 122:f9eeca106725 4975
Kojto 122:f9eeca106725 4976 #define USB_EP6R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 122:f9eeca106725 4977 #define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4978 #define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4979
Kojto 122:f9eeca106725 4980 #define USB_EP6R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
Kojto 122:f9eeca106725 4981 #define USB_EP6R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
Kojto 122:f9eeca106725 4982 #define USB_EP6R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
Kojto 122:f9eeca106725 4983
Kojto 122:f9eeca106725 4984 #define USB_EP6R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
Kojto 122:f9eeca106725 4985 #define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4986 #define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4987
Kojto 122:f9eeca106725 4988 #define USB_EP6R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
Kojto 122:f9eeca106725 4989
Kojto 122:f9eeca106725 4990 #define USB_EP6R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 122:f9eeca106725 4991 #define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 4992 #define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 4993
Kojto 122:f9eeca106725 4994 #define USB_EP6R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
Kojto 122:f9eeca106725 4995 #define USB_EP6R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
Kojto 90:cb3d968589d8 4996
Kojto 90:cb3d968589d8 4997 /******************* Bit definition for USB_EP7R register *******************/
Kojto 122:f9eeca106725 4998 #define USB_EP7R_EA ((uint32_t)0x0000000FU) /*!<Endpoint Address */
Kojto 122:f9eeca106725 4999
Kojto 122:f9eeca106725 5000 #define USB_EP7R_STAT_TX ((uint32_t)0x00000030U) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
Kojto 122:f9eeca106725 5001 #define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 122:f9eeca106725 5002 #define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 122:f9eeca106725 5003
Kojto 122:f9eeca106725 5004 #define USB_EP7R_DTOG_TX ((uint32_t)0x00000040U) /*!<Data Toggle, for transmission transfers */
Kojto 122:f9eeca106725 5005 #define USB_EP7R_CTR_TX ((uint32_t)0x00000080U) /*!<Correct Transfer for transmission */
Kojto 122:f9eeca106725 5006 #define USB_EP7R_EP_KIND ((uint32_t)0x00000100U) /*!<Endpoint Kind */
Kojto 122:f9eeca106725 5007
Kojto 122:f9eeca106725 5008 #define USB_EP7R_EP_TYPE ((uint32_t)0x00000600U) /*!<EP_TYPE[1:0] bits (Endpoint type) */
Kojto 122:f9eeca106725 5009 #define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200U) /*!<Bit 0 */
Kojto 122:f9eeca106725 5010 #define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400U) /*!<Bit 1 */
Kojto 122:f9eeca106725 5011
Kojto 122:f9eeca106725 5012 #define USB_EP7R_SETUP ((uint32_t)0x00000800U) /*!<Setup transaction completed */
Kojto 122:f9eeca106725 5013
Kojto 122:f9eeca106725 5014 #define USB_EP7R_STAT_RX ((uint32_t)0x00003000U) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
Kojto 122:f9eeca106725 5015 #define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 122:f9eeca106725 5016 #define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 122:f9eeca106725 5017
Kojto 122:f9eeca106725 5018 #define USB_EP7R_DTOG_RX ((uint32_t)0x00004000U) /*!<Data Toggle, for reception transfers */
Kojto 122:f9eeca106725 5019 #define USB_EP7R_CTR_RX ((uint32_t)0x00008000U) /*!<Correct Transfer for reception */
Kojto 90:cb3d968589d8 5020
Kojto 90:cb3d968589d8 5021 /*!<Common registers */
Kojto 90:cb3d968589d8 5022
Kojto 122:f9eeca106725 5023 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
Kojto 122:f9eeca106725 5024 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
Kojto 122:f9eeca106725 5025 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
Kojto 122:f9eeca106725 5026 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
Kojto 122:f9eeca106725 5027 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
Kojto 90:cb3d968589d8 5028
Kojto 90:cb3d968589d8 5029
Kojto 90:cb3d968589d8 5030
Kojto 90:cb3d968589d8 5031 /******************* Bit definition for USB_CNTR register *******************/
Kojto 122:f9eeca106725 5032 #define USB_CNTR_FRES ((uint32_t)0x00000001U) /*!<Force USB Reset */
Kojto 122:f9eeca106725 5033 #define USB_CNTR_PDWN ((uint32_t)0x00000002U) /*!<Power down */
Kojto 122:f9eeca106725 5034 #define USB_CNTR_LPMODE ((uint32_t)0x00000004U) /*!<Low-power mode */
Kojto 122:f9eeca106725 5035 #define USB_CNTR_FSUSP ((uint32_t)0x00000008U) /*!<Force suspend */
Kojto 122:f9eeca106725 5036 #define USB_CNTR_RESUME ((uint32_t)0x00000010U) /*!<Resume request */
Kojto 122:f9eeca106725 5037 #define USB_CNTR_ESOFM ((uint32_t)0x00000100U) /*!<Expected Start Of Frame Interrupt Mask */
Kojto 122:f9eeca106725 5038 #define USB_CNTR_SOFM ((uint32_t)0x00000200U) /*!<Start Of Frame Interrupt Mask */
Kojto 122:f9eeca106725 5039 #define USB_CNTR_RESETM ((uint32_t)0x00000400U) /*!<RESET Interrupt Mask */
Kojto 122:f9eeca106725 5040 #define USB_CNTR_SUSPM ((uint32_t)0x00000800U) /*!<Suspend mode Interrupt Mask */
Kojto 122:f9eeca106725 5041 #define USB_CNTR_WKUPM ((uint32_t)0x00001000U) /*!<Wakeup Interrupt Mask */
Kojto 122:f9eeca106725 5042 #define USB_CNTR_ERRM ((uint32_t)0x00002000U) /*!<Error Interrupt Mask */
Kojto 122:f9eeca106725 5043 #define USB_CNTR_PMAOVRM ((uint32_t)0x00004000U) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
Kojto 122:f9eeca106725 5044 #define USB_CNTR_CTRM ((uint32_t)0x00008000U) /*!<Correct Transfer Interrupt Mask */
Kojto 90:cb3d968589d8 5045
Kojto 90:cb3d968589d8 5046 /******************* Bit definition for USB_ISTR register *******************/
Kojto 122:f9eeca106725 5047 #define USB_ISTR_EP_ID ((uint32_t)0x0000000FU) /*!<Endpoint Identifier */
Kojto 122:f9eeca106725 5048 #define USB_ISTR_DIR ((uint32_t)0x00000010U) /*!<Direction of transaction */
Kojto 122:f9eeca106725 5049 #define USB_ISTR_ESOF ((uint32_t)0x00000100U) /*!<Expected Start Of Frame */
Kojto 122:f9eeca106725 5050 #define USB_ISTR_SOF ((uint32_t)0x00000200U) /*!<Start Of Frame */
Kojto 122:f9eeca106725 5051 #define USB_ISTR_RESET ((uint32_t)0x00000400U) /*!<USB RESET request */
Kojto 122:f9eeca106725 5052 #define USB_ISTR_SUSP ((uint32_t)0x00000800U) /*!<Suspend mode request */
Kojto 122:f9eeca106725 5053 #define USB_ISTR_WKUP ((uint32_t)0x00001000U) /*!<Wake up */
Kojto 122:f9eeca106725 5054 #define USB_ISTR_ERR ((uint32_t)0x00002000U) /*!<Error */
Kojto 122:f9eeca106725 5055 #define USB_ISTR_PMAOVR ((uint32_t)0x00004000U) /*!<Packet Memory Area Over / Underrun */
Kojto 122:f9eeca106725 5056 #define USB_ISTR_CTR ((uint32_t)0x00008000U) /*!<Correct Transfer */
Kojto 90:cb3d968589d8 5057
Kojto 90:cb3d968589d8 5058 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
Kojto 90:cb3d968589d8 5059 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
Kojto 90:cb3d968589d8 5060 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
Kojto 90:cb3d968589d8 5061 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
Kojto 90:cb3d968589d8 5062 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
Kojto 90:cb3d968589d8 5063 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
Kojto 90:cb3d968589d8 5064 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
Kojto 90:cb3d968589d8 5065 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
Kojto 90:cb3d968589d8 5066
Kojto 90:cb3d968589d8 5067
Kojto 90:cb3d968589d8 5068 /******************* Bit definition for USB_FNR register ********************/
Kojto 122:f9eeca106725 5069 #define USB_FNR_FN ((uint32_t)0x000007FFU) /*!<Frame Number */
Kojto 122:f9eeca106725 5070 #define USB_FNR_LSOF ((uint32_t)0x00001800U) /*!<Lost SOF */
Kojto 122:f9eeca106725 5071 #define USB_FNR_LCK ((uint32_t)0x00002000U) /*!<Locked */
Kojto 122:f9eeca106725 5072 #define USB_FNR_RXDM ((uint32_t)0x00004000U) /*!<Receive Data - Line Status */
Kojto 122:f9eeca106725 5073 #define USB_FNR_RXDP ((uint32_t)0x00008000U) /*!<Receive Data + Line Status */
Kojto 90:cb3d968589d8 5074
Kojto 90:cb3d968589d8 5075 /****************** Bit definition for USB_DADDR register *******************/
Kojto 122:f9eeca106725 5076 #define USB_DADDR_ADD ((uint32_t)0x0000007FU) /*!<ADD[6:0] bits (Device Address) */
Kojto 122:f9eeca106725 5077 #define USB_DADDR_ADD0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 122:f9eeca106725 5078 #define USB_DADDR_ADD1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 122:f9eeca106725 5079 #define USB_DADDR_ADD2 ((uint32_t)0x00000004U) /*!<Bit 2 */
Kojto 122:f9eeca106725 5080 #define USB_DADDR_ADD3 ((uint32_t)0x00000008U) /*!<Bit 3 */
Kojto 122:f9eeca106725 5081 #define USB_DADDR_ADD4 ((uint32_t)0x00000010U) /*!<Bit 4 */
Kojto 122:f9eeca106725 5082 #define USB_DADDR_ADD5 ((uint32_t)0x00000020U) /*!<Bit 5 */
Kojto 122:f9eeca106725 5083 #define USB_DADDR_ADD6 ((uint32_t)0x00000040U) /*!<Bit 6 */
Kojto 122:f9eeca106725 5084
Kojto 122:f9eeca106725 5085 #define USB_DADDR_EF ((uint32_t)0x00000080U) /*!<Enable Function */
Kojto 90:cb3d968589d8 5086
Kojto 90:cb3d968589d8 5087 /****************** Bit definition for USB_BTABLE register ******************/
Kojto 122:f9eeca106725 5088 #define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8U) /*!<Buffer Table */
Kojto 90:cb3d968589d8 5089
Kojto 90:cb3d968589d8 5090 /*!< Buffer descriptor table */
Kojto 90:cb3d968589d8 5091 /***************** Bit definition for USB_ADDR0_TX register *****************/
Kojto 122:f9eeca106725 5092 #define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 0 */
Kojto 90:cb3d968589d8 5093
Kojto 90:cb3d968589d8 5094 /***************** Bit definition for USB_ADDR1_TX register *****************/
Kojto 122:f9eeca106725 5095 #define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 1 */
Kojto 90:cb3d968589d8 5096
Kojto 90:cb3d968589d8 5097 /***************** Bit definition for USB_ADDR2_TX register *****************/
Kojto 122:f9eeca106725 5098 #define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 2 */
Kojto 90:cb3d968589d8 5099
Kojto 90:cb3d968589d8 5100 /***************** Bit definition for USB_ADDR3_TX register *****************/
Kojto 122:f9eeca106725 5101 #define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 3 */
Kojto 90:cb3d968589d8 5102
Kojto 90:cb3d968589d8 5103 /***************** Bit definition for USB_ADDR4_TX register *****************/
Kojto 122:f9eeca106725 5104 #define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 4 */
Kojto 90:cb3d968589d8 5105
Kojto 90:cb3d968589d8 5106 /***************** Bit definition for USB_ADDR5_TX register *****************/
Kojto 122:f9eeca106725 5107 #define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 5 */
Kojto 90:cb3d968589d8 5108
Kojto 90:cb3d968589d8 5109 /***************** Bit definition for USB_ADDR6_TX register *****************/
Kojto 122:f9eeca106725 5110 #define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 6 */
Kojto 90:cb3d968589d8 5111
Kojto 90:cb3d968589d8 5112 /***************** Bit definition for USB_ADDR7_TX register *****************/
Kojto 122:f9eeca106725 5113 #define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFEU) /*!< Transmission Buffer Address 7 */
Kojto 90:cb3d968589d8 5114
Kojto 90:cb3d968589d8 5115 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 5116
Kojto 90:cb3d968589d8 5117 /***************** Bit definition for USB_COUNT0_TX register ****************/
Kojto 122:f9eeca106725 5118 #define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 0 */
Kojto 90:cb3d968589d8 5119
Kojto 90:cb3d968589d8 5120 /***************** Bit definition for USB_COUNT1_TX register ****************/
Kojto 122:f9eeca106725 5121 #define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 1 */
Kojto 90:cb3d968589d8 5122
Kojto 90:cb3d968589d8 5123 /***************** Bit definition for USB_COUNT2_TX register ****************/
Kojto 122:f9eeca106725 5124 #define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 2 */
Kojto 90:cb3d968589d8 5125
Kojto 90:cb3d968589d8 5126 /***************** Bit definition for USB_COUNT3_TX register ****************/
Kojto 122:f9eeca106725 5127 #define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 3 */
Kojto 90:cb3d968589d8 5128
Kojto 90:cb3d968589d8 5129 /***************** Bit definition for USB_COUNT4_TX register ****************/
Kojto 122:f9eeca106725 5130 #define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 4 */
Kojto 90:cb3d968589d8 5131
Kojto 90:cb3d968589d8 5132 /***************** Bit definition for USB_COUNT5_TX register ****************/
Kojto 122:f9eeca106725 5133 #define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 5 */
Kojto 90:cb3d968589d8 5134
Kojto 90:cb3d968589d8 5135 /***************** Bit definition for USB_COUNT6_TX register ****************/
Kojto 122:f9eeca106725 5136 #define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 6 */
Kojto 90:cb3d968589d8 5137
Kojto 90:cb3d968589d8 5138 /***************** Bit definition for USB_COUNT7_TX register ****************/
Kojto 122:f9eeca106725 5139 #define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 7 */
Kojto 90:cb3d968589d8 5140
Kojto 90:cb3d968589d8 5141 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 5142
Kojto 90:cb3d968589d8 5143 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
Kojto 122:f9eeca106725 5144 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 0 (low) */
Kojto 90:cb3d968589d8 5145
Kojto 90:cb3d968589d8 5146 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
Kojto 122:f9eeca106725 5147 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
Kojto 90:cb3d968589d8 5148
Kojto 90:cb3d968589d8 5149 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
Kojto 122:f9eeca106725 5150 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 1 (low) */
Kojto 90:cb3d968589d8 5151
Kojto 90:cb3d968589d8 5152 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
Kojto 122:f9eeca106725 5153 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
Kojto 90:cb3d968589d8 5154
Kojto 90:cb3d968589d8 5155 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
Kojto 122:f9eeca106725 5156 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 2 (low) */
Kojto 90:cb3d968589d8 5157
Kojto 90:cb3d968589d8 5158 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
Kojto 122:f9eeca106725 5159 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
Kojto 90:cb3d968589d8 5160
Kojto 90:cb3d968589d8 5161 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
Kojto 122:f9eeca106725 5162 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x00000000U03FF) /*!< Transmission Byte Count 3 (low) */
Kojto 90:cb3d968589d8 5163
Kojto 90:cb3d968589d8 5164 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
Kojto 122:f9eeca106725 5165 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FFU0000) /*!< Transmission Byte Count 3 (high) */
Kojto 90:cb3d968589d8 5166
Kojto 90:cb3d968589d8 5167 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
Kojto 122:f9eeca106725 5168 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 4 (low) */
Kojto 90:cb3d968589d8 5169
Kojto 90:cb3d968589d8 5170 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
Kojto 122:f9eeca106725 5171 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
Kojto 90:cb3d968589d8 5172
Kojto 90:cb3d968589d8 5173 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
Kojto 122:f9eeca106725 5174 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 5 (low) */
Kojto 90:cb3d968589d8 5175
Kojto 90:cb3d968589d8 5176 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
Kojto 122:f9eeca106725 5177 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
Kojto 90:cb3d968589d8 5178
Kojto 90:cb3d968589d8 5179 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
Kojto 122:f9eeca106725 5180 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 6 (low) */
Kojto 90:cb3d968589d8 5181
Kojto 90:cb3d968589d8 5182 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
Kojto 122:f9eeca106725 5183 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
Kojto 90:cb3d968589d8 5184
Kojto 90:cb3d968589d8 5185 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
Kojto 122:f9eeca106725 5186 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FFU) /*!< Transmission Byte Count 7 (low) */
Kojto 90:cb3d968589d8 5187
Kojto 90:cb3d968589d8 5188 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
Kojto 122:f9eeca106725 5189 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
Kojto 90:cb3d968589d8 5190
Kojto 90:cb3d968589d8 5191 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 5192
Kojto 90:cb3d968589d8 5193 /***************** Bit definition for USB_ADDR0_RX register *****************/
Kojto 122:f9eeca106725 5194 #define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 0 */
Kojto 90:cb3d968589d8 5195
Kojto 90:cb3d968589d8 5196 /***************** Bit definition for USB_ADDR1_RX register *****************/
Kojto 122:f9eeca106725 5197 #define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 1 */
Kojto 90:cb3d968589d8 5198
Kojto 90:cb3d968589d8 5199 /***************** Bit definition for USB_ADDR2_RX register *****************/
Kojto 122:f9eeca106725 5200 #define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 2 */
Kojto 90:cb3d968589d8 5201
Kojto 90:cb3d968589d8 5202 /***************** Bit definition for USB_ADDR3_RX register *****************/
Kojto 122:f9eeca106725 5203 #define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 3 */
Kojto 90:cb3d968589d8 5204
Kojto 90:cb3d968589d8 5205 /***************** Bit definition for USB_ADDR4_RX register *****************/
Kojto 122:f9eeca106725 5206 #define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 4 */
Kojto 90:cb3d968589d8 5207
Kojto 90:cb3d968589d8 5208 /***************** Bit definition for USB_ADDR5_RX register *****************/
Kojto 122:f9eeca106725 5209 #define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 5 */
Kojto 90:cb3d968589d8 5210
Kojto 90:cb3d968589d8 5211 /***************** Bit definition for USB_ADDR6_RX register *****************/
Kojto 122:f9eeca106725 5212 #define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 6 */
Kojto 90:cb3d968589d8 5213
Kojto 90:cb3d968589d8 5214 /***************** Bit definition for USB_ADDR7_RX register *****************/
Kojto 122:f9eeca106725 5215 #define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFEU) /*!< Reception Buffer Address 7 */
Kojto 90:cb3d968589d8 5216
Kojto 90:cb3d968589d8 5217 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 5218
Kojto 90:cb3d968589d8 5219 /***************** Bit definition for USB_COUNT0_RX register ****************/
Kojto 122:f9eeca106725 5220 #define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
Kojto 122:f9eeca106725 5221
Kojto 122:f9eeca106725 5222 #define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 5223 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5224 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5225 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5226 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5227 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5228
Kojto 122:f9eeca106725 5229 #define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
Kojto 90:cb3d968589d8 5230
Kojto 90:cb3d968589d8 5231 /***************** Bit definition for USB_COUNT1_RX register ****************/
Kojto 122:f9eeca106725 5232 #define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
Kojto 122:f9eeca106725 5233
Kojto 122:f9eeca106725 5234 #define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 5235 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5236 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5237 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5238 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5239 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5240
Kojto 122:f9eeca106725 5241 #define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
Kojto 90:cb3d968589d8 5242
Kojto 90:cb3d968589d8 5243 /***************** Bit definition for USB_COUNT2_RX register ****************/
Kojto 122:f9eeca106725 5244 #define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
Kojto 122:f9eeca106725 5245
Kojto 122:f9eeca106725 5246 #define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 5247 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5248 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5249 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5250 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5251 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5252
Kojto 122:f9eeca106725 5253 #define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
Kojto 90:cb3d968589d8 5254
Kojto 90:cb3d968589d8 5255 /***************** Bit definition for USB_COUNT3_RX register ****************/
Kojto 122:f9eeca106725 5256 #define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
Kojto 122:f9eeca106725 5257
Kojto 122:f9eeca106725 5258 #define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 5259 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5260 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5261 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5262 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5263 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5264
Kojto 122:f9eeca106725 5265 #define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
Kojto 90:cb3d968589d8 5266
Kojto 90:cb3d968589d8 5267 /***************** Bit definition for USB_COUNT4_RX register ****************/
Kojto 122:f9eeca106725 5268 #define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
Kojto 122:f9eeca106725 5269
Kojto 122:f9eeca106725 5270 #define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 5271 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5272 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5273 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5274 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5275 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5276
Kojto 122:f9eeca106725 5277 #define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
Kojto 90:cb3d968589d8 5278
Kojto 90:cb3d968589d8 5279 /***************** Bit definition for USB_COUNT5_RX register ****************/
Kojto 122:f9eeca106725 5280 #define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
Kojto 122:f9eeca106725 5281
Kojto 122:f9eeca106725 5282 #define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 5283 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5284 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5285 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5286 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5287 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5288
Kojto 122:f9eeca106725 5289 #define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
Kojto 90:cb3d968589d8 5290
Kojto 90:cb3d968589d8 5291 /***************** Bit definition for USB_COUNT6_RX register ****************/
Kojto 122:f9eeca106725 5292 #define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
Kojto 122:f9eeca106725 5293
Kojto 122:f9eeca106725 5294 #define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 5295 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5296 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5297 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5298 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5299 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5300
Kojto 122:f9eeca106725 5301 #define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
Kojto 90:cb3d968589d8 5302
Kojto 90:cb3d968589d8 5303 /***************** Bit definition for USB_COUNT7_RX register ****************/
Kojto 122:f9eeca106725 5304 #define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FFU) /*!< Reception Byte Count */
Kojto 122:f9eeca106725 5305
Kojto 122:f9eeca106725 5306 #define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00U) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
Kojto 122:f9eeca106725 5307 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5308 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5309 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5310 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5311 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5312
Kojto 122:f9eeca106725 5313 #define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000U) /*!< BLock SIZE */
Kojto 90:cb3d968589d8 5314
Kojto 90:cb3d968589d8 5315 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 5316
Kojto 90:cb3d968589d8 5317 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
Kojto 122:f9eeca106725 5318 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 5319
Kojto 122:f9eeca106725 5320 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 5321 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5322 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5323 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5324 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5325 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5326
Kojto 122:f9eeca106725 5327 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
Kojto 90:cb3d968589d8 5328
Kojto 90:cb3d968589d8 5329 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
Kojto 122:f9eeca106725 5330 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 5331
Kojto 122:f9eeca106725 5332 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 5333 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5334 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5335 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5336 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5337 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5338
Kojto 122:f9eeca106725 5339 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
Kojto 90:cb3d968589d8 5340
Kojto 90:cb3d968589d8 5341 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
Kojto 122:f9eeca106725 5342 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 5343
Kojto 122:f9eeca106725 5344 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 5345 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5346 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5347 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5348 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5349 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5350
Kojto 122:f9eeca106725 5351 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
Kojto 90:cb3d968589d8 5352
Kojto 90:cb3d968589d8 5353 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
Kojto 122:f9eeca106725 5354 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 5355
Kojto 122:f9eeca106725 5356 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 5357 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5358 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5359 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5360 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5361 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5362
Kojto 122:f9eeca106725 5363 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
Kojto 90:cb3d968589d8 5364
Kojto 90:cb3d968589d8 5365 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
Kojto 122:f9eeca106725 5366 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 5367
Kojto 122:f9eeca106725 5368 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 5369 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5370 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5371 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5372 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5373 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5374
Kojto 122:f9eeca106725 5375 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
Kojto 90:cb3d968589d8 5376
Kojto 90:cb3d968589d8 5377 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
Kojto 122:f9eeca106725 5378 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 5379
Kojto 122:f9eeca106725 5380 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 5381 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5382 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5383 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5384 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5385 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5386
Kojto 122:f9eeca106725 5387 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
Kojto 90:cb3d968589d8 5388
Kojto 90:cb3d968589d8 5389 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
Kojto 122:f9eeca106725 5390 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 5391
Kojto 122:f9eeca106725 5392 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 5393 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5394 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5395 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5396 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5397 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5398
Kojto 122:f9eeca106725 5399 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
Kojto 90:cb3d968589d8 5400
Kojto 90:cb3d968589d8 5401 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
Kojto 122:f9eeca106725 5402 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 5403
Kojto 122:f9eeca106725 5404 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 5405 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5406 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5407 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5408 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5409 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5410
Kojto 122:f9eeca106725 5411 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
Kojto 90:cb3d968589d8 5412
Kojto 90:cb3d968589d8 5413 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
Kojto 122:f9eeca106725 5414 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 5415
Kojto 122:f9eeca106725 5416 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 5417 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5418 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5419 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5420 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5421 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5422
Kojto 122:f9eeca106725 5423 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
Kojto 90:cb3d968589d8 5424
Kojto 90:cb3d968589d8 5425 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
Kojto 122:f9eeca106725 5426 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 5427
Kojto 122:f9eeca106725 5428 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 5429 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5430 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5431 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5432 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5433 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5434
Kojto 122:f9eeca106725 5435 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
Kojto 90:cb3d968589d8 5436
Kojto 90:cb3d968589d8 5437 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
Kojto 122:f9eeca106725 5438 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 5439
Kojto 122:f9eeca106725 5440 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 5441 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5442 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5443 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5444 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5445 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5446
Kojto 122:f9eeca106725 5447 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
Kojto 90:cb3d968589d8 5448
Kojto 90:cb3d968589d8 5449 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
Kojto 122:f9eeca106725 5450 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 5451
Kojto 122:f9eeca106725 5452 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 5453 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5454 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5455 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5456 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5457 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5458
Kojto 122:f9eeca106725 5459 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
Kojto 90:cb3d968589d8 5460
Kojto 90:cb3d968589d8 5461 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
Kojto 122:f9eeca106725 5462 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 5463
Kojto 122:f9eeca106725 5464 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 5465 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5466 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5467 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5468 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5469 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5470
Kojto 122:f9eeca106725 5471 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
Kojto 90:cb3d968589d8 5472
Kojto 90:cb3d968589d8 5473 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
Kojto 122:f9eeca106725 5474 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 5475
Kojto 122:f9eeca106725 5476 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 5477 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5478 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5479 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5480 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5481 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5482
Kojto 122:f9eeca106725 5483 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
Kojto 90:cb3d968589d8 5484
Kojto 90:cb3d968589d8 5485 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
Kojto 122:f9eeca106725 5486 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FFU) /*!< Reception Byte Count (low) */
Kojto 122:f9eeca106725 5487
Kojto 122:f9eeca106725 5488 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
Kojto 122:f9eeca106725 5489 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5490 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5491 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5492 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5493 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5494
Kojto 122:f9eeca106725 5495 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000U) /*!< BLock SIZE (low) */
Kojto 90:cb3d968589d8 5496
Kojto 90:cb3d968589d8 5497 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
Kojto 122:f9eeca106725 5498 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000U) /*!< Reception Byte Count (high) */
Kojto 122:f9eeca106725 5499
Kojto 122:f9eeca106725 5500 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
Kojto 122:f9eeca106725 5501 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5502 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5503 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5504 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5505 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5506
Kojto 122:f9eeca106725 5507 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000U) /*!< BLock SIZE (high) */
Kojto 90:cb3d968589d8 5508
Kojto 90:cb3d968589d8 5509 /******************************************************************************/
Kojto 90:cb3d968589d8 5510 /* */
Kojto 90:cb3d968589d8 5511 /* Window WATCHDOG (WWDG) */
Kojto 90:cb3d968589d8 5512 /* */
Kojto 90:cb3d968589d8 5513 /******************************************************************************/
Kojto 90:cb3d968589d8 5514
Kojto 90:cb3d968589d8 5515 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 5516 #define WWDG_CR_T ((uint32_t)0x0000007FU) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 5517 #define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5518 #define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5519 #define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5520 #define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5521 #define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5522 #define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 5523 #define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 5524
Kojto 122:f9eeca106725 5525 /* Legacy defines */
Kojto 122:f9eeca106725 5526 #define WWDG_CR_T0 WWDG_CR_T_0
Kojto 122:f9eeca106725 5527 #define WWDG_CR_T1 WWDG_CR_T_1
Kojto 122:f9eeca106725 5528 #define WWDG_CR_T2 WWDG_CR_T_2
Kojto 122:f9eeca106725 5529 #define WWDG_CR_T3 WWDG_CR_T_3
Kojto 122:f9eeca106725 5530 #define WWDG_CR_T4 WWDG_CR_T_4
Kojto 122:f9eeca106725 5531 #define WWDG_CR_T5 WWDG_CR_T_5
Kojto 122:f9eeca106725 5532 #define WWDG_CR_T6 WWDG_CR_T_6
Kojto 122:f9eeca106725 5533
Kojto 122:f9eeca106725 5534 #define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!< Activation bit */
Kojto 90:cb3d968589d8 5535
Kojto 90:cb3d968589d8 5536 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 5537 #define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!< W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 5538 #define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5539 #define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5540 #define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 122:f9eeca106725 5541 #define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 122:f9eeca106725 5542 #define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 122:f9eeca106725 5543 #define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 122:f9eeca106725 5544 #define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 122:f9eeca106725 5545
Kojto 122:f9eeca106725 5546 /* Legacy defines */
Kojto 122:f9eeca106725 5547 #define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto 122:f9eeca106725 5548 #define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto 122:f9eeca106725 5549 #define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto 122:f9eeca106725 5550 #define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto 122:f9eeca106725 5551 #define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto 122:f9eeca106725 5552 #define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto 122:f9eeca106725 5553 #define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto 122:f9eeca106725 5554
Kojto 122:f9eeca106725 5555 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!< WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 5556 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5557 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5558
Kojto 122:f9eeca106725 5559 /* Legacy defines */
Kojto 122:f9eeca106725 5560 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto 122:f9eeca106725 5561 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto 122:f9eeca106725 5562
Kojto 122:f9eeca106725 5563 #define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!< Early Wakeup Interrupt */
Kojto 90:cb3d968589d8 5564
Kojto 90:cb3d968589d8 5565 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 5566 #define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!< Early Wakeup Interrupt Flag */
Kojto 90:cb3d968589d8 5567
Kojto 90:cb3d968589d8 5568 /******************************************************************************/
Kojto 90:cb3d968589d8 5569 /* */
Kojto 90:cb3d968589d8 5570 /* SystemTick (SysTick) */
Kojto 90:cb3d968589d8 5571 /* */
Kojto 90:cb3d968589d8 5572 /******************************************************************************/
Kojto 90:cb3d968589d8 5573
Kojto 90:cb3d968589d8 5574 /***************** Bit definition for SysTick_CTRL register *****************/
Kojto 122:f9eeca106725 5575 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001U) /*!< Counter enable */
Kojto 122:f9eeca106725 5576 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002U) /*!< Counting down to 0 pends the SysTick handler */
Kojto 122:f9eeca106725 5577 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004U) /*!< Clock source */
Kojto 122:f9eeca106725 5578 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000U) /*!< Count Flag */
Kojto 90:cb3d968589d8 5579
Kojto 90:cb3d968589d8 5580 /***************** Bit definition for SysTick_LOAD register *****************/
Kojto 122:f9eeca106725 5581 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
Kojto 90:cb3d968589d8 5582
Kojto 90:cb3d968589d8 5583 /***************** Bit definition for SysTick_VAL register ******************/
Kojto 122:f9eeca106725 5584 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFFU) /*!< Current value at the time the register is accessed */
Kojto 90:cb3d968589d8 5585
Kojto 90:cb3d968589d8 5586 /***************** Bit definition for SysTick_CALIB register ****************/
Kojto 122:f9eeca106725 5587 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFFU) /*!< Reload value to use for 10ms timing */
Kojto 122:f9eeca106725 5588 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000U) /*!< Calibration value is not exactly 10 ms */
Kojto 122:f9eeca106725 5589 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000U) /*!< The reference clock is not provided */
Kojto 90:cb3d968589d8 5590
Kojto 90:cb3d968589d8 5591 /******************************************************************************/
Kojto 90:cb3d968589d8 5592 /* */
Kojto 90:cb3d968589d8 5593 /* Nested Vectored Interrupt Controller (NVIC) */
Kojto 90:cb3d968589d8 5594 /* */
Kojto 90:cb3d968589d8 5595 /******************************************************************************/
Kojto 90:cb3d968589d8 5596
Kojto 90:cb3d968589d8 5597 /****************** Bit definition for NVIC_ISER register *******************/
Kojto 122:f9eeca106725 5598 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFFU) /*!< Interrupt set enable bits */
Kojto 122:f9eeca106725 5599 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
Kojto 122:f9eeca106725 5600 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
Kojto 122:f9eeca106725 5601 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
Kojto 122:f9eeca106725 5602 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
Kojto 122:f9eeca106725 5603 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
Kojto 122:f9eeca106725 5604 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
Kojto 122:f9eeca106725 5605 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
Kojto 122:f9eeca106725 5606 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
Kojto 122:f9eeca106725 5607 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
Kojto 122:f9eeca106725 5608 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
Kojto 122:f9eeca106725 5609 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
Kojto 122:f9eeca106725 5610 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
Kojto 122:f9eeca106725 5611 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
Kojto 122:f9eeca106725 5612 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
Kojto 122:f9eeca106725 5613 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
Kojto 122:f9eeca106725 5614 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
Kojto 122:f9eeca106725 5615 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000U) /*!< bit 16 */
Kojto 122:f9eeca106725 5616 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000U) /*!< bit 17 */
Kojto 122:f9eeca106725 5617 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000U) /*!< bit 18 */
Kojto 122:f9eeca106725 5618 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000U) /*!< bit 19 */
Kojto 122:f9eeca106725 5619 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000U) /*!< bit 20 */
Kojto 122:f9eeca106725 5620 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000U) /*!< bit 21 */
Kojto 122:f9eeca106725 5621 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000U) /*!< bit 22 */
Kojto 122:f9eeca106725 5622 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000U) /*!< bit 23 */
Kojto 122:f9eeca106725 5623 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000U) /*!< bit 24 */
Kojto 122:f9eeca106725 5624 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000U) /*!< bit 25 */
Kojto 122:f9eeca106725 5625 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000U) /*!< bit 26 */
Kojto 122:f9eeca106725 5626 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000U) /*!< bit 27 */
Kojto 122:f9eeca106725 5627 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000U) /*!< bit 28 */
Kojto 122:f9eeca106725 5628 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000U) /*!< bit 29 */
Kojto 122:f9eeca106725 5629 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000U) /*!< bit 30 */
Kojto 122:f9eeca106725 5630 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000U) /*!< bit 31 */
Kojto 90:cb3d968589d8 5631
Kojto 90:cb3d968589d8 5632 /****************** Bit definition for NVIC_ICER register *******************/
Kojto 122:f9eeca106725 5633 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFFU) /*!< Interrupt clear-enable bits */
Kojto 122:f9eeca106725 5634 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001U) /*!< bit 0 */
Kojto 122:f9eeca106725 5635 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002U) /*!< bit 1 */
Kojto 122:f9eeca106725 5636 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004U) /*!< bit 2 */
Kojto 122:f9eeca106725 5637 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008U) /*!< bit 3 */
Kojto 122:f9eeca106725 5638 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010U) /*!< bit 4 */
Kojto 122:f9eeca106725 5639 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020U) /*!< bit 5 */
Kojto 122:f9eeca106725 5640 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040U) /*!< bit 6 */
Kojto 122:f9eeca106725 5641 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080U) /*!< bit 7 */
Kojto 122:f9eeca106725 5642 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100U) /*!< bit 8 */
Kojto 122:f9eeca106725 5643 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200U) /*!< bit 9 */
Kojto 122:f9eeca106725 5644 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400U) /*!< bit 10 */
Kojto 122:f9eeca106725 5645 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800U) /*!< bit 11 */
Kojto 122:f9eeca106725 5646 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000U) /*!< bit 12 */
Kojto 122:f9eeca106725 5647 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000U) /*!< bit 13 */
Kojto 122:f9eeca106725 5648 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000U) /*!< bit 14 */
Kojto 122:f9eeca106725 5649 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000U) /*!< bit 15 */
Kojto 122:f9eeca106725 5650 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000U) /*!< bit 16 */
Kojto 122:f9eeca106725 5651 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000U) /*!< bit 17 */
Kojto 122:f9eeca106725 5652 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000U) /*!< bit 18 */
Kojto 122:f9eeca106725 5653 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000U) /*!< bit 19 */
Kojto 122:f9eeca106725 5654 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000U) /*!< bit 20 */
Kojto 122:f9eeca106725 5655 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000U) /*!< bit 21 */
Kojto 122:f9eeca106725 5656 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000U) /*!< bit 22 */
Kojto 122:f9eeca106725 5657 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000U) /*!< bit 23 */
Kojto 122:f9eeca106725 5658 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000U) /*!< bit 24 */
Kojto 122:f9eeca106725 5659 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000U) /*!< bit 25 */
Kojto 122:f9eeca106725 5660 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000U) /*!< bit 26 */
Kojto 122:f9eeca106725 5661 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000U) /*!< bit 27 */
Kojto 122:f9eeca106725 5662 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000U) /*!< bit 28 */
Kojto 122:f9eeca106725 5663 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000U) /*!< bit 29 */
Kojto 122:f9eeca106725 5664 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000U) /*!< bit 30 */
Kojto 122:f9eeca106725 5665 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000U) /*!< bit 31 */
Kojto 90:cb3d968589d8 5666
Kojto 90:cb3d968589d8 5667 /****************** Bit definition for NVIC_ISPR register *******************/
Kojto 122:f9eeca106725 5668 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFFU) /*!< Interrupt set-pending bits */
Kojto 122:f9eeca106725 5669 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001U) /*!< bit 0 */
Kojto 122:f9eeca106725 5670 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002U) /*!< bit 1 */
Kojto 122:f9eeca106725 5671 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004U) /*!< bit 2 */
Kojto 122:f9eeca106725 5672 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008U) /*!< bit 3 */
Kojto 122:f9eeca106725 5673 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010U) /*!< bit 4 */
Kojto 122:f9eeca106725 5674 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020U) /*!< bit 5 */
Kojto 122:f9eeca106725 5675 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040U) /*!< bit 6 */
Kojto 122:f9eeca106725 5676 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080U) /*!< bit 7 */
Kojto 122:f9eeca106725 5677 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100U) /*!< bit 8 */
Kojto 122:f9eeca106725 5678 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200U) /*!< bit 9 */
Kojto 122:f9eeca106725 5679 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400U) /*!< bit 10 */
Kojto 122:f9eeca106725 5680 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800U) /*!< bit 11 */
Kojto 122:f9eeca106725 5681 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000U) /*!< bit 12 */
Kojto 122:f9eeca106725 5682 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000U) /*!< bit 13 */
Kojto 122:f9eeca106725 5683 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000U) /*!< bit 14 */
Kojto 122:f9eeca106725 5684 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000U) /*!< bit 15 */
Kojto 122:f9eeca106725 5685 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000U) /*!< bit 16 */
Kojto 122:f9eeca106725 5686 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000U) /*!< bit 17 */
Kojto 122:f9eeca106725 5687 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000U) /*!< bit 18 */
Kojto 122:f9eeca106725 5688 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000U) /*!< bit 19 */
Kojto 122:f9eeca106725 5689 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000U) /*!< bit 20 */
Kojto 122:f9eeca106725 5690 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000U) /*!< bit 21 */
Kojto 122:f9eeca106725 5691 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000U) /*!< bit 22 */
Kojto 122:f9eeca106725 5692 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000U) /*!< bit 23 */
Kojto 122:f9eeca106725 5693 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000U) /*!< bit 24 */
Kojto 122:f9eeca106725 5694 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000U) /*!< bit 25 */
Kojto 122:f9eeca106725 5695 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000U) /*!< bit 26 */
Kojto 122:f9eeca106725 5696 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000U) /*!< bit 27 */
Kojto 122:f9eeca106725 5697 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000U) /*!< bit 28 */
Kojto 122:f9eeca106725 5698 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000U) /*!< bit 29 */
Kojto 122:f9eeca106725 5699 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000U) /*!< bit 30 */
Kojto 122:f9eeca106725 5700 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000U) /*!< bit 31 */
Kojto 90:cb3d968589d8 5701
Kojto 90:cb3d968589d8 5702 /****************** Bit definition for NVIC_ICPR register *******************/
Kojto 122:f9eeca106725 5703 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFFU) /*!< Interrupt clear-pending bits */
Kojto 122:f9eeca106725 5704 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001U) /*!< bit 0 */
Kojto 122:f9eeca106725 5705 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002U) /*!< bit 1 */
Kojto 122:f9eeca106725 5706 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004U) /*!< bit 2 */
Kojto 122:f9eeca106725 5707 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008U) /*!< bit 3 */
Kojto 122:f9eeca106725 5708 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010U) /*!< bit 4 */
Kojto 122:f9eeca106725 5709 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020U) /*!< bit 5 */
Kojto 122:f9eeca106725 5710 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040U) /*!< bit 6 */
Kojto 122:f9eeca106725 5711 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080U) /*!< bit 7 */
Kojto 122:f9eeca106725 5712 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100U) /*!< bit 8 */
Kojto 122:f9eeca106725 5713 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200U) /*!< bit 9 */
Kojto 122:f9eeca106725 5714 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400U) /*!< bit 10 */
Kojto 122:f9eeca106725 5715 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800U) /*!< bit 11 */
Kojto 122:f9eeca106725 5716 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000U) /*!< bit 12 */
Kojto 122:f9eeca106725 5717 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000U) /*!< bit 13 */
Kojto 122:f9eeca106725 5718 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000U) /*!< bit 14 */
Kojto 122:f9eeca106725 5719 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000U) /*!< bit 15 */
Kojto 122:f9eeca106725 5720 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000U) /*!< bit 16 */
Kojto 122:f9eeca106725 5721 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000U) /*!< bit 17 */
Kojto 122:f9eeca106725 5722 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000U) /*!< bit 18 */
Kojto 122:f9eeca106725 5723 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000U) /*!< bit 19 */
Kojto 122:f9eeca106725 5724 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000U) /*!< bit 20 */
Kojto 122:f9eeca106725 5725 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000U) /*!< bit 21 */
Kojto 122:f9eeca106725 5726 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000U) /*!< bit 22 */
Kojto 122:f9eeca106725 5727 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000U) /*!< bit 23 */
Kojto 122:f9eeca106725 5728 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000U) /*!< bit 24 */
Kojto 122:f9eeca106725 5729 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000U) /*!< bit 25 */
Kojto 122:f9eeca106725 5730 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000U) /*!< bit 26 */
Kojto 122:f9eeca106725 5731 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000U) /*!< bit 27 */
Kojto 122:f9eeca106725 5732 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000U) /*!< bit 28 */
Kojto 122:f9eeca106725 5733 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000U) /*!< bit 29 */
Kojto 122:f9eeca106725 5734 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000U) /*!< bit 30 */
Kojto 122:f9eeca106725 5735 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000U) /*!< bit 31 */
Kojto 90:cb3d968589d8 5736
Kojto 90:cb3d968589d8 5737 /****************** Bit definition for NVIC_IABR register *******************/
Kojto 122:f9eeca106725 5738 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFFU) /*!< Interrupt active flags */
Kojto 122:f9eeca106725 5739 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001U) /*!< bit 0 */
Kojto 122:f9eeca106725 5740 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002U) /*!< bit 1 */
Kojto 122:f9eeca106725 5741 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004U) /*!< bit 2 */
Kojto 122:f9eeca106725 5742 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008U) /*!< bit 3 */
Kojto 122:f9eeca106725 5743 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010U) /*!< bit 4 */
Kojto 122:f9eeca106725 5744 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020U) /*!< bit 5 */
Kojto 122:f9eeca106725 5745 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040U) /*!< bit 6 */
Kojto 122:f9eeca106725 5746 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080U) /*!< bit 7 */
Kojto 122:f9eeca106725 5747 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100U) /*!< bit 8 */
Kojto 122:f9eeca106725 5748 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200U) /*!< bit 9 */
Kojto 122:f9eeca106725 5749 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400U) /*!< bit 10 */
Kojto 122:f9eeca106725 5750 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800U) /*!< bit 11 */
Kojto 122:f9eeca106725 5751 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000U) /*!< bit 12 */
Kojto 122:f9eeca106725 5752 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000U) /*!< bit 13 */
Kojto 122:f9eeca106725 5753 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000U) /*!< bit 14 */
Kojto 122:f9eeca106725 5754 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000U) /*!< bit 15 */
Kojto 122:f9eeca106725 5755 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000U) /*!< bit 16 */
Kojto 122:f9eeca106725 5756 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000U) /*!< bit 17 */
Kojto 122:f9eeca106725 5757 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000U) /*!< bit 18 */
Kojto 122:f9eeca106725 5758 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000U) /*!< bit 19 */
Kojto 122:f9eeca106725 5759 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000U) /*!< bit 20 */
Kojto 122:f9eeca106725 5760 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000U) /*!< bit 21 */
Kojto 122:f9eeca106725 5761 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000U) /*!< bit 22 */
Kojto 122:f9eeca106725 5762 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000U) /*!< bit 23 */
Kojto 122:f9eeca106725 5763 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000U) /*!< bit 24 */
Kojto 122:f9eeca106725 5764 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000U) /*!< bit 25 */
Kojto 122:f9eeca106725 5765 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000U) /*!< bit 26 */
Kojto 122:f9eeca106725 5766 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000U) /*!< bit 27 */
Kojto 122:f9eeca106725 5767 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000U) /*!< bit 28 */
Kojto 122:f9eeca106725 5768 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000U) /*!< bit 29 */
Kojto 122:f9eeca106725 5769 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000U) /*!< bit 30 */
Kojto 122:f9eeca106725 5770 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000U) /*!< bit 31 */
Kojto 90:cb3d968589d8 5771
Kojto 90:cb3d968589d8 5772 /****************** Bit definition for NVIC_PRI0 register *******************/
Kojto 122:f9eeca106725 5773 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 0 */
Kojto 122:f9eeca106725 5774 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 1 */
Kojto 122:f9eeca106725 5775 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 2 */
Kojto 122:f9eeca106725 5776 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 3 */
Kojto 90:cb3d968589d8 5777
Kojto 90:cb3d968589d8 5778 /****************** Bit definition for NVIC_PRI1 register *******************/
Kojto 122:f9eeca106725 5779 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 4 */
Kojto 122:f9eeca106725 5780 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 5 */
Kojto 122:f9eeca106725 5781 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 6 */
Kojto 122:f9eeca106725 5782 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 7 */
Kojto 90:cb3d968589d8 5783
Kojto 90:cb3d968589d8 5784 /****************** Bit definition for NVIC_PRI2 register *******************/
Kojto 122:f9eeca106725 5785 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 8 */
Kojto 122:f9eeca106725 5786 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 9 */
Kojto 122:f9eeca106725 5787 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 10 */
Kojto 122:f9eeca106725 5788 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 11 */
Kojto 90:cb3d968589d8 5789
Kojto 90:cb3d968589d8 5790 /****************** Bit definition for NVIC_PRI3 register *******************/
Kojto 122:f9eeca106725 5791 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 12 */
Kojto 122:f9eeca106725 5792 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 13 */
Kojto 122:f9eeca106725 5793 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 14 */
Kojto 122:f9eeca106725 5794 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 15 */
Kojto 90:cb3d968589d8 5795
Kojto 90:cb3d968589d8 5796 /****************** Bit definition for NVIC_PRI4 register *******************/
Kojto 122:f9eeca106725 5797 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 16 */
Kojto 122:f9eeca106725 5798 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 17 */
Kojto 122:f9eeca106725 5799 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 18 */
Kojto 122:f9eeca106725 5800 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 19 */
Kojto 90:cb3d968589d8 5801
Kojto 90:cb3d968589d8 5802 /****************** Bit definition for NVIC_PRI5 register *******************/
Kojto 122:f9eeca106725 5803 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 20 */
Kojto 122:f9eeca106725 5804 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 21 */
Kojto 122:f9eeca106725 5805 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 22 */
Kojto 122:f9eeca106725 5806 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 23 */
Kojto 90:cb3d968589d8 5807
Kojto 90:cb3d968589d8 5808 /****************** Bit definition for NVIC_PRI6 register *******************/
Kojto 122:f9eeca106725 5809 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 24 */
Kojto 122:f9eeca106725 5810 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 25 */
Kojto 122:f9eeca106725 5811 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 26 */
Kojto 122:f9eeca106725 5812 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 27 */
Kojto 90:cb3d968589d8 5813
Kojto 90:cb3d968589d8 5814 /****************** Bit definition for NVIC_PRI7 register *******************/
Kojto 122:f9eeca106725 5815 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FFU) /*!< Priority of interrupt 28 */
Kojto 122:f9eeca106725 5816 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00U) /*!< Priority of interrupt 29 */
Kojto 122:f9eeca106725 5817 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000U) /*!< Priority of interrupt 30 */
Kojto 122:f9eeca106725 5818 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000U) /*!< Priority of interrupt 31 */
Kojto 90:cb3d968589d8 5819
Kojto 90:cb3d968589d8 5820 /****************** Bit definition for SCB_CPUID register *******************/
Kojto 122:f9eeca106725 5821 #define SCB_CPUID_REVISION ((uint32_t)0x0000000FU) /*!< Implementation defined revision number */
Kojto 122:f9eeca106725 5822 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0U) /*!< Number of processor within family */
Kojto 122:f9eeca106725 5823 #define SCB_CPUID_Constant ((uint32_t)0x000F0000U) /*!< Reads as 0x0F */
Kojto 122:f9eeca106725 5824 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000U) /*!< Implementation defined variant number */
Kojto 122:f9eeca106725 5825 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000U) /*!< Implementer code. ARM is 0x41 */
Kojto 90:cb3d968589d8 5826
Kojto 90:cb3d968589d8 5827 /******************* Bit definition for SCB_ICSR register *******************/
Kojto 122:f9eeca106725 5828 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FFU) /*!< Active ISR number field */
Kojto 122:f9eeca106725 5829 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
Kojto 122:f9eeca106725 5830 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000U) /*!< Pending ISR number field */
Kojto 122:f9eeca106725 5831 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000U) /*!< Interrupt pending flag */
Kojto 122:f9eeca106725 5832 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
Kojto 122:f9eeca106725 5833 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000U) /*!< Clear pending SysTick bit */
Kojto 122:f9eeca106725 5834 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000U) /*!< Set pending SysTick bit */
Kojto 122:f9eeca106725 5835 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000U) /*!< Clear pending pendSV bit */
Kojto 122:f9eeca106725 5836 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000U) /*!< Set pending pendSV bit */
Kojto 122:f9eeca106725 5837 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000U) /*!< Set pending NMI bit */
Kojto 90:cb3d968589d8 5838
Kojto 90:cb3d968589d8 5839 /******************* Bit definition for SCB_VTOR register *******************/
Kojto 122:f9eeca106725 5840 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80U) /*!< Vector table base offset field */
Kojto 122:f9eeca106725 5841 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000U) /*!< Table base in code(0) or RAM(1) */
Kojto 90:cb3d968589d8 5842
Kojto 90:cb3d968589d8 5843 /*!<***************** Bit definition for SCB_AIRCR register *******************/
Kojto 122:f9eeca106725 5844 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001U) /*!< System Reset bit */
Kojto 122:f9eeca106725 5845 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002U) /*!< Clear active vector bit */
Kojto 122:f9eeca106725 5846 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004U) /*!< Requests chip control logic to generate a reset */
Kojto 122:f9eeca106725 5847
Kojto 122:f9eeca106725 5848 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */
Kojto 122:f9eeca106725 5849 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
Kojto 122:f9eeca106725 5850 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
Kojto 122:f9eeca106725 5851 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
Kojto 90:cb3d968589d8 5852
Kojto 90:cb3d968589d8 5853 /* prority group configuration */
Kojto 122:f9eeca106725 5854 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
Kojto 122:f9eeca106725 5855 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
Kojto 122:f9eeca106725 5856 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
Kojto 122:f9eeca106725 5857 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
Kojto 122:f9eeca106725 5858 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
Kojto 122:f9eeca106725 5859 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
Kojto 122:f9eeca106725 5860 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
Kojto 122:f9eeca106725 5861 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
Kojto 122:f9eeca106725 5862
Kojto 122:f9eeca106725 5863 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000U) /*!< Data endianness bit */
Kojto 122:f9eeca106725 5864 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
Kojto 90:cb3d968589d8 5865
Kojto 90:cb3d968589d8 5866 /******************* Bit definition for SCB_SCR register ********************/
Kojto 122:f9eeca106725 5867 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002U) /*!< Sleep on exit bit */
Kojto 122:f9eeca106725 5868 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004U) /*!< Sleep deep bit */
Kojto 122:f9eeca106725 5869 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010U) /*!< Wake up from WFE */
Kojto 90:cb3d968589d8 5870
Kojto 90:cb3d968589d8 5871 /******************** Bit definition for SCB_CCR register *******************/
Kojto 122:f9eeca106725 5872 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
Kojto 122:f9eeca106725 5873 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
Kojto 122:f9eeca106725 5874 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008U) /*!< Trap for unaligned access */
Kojto 122:f9eeca106725 5875 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010U) /*!< Trap on Divide by 0 */
Kojto 122:f9eeca106725 5876 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100U) /*!< Handlers running at priority -1 and -2 */
Kojto 122:f9eeca106725 5877 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
Kojto 90:cb3d968589d8 5878
Kojto 90:cb3d968589d8 5879 /******************* Bit definition for SCB_SHPR register ********************/
Kojto 122:f9eeca106725 5880 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FFU) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
Kojto 122:f9eeca106725 5881 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00U) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
Kojto 122:f9eeca106725 5882 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000U) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
Kojto 122:f9eeca106725 5883 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000U) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
Kojto 90:cb3d968589d8 5884
Kojto 90:cb3d968589d8 5885 /****************** Bit definition for SCB_SHCSR register *******************/
Kojto 122:f9eeca106725 5886 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001U) /*!< MemManage is active */
Kojto 122:f9eeca106725 5887 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002U) /*!< BusFault is active */
Kojto 122:f9eeca106725 5888 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008U) /*!< UsageFault is active */
Kojto 122:f9eeca106725 5889 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080U) /*!< SVCall is active */
Kojto 122:f9eeca106725 5890 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100U) /*!< Monitor is active */
Kojto 122:f9eeca106725 5891 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400U) /*!< PendSV is active */
Kojto 122:f9eeca106725 5892 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800U) /*!< SysTick is active */
Kojto 122:f9eeca106725 5893 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000U) /*!< Usage Fault is pended */
Kojto 122:f9eeca106725 5894 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000U) /*!< MemManage is pended */
Kojto 122:f9eeca106725 5895 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000U) /*!< Bus Fault is pended */
Kojto 122:f9eeca106725 5896 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000U) /*!< SVCall is pended */
Kojto 122:f9eeca106725 5897 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000U) /*!< MemManage enable */
Kojto 122:f9eeca106725 5898 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000U) /*!< Bus Fault enable */
Kojto 122:f9eeca106725 5899 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000U) /*!< UsageFault enable */
Kojto 90:cb3d968589d8 5900
Kojto 90:cb3d968589d8 5901 /******************* Bit definition for SCB_CFSR register *******************/
Kojto 90:cb3d968589d8 5902 /*!< MFSR */
Kojto 122:f9eeca106725 5903 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001U) /*!< Instruction access violation */
Kojto 122:f9eeca106725 5904 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002U) /*!< Data access violation */
Kojto 122:f9eeca106725 5905 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008U) /*!< Unstacking error */
Kojto 122:f9eeca106725 5906 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010U) /*!< Stacking error */
Kojto 122:f9eeca106725 5907 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080U) /*!< Memory Manage Address Register address valid flag */
Kojto 90:cb3d968589d8 5908 /*!< BFSR */
Kojto 122:f9eeca106725 5909 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100U) /*!< Instruction bus error flag */
Kojto 122:f9eeca106725 5910 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200U) /*!< Precise data bus error */
Kojto 122:f9eeca106725 5911 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400U) /*!< Imprecise data bus error */
Kojto 122:f9eeca106725 5912 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800U) /*!< Unstacking error */
Kojto 122:f9eeca106725 5913 #define SCB_CFSR_STKERR ((uint32_t)0x00001000U) /*!< Stacking error */
Kojto 122:f9eeca106725 5914 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000U) /*!< Bus Fault Address Register address valid flag */
Kojto 90:cb3d968589d8 5915 /*!< UFSR */
Kojto 122:f9eeca106725 5916 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000U) /*!< The processor attempt to excecute an undefined instruction */
Kojto 122:f9eeca106725 5917 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000U) /*!< Invalid combination of EPSR and instruction */
Kojto 122:f9eeca106725 5918 #define SCB_CFSR_INVPC ((uint32_t)0x00040000U) /*!< Attempt to load EXC_RETURN into pc illegally */
Kojto 122:f9eeca106725 5919 #define SCB_CFSR_NOCP ((uint32_t)0x00080000U) /*!< Attempt to use a coprocessor instruction */
Kojto 122:f9eeca106725 5920 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000U) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
Kojto 122:f9eeca106725 5921 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000U) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
Kojto 90:cb3d968589d8 5922
Kojto 90:cb3d968589d8 5923 /******************* Bit definition for SCB_HFSR register *******************/
Kojto 122:f9eeca106725 5924 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002U) /*!< Fault occures because of vector table read on exception processing */
Kojto 122:f9eeca106725 5925 #define SCB_HFSR_FORCED ((uint32_t)0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
Kojto 122:f9eeca106725 5926 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000U) /*!< Fault related to debug */
Kojto 90:cb3d968589d8 5927
Kojto 90:cb3d968589d8 5928 /******************* Bit definition for SCB_DFSR register *******************/
Kojto 122:f9eeca106725 5929 #define SCB_DFSR_HALTED ((uint32_t)0x00000001U) /*!< Halt request flag */
Kojto 122:f9eeca106725 5930 #define SCB_DFSR_BKPT ((uint32_t)0x00000002U) /*!< BKPT flag */
Kojto 122:f9eeca106725 5931 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */
Kojto 122:f9eeca106725 5932 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008U) /*!< Vector catch flag */
Kojto 122:f9eeca106725 5933 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010U) /*!< External debug request flag */
Kojto 90:cb3d968589d8 5934
Kojto 90:cb3d968589d8 5935 /******************* Bit definition for SCB_MMFAR register ******************/
Kojto 122:f9eeca106725 5936 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFFU) /*!< Mem Manage fault address field */
Kojto 90:cb3d968589d8 5937
Kojto 90:cb3d968589d8 5938 /******************* Bit definition for SCB_BFAR register *******************/
Kojto 122:f9eeca106725 5939 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFFU) /*!< Bus fault address field */
Kojto 90:cb3d968589d8 5940
Kojto 90:cb3d968589d8 5941 /******************* Bit definition for SCB_afsr register *******************/
Kojto 122:f9eeca106725 5942 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFFU) /*!< Implementation defined */
Kojto 90:cb3d968589d8 5943 /**
Kojto 90:cb3d968589d8 5944 * @}
Kojto 90:cb3d968589d8 5945 */
Kojto 90:cb3d968589d8 5946
Kojto 90:cb3d968589d8 5947 /**
Kojto 90:cb3d968589d8 5948 * @}
Kojto 90:cb3d968589d8 5949 */
Kojto 90:cb3d968589d8 5950 /** @addtogroup Exported_macro
Kojto 90:cb3d968589d8 5951 * @{
Kojto 90:cb3d968589d8 5952 */
Kojto 90:cb3d968589d8 5953
Kojto 90:cb3d968589d8 5954 /****************************** ADC Instances *********************************/
Kojto 90:cb3d968589d8 5955 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 90:cb3d968589d8 5956
Kojto 122:f9eeca106725 5957 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
Kojto 122:f9eeca106725 5958
Kojto 90:cb3d968589d8 5959 /******************************** COMP Instances ******************************/
Kojto 90:cb3d968589d8 5960 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
Kojto 90:cb3d968589d8 5961 ((INSTANCE) == COMP2))
Kojto 90:cb3d968589d8 5962
Kojto 90:cb3d968589d8 5963 /****************************** CRC Instances *********************************/
Kojto 90:cb3d968589d8 5964 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 90:cb3d968589d8 5965
Kojto 90:cb3d968589d8 5966 /****************************** DAC Instances *********************************/
Kojto 90:cb3d968589d8 5967 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Kojto 90:cb3d968589d8 5968
Kojto 90:cb3d968589d8 5969 /****************************** DMA Instances *********************************/
Kojto 90:cb3d968589d8 5970 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 90:cb3d968589d8 5971 ((INSTANCE) == DMA1_Channel2) || \
Kojto 90:cb3d968589d8 5972 ((INSTANCE) == DMA1_Channel3) || \
Kojto 90:cb3d968589d8 5973 ((INSTANCE) == DMA1_Channel4) || \
Kojto 90:cb3d968589d8 5974 ((INSTANCE) == DMA1_Channel5) || \
Kojto 90:cb3d968589d8 5975 ((INSTANCE) == DMA1_Channel6) || \
Kojto 90:cb3d968589d8 5976 ((INSTANCE) == DMA1_Channel7) || \
Kojto 90:cb3d968589d8 5977 ((INSTANCE) == DMA2_Channel1) || \
Kojto 90:cb3d968589d8 5978 ((INSTANCE) == DMA2_Channel2) || \
Kojto 90:cb3d968589d8 5979 ((INSTANCE) == DMA2_Channel3) || \
Kojto 90:cb3d968589d8 5980 ((INSTANCE) == DMA2_Channel4) || \
Kojto 90:cb3d968589d8 5981 ((INSTANCE) == DMA2_Channel5))
Kojto 90:cb3d968589d8 5982
Kojto 90:cb3d968589d8 5983 /******************************* GPIO Instances *******************************/
Kojto 90:cb3d968589d8 5984 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 90:cb3d968589d8 5985 ((INSTANCE) == GPIOB) || \
Kojto 90:cb3d968589d8 5986 ((INSTANCE) == GPIOC) || \
Kojto 90:cb3d968589d8 5987 ((INSTANCE) == GPIOD) || \
Kojto 90:cb3d968589d8 5988 ((INSTANCE) == GPIOE) || \
Kojto 90:cb3d968589d8 5989 ((INSTANCE) == GPIOF) || \
Kojto 90:cb3d968589d8 5990 ((INSTANCE) == GPIOG) || \
Kojto 90:cb3d968589d8 5991 ((INSTANCE) == GPIOH))
Kojto 90:cb3d968589d8 5992
Kojto 122:f9eeca106725 5993 /**************************** GPIO Alternate Function Instances ***************/
Kojto 122:f9eeca106725 5994 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
Kojto 122:f9eeca106725 5995
Kojto 90:cb3d968589d8 5996 /**************************** GPIO Lock Instances *****************************/
Kojto 90:cb3d968589d8 5997 /* On L1, all GPIO Bank support the Lock mechanism */
Kojto 90:cb3d968589d8 5998 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
Kojto 90:cb3d968589d8 5999
Kojto 90:cb3d968589d8 6000 /******************************** I2C Instances *******************************/
Kojto 90:cb3d968589d8 6001 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 90:cb3d968589d8 6002 ((INSTANCE) == I2C2))
Kojto 90:cb3d968589d8 6003
Kojto 122:f9eeca106725 6004 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
Kojto 90:cb3d968589d8 6005 ((INSTANCE) == SPI3))
Kojto 90:cb3d968589d8 6006 /****************************** IWDG Instances ********************************/
Kojto 90:cb3d968589d8 6007 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 90:cb3d968589d8 6008
Kojto 90:cb3d968589d8 6009 /****************************** OPAMP Instances *******************************/
Kojto 90:cb3d968589d8 6010 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
Kojto 90:cb3d968589d8 6011 ((INSTANCE) == OPAMP2))
Kojto 90:cb3d968589d8 6012
Kojto 90:cb3d968589d8 6013 /****************************** RTC Instances *********************************/
Kojto 90:cb3d968589d8 6014 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 90:cb3d968589d8 6015
Kojto 90:cb3d968589d8 6016 /******************************** SPI Instances *******************************/
Kojto 90:cb3d968589d8 6017 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 90:cb3d968589d8 6018 ((INSTANCE) == SPI2) || \
Kojto 90:cb3d968589d8 6019 ((INSTANCE) == SPI3))
Kojto 90:cb3d968589d8 6020
Kojto 90:cb3d968589d8 6021 /****************************** TIM Instances *********************************/
Kojto 90:cb3d968589d8 6022 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6023 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6024 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6025 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6026 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 6027 ((INSTANCE) == TIM7) || \
Kojto 90:cb3d968589d8 6028 ((INSTANCE) == TIM9) || \
Kojto 90:cb3d968589d8 6029 ((INSTANCE) == TIM10) || \
Kojto 90:cb3d968589d8 6030 ((INSTANCE) == TIM11))
Kojto 90:cb3d968589d8 6031
Kojto 90:cb3d968589d8 6032 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6033 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6034 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6035 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6036 ((INSTANCE) == TIM9) || \
Kojto 90:cb3d968589d8 6037 ((INSTANCE) == TIM10) || \
Kojto 90:cb3d968589d8 6038 ((INSTANCE) == TIM11))
Kojto 90:cb3d968589d8 6039
Kojto 90:cb3d968589d8 6040 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6041 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6042 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6043 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6044 ((INSTANCE) == TIM9))
Kojto 90:cb3d968589d8 6045
Kojto 90:cb3d968589d8 6046 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6047 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6048 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6049 ((INSTANCE) == TIM5))
Kojto 90:cb3d968589d8 6050
Kojto 90:cb3d968589d8 6051 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6052 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6053 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6054 ((INSTANCE) == TIM5))
Kojto 90:cb3d968589d8 6055
Kojto 90:cb3d968589d8 6056 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6057 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6058 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6059 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6060 ((INSTANCE) == TIM9))
Kojto 90:cb3d968589d8 6061
Kojto 90:cb3d968589d8 6062 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6063 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6064 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6065 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6066 ((INSTANCE) == TIM9) || \
Kojto 90:cb3d968589d8 6067 ((INSTANCE) == TIM10) || \
Kojto 90:cb3d968589d8 6068 ((INSTANCE) == TIM11))
Kojto 90:cb3d968589d8 6069
Kojto 90:cb3d968589d8 6070 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6071 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6072 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6073 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6074 ((INSTANCE) == TIM9))
Kojto 90:cb3d968589d8 6075
Kojto 90:cb3d968589d8 6076 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6077 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6078 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6079 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6080 ((INSTANCE) == TIM9))
Kojto 90:cb3d968589d8 6081
Kojto 90:cb3d968589d8 6082 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6083 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6084 ((INSTANCE) == TIM4))
Kojto 90:cb3d968589d8 6085
Kojto 90:cb3d968589d8 6086 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6087 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6088 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6089 ((INSTANCE) == TIM5))
Kojto 90:cb3d968589d8 6090
Kojto 90:cb3d968589d8 6091 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6092 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6093 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6094 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6095 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 6096 ((INSTANCE) == TIM7) || \
Kojto 90:cb3d968589d8 6097 ((INSTANCE) == TIM9))
Kojto 90:cb3d968589d8 6098
Kojto 90:cb3d968589d8 6099 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6100 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6101 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6102 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6103 ((INSTANCE) == TIM9))
Kojto 90:cb3d968589d8 6104
Kojto 90:cb3d968589d8 6105 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
Kojto 90:cb3d968589d8 6106
Kojto 90:cb3d968589d8 6107 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6108 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6109 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6110 ((INSTANCE) == TIM5))
Kojto 90:cb3d968589d8 6111
Kojto 90:cb3d968589d8 6112 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 90:cb3d968589d8 6113 ((((INSTANCE) == TIM2) && \
Kojto 90:cb3d968589d8 6114 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 6115 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 6116 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 6117 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 6118 || \
Kojto 90:cb3d968589d8 6119 (((INSTANCE) == TIM3) && \
Kojto 90:cb3d968589d8 6120 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 6121 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 6122 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 6123 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 6124 || \
Kojto 90:cb3d968589d8 6125 (((INSTANCE) == TIM4) && \
Kojto 90:cb3d968589d8 6126 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 6127 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 6128 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 6129 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 6130 || \
Kojto 90:cb3d968589d8 6131 (((INSTANCE) == TIM5) && \
Kojto 90:cb3d968589d8 6132 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 6133 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 6134 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 6135 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 6136 || \
Kojto 90:cb3d968589d8 6137 (((INSTANCE) == TIM9) && \
Kojto 90:cb3d968589d8 6138 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 6139 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 90:cb3d968589d8 6140 || \
Kojto 90:cb3d968589d8 6141 (((INSTANCE) == TIM10) && \
Kojto 90:cb3d968589d8 6142 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 90:cb3d968589d8 6143 || \
Kojto 90:cb3d968589d8 6144 (((INSTANCE) == TIM11) && \
Kojto 90:cb3d968589d8 6145 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 90:cb3d968589d8 6146
Kojto 90:cb3d968589d8 6147 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6148 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6149 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6150 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6151 ((INSTANCE) == TIM9) || \
Kojto 90:cb3d968589d8 6152 ((INSTANCE) == TIM10) || \
Kojto 90:cb3d968589d8 6153 ((INSTANCE) == TIM11))
Kojto 90:cb3d968589d8 6154
Kojto 90:cb3d968589d8 6155 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6156 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6157 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6158 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6159 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 6160 ((INSTANCE) == TIM7))
Kojto 90:cb3d968589d8 6161
Kojto 90:cb3d968589d8 6162 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6163 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6164 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6165 ((INSTANCE) == TIM5))
Kojto 90:cb3d968589d8 6166
Kojto 90:cb3d968589d8 6167 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6168 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6169 ((INSTANCE) == TIM4) || \
Kojto 90:cb3d968589d8 6170 ((INSTANCE) == TIM5) || \
Kojto 90:cb3d968589d8 6171 ((INSTANCE) == TIM9))
Kojto 90:cb3d968589d8 6172
Kojto 90:cb3d968589d8 6173 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6174 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6175 ((INSTANCE) == TIM4) || \
Kojto 122:f9eeca106725 6176 ((INSTANCE) == TIM5))
Kojto 90:cb3d968589d8 6177
Kojto 90:cb3d968589d8 6178 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 90:cb3d968589d8 6179 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 6180 ((INSTANCE) == TIM9) || \
Kojto 90:cb3d968589d8 6181 ((INSTANCE) == TIM10) || \
Kojto 90:cb3d968589d8 6182 ((INSTANCE) == TIM11))
Kojto 90:cb3d968589d8 6183
Kojto 90:cb3d968589d8 6184 /******************** USART Instances : Synchronous mode **********************/
Kojto 90:cb3d968589d8 6185 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 6186 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 6187 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 6188
Kojto 90:cb3d968589d8 6189 /******************** UART Instances : Asynchronous mode **********************/
Kojto 90:cb3d968589d8 6190 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 6191 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 6192 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 6193 ((INSTANCE) == UART4) || \
Kojto 90:cb3d968589d8 6194 ((INSTANCE) == UART5))
Kojto 90:cb3d968589d8 6195
Kojto 90:cb3d968589d8 6196 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 90:cb3d968589d8 6197 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 6198 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 6199 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 6200 ((INSTANCE) == UART4) || \
Kojto 90:cb3d968589d8 6201 ((INSTANCE) == UART5))
Kojto 90:cb3d968589d8 6202
Kojto 90:cb3d968589d8 6203 /******************** UART Instances : LIN mode **********************/
Kojto 90:cb3d968589d8 6204 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 6205 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 6206 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 6207 ((INSTANCE) == UART4) || \
Kojto 90:cb3d968589d8 6208 ((INSTANCE) == UART5))
Kojto 90:cb3d968589d8 6209
Kojto 90:cb3d968589d8 6210 /****************** UART Instances : Hardware Flow control ********************/
Kojto 90:cb3d968589d8 6211 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 6212 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 6213 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 6214
Kojto 90:cb3d968589d8 6215 /********************* UART Instances : Smard card mode ***********************/
Kojto 90:cb3d968589d8 6216 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 6217 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 6218 ((INSTANCE) == USART3))
Kojto 90:cb3d968589d8 6219
Kojto 90:cb3d968589d8 6220 /*********************** UART Instances : IRDA mode ***************************/
Kojto 90:cb3d968589d8 6221 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 6222 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 6223 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 6224 ((INSTANCE) == UART4) || \
Kojto 90:cb3d968589d8 6225 ((INSTANCE) == UART5))
Kojto 90:cb3d968589d8 6226
Kojto 90:cb3d968589d8 6227 /***************** UART Instances : Multi-Processor mode **********************/
Kojto 90:cb3d968589d8 6228 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 6229 ((INSTANCE) == USART2) || \
Kojto 90:cb3d968589d8 6230 ((INSTANCE) == USART3) || \
Kojto 90:cb3d968589d8 6231 ((INSTANCE) == UART4) || \
Kojto 90:cb3d968589d8 6232 ((INSTANCE) == UART5))
Kojto 90:cb3d968589d8 6233
Kojto 90:cb3d968589d8 6234 /****************************** WWDG Instances ********************************/
Kojto 90:cb3d968589d8 6235 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 90:cb3d968589d8 6236
Kojto 90:cb3d968589d8 6237
Kojto 90:cb3d968589d8 6238 /****************************** LCD Instances ********************************/
Kojto 90:cb3d968589d8 6239 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
Kojto 90:cb3d968589d8 6240
Kojto 90:cb3d968589d8 6241 /****************************** USB Instances ********************************/
Kojto 90:cb3d968589d8 6242 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
Kojto 90:cb3d968589d8 6243
Kojto 90:cb3d968589d8 6244 /**
Kojto 90:cb3d968589d8 6245 * @}
Kojto 90:cb3d968589d8 6246 */
Kojto 90:cb3d968589d8 6247
Kojto 90:cb3d968589d8 6248 /******************************************************************************/
Kojto 90:cb3d968589d8 6249 /* For a painless codes migration between the STM32L1xx device product */
Kojto 90:cb3d968589d8 6250 /* lines, the aliases defined below are put in place to overcome the */
Kojto 90:cb3d968589d8 6251 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 90:cb3d968589d8 6252 /* No need to update developed interrupt code when moving across */
Kojto 90:cb3d968589d8 6253 /* product lines within the same STM32L1 Family */
Kojto 90:cb3d968589d8 6254 /******************************************************************************/
Kojto 90:cb3d968589d8 6255
Kojto 90:cb3d968589d8 6256 /* Aliases for __IRQn */
Kojto 90:cb3d968589d8 6257
Kojto 90:cb3d968589d8 6258 /* Aliases for __IRQHandler */
Kojto 90:cb3d968589d8 6259
Kojto 90:cb3d968589d8 6260 /**
Kojto 90:cb3d968589d8 6261 * @}
Kojto 90:cb3d968589d8 6262 */
Kojto 90:cb3d968589d8 6263
Kojto 90:cb3d968589d8 6264 /**
Kojto 90:cb3d968589d8 6265 * @}
Kojto 90:cb3d968589d8 6266 */
Kojto 90:cb3d968589d8 6267
Kojto 90:cb3d968589d8 6268 #ifdef __cplusplus
Kojto 90:cb3d968589d8 6269 }
Kojto 90:cb3d968589d8 6270 #endif /* __cplusplus */
Kojto 90:cb3d968589d8 6271
Kojto 90:cb3d968589d8 6272 #endif /* __STM32L152xE_H */
Kojto 90:cb3d968589d8 6273
Kojto 90:cb3d968589d8 6274
Kojto 90:cb3d968589d8 6275
Kojto 90:cb3d968589d8 6276 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/