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TARGET_NUCLEO_F767ZI/stm32f767xx.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /**
Kojto 122:f9eeca106725 2 ******************************************************************************
Kojto 122:f9eeca106725 3 * @file stm32f767xx.h
Kojto 122:f9eeca106725 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.1.0
Kojto 122:f9eeca106725 6 * @date 22-April-2016
Kojto 122:f9eeca106725 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
Kojto 122:f9eeca106725 8 *
Kojto 122:f9eeca106725 9 * This file contains:
Kojto 122:f9eeca106725 10 * - Data structures and the address mapping for all peripherals
Kojto 122:f9eeca106725 11 * - Peripheral's registers declarations and bits definition
Kojto 122:f9eeca106725 12 * - Macros to access peripheral’s registers hardware
Kojto 122:f9eeca106725 13 *
Kojto 122:f9eeca106725 14 ******************************************************************************
Kojto 122:f9eeca106725 15 * @attention
Kojto 122:f9eeca106725 16 *
Kojto 122:f9eeca106725 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 122:f9eeca106725 18 *
Kojto 122:f9eeca106725 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 20 * are permitted provided that the following conditions are met:
Kojto 122:f9eeca106725 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 122:f9eeca106725 22 * this list of conditions and the following disclaimer.
Kojto 122:f9eeca106725 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 122:f9eeca106725 24 * this list of conditions and the following disclaimer in the documentation
Kojto 122:f9eeca106725 25 * and/or other materials provided with the distribution.
Kojto 122:f9eeca106725 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 122:f9eeca106725 27 * may be used to endorse or promote products derived from this software
Kojto 122:f9eeca106725 28 * without specific prior written permission.
Kojto 122:f9eeca106725 29 *
Kojto 122:f9eeca106725 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 122:f9eeca106725 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 122:f9eeca106725 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 122:f9eeca106725 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 122:f9eeca106725 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 122:f9eeca106725 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 122:f9eeca106725 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 122:f9eeca106725 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 122:f9eeca106725 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 40 *
Kojto 122:f9eeca106725 41 ******************************************************************************
Kojto 122:f9eeca106725 42 */
Kojto 122:f9eeca106725 43
Kojto 122:f9eeca106725 44 /** @addtogroup CMSIS_Device
Kojto 122:f9eeca106725 45 * @{
Kojto 122:f9eeca106725 46 */
Kojto 122:f9eeca106725 47
Kojto 122:f9eeca106725 48 /** @addtogroup stm32f767xx
Kojto 122:f9eeca106725 49 * @{
Kojto 122:f9eeca106725 50 */
Kojto 122:f9eeca106725 51
Kojto 122:f9eeca106725 52 #ifndef __STM32F767xx_H
Kojto 122:f9eeca106725 53 #define __STM32F767xx_H
Kojto 122:f9eeca106725 54
Kojto 122:f9eeca106725 55 #ifdef __cplusplus
Kojto 122:f9eeca106725 56 extern "C" {
Kojto 122:f9eeca106725 57 #endif /* __cplusplus */
Kojto 122:f9eeca106725 58
Kojto 122:f9eeca106725 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 122:f9eeca106725 60 * @{
Kojto 122:f9eeca106725 61 */
Kojto 122:f9eeca106725 62
Kojto 122:f9eeca106725 63 /**
Kojto 122:f9eeca106725 64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
Kojto 122:f9eeca106725 65 * in @ref Library_configuration_section
Kojto 122:f9eeca106725 66 */
Kojto 122:f9eeca106725 67 typedef enum
Kojto 122:f9eeca106725 68 {
Kojto 122:f9eeca106725 69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
Kojto 122:f9eeca106725 70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 122:f9eeca106725 71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
Kojto 122:f9eeca106725 72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
Kojto 122:f9eeca106725 73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
Kojto 122:f9eeca106725 74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
Kojto 122:f9eeca106725 75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
Kojto 122:f9eeca106725 76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
Kojto 122:f9eeca106725 77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
Kojto 122:f9eeca106725 78 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 122:f9eeca106725 79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 122:f9eeca106725 80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 122:f9eeca106725 81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 122:f9eeca106725 82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 122:f9eeca106725 83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 122:f9eeca106725 84 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 122:f9eeca106725 85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 122:f9eeca106725 86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 122:f9eeca106725 87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 122:f9eeca106725 88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 122:f9eeca106725 89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 122:f9eeca106725 90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
Kojto 122:f9eeca106725 91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
Kojto 122:f9eeca106725 92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
Kojto 122:f9eeca106725 93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
Kojto 122:f9eeca106725 94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
Kojto 122:f9eeca106725 95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
Kojto 122:f9eeca106725 96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
Kojto 122:f9eeca106725 97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
Kojto 122:f9eeca106725 98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
Kojto 122:f9eeca106725 99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
Kojto 122:f9eeca106725 100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
Kojto 122:f9eeca106725 101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
Kojto 122:f9eeca106725 102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 122:f9eeca106725 103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
Kojto 122:f9eeca106725 104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
Kojto 122:f9eeca106725 105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
Kojto 122:f9eeca106725 106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 122:f9eeca106725 107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 122:f9eeca106725 108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 122:f9eeca106725 109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 122:f9eeca106725 110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 122:f9eeca106725 111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 122:f9eeca106725 112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 122:f9eeca106725 113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 122:f9eeca106725 114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 122:f9eeca106725 115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 122:f9eeca106725 116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 122:f9eeca106725 117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 122:f9eeca106725 118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
Kojto 122:f9eeca106725 119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 122:f9eeca106725 120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 122:f9eeca106725 121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
Kojto 122:f9eeca106725 122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
Kojto 122:f9eeca106725 123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
Kojto 122:f9eeca106725 124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
Kojto 122:f9eeca106725 125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
Kojto 122:f9eeca106725 126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
Kojto 122:f9eeca106725 127 FMC_IRQn = 48, /*!< FMC global Interrupt */
Kojto 122:f9eeca106725 128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
Kojto 122:f9eeca106725 129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
Kojto 122:f9eeca106725 130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 122:f9eeca106725 131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
Kojto 122:f9eeca106725 132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
Kojto 122:f9eeca106725 133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
Kojto 122:f9eeca106725 134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
Kojto 122:f9eeca106725 135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
Kojto 122:f9eeca106725 136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
Kojto 122:f9eeca106725 137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
Kojto 122:f9eeca106725 138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
Kojto 122:f9eeca106725 139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
Kojto 122:f9eeca106725 140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
Kojto 122:f9eeca106725 141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
Kojto 122:f9eeca106725 142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
Kojto 122:f9eeca106725 143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
Kojto 122:f9eeca106725 144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
Kojto 122:f9eeca106725 145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
Kojto 122:f9eeca106725 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
Kojto 122:f9eeca106725 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
Kojto 122:f9eeca106725 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
Kojto 122:f9eeca106725 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
Kojto 122:f9eeca106725 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
Kojto 122:f9eeca106725 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 122:f9eeca106725 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 122:f9eeca106725 153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
Kojto 122:f9eeca106725 154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
Kojto 122:f9eeca106725 155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
Kojto 122:f9eeca106725 156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
Kojto 122:f9eeca106725 157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
Kojto 122:f9eeca106725 158 RNG_IRQn = 80, /*!< RNG global interrupt */
Kojto 122:f9eeca106725 159 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 122:f9eeca106725 160 UART7_IRQn = 82, /*!< UART7 global interrupt */
Kojto 122:f9eeca106725 161 UART8_IRQn = 83, /*!< UART8 global interrupt */
Kojto 122:f9eeca106725 162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
Kojto 122:f9eeca106725 163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
Kojto 122:f9eeca106725 164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
Kojto 122:f9eeca106725 165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
Kojto 122:f9eeca106725 166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
Kojto 122:f9eeca106725 167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
Kojto 122:f9eeca106725 168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
Kojto 122:f9eeca106725 169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
Kojto 122:f9eeca106725 170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
Kojto 122:f9eeca106725 171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
Kojto 122:f9eeca106725 172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
Kojto 122:f9eeca106725 173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
Kojto 122:f9eeca106725 174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
Kojto 122:f9eeca106725 175 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
Kojto 122:f9eeca106725 176 DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
Kojto 122:f9eeca106725 177 DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
Kojto 122:f9eeca106725 178 DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
Kojto 122:f9eeca106725 179 DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
Kojto 122:f9eeca106725 180 SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
Kojto 122:f9eeca106725 181 CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
Kojto 122:f9eeca106725 182 CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
Kojto 122:f9eeca106725 183 CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
Kojto 122:f9eeca106725 184 CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
Kojto 122:f9eeca106725 185 JPEG_IRQn = 108, /*!< JPEG global Interrupt */
Kojto 122:f9eeca106725 186 MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
Kojto 122:f9eeca106725 187 } IRQn_Type;
Kojto 122:f9eeca106725 188
Kojto 122:f9eeca106725 189 /**
Kojto 122:f9eeca106725 190 * @}
Kojto 122:f9eeca106725 191 */
Kojto 122:f9eeca106725 192
Kojto 122:f9eeca106725 193 /**
Kojto 122:f9eeca106725 194 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
Kojto 122:f9eeca106725 195 */
Kojto 122:f9eeca106725 196 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
Kojto 122:f9eeca106725 197 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
Kojto 122:f9eeca106725 198 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
Kojto 122:f9eeca106725 199 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 122:f9eeca106725 200 #define __FPU_PRESENT 1 /*!< FPU present */
Kojto 122:f9eeca106725 201 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
Kojto 122:f9eeca106725 202 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
Kojto 122:f9eeca106725 203 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
Kojto 122:f9eeca106725 204
Kojto 122:f9eeca106725 205
Kojto 122:f9eeca106725 206 #include "system_stm32f7xx.h"
Kojto 122:f9eeca106725 207 #include <stdint.h>
Kojto 122:f9eeca106725 208
Kojto 122:f9eeca106725 209 /** @addtogroup Peripheral_registers_structures
Kojto 122:f9eeca106725 210 * @{
Kojto 122:f9eeca106725 211 */
Kojto 122:f9eeca106725 212
Kojto 122:f9eeca106725 213 /**
Kojto 122:f9eeca106725 214 * @brief Analog to Digital Converter
Kojto 122:f9eeca106725 215 */
Kojto 122:f9eeca106725 216
Kojto 122:f9eeca106725 217 typedef struct
Kojto 122:f9eeca106725 218 {
Kojto 122:f9eeca106725 219 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 220 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 122:f9eeca106725 221 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 122:f9eeca106725 222 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 122:f9eeca106725 223 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 122:f9eeca106725 224 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
Kojto 122:f9eeca106725 225 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
Kojto 122:f9eeca106725 226 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
Kojto 122:f9eeca106725 227 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
Kojto 122:f9eeca106725 228 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
Kojto 122:f9eeca106725 229 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
Kojto 122:f9eeca106725 230 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
Kojto 122:f9eeca106725 231 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
Kojto 122:f9eeca106725 232 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
Kojto 122:f9eeca106725 233 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
Kojto 122:f9eeca106725 234 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
Kojto 122:f9eeca106725 235 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
Kojto 122:f9eeca106725 236 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
Kojto 122:f9eeca106725 237 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
Kojto 122:f9eeca106725 238 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
Kojto 122:f9eeca106725 239 } ADC_TypeDef;
Kojto 122:f9eeca106725 240
Kojto 122:f9eeca106725 241 typedef struct
Kojto 122:f9eeca106725 242 {
Kojto 122:f9eeca106725 243 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
Kojto 122:f9eeca106725 244 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 122:f9eeca106725 245 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 122:f9eeca106725 246 AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto 122:f9eeca106725 247 } ADC_Common_TypeDef;
Kojto 122:f9eeca106725 248
Kojto 122:f9eeca106725 249
Kojto 122:f9eeca106725 250 /**
Kojto 122:f9eeca106725 251 * @brief Controller Area Network TxMailBox
Kojto 122:f9eeca106725 252 */
Kojto 122:f9eeca106725 253
Kojto 122:f9eeca106725 254 typedef struct
Kojto 122:f9eeca106725 255 {
Kojto 122:f9eeca106725 256 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 122:f9eeca106725 257 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 122:f9eeca106725 258 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 122:f9eeca106725 259 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 122:f9eeca106725 260 } CAN_TxMailBox_TypeDef;
Kojto 122:f9eeca106725 261
Kojto 122:f9eeca106725 262 /**
Kojto 122:f9eeca106725 263 * @brief Controller Area Network FIFOMailBox
Kojto 122:f9eeca106725 264 */
Kojto 122:f9eeca106725 265
Kojto 122:f9eeca106725 266 typedef struct
Kojto 122:f9eeca106725 267 {
Kojto 122:f9eeca106725 268 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 122:f9eeca106725 269 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 122:f9eeca106725 270 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 122:f9eeca106725 271 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 122:f9eeca106725 272 } CAN_FIFOMailBox_TypeDef;
Kojto 122:f9eeca106725 273
Kojto 122:f9eeca106725 274 /**
Kojto 122:f9eeca106725 275 * @brief Controller Area Network FilterRegister
Kojto 122:f9eeca106725 276 */
Kojto 122:f9eeca106725 277
Kojto 122:f9eeca106725 278 typedef struct
Kojto 122:f9eeca106725 279 {
Kojto 122:f9eeca106725 280 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 122:f9eeca106725 281 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 122:f9eeca106725 282 } CAN_FilterRegister_TypeDef;
Kojto 122:f9eeca106725 283
Kojto 122:f9eeca106725 284 /**
Kojto 122:f9eeca106725 285 * @brief Controller Area Network
Kojto 122:f9eeca106725 286 */
Kojto 122:f9eeca106725 287
Kojto 122:f9eeca106725 288 typedef struct
Kojto 122:f9eeca106725 289 {
Kojto 122:f9eeca106725 290 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 291 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 122:f9eeca106725 292 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 293 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 122:f9eeca106725 294 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 122:f9eeca106725 295 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 122:f9eeca106725 296 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 122:f9eeca106725 297 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 122:f9eeca106725 298 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 122:f9eeca106725 299 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 122:f9eeca106725 300 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 122:f9eeca106725 301 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 122:f9eeca106725 302 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 122:f9eeca106725 303 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 122:f9eeca106725 304 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 122:f9eeca106725 305 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 122:f9eeca106725 306 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 122:f9eeca106725 307 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 122:f9eeca106725 308 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 122:f9eeca106725 309 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 122:f9eeca106725 310 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 122:f9eeca106725 311 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 122:f9eeca106725 312 } CAN_TypeDef;
Kojto 122:f9eeca106725 313
Kojto 122:f9eeca106725 314 /**
Kojto 122:f9eeca106725 315 * @brief HDMI-CEC
Kojto 122:f9eeca106725 316 */
Kojto 122:f9eeca106725 317
Kojto 122:f9eeca106725 318 typedef struct
Kojto 122:f9eeca106725 319 {
Kojto 122:f9eeca106725 320 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
Kojto 122:f9eeca106725 321 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
Kojto 122:f9eeca106725 322 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
Kojto 122:f9eeca106725 323 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
Kojto 122:f9eeca106725 324 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
Kojto 122:f9eeca106725 325 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
Kojto 122:f9eeca106725 326 }CEC_TypeDef;
Kojto 122:f9eeca106725 327
Kojto 122:f9eeca106725 328
Kojto 122:f9eeca106725 329 /**
Kojto 122:f9eeca106725 330 * @brief CRC calculation unit
Kojto 122:f9eeca106725 331 */
Kojto 122:f9eeca106725 332
Kojto 122:f9eeca106725 333 typedef struct
Kojto 122:f9eeca106725 334 {
Kojto 122:f9eeca106725 335 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 122:f9eeca106725 336 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 122:f9eeca106725 337 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 122:f9eeca106725 338 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 122:f9eeca106725 339 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 340 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 122:f9eeca106725 341 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 122:f9eeca106725 342 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 122:f9eeca106725 343 } CRC_TypeDef;
Kojto 122:f9eeca106725 344
Kojto 122:f9eeca106725 345 /**
Kojto 122:f9eeca106725 346 * @brief Digital to Analog Converter
Kojto 122:f9eeca106725 347 */
Kojto 122:f9eeca106725 348
Kojto 122:f9eeca106725 349 typedef struct
Kojto 122:f9eeca106725 350 {
Kojto 122:f9eeca106725 351 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 352 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 122:f9eeca106725 353 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 122:f9eeca106725 354 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 122:f9eeca106725 355 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 122:f9eeca106725 356 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 122:f9eeca106725 357 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 122:f9eeca106725 358 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 122:f9eeca106725 359 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 122:f9eeca106725 360 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 122:f9eeca106725 361 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 122:f9eeca106725 362 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 122:f9eeca106725 363 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 122:f9eeca106725 364 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 122:f9eeca106725 365 } DAC_TypeDef;
Kojto 122:f9eeca106725 366
Kojto 122:f9eeca106725 367 /**
Kojto 122:f9eeca106725 368 * @brief DFSDM module registers
Kojto 122:f9eeca106725 369 */
Kojto 122:f9eeca106725 370 typedef struct
Kojto 122:f9eeca106725 371 {
Kojto 122:f9eeca106725 372 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
Kojto 122:f9eeca106725 373 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
Kojto 122:f9eeca106725 374 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
Kojto 122:f9eeca106725 375 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
Kojto 122:f9eeca106725 376 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
Kojto 122:f9eeca106725 377 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
Kojto 122:f9eeca106725 378 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
Kojto 122:f9eeca106725 379 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
Kojto 122:f9eeca106725 380 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
Kojto 122:f9eeca106725 381 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
Kojto 122:f9eeca106725 382 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
Kojto 122:f9eeca106725 383 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
Kojto 122:f9eeca106725 384 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
Kojto 122:f9eeca106725 385 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
Kojto 122:f9eeca106725 386 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
Kojto 122:f9eeca106725 387 } DFSDM_Filter_TypeDef;
Kojto 122:f9eeca106725 388
Kojto 122:f9eeca106725 389 /**
Kojto 122:f9eeca106725 390 * @brief DFSDM channel configuration registers
Kojto 122:f9eeca106725 391 */
Kojto 122:f9eeca106725 392 typedef struct
Kojto 122:f9eeca106725 393 {
Kojto 122:f9eeca106725 394 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
Kojto 122:f9eeca106725 395 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
Kojto 122:f9eeca106725 396 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
Kojto 122:f9eeca106725 397 short circuit detector register, Address offset: 0x08 */
Kojto 122:f9eeca106725 398 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
Kojto 122:f9eeca106725 399 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
Kojto 122:f9eeca106725 400 } DFSDM_Channel_TypeDef;
Kojto 122:f9eeca106725 401
Kojto 122:f9eeca106725 402 /**
Kojto 122:f9eeca106725 403 * @brief Debug MCU
Kojto 122:f9eeca106725 404 */
Kojto 122:f9eeca106725 405
Kojto 122:f9eeca106725 406 typedef struct
Kojto 122:f9eeca106725 407 {
Kojto 122:f9eeca106725 408 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 122:f9eeca106725 409 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 410 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 122:f9eeca106725 411 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 122:f9eeca106725 412 }DBGMCU_TypeDef;
Kojto 122:f9eeca106725 413
Kojto 122:f9eeca106725 414 /**
Kojto 122:f9eeca106725 415 * @brief DCMI
Kojto 122:f9eeca106725 416 */
Kojto 122:f9eeca106725 417
Kojto 122:f9eeca106725 418 typedef struct
Kojto 122:f9eeca106725 419 {
Kojto 122:f9eeca106725 420 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 421 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
Kojto 122:f9eeca106725 422 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 423 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
Kojto 122:f9eeca106725 424 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
Kojto 122:f9eeca106725 425 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
Kojto 122:f9eeca106725 426 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
Kojto 122:f9eeca106725 427 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
Kojto 122:f9eeca106725 428 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
Kojto 122:f9eeca106725 429 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
Kojto 122:f9eeca106725 430 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
Kojto 122:f9eeca106725 431 } DCMI_TypeDef;
Kojto 122:f9eeca106725 432
Kojto 122:f9eeca106725 433 /**
Kojto 122:f9eeca106725 434 * @brief DMA Controller
Kojto 122:f9eeca106725 435 */
Kojto 122:f9eeca106725 436
Kojto 122:f9eeca106725 437 typedef struct
Kojto 122:f9eeca106725 438 {
Kojto 122:f9eeca106725 439 __IO uint32_t CR; /*!< DMA stream x configuration register */
Kojto 122:f9eeca106725 440 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
Kojto 122:f9eeca106725 441 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
Kojto 122:f9eeca106725 442 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
Kojto 122:f9eeca106725 443 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
Kojto 122:f9eeca106725 444 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
Kojto 122:f9eeca106725 445 } DMA_Stream_TypeDef;
Kojto 122:f9eeca106725 446
Kojto 122:f9eeca106725 447 typedef struct
Kojto 122:f9eeca106725 448 {
Kojto 122:f9eeca106725 449 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 450 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
Kojto 122:f9eeca106725 451 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
Kojto 122:f9eeca106725 452 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
Kojto 122:f9eeca106725 453 } DMA_TypeDef;
Kojto 122:f9eeca106725 454
Kojto 122:f9eeca106725 455
Kojto 122:f9eeca106725 456 /**
Kojto 122:f9eeca106725 457 * @brief DMA2D Controller
Kojto 122:f9eeca106725 458 */
Kojto 122:f9eeca106725 459
Kojto 122:f9eeca106725 460 typedef struct
Kojto 122:f9eeca106725 461 {
Kojto 122:f9eeca106725 462 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
Kojto 122:f9eeca106725 463 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
Kojto 122:f9eeca106725 464 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
Kojto 122:f9eeca106725 465 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
Kojto 122:f9eeca106725 466 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
Kojto 122:f9eeca106725 467 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
Kojto 122:f9eeca106725 468 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
Kojto 122:f9eeca106725 469 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
Kojto 122:f9eeca106725 470 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
Kojto 122:f9eeca106725 471 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
Kojto 122:f9eeca106725 472 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
Kojto 122:f9eeca106725 473 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
Kojto 122:f9eeca106725 474 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
Kojto 122:f9eeca106725 475 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
Kojto 122:f9eeca106725 476 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
Kojto 122:f9eeca106725 477 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
Kojto 122:f9eeca106725 478 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
Kojto 122:f9eeca106725 479 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
Kojto 122:f9eeca106725 480 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
Kojto 122:f9eeca106725 481 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
Kojto 122:f9eeca106725 482 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
Kojto 122:f9eeca106725 483 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
Kojto 122:f9eeca106725 484 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
Kojto 122:f9eeca106725 485 } DMA2D_TypeDef;
Kojto 122:f9eeca106725 486
Kojto 122:f9eeca106725 487
Kojto 122:f9eeca106725 488 /**
Kojto 122:f9eeca106725 489 * @brief Ethernet MAC
Kojto 122:f9eeca106725 490 */
Kojto 122:f9eeca106725 491
Kojto 122:f9eeca106725 492 typedef struct
Kojto 122:f9eeca106725 493 {
Kojto 122:f9eeca106725 494 __IO uint32_t MACCR;
Kojto 122:f9eeca106725 495 __IO uint32_t MACFFR;
Kojto 122:f9eeca106725 496 __IO uint32_t MACHTHR;
Kojto 122:f9eeca106725 497 __IO uint32_t MACHTLR;
Kojto 122:f9eeca106725 498 __IO uint32_t MACMIIAR;
Kojto 122:f9eeca106725 499 __IO uint32_t MACMIIDR;
Kojto 122:f9eeca106725 500 __IO uint32_t MACFCR;
Kojto 122:f9eeca106725 501 __IO uint32_t MACVLANTR; /* 8 */
Kojto 122:f9eeca106725 502 uint32_t RESERVED0[2];
Kojto 122:f9eeca106725 503 __IO uint32_t MACRWUFFR; /* 11 */
Kojto 122:f9eeca106725 504 __IO uint32_t MACPMTCSR;
Kojto 122:f9eeca106725 505 uint32_t RESERVED1[2];
Kojto 122:f9eeca106725 506 __IO uint32_t MACSR; /* 15 */
Kojto 122:f9eeca106725 507 __IO uint32_t MACIMR;
Kojto 122:f9eeca106725 508 __IO uint32_t MACA0HR;
Kojto 122:f9eeca106725 509 __IO uint32_t MACA0LR;
Kojto 122:f9eeca106725 510 __IO uint32_t MACA1HR;
Kojto 122:f9eeca106725 511 __IO uint32_t MACA1LR;
Kojto 122:f9eeca106725 512 __IO uint32_t MACA2HR;
Kojto 122:f9eeca106725 513 __IO uint32_t MACA2LR;
Kojto 122:f9eeca106725 514 __IO uint32_t MACA3HR;
Kojto 122:f9eeca106725 515 __IO uint32_t MACA3LR; /* 24 */
Kojto 122:f9eeca106725 516 uint32_t RESERVED2[40];
Kojto 122:f9eeca106725 517 __IO uint32_t MMCCR; /* 65 */
Kojto 122:f9eeca106725 518 __IO uint32_t MMCRIR;
Kojto 122:f9eeca106725 519 __IO uint32_t MMCTIR;
Kojto 122:f9eeca106725 520 __IO uint32_t MMCRIMR;
Kojto 122:f9eeca106725 521 __IO uint32_t MMCTIMR; /* 69 */
Kojto 122:f9eeca106725 522 uint32_t RESERVED3[14];
Kojto 122:f9eeca106725 523 __IO uint32_t MMCTGFSCCR; /* 84 */
Kojto 122:f9eeca106725 524 __IO uint32_t MMCTGFMSCCR;
Kojto 122:f9eeca106725 525 uint32_t RESERVED4[5];
Kojto 122:f9eeca106725 526 __IO uint32_t MMCTGFCR;
Kojto 122:f9eeca106725 527 uint32_t RESERVED5[10];
Kojto 122:f9eeca106725 528 __IO uint32_t MMCRFCECR;
Kojto 122:f9eeca106725 529 __IO uint32_t MMCRFAECR;
Kojto 122:f9eeca106725 530 uint32_t RESERVED6[10];
Kojto 122:f9eeca106725 531 __IO uint32_t MMCRGUFCR;
Kojto 122:f9eeca106725 532 uint32_t RESERVED7[334];
Kojto 122:f9eeca106725 533 __IO uint32_t PTPTSCR;
Kojto 122:f9eeca106725 534 __IO uint32_t PTPSSIR;
Kojto 122:f9eeca106725 535 __IO uint32_t PTPTSHR;
Kojto 122:f9eeca106725 536 __IO uint32_t PTPTSLR;
Kojto 122:f9eeca106725 537 __IO uint32_t PTPTSHUR;
Kojto 122:f9eeca106725 538 __IO uint32_t PTPTSLUR;
Kojto 122:f9eeca106725 539 __IO uint32_t PTPTSAR;
Kojto 122:f9eeca106725 540 __IO uint32_t PTPTTHR;
Kojto 122:f9eeca106725 541 __IO uint32_t PTPTTLR;
Kojto 122:f9eeca106725 542 __IO uint32_t RESERVED8;
Kojto 122:f9eeca106725 543 __IO uint32_t PTPTSSR;
Kojto 122:f9eeca106725 544 uint32_t RESERVED9[565];
Kojto 122:f9eeca106725 545 __IO uint32_t DMABMR;
Kojto 122:f9eeca106725 546 __IO uint32_t DMATPDR;
Kojto 122:f9eeca106725 547 __IO uint32_t DMARPDR;
Kojto 122:f9eeca106725 548 __IO uint32_t DMARDLAR;
Kojto 122:f9eeca106725 549 __IO uint32_t DMATDLAR;
Kojto 122:f9eeca106725 550 __IO uint32_t DMASR;
Kojto 122:f9eeca106725 551 __IO uint32_t DMAOMR;
Kojto 122:f9eeca106725 552 __IO uint32_t DMAIER;
Kojto 122:f9eeca106725 553 __IO uint32_t DMAMFBOCR;
Kojto 122:f9eeca106725 554 __IO uint32_t DMARSWTR;
Kojto 122:f9eeca106725 555 uint32_t RESERVED10[8];
Kojto 122:f9eeca106725 556 __IO uint32_t DMACHTDR;
Kojto 122:f9eeca106725 557 __IO uint32_t DMACHRDR;
Kojto 122:f9eeca106725 558 __IO uint32_t DMACHTBAR;
Kojto 122:f9eeca106725 559 __IO uint32_t DMACHRBAR;
Kojto 122:f9eeca106725 560 } ETH_TypeDef;
Kojto 122:f9eeca106725 561
Kojto 122:f9eeca106725 562 /**
Kojto 122:f9eeca106725 563 * @brief External Interrupt/Event Controller
Kojto 122:f9eeca106725 564 */
Kojto 122:f9eeca106725 565
Kojto 122:f9eeca106725 566 typedef struct
Kojto 122:f9eeca106725 567 {
Kojto 122:f9eeca106725 568 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 122:f9eeca106725 569 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 122:f9eeca106725 570 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 122:f9eeca106725 571 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 122:f9eeca106725 572 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 122:f9eeca106725 573 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 122:f9eeca106725 574 } EXTI_TypeDef;
Kojto 122:f9eeca106725 575
Kojto 122:f9eeca106725 576 /**
Kojto 122:f9eeca106725 577 * @brief FLASH Registers
Kojto 122:f9eeca106725 578 */
Kojto 122:f9eeca106725 579
Kojto 122:f9eeca106725 580 typedef struct
Kojto 122:f9eeca106725 581 {
Kojto 122:f9eeca106725 582 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 583 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 122:f9eeca106725 584 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 122:f9eeca106725 585 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 586 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 122:f9eeca106725 587 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
Kojto 122:f9eeca106725 588 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
Kojto 122:f9eeca106725 589 } FLASH_TypeDef;
Kojto 122:f9eeca106725 590
Kojto 122:f9eeca106725 591
Kojto 122:f9eeca106725 592
Kojto 122:f9eeca106725 593 /**
Kojto 122:f9eeca106725 594 * @brief Flexible Memory Controller
Kojto 122:f9eeca106725 595 */
Kojto 122:f9eeca106725 596
Kojto 122:f9eeca106725 597 typedef struct
Kojto 122:f9eeca106725 598 {
Kojto 122:f9eeca106725 599 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
Kojto 122:f9eeca106725 600 } FMC_Bank1_TypeDef;
Kojto 122:f9eeca106725 601
Kojto 122:f9eeca106725 602 /**
Kojto 122:f9eeca106725 603 * @brief Flexible Memory Controller Bank1E
Kojto 122:f9eeca106725 604 */
Kojto 122:f9eeca106725 605
Kojto 122:f9eeca106725 606 typedef struct
Kojto 122:f9eeca106725 607 {
Kojto 122:f9eeca106725 608 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
Kojto 122:f9eeca106725 609 } FMC_Bank1E_TypeDef;
Kojto 122:f9eeca106725 610
Kojto 122:f9eeca106725 611 /**
Kojto 122:f9eeca106725 612 * @brief Flexible Memory Controller Bank3
Kojto 122:f9eeca106725 613 */
Kojto 122:f9eeca106725 614
Kojto 122:f9eeca106725 615 typedef struct
Kojto 122:f9eeca106725 616 {
Kojto 122:f9eeca106725 617 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
Kojto 122:f9eeca106725 618 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
Kojto 122:f9eeca106725 619 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
Kojto 122:f9eeca106725 620 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
Kojto 122:f9eeca106725 621 uint32_t RESERVED0; /*!< Reserved, 0x90 */
Kojto 122:f9eeca106725 622 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
Kojto 122:f9eeca106725 623 } FMC_Bank3_TypeDef;
Kojto 122:f9eeca106725 624
Kojto 122:f9eeca106725 625 /**
Kojto 122:f9eeca106725 626 * @brief Flexible Memory Controller Bank5_6
Kojto 122:f9eeca106725 627 */
Kojto 122:f9eeca106725 628
Kojto 122:f9eeca106725 629 typedef struct
Kojto 122:f9eeca106725 630 {
Kojto 122:f9eeca106725 631 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
Kojto 122:f9eeca106725 632 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
Kojto 122:f9eeca106725 633 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
Kojto 122:f9eeca106725 634 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
Kojto 122:f9eeca106725 635 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
Kojto 122:f9eeca106725 636 } FMC_Bank5_6_TypeDef;
Kojto 122:f9eeca106725 637
Kojto 122:f9eeca106725 638
Kojto 122:f9eeca106725 639 /**
Kojto 122:f9eeca106725 640 * @brief General Purpose I/O
Kojto 122:f9eeca106725 641 */
Kojto 122:f9eeca106725 642
Kojto 122:f9eeca106725 643 typedef struct
Kojto 122:f9eeca106725 644 {
Kojto 122:f9eeca106725 645 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 122:f9eeca106725 646 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 122:f9eeca106725 647 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 122:f9eeca106725 648 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 122:f9eeca106725 649 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 122:f9eeca106725 650 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 122:f9eeca106725 651 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 122:f9eeca106725 652 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 122:f9eeca106725 653 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 122:f9eeca106725 654 } GPIO_TypeDef;
Kojto 122:f9eeca106725 655
Kojto 122:f9eeca106725 656 /**
Kojto 122:f9eeca106725 657 * @brief System configuration controller
Kojto 122:f9eeca106725 658 */
Kojto 122:f9eeca106725 659
Kojto 122:f9eeca106725 660 typedef struct
Kojto 122:f9eeca106725 661 {
Kojto 122:f9eeca106725 662 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 122:f9eeca106725 663 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 664 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 122:f9eeca106725 665 uint32_t RESERVED; /*!< Reserved, 0x18 */
Kojto 122:f9eeca106725 666 __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
Kojto 122:f9eeca106725 667 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
Kojto 122:f9eeca106725 668 } SYSCFG_TypeDef;
Kojto 122:f9eeca106725 669
Kojto 122:f9eeca106725 670 /**
Kojto 122:f9eeca106725 671 * @brief Inter-integrated Circuit Interface
Kojto 122:f9eeca106725 672 */
Kojto 122:f9eeca106725 673
Kojto 122:f9eeca106725 674 typedef struct
Kojto 122:f9eeca106725 675 {
Kojto 122:f9eeca106725 676 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 677 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 678 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 122:f9eeca106725 679 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 122:f9eeca106725 680 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 122:f9eeca106725 681 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 122:f9eeca106725 682 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 122:f9eeca106725 683 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 122:f9eeca106725 684 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 122:f9eeca106725 685 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 122:f9eeca106725 686 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 122:f9eeca106725 687 } I2C_TypeDef;
Kojto 122:f9eeca106725 688
Kojto 122:f9eeca106725 689 /**
Kojto 122:f9eeca106725 690 * @brief Independent WATCHDOG
Kojto 122:f9eeca106725 691 */
Kojto 122:f9eeca106725 692
Kojto 122:f9eeca106725 693 typedef struct
Kojto 122:f9eeca106725 694 {
Kojto 122:f9eeca106725 695 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 122:f9eeca106725 696 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 122:f9eeca106725 697 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 122:f9eeca106725 698 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 699 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 122:f9eeca106725 700 } IWDG_TypeDef;
Kojto 122:f9eeca106725 701
Kojto 122:f9eeca106725 702
Kojto 122:f9eeca106725 703 /**
Kojto 122:f9eeca106725 704 * @brief LCD-TFT Display Controller
Kojto 122:f9eeca106725 705 */
Kojto 122:f9eeca106725 706
Kojto 122:f9eeca106725 707 typedef struct
Kojto 122:f9eeca106725 708 {
Kojto 122:f9eeca106725 709 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
Kojto 122:f9eeca106725 710 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
Kojto 122:f9eeca106725 711 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
Kojto 122:f9eeca106725 712 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
Kojto 122:f9eeca106725 713 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
Kojto 122:f9eeca106725 714 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
Kojto 122:f9eeca106725 715 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
Kojto 122:f9eeca106725 716 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
Kojto 122:f9eeca106725 717 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
Kojto 122:f9eeca106725 718 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
Kojto 122:f9eeca106725 719 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
Kojto 122:f9eeca106725 720 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
Kojto 122:f9eeca106725 721 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
Kojto 122:f9eeca106725 722 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
Kojto 122:f9eeca106725 723 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
Kojto 122:f9eeca106725 724 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
Kojto 122:f9eeca106725 725 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
Kojto 122:f9eeca106725 726 } LTDC_TypeDef;
Kojto 122:f9eeca106725 727
Kojto 122:f9eeca106725 728 /**
Kojto 122:f9eeca106725 729 * @brief LCD-TFT Display layer x Controller
Kojto 122:f9eeca106725 730 */
Kojto 122:f9eeca106725 731
Kojto 122:f9eeca106725 732 typedef struct
Kojto 122:f9eeca106725 733 {
Kojto 122:f9eeca106725 734 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
Kojto 122:f9eeca106725 735 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
Kojto 122:f9eeca106725 736 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
Kojto 122:f9eeca106725 737 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
Kojto 122:f9eeca106725 738 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
Kojto 122:f9eeca106725 739 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
Kojto 122:f9eeca106725 740 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
Kojto 122:f9eeca106725 741 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
Kojto 122:f9eeca106725 742 uint32_t RESERVED0[2]; /*!< Reserved */
Kojto 122:f9eeca106725 743 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
Kojto 122:f9eeca106725 744 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
Kojto 122:f9eeca106725 745 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
Kojto 122:f9eeca106725 746 uint32_t RESERVED1[3]; /*!< Reserved */
Kojto 122:f9eeca106725 747 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
Kojto 122:f9eeca106725 748
Kojto 122:f9eeca106725 749 } LTDC_Layer_TypeDef;
Kojto 122:f9eeca106725 750
Kojto 122:f9eeca106725 751 /**
Kojto 122:f9eeca106725 752 * @brief Power Control
Kojto 122:f9eeca106725 753 */
Kojto 122:f9eeca106725 754
Kojto 122:f9eeca106725 755 typedef struct
Kojto 122:f9eeca106725 756 {
Kojto 122:f9eeca106725 757 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 758 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 759 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
Kojto 122:f9eeca106725 760 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
Kojto 122:f9eeca106725 761 } PWR_TypeDef;
Kojto 122:f9eeca106725 762
Kojto 122:f9eeca106725 763
Kojto 122:f9eeca106725 764 /**
Kojto 122:f9eeca106725 765 * @brief Reset and Clock Control
Kojto 122:f9eeca106725 766 */
Kojto 122:f9eeca106725 767
Kojto 122:f9eeca106725 768 typedef struct
Kojto 122:f9eeca106725 769 {
Kojto 122:f9eeca106725 770 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 771 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 772 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 122:f9eeca106725 773 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
Kojto 122:f9eeca106725 774 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
Kojto 122:f9eeca106725 775 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
Kojto 122:f9eeca106725 776 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
Kojto 122:f9eeca106725 777 uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 122:f9eeca106725 778 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
Kojto 122:f9eeca106725 779 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 122:f9eeca106725 780 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
Kojto 122:f9eeca106725 781 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
Kojto 122:f9eeca106725 782 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
Kojto 122:f9eeca106725 783 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
Kojto 122:f9eeca106725 784 uint32_t RESERVED2; /*!< Reserved, 0x3C */
Kojto 122:f9eeca106725 785 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
Kojto 122:f9eeca106725 786 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
Kojto 122:f9eeca106725 787 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
Kojto 122:f9eeca106725 788 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
Kojto 122:f9eeca106725 789 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
Kojto 122:f9eeca106725 790 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
Kojto 122:f9eeca106725 791 uint32_t RESERVED4; /*!< Reserved, 0x5C */
Kojto 122:f9eeca106725 792 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
Kojto 122:f9eeca106725 793 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
Kojto 122:f9eeca106725 794 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
Kojto 122:f9eeca106725 795 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
Kojto 122:f9eeca106725 796 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
Kojto 122:f9eeca106725 797 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
Kojto 122:f9eeca106725 798 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
Kojto 122:f9eeca106725 799 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
Kojto 122:f9eeca106725 800 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
Kojto 122:f9eeca106725 801 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
Kojto 122:f9eeca106725 802 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
Kojto 122:f9eeca106725 803
Kojto 122:f9eeca106725 804 } RCC_TypeDef;
Kojto 122:f9eeca106725 805
Kojto 122:f9eeca106725 806 /**
Kojto 122:f9eeca106725 807 * @brief Real-Time Clock
Kojto 122:f9eeca106725 808 */
Kojto 122:f9eeca106725 809
Kojto 122:f9eeca106725 810 typedef struct
Kojto 122:f9eeca106725 811 {
Kojto 122:f9eeca106725 812 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 122:f9eeca106725 813 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 122:f9eeca106725 814 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 815 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 816 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 122:f9eeca106725 817 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 122:f9eeca106725 818 uint32_t reserved; /*!< Reserved */
Kojto 122:f9eeca106725 819 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 122:f9eeca106725 820 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 122:f9eeca106725 821 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 122:f9eeca106725 822 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 122:f9eeca106725 823 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 122:f9eeca106725 824 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 122:f9eeca106725 825 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 122:f9eeca106725 826 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 122:f9eeca106725 827 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 122:f9eeca106725 828 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
Kojto 122:f9eeca106725 829 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 122:f9eeca106725 830 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 122:f9eeca106725 831 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
Kojto 122:f9eeca106725 832 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 122:f9eeca106725 833 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 122:f9eeca106725 834 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 122:f9eeca106725 835 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 122:f9eeca106725 836 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 122:f9eeca106725 837 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 122:f9eeca106725 838 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 122:f9eeca106725 839 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 122:f9eeca106725 840 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 122:f9eeca106725 841 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 122:f9eeca106725 842 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 122:f9eeca106725 843 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 122:f9eeca106725 844 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 122:f9eeca106725 845 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 122:f9eeca106725 846 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 122:f9eeca106725 847 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 122:f9eeca106725 848 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 122:f9eeca106725 849 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 122:f9eeca106725 850 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 122:f9eeca106725 851 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 122:f9eeca106725 852 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
Kojto 122:f9eeca106725 853 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
Kojto 122:f9eeca106725 854 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
Kojto 122:f9eeca106725 855 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
Kojto 122:f9eeca106725 856 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
Kojto 122:f9eeca106725 857 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
Kojto 122:f9eeca106725 858 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
Kojto 122:f9eeca106725 859 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
Kojto 122:f9eeca106725 860 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
Kojto 122:f9eeca106725 861 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
Kojto 122:f9eeca106725 862 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
Kojto 122:f9eeca106725 863 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
Kojto 122:f9eeca106725 864 } RTC_TypeDef;
Kojto 122:f9eeca106725 865
Kojto 122:f9eeca106725 866
Kojto 122:f9eeca106725 867 /**
Kojto 122:f9eeca106725 868 * @brief Serial Audio Interface
Kojto 122:f9eeca106725 869 */
Kojto 122:f9eeca106725 870
Kojto 122:f9eeca106725 871 typedef struct
Kojto 122:f9eeca106725 872 {
Kojto 122:f9eeca106725 873 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
Kojto 122:f9eeca106725 874 } SAI_TypeDef;
Kojto 122:f9eeca106725 875
Kojto 122:f9eeca106725 876 typedef struct
Kojto 122:f9eeca106725 877 {
Kojto 122:f9eeca106725 878 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
Kojto 122:f9eeca106725 879 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
Kojto 122:f9eeca106725 880 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
Kojto 122:f9eeca106725 881 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
Kojto 122:f9eeca106725 882 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
Kojto 122:f9eeca106725 883 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
Kojto 122:f9eeca106725 884 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
Kojto 122:f9eeca106725 885 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
Kojto 122:f9eeca106725 886 } SAI_Block_TypeDef;
Kojto 122:f9eeca106725 887
Kojto 122:f9eeca106725 888 /**
Kojto 122:f9eeca106725 889 * @brief SPDIF-RX Interface
Kojto 122:f9eeca106725 890 */
Kojto 122:f9eeca106725 891
Kojto 122:f9eeca106725 892 typedef struct
Kojto 122:f9eeca106725 893 {
Kojto 122:f9eeca106725 894 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 895 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
Kojto 122:f9eeca106725 896 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 897 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
Kojto 122:f9eeca106725 898 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
Kojto 122:f9eeca106725 899 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
Kojto 122:f9eeca106725 900 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
Kojto 122:f9eeca106725 901 } SPDIFRX_TypeDef;
Kojto 122:f9eeca106725 902
Kojto 122:f9eeca106725 903
Kojto 122:f9eeca106725 904 /**
Kojto 122:f9eeca106725 905 * @brief SD host Interface
Kojto 122:f9eeca106725 906 */
Kojto 122:f9eeca106725 907
Kojto 122:f9eeca106725 908 typedef struct
Kojto 122:f9eeca106725 909 {
Kojto 122:f9eeca106725 910 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 911 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
Kojto 122:f9eeca106725 912 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
Kojto 122:f9eeca106725 913 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
Kojto 122:f9eeca106725 914 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
Kojto 122:f9eeca106725 915 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
Kojto 122:f9eeca106725 916 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
Kojto 122:f9eeca106725 917 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
Kojto 122:f9eeca106725 918 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
Kojto 122:f9eeca106725 919 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
Kojto 122:f9eeca106725 920 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
Kojto 122:f9eeca106725 921 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
Kojto 122:f9eeca106725 922 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
Kojto 122:f9eeca106725 923 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
Kojto 122:f9eeca106725 924 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
Kojto 122:f9eeca106725 925 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
Kojto 122:f9eeca106725 926 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
Kojto 122:f9eeca106725 927 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
Kojto 122:f9eeca106725 928 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
Kojto 122:f9eeca106725 929 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
Kojto 122:f9eeca106725 930 } SDMMC_TypeDef;
Kojto 122:f9eeca106725 931
Kojto 122:f9eeca106725 932 /**
Kojto 122:f9eeca106725 933 * @brief Serial Peripheral Interface
Kojto 122:f9eeca106725 934 */
Kojto 122:f9eeca106725 935
Kojto 122:f9eeca106725 936 typedef struct
Kojto 122:f9eeca106725 937 {
Kojto 122:f9eeca106725 938 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 122:f9eeca106725 939 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 940 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 941 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 122:f9eeca106725 942 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 122:f9eeca106725 943 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 122:f9eeca106725 944 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 122:f9eeca106725 945 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 122:f9eeca106725 946 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 122:f9eeca106725 947 } SPI_TypeDef;
Kojto 122:f9eeca106725 948
Kojto 122:f9eeca106725 949 /**
Kojto 122:f9eeca106725 950 * @brief QUAD Serial Peripheral Interface
Kojto 122:f9eeca106725 951 */
Kojto 122:f9eeca106725 952
Kojto 122:f9eeca106725 953 typedef struct
Kojto 122:f9eeca106725 954 {
Kojto 122:f9eeca106725 955 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 956 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 957 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 958 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
Kojto 122:f9eeca106725 959 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
Kojto 122:f9eeca106725 960 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
Kojto 122:f9eeca106725 961 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
Kojto 122:f9eeca106725 962 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
Kojto 122:f9eeca106725 963 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
Kojto 122:f9eeca106725 964 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
Kojto 122:f9eeca106725 965 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
Kojto 122:f9eeca106725 966 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
Kojto 122:f9eeca106725 967 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
Kojto 122:f9eeca106725 968 } QUADSPI_TypeDef;
Kojto 122:f9eeca106725 969
Kojto 122:f9eeca106725 970 /**
Kojto 122:f9eeca106725 971 * @brief TIM
Kojto 122:f9eeca106725 972 */
Kojto 122:f9eeca106725 973
Kojto 122:f9eeca106725 974 typedef struct
Kojto 122:f9eeca106725 975 {
Kojto 122:f9eeca106725 976 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 977 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 978 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 979 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 122:f9eeca106725 980 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 122:f9eeca106725 981 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 122:f9eeca106725 982 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 122:f9eeca106725 983 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 122:f9eeca106725 984 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 122:f9eeca106725 985 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 122:f9eeca106725 986 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 122:f9eeca106725 987 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 122:f9eeca106725 988 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 122:f9eeca106725 989 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 122:f9eeca106725 990 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 122:f9eeca106725 991 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 122:f9eeca106725 992 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 122:f9eeca106725 993 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 122:f9eeca106725 994 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 122:f9eeca106725 995 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 122:f9eeca106725 996 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 122:f9eeca106725 997 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
Kojto 122:f9eeca106725 998 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
Kojto 122:f9eeca106725 999 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
Kojto 122:f9eeca106725 1000 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
Kojto 122:f9eeca106725 1001 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
Kojto 122:f9eeca106725 1002
Kojto 122:f9eeca106725 1003 } TIM_TypeDef;
Kojto 122:f9eeca106725 1004
Kojto 122:f9eeca106725 1005 /**
Kojto 122:f9eeca106725 1006 * @brief LPTIMIMER
Kojto 122:f9eeca106725 1007 */
Kojto 122:f9eeca106725 1008 typedef struct
Kojto 122:f9eeca106725 1009 {
Kojto 122:f9eeca106725 1010 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 1011 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
Kojto 122:f9eeca106725 1012 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
Kojto 122:f9eeca106725 1013 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
Kojto 122:f9eeca106725 1014 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
Kojto 122:f9eeca106725 1015 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
Kojto 122:f9eeca106725 1016 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
Kojto 122:f9eeca106725 1017 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
Kojto 122:f9eeca106725 1018 } LPTIM_TypeDef;
Kojto 122:f9eeca106725 1019
Kojto 122:f9eeca106725 1020
Kojto 122:f9eeca106725 1021 /**
Kojto 122:f9eeca106725 1022 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 122:f9eeca106725 1023 */
Kojto 122:f9eeca106725 1024
Kojto 122:f9eeca106725 1025 typedef struct
Kojto 122:f9eeca106725 1026 {
Kojto 122:f9eeca106725 1027 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 1028 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 1029 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 122:f9eeca106725 1030 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 122:f9eeca106725 1031 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 122:f9eeca106725 1032 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 122:f9eeca106725 1033 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 122:f9eeca106725 1034 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 122:f9eeca106725 1035 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 122:f9eeca106725 1036 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 122:f9eeca106725 1037 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 122:f9eeca106725 1038 } USART_TypeDef;
Kojto 122:f9eeca106725 1039
Kojto 122:f9eeca106725 1040
Kojto 122:f9eeca106725 1041 /**
Kojto 122:f9eeca106725 1042 * @brief Window WATCHDOG
Kojto 122:f9eeca106725 1043 */
Kojto 122:f9eeca106725 1044
Kojto 122:f9eeca106725 1045 typedef struct
Kojto 122:f9eeca106725 1046 {
Kojto 122:f9eeca106725 1047 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 1048 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 122:f9eeca106725 1049 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 1050 } WWDG_TypeDef;
Kojto 122:f9eeca106725 1051
Kojto 122:f9eeca106725 1052
Kojto 122:f9eeca106725 1053 /**
Kojto 122:f9eeca106725 1054 * @brief RNG
Kojto 122:f9eeca106725 1055 */
Kojto 122:f9eeca106725 1056
Kojto 122:f9eeca106725 1057 typedef struct
Kojto 122:f9eeca106725 1058 {
Kojto 122:f9eeca106725 1059 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 1060 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
Kojto 122:f9eeca106725 1061 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
Kojto 122:f9eeca106725 1062 } RNG_TypeDef;
Kojto 122:f9eeca106725 1063
Kojto 122:f9eeca106725 1064 /**
Kojto 122:f9eeca106725 1065 * @}
Kojto 122:f9eeca106725 1066 */
Kojto 122:f9eeca106725 1067
Kojto 122:f9eeca106725 1068 /**
Kojto 122:f9eeca106725 1069 * @brief USB_OTG_Core_Registers
Kojto 122:f9eeca106725 1070 */
Kojto 122:f9eeca106725 1071 typedef struct
Kojto 122:f9eeca106725 1072 {
Kojto 122:f9eeca106725 1073 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
Kojto 122:f9eeca106725 1074 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
Kojto 122:f9eeca106725 1075 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
Kojto 122:f9eeca106725 1076 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
Kojto 122:f9eeca106725 1077 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
Kojto 122:f9eeca106725 1078 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
Kojto 122:f9eeca106725 1079 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
Kojto 122:f9eeca106725 1080 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
Kojto 122:f9eeca106725 1081 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
Kojto 122:f9eeca106725 1082 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
Kojto 122:f9eeca106725 1083 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
Kojto 122:f9eeca106725 1084 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
Kojto 122:f9eeca106725 1085 uint32_t Reserved30[2]; /*!< Reserved 030h */
Kojto 122:f9eeca106725 1086 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
Kojto 122:f9eeca106725 1087 __IO uint32_t CID; /*!< User ID Register 03Ch */
Kojto 122:f9eeca106725 1088 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
Kojto 122:f9eeca106725 1089 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
Kojto 122:f9eeca106725 1090 uint32_t Reserved6; /*!< Reserved 050h */
Kojto 122:f9eeca106725 1091 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
Kojto 122:f9eeca106725 1092 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
Kojto 122:f9eeca106725 1093 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
Kojto 122:f9eeca106725 1094 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
Kojto 122:f9eeca106725 1095 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
Kojto 122:f9eeca106725 1096 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
Kojto 122:f9eeca106725 1097 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
Kojto 122:f9eeca106725 1098 } USB_OTG_GlobalTypeDef;
Kojto 122:f9eeca106725 1099
Kojto 122:f9eeca106725 1100
Kojto 122:f9eeca106725 1101 /**
Kojto 122:f9eeca106725 1102 * @brief USB_OTG_device_Registers
Kojto 122:f9eeca106725 1103 */
Kojto 122:f9eeca106725 1104 typedef struct
Kojto 122:f9eeca106725 1105 {
Kojto 122:f9eeca106725 1106 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
Kojto 122:f9eeca106725 1107 __IO uint32_t DCTL; /*!< dev Control Register 804h */
Kojto 122:f9eeca106725 1108 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
Kojto 122:f9eeca106725 1109 uint32_t Reserved0C; /*!< Reserved 80Ch */
Kojto 122:f9eeca106725 1110 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
Kojto 122:f9eeca106725 1111 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
Kojto 122:f9eeca106725 1112 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
Kojto 122:f9eeca106725 1113 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
Kojto 122:f9eeca106725 1114 uint32_t Reserved20; /*!< Reserved 820h */
Kojto 122:f9eeca106725 1115 uint32_t Reserved9; /*!< Reserved 824h */
Kojto 122:f9eeca106725 1116 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
Kojto 122:f9eeca106725 1117 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
Kojto 122:f9eeca106725 1118 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
Kojto 122:f9eeca106725 1119 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
Kojto 122:f9eeca106725 1120 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
Kojto 122:f9eeca106725 1121 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
Kojto 122:f9eeca106725 1122 uint32_t Reserved40; /*!< dedicated EP mask 840h */
Kojto 122:f9eeca106725 1123 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
Kojto 122:f9eeca106725 1124 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
Kojto 122:f9eeca106725 1125 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
Kojto 122:f9eeca106725 1126 } USB_OTG_DeviceTypeDef;
Kojto 122:f9eeca106725 1127
Kojto 122:f9eeca106725 1128
Kojto 122:f9eeca106725 1129 /**
Kojto 122:f9eeca106725 1130 * @brief USB_OTG_IN_Endpoint-Specific_Register
Kojto 122:f9eeca106725 1131 */
Kojto 122:f9eeca106725 1132 typedef struct
Kojto 122:f9eeca106725 1133 {
Kojto 122:f9eeca106725 1134 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
Kojto 122:f9eeca106725 1135 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
Kojto 122:f9eeca106725 1136 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
Kojto 122:f9eeca106725 1137 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
Kojto 122:f9eeca106725 1138 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
Kojto 122:f9eeca106725 1139 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
Kojto 122:f9eeca106725 1140 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
Kojto 122:f9eeca106725 1141 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto 122:f9eeca106725 1142 } USB_OTG_INEndpointTypeDef;
Kojto 122:f9eeca106725 1143
Kojto 122:f9eeca106725 1144
Kojto 122:f9eeca106725 1145 /**
Kojto 122:f9eeca106725 1146 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
Kojto 122:f9eeca106725 1147 */
Kojto 122:f9eeca106725 1148 typedef struct
Kojto 122:f9eeca106725 1149 {
Kojto 122:f9eeca106725 1150 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
Kojto 122:f9eeca106725 1151 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
Kojto 122:f9eeca106725 1152 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
Kojto 122:f9eeca106725 1153 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
Kojto 122:f9eeca106725 1154 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
Kojto 122:f9eeca106725 1155 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
Kojto 122:f9eeca106725 1156 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
Kojto 122:f9eeca106725 1157 } USB_OTG_OUTEndpointTypeDef;
Kojto 122:f9eeca106725 1158
Kojto 122:f9eeca106725 1159
Kojto 122:f9eeca106725 1160 /**
Kojto 122:f9eeca106725 1161 * @brief USB_OTG_Host_Mode_Register_Structures
Kojto 122:f9eeca106725 1162 */
Kojto 122:f9eeca106725 1163 typedef struct
Kojto 122:f9eeca106725 1164 {
Kojto 122:f9eeca106725 1165 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
Kojto 122:f9eeca106725 1166 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
Kojto 122:f9eeca106725 1167 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
Kojto 122:f9eeca106725 1168 uint32_t Reserved40C; /*!< Reserved 40Ch */
Kojto 122:f9eeca106725 1169 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
Kojto 122:f9eeca106725 1170 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
Kojto 122:f9eeca106725 1171 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
Kojto 122:f9eeca106725 1172 } USB_OTG_HostTypeDef;
Kojto 122:f9eeca106725 1173
Kojto 122:f9eeca106725 1174 /**
Kojto 122:f9eeca106725 1175 * @brief USB_OTG_Host_Channel_Specific_Registers
Kojto 122:f9eeca106725 1176 */
Kojto 122:f9eeca106725 1177 typedef struct
Kojto 122:f9eeca106725 1178 {
Kojto 122:f9eeca106725 1179 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
Kojto 122:f9eeca106725 1180 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
Kojto 122:f9eeca106725 1181 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
Kojto 122:f9eeca106725 1182 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
Kojto 122:f9eeca106725 1183 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
Kojto 122:f9eeca106725 1184 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
Kojto 122:f9eeca106725 1185 uint32_t Reserved[2]; /*!< Reserved */
Kojto 122:f9eeca106725 1186 } USB_OTG_HostChannelTypeDef;
Kojto 122:f9eeca106725 1187 /**
Kojto 122:f9eeca106725 1188 * @}
Kojto 122:f9eeca106725 1189 */
Kojto 122:f9eeca106725 1190
Kojto 122:f9eeca106725 1191 /**
Kojto 122:f9eeca106725 1192 * @brief JPEG Codec
Kojto 122:f9eeca106725 1193 */
Kojto 122:f9eeca106725 1194 typedef struct
Kojto 122:f9eeca106725 1195 {
Kojto 122:f9eeca106725 1196 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
Kojto 122:f9eeca106725 1197 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
Kojto 122:f9eeca106725 1198 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
Kojto 122:f9eeca106725 1199 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
Kojto 122:f9eeca106725 1200 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
Kojto 122:f9eeca106725 1201 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
Kojto 122:f9eeca106725 1202 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
Kojto 122:f9eeca106725 1203 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
Kojto 122:f9eeca106725 1204 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
Kojto 122:f9eeca106725 1205 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
Kojto 122:f9eeca106725 1206 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
Kojto 122:f9eeca106725 1207 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
Kojto 122:f9eeca106725 1208 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
Kojto 122:f9eeca106725 1209 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
Kojto 122:f9eeca106725 1210 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
Kojto 122:f9eeca106725 1211 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
Kojto 122:f9eeca106725 1212 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
Kojto 122:f9eeca106725 1213 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
Kojto 122:f9eeca106725 1214 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
Kojto 122:f9eeca106725 1215 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
Kojto 122:f9eeca106725 1216 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
Kojto 122:f9eeca106725 1217 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
Kojto 122:f9eeca106725 1218 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
Kojto 122:f9eeca106725 1219 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
Kojto 122:f9eeca106725 1220 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
Kojto 122:f9eeca106725 1221 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
Kojto 122:f9eeca106725 1222 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
Kojto 122:f9eeca106725 1223 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
Kojto 122:f9eeca106725 1224 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
Kojto 122:f9eeca106725 1225
Kojto 122:f9eeca106725 1226 } JPEG_TypeDef;
Kojto 122:f9eeca106725 1227
Kojto 122:f9eeca106725 1228 /**
Kojto 122:f9eeca106725 1229 * @brief MDIOS
Kojto 122:f9eeca106725 1230 */
Kojto 122:f9eeca106725 1231
Kojto 122:f9eeca106725 1232 typedef struct
Kojto 122:f9eeca106725 1233 {
Kojto 122:f9eeca106725 1234 __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
Kojto 122:f9eeca106725 1235 __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
Kojto 122:f9eeca106725 1236 __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
Kojto 122:f9eeca106725 1237 __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
Kojto 122:f9eeca106725 1238 __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
Kojto 122:f9eeca106725 1239 __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
Kojto 122:f9eeca106725 1240 __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
Kojto 122:f9eeca106725 1241 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
Kojto 122:f9eeca106725 1242 __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
Kojto 122:f9eeca106725 1243 __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
Kojto 122:f9eeca106725 1244 __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
Kojto 122:f9eeca106725 1245 __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
Kojto 122:f9eeca106725 1246 __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
Kojto 122:f9eeca106725 1247 __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
Kojto 122:f9eeca106725 1248 __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
Kojto 122:f9eeca106725 1249 __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
Kojto 122:f9eeca106725 1250 __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
Kojto 122:f9eeca106725 1251 __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
Kojto 122:f9eeca106725 1252 __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
Kojto 122:f9eeca106725 1253 __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
Kojto 122:f9eeca106725 1254 __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
Kojto 122:f9eeca106725 1255 __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
Kojto 122:f9eeca106725 1256 __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
Kojto 122:f9eeca106725 1257 __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
Kojto 122:f9eeca106725 1258 __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
Kojto 122:f9eeca106725 1259 __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
Kojto 122:f9eeca106725 1260 __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
Kojto 122:f9eeca106725 1261 __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
Kojto 122:f9eeca106725 1262 __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
Kojto 122:f9eeca106725 1263 __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
Kojto 122:f9eeca106725 1264 __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
Kojto 122:f9eeca106725 1265 __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
Kojto 122:f9eeca106725 1266 __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
Kojto 122:f9eeca106725 1267 __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
Kojto 122:f9eeca106725 1268 __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
Kojto 122:f9eeca106725 1269 __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
Kojto 122:f9eeca106725 1270 __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
Kojto 122:f9eeca106725 1271 __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
Kojto 122:f9eeca106725 1272 __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
Kojto 122:f9eeca106725 1273 __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
Kojto 122:f9eeca106725 1274 __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
Kojto 122:f9eeca106725 1275 __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
Kojto 122:f9eeca106725 1276 __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
Kojto 122:f9eeca106725 1277 __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
Kojto 122:f9eeca106725 1278 __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
Kojto 122:f9eeca106725 1279 __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
Kojto 122:f9eeca106725 1280 __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
Kojto 122:f9eeca106725 1281 __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
Kojto 122:f9eeca106725 1282 __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
Kojto 122:f9eeca106725 1283 __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
Kojto 122:f9eeca106725 1284 __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
Kojto 122:f9eeca106725 1285 __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
Kojto 122:f9eeca106725 1286 __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
Kojto 122:f9eeca106725 1287 __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
Kojto 122:f9eeca106725 1288 __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
Kojto 122:f9eeca106725 1289 __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
Kojto 122:f9eeca106725 1290 __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
Kojto 122:f9eeca106725 1291 __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
Kojto 122:f9eeca106725 1292 __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
Kojto 122:f9eeca106725 1293 __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
Kojto 122:f9eeca106725 1294 __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
Kojto 122:f9eeca106725 1295 __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
Kojto 122:f9eeca106725 1296 __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
Kojto 122:f9eeca106725 1297 __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
Kojto 122:f9eeca106725 1298 __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
Kojto 122:f9eeca106725 1299 __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
Kojto 122:f9eeca106725 1300 __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
Kojto 122:f9eeca106725 1301 __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
Kojto 122:f9eeca106725 1302 __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
Kojto 122:f9eeca106725 1303 __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
Kojto 122:f9eeca106725 1304 __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
Kojto 122:f9eeca106725 1305 __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
Kojto 122:f9eeca106725 1306 } MDIOS_TypeDef;
Kojto 122:f9eeca106725 1307
Kojto 122:f9eeca106725 1308
Kojto 122:f9eeca106725 1309 /** @addtogroup Peripheral_memory_map
Kojto 122:f9eeca106725 1310 * @{
Kojto 122:f9eeca106725 1311 */
Kojto 122:f9eeca106725 1312 #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
Kojto 122:f9eeca106725 1313 #define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
Kojto 122:f9eeca106725 1314 #define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
Kojto 122:f9eeca106725 1315 #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
Kojto 122:f9eeca106725 1316 #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
Kojto 122:f9eeca106725 1317 #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
Kojto 122:f9eeca106725 1318 #define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
Kojto 122:f9eeca106725 1319 #define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
Kojto 122:f9eeca106725 1320 #define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
Kojto 122:f9eeca106725 1321 #define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
Kojto 122:f9eeca106725 1322 #define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
Kojto 122:f9eeca106725 1323 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
Kojto 122:f9eeca106725 1324
Kojto 122:f9eeca106725 1325 /* Legacy define */
Kojto 122:f9eeca106725 1326 #define FLASH_BASE FLASHAXI_BASE
Kojto 122:f9eeca106725 1327
Kojto 122:f9eeca106725 1328 /*!< Peripheral memory map */
Kojto 122:f9eeca106725 1329 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 122:f9eeca106725 1330 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto 122:f9eeca106725 1331 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto 122:f9eeca106725 1332 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
Kojto 122:f9eeca106725 1333
Kojto 122:f9eeca106725 1334 /*!< APB1 peripherals */
Kojto 122:f9eeca106725 1335 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 1336 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 1337 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 1338 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
Kojto 122:f9eeca106725 1339 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 1340 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 1341 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
Kojto 122:f9eeca106725 1342 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 1343 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 1344 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
Kojto 122:f9eeca106725 1345 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
Kojto 122:f9eeca106725 1346 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 1347 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 1348 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
Kojto 122:f9eeca106725 1349 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 1350 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 1351 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 1352 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 1353 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
Kojto 122:f9eeca106725 1354 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
Kojto 122:f9eeca106725 1355 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
Kojto 122:f9eeca106725 1356 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
Kojto 122:f9eeca106725 1357 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
Kojto 122:f9eeca106725 1358 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
Kojto 122:f9eeca106725 1359 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
Kojto 122:f9eeca106725 1360 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
Kojto 122:f9eeca106725 1361 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
Kojto 122:f9eeca106725 1362 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
Kojto 122:f9eeca106725 1363 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
Kojto 122:f9eeca106725 1364 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
Kojto 122:f9eeca106725 1365 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
Kojto 122:f9eeca106725 1366 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
Kojto 122:f9eeca106725 1367
Kojto 122:f9eeca106725 1368 /*!< APB2 peripherals */
Kojto 122:f9eeca106725 1369 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 1370 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 1371 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 1372 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 1373 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 1374 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 1375 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
Kojto 122:f9eeca106725 1376 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
Kojto 122:f9eeca106725 1377 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
Kojto 122:f9eeca106725 1378 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
Kojto 122:f9eeca106725 1379 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 1380 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
Kojto 122:f9eeca106725 1381 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 1382 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 1383 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
Kojto 122:f9eeca106725 1384 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
Kojto 122:f9eeca106725 1385 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
Kojto 122:f9eeca106725 1386 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
Kojto 122:f9eeca106725 1387 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
Kojto 122:f9eeca106725 1388 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
Kojto 122:f9eeca106725 1389 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
Kojto 122:f9eeca106725 1390 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
Kojto 122:f9eeca106725 1391 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
Kojto 122:f9eeca106725 1392 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
Kojto 122:f9eeca106725 1393 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
Kojto 122:f9eeca106725 1394 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
Kojto 122:f9eeca106725 1395 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
Kojto 122:f9eeca106725 1396 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
Kojto 122:f9eeca106725 1397 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
Kojto 122:f9eeca106725 1398 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
Kojto 122:f9eeca106725 1399 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
Kojto 122:f9eeca106725 1400 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
Kojto 122:f9eeca106725 1401 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
Kojto 122:f9eeca106725 1402 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
Kojto 122:f9eeca106725 1403 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
Kojto 122:f9eeca106725 1404 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
Kojto 122:f9eeca106725 1405 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
Kojto 122:f9eeca106725 1406 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
Kojto 122:f9eeca106725 1407 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
Kojto 122:f9eeca106725 1408 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
Kojto 122:f9eeca106725 1409 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
Kojto 122:f9eeca106725 1410 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
Kojto 122:f9eeca106725 1411 /*!< AHB1 peripherals */
Kojto 122:f9eeca106725 1412 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
Kojto 122:f9eeca106725 1413 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
Kojto 122:f9eeca106725 1414 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
Kojto 122:f9eeca106725 1415 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
Kojto 122:f9eeca106725 1416 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
Kojto 122:f9eeca106725 1417 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
Kojto 122:f9eeca106725 1418 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
Kojto 122:f9eeca106725 1419 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
Kojto 122:f9eeca106725 1420 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
Kojto 122:f9eeca106725 1421 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
Kojto 122:f9eeca106725 1422 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
Kojto 122:f9eeca106725 1423 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
Kojto 122:f9eeca106725 1424 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
Kojto 122:f9eeca106725 1425 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
Kojto 122:f9eeca106725 1426 #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
Kojto 122:f9eeca106725 1427 #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
Kojto 122:f9eeca106725 1428 #define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */
Kojto 122:f9eeca106725 1429 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
Kojto 122:f9eeca106725 1430 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
Kojto 122:f9eeca106725 1431 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
Kojto 122:f9eeca106725 1432 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
Kojto 122:f9eeca106725 1433 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
Kojto 122:f9eeca106725 1434 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
Kojto 122:f9eeca106725 1435 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
Kojto 122:f9eeca106725 1436 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
Kojto 122:f9eeca106725 1437 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
Kojto 122:f9eeca106725 1438 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
Kojto 122:f9eeca106725 1439 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
Kojto 122:f9eeca106725 1440 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
Kojto 122:f9eeca106725 1441 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
Kojto 122:f9eeca106725 1442 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
Kojto 122:f9eeca106725 1443 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
Kojto 122:f9eeca106725 1444 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
Kojto 122:f9eeca106725 1445 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
Kojto 122:f9eeca106725 1446 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
Kojto 122:f9eeca106725 1447 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
Kojto 122:f9eeca106725 1448 #define ETH_MAC_BASE (ETH_BASE)
Kojto 122:f9eeca106725 1449 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
Kojto 122:f9eeca106725 1450 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
Kojto 122:f9eeca106725 1451 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
Kojto 122:f9eeca106725 1452 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
Kojto 122:f9eeca106725 1453 /*!< AHB2 peripherals */
Kojto 122:f9eeca106725 1454 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
Kojto 122:f9eeca106725 1455 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
Kojto 122:f9eeca106725 1456 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
Kojto 122:f9eeca106725 1457 /*!< FMC Bankx registers base address */
Kojto 122:f9eeca106725 1458 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
Kojto 122:f9eeca106725 1459 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
Kojto 122:f9eeca106725 1460 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
Kojto 122:f9eeca106725 1461 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
Kojto 122:f9eeca106725 1462
Kojto 122:f9eeca106725 1463 /* Debug MCU registers base address */
Kojto 122:f9eeca106725 1464 #define DBGMCU_BASE 0xE0042000U
Kojto 122:f9eeca106725 1465
Kojto 122:f9eeca106725 1466 /*!< USB registers base address */
Kojto 122:f9eeca106725 1467 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
Kojto 122:f9eeca106725 1468 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
Kojto 122:f9eeca106725 1469
Kojto 122:f9eeca106725 1470 #define USB_OTG_GLOBAL_BASE 0x000U
Kojto 122:f9eeca106725 1471 #define USB_OTG_DEVICE_BASE 0x800U
Kojto 122:f9eeca106725 1472 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
Kojto 122:f9eeca106725 1473 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
Kojto 122:f9eeca106725 1474 #define USB_OTG_EP_REG_SIZE 0x20U
Kojto 122:f9eeca106725 1475 #define USB_OTG_HOST_BASE 0x400U
Kojto 122:f9eeca106725 1476 #define USB_OTG_HOST_PORT_BASE 0x440U
Kojto 122:f9eeca106725 1477 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
Kojto 122:f9eeca106725 1478 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
Kojto 122:f9eeca106725 1479 #define USB_OTG_PCGCCTL_BASE 0xE00U
Kojto 122:f9eeca106725 1480 #define USB_OTG_FIFO_BASE 0x1000U
Kojto 122:f9eeca106725 1481 #define USB_OTG_FIFO_SIZE 0x1000U
Kojto 122:f9eeca106725 1482
Kojto 122:f9eeca106725 1483 /**
Kojto 122:f9eeca106725 1484 * @}
Kojto 122:f9eeca106725 1485 */
Kojto 122:f9eeca106725 1486
Kojto 122:f9eeca106725 1487 /** @addtogroup Peripheral_declaration
Kojto 122:f9eeca106725 1488 * @{
Kojto 122:f9eeca106725 1489 */
Kojto 122:f9eeca106725 1490 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 122:f9eeca106725 1491 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 122:f9eeca106725 1492 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 122:f9eeca106725 1493 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 122:f9eeca106725 1494 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 122:f9eeca106725 1495 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 122:f9eeca106725 1496 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Kojto 122:f9eeca106725 1497 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Kojto 122:f9eeca106725 1498 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 122:f9eeca106725 1499 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
Kojto 122:f9eeca106725 1500 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 122:f9eeca106725 1501 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 122:f9eeca106725 1502 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 122:f9eeca106725 1503 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 122:f9eeca106725 1504 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 122:f9eeca106725 1505 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
Kojto 122:f9eeca106725 1506 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 122:f9eeca106725 1507 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 122:f9eeca106725 1508 #define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto 122:f9eeca106725 1509 #define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto 122:f9eeca106725 1510 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 122:f9eeca106725 1511 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 122:f9eeca106725 1512 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 122:f9eeca106725 1513 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
Kojto 122:f9eeca106725 1514 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto 122:f9eeca106725 1515 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Kojto 122:f9eeca106725 1516 #define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto 122:f9eeca106725 1517 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 122:f9eeca106725 1518 #define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto 122:f9eeca106725 1519 #define UART7 ((USART_TypeDef *) UART7_BASE)
Kojto 122:f9eeca106725 1520 #define UART8 ((USART_TypeDef *) UART8_BASE)
Kojto 122:f9eeca106725 1521 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 122:f9eeca106725 1522 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Kojto 122:f9eeca106725 1523 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 122:f9eeca106725 1524 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 122:f9eeca106725 1525 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 122:f9eeca106725 1526 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 122:f9eeca106725 1527 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto 122:f9eeca106725 1528 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Kojto 122:f9eeca106725 1529 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
Kojto 122:f9eeca106725 1530 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 122:f9eeca106725 1531 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto 122:f9eeca106725 1532 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 122:f9eeca106725 1533 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 122:f9eeca106725 1534 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 122:f9eeca106725 1535 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 122:f9eeca106725 1536 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 122:f9eeca106725 1537 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto 122:f9eeca106725 1538 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
Kojto 122:f9eeca106725 1539 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto 122:f9eeca106725 1540 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
Kojto 122:f9eeca106725 1541 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto 122:f9eeca106725 1542 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto 122:f9eeca106725 1543 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
Kojto 122:f9eeca106725 1544 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
Kojto 122:f9eeca106725 1545 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
Kojto 122:f9eeca106725 1546 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
Kojto 122:f9eeca106725 1547 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
Kojto 122:f9eeca106725 1548 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 122:f9eeca106725 1549 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 122:f9eeca106725 1550 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 122:f9eeca106725 1551 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 122:f9eeca106725 1552 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 122:f9eeca106725 1553 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 122:f9eeca106725 1554 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto 122:f9eeca106725 1555 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 122:f9eeca106725 1556 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
Kojto 122:f9eeca106725 1557 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
Kojto 122:f9eeca106725 1558 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
Kojto 122:f9eeca106725 1559 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 122:f9eeca106725 1560 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 122:f9eeca106725 1561 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 122:f9eeca106725 1562 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 122:f9eeca106725 1563 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto 122:f9eeca106725 1564 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto 122:f9eeca106725 1565 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto 122:f9eeca106725 1566 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto 122:f9eeca106725 1567 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto 122:f9eeca106725 1568 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto 122:f9eeca106725 1569 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto 122:f9eeca106725 1570 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto 122:f9eeca106725 1571 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 122:f9eeca106725 1572 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto 122:f9eeca106725 1573 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto 122:f9eeca106725 1574 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto 122:f9eeca106725 1575 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto 122:f9eeca106725 1576 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto 122:f9eeca106725 1577 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto 122:f9eeca106725 1578 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto 122:f9eeca106725 1579 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto 122:f9eeca106725 1580 #define ETH ((ETH_TypeDef *) ETH_BASE)
Kojto 122:f9eeca106725 1581 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
Kojto 122:f9eeca106725 1582 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
Kojto 122:f9eeca106725 1583 #define RNG ((RNG_TypeDef *) RNG_BASE)
Kojto 122:f9eeca106725 1584 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
Kojto 122:f9eeca106725 1585 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
Kojto 122:f9eeca106725 1586 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
Kojto 122:f9eeca106725 1587 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
Kojto 122:f9eeca106725 1588 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto 122:f9eeca106725 1589 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 122:f9eeca106725 1590 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto 122:f9eeca106725 1591 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
Kojto 122:f9eeca106725 1592 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
Kojto 122:f9eeca106725 1593 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
Kojto 122:f9eeca106725 1594 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
Kojto 122:f9eeca106725 1595 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
Kojto 122:f9eeca106725 1596 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
Kojto 122:f9eeca106725 1597 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
Kojto 122:f9eeca106725 1598 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
Kojto 122:f9eeca106725 1599 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
Kojto 122:f9eeca106725 1600 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
Kojto 122:f9eeca106725 1601 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
Kojto 122:f9eeca106725 1602 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
Kojto 122:f9eeca106725 1603 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
Kojto 122:f9eeca106725 1604 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
Kojto 122:f9eeca106725 1605 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
Kojto 122:f9eeca106725 1606 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
Kojto 122:f9eeca106725 1607 #define JPEG ((JPEG_TypeDef *) JPEG_BASE)
Kojto 122:f9eeca106725 1608
Kojto 122:f9eeca106725 1609 /**
Kojto 122:f9eeca106725 1610 * @}
Kojto 122:f9eeca106725 1611 */
Kojto 122:f9eeca106725 1612
Kojto 122:f9eeca106725 1613 /** @addtogroup Exported_constants
Kojto 122:f9eeca106725 1614 * @{
Kojto 122:f9eeca106725 1615 */
Kojto 122:f9eeca106725 1616
Kojto 122:f9eeca106725 1617 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 122:f9eeca106725 1618 * @{
Kojto 122:f9eeca106725 1619 */
Kojto 122:f9eeca106725 1620
Kojto 122:f9eeca106725 1621 /******************************************************************************/
Kojto 122:f9eeca106725 1622 /* Peripheral Registers_Bits_Definition */
Kojto 122:f9eeca106725 1623 /******************************************************************************/
Kojto 122:f9eeca106725 1624
Kojto 122:f9eeca106725 1625 /******************************************************************************/
Kojto 122:f9eeca106725 1626 /* */
Kojto 122:f9eeca106725 1627 /* Analog to Digital Converter */
Kojto 122:f9eeca106725 1628 /* */
Kojto 122:f9eeca106725 1629 /******************************************************************************/
Kojto 122:f9eeca106725 1630 /******************** Bit definition for ADC_SR register ********************/
Kojto 122:f9eeca106725 1631 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
Kojto 122:f9eeca106725 1632 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
Kojto 122:f9eeca106725 1633 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
Kojto 122:f9eeca106725 1634 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
Kojto 122:f9eeca106725 1635 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
Kojto 122:f9eeca106725 1636 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
Kojto 122:f9eeca106725 1637
Kojto 122:f9eeca106725 1638 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 122:f9eeca106725 1639 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 122:f9eeca106725 1640 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1641 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1642 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1643 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1644 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1645 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
Kojto 122:f9eeca106725 1646 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
Kojto 122:f9eeca106725 1647 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
Kojto 122:f9eeca106725 1648 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
Kojto 122:f9eeca106725 1649 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
Kojto 122:f9eeca106725 1650 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
Kojto 122:f9eeca106725 1651 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
Kojto 122:f9eeca106725 1652 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
Kojto 122:f9eeca106725 1653 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 122:f9eeca106725 1654 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1655 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1656 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1657 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
Kojto 122:f9eeca106725 1658 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
Kojto 122:f9eeca106725 1659 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
Kojto 122:f9eeca106725 1660 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1661 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1662 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
Kojto 122:f9eeca106725 1663
Kojto 122:f9eeca106725 1664 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 122:f9eeca106725 1665 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
Kojto 122:f9eeca106725 1666 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
Kojto 122:f9eeca106725 1667 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
Kojto 122:f9eeca106725 1668 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
Kojto 122:f9eeca106725 1669 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
Kojto 122:f9eeca106725 1670 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
Kojto 122:f9eeca106725 1671 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 122:f9eeca106725 1672 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1673 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1674 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1675 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1676 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 122:f9eeca106725 1677 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1678 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1679 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
Kojto 122:f9eeca106725 1680 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 122:f9eeca106725 1681 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1682 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1683 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1684 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1685 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 122:f9eeca106725 1686 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1687 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1688 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
Kojto 122:f9eeca106725 1689
Kojto 122:f9eeca106725 1690 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 122:f9eeca106725 1691 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 122:f9eeca106725 1692 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1693 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1694 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1695 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 122:f9eeca106725 1696 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 1697 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 1698 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 1699 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 122:f9eeca106725 1700 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 1701 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 1702 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 1703 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 122:f9eeca106725 1704 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 1705 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 1706 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 1707 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 122:f9eeca106725 1708 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1709 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1710 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1711 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 122:f9eeca106725 1712 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1713 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1714 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1715 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 122:f9eeca106725 1716 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1717 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1718 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1719 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 122:f9eeca106725 1720 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1721 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1722 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1723 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 122:f9eeca106725 1724 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1725 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1726 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1727
Kojto 122:f9eeca106725 1728 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 122:f9eeca106725 1729 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 122:f9eeca106725 1730 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1731 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1732 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1733 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 122:f9eeca106725 1734 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 1735 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 1736 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 1737 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 122:f9eeca106725 1738 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 1739 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 1740 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 1741 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 122:f9eeca106725 1742 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 1743 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 1744 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 1745 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 122:f9eeca106725 1746 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1747 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1748 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1749 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 122:f9eeca106725 1750 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1751 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1752 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1753 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 122:f9eeca106725 1754 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1755 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1756 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1757 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 122:f9eeca106725 1758 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1759 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1760 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1761 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 122:f9eeca106725 1762 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1763 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1764 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1765 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 122:f9eeca106725 1766 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1767 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1768 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1769
Kojto 122:f9eeca106725 1770 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 122:f9eeca106725 1771 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
Kojto 122:f9eeca106725 1772
Kojto 122:f9eeca106725 1773 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 122:f9eeca106725 1774 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
Kojto 122:f9eeca106725 1775
Kojto 122:f9eeca106725 1776 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 122:f9eeca106725 1777 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
Kojto 122:f9eeca106725 1778
Kojto 122:f9eeca106725 1779 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 122:f9eeca106725 1780 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
Kojto 122:f9eeca106725 1781
Kojto 122:f9eeca106725 1782 /******************* Bit definition for ADC_HTR register ********************/
Kojto 122:f9eeca106725 1783 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
Kojto 122:f9eeca106725 1784
Kojto 122:f9eeca106725 1785 /******************* Bit definition for ADC_LTR register ********************/
Kojto 122:f9eeca106725 1786 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
Kojto 122:f9eeca106725 1787
Kojto 122:f9eeca106725 1788 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 122:f9eeca106725 1789 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 122:f9eeca106725 1790 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1791 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1792 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1793 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1794 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1795 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 122:f9eeca106725 1796 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1797 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1798 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1799 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1800 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1801 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 122:f9eeca106725 1802 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1803 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1804 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1805 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1806 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1807 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 122:f9eeca106725 1808 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1809 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1810 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1811 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1812 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1813 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 122:f9eeca106725 1814 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1815 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1816 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1817 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1818
Kojto 122:f9eeca106725 1819 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 122:f9eeca106725 1820 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 122:f9eeca106725 1821 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1822 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1823 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1824 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1825 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1826 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 122:f9eeca106725 1827 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1828 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1829 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1830 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1831 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1832 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 122:f9eeca106725 1833 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1834 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1835 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1836 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1837 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1838 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 122:f9eeca106725 1839 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1840 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1841 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1842 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1843 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1844 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 122:f9eeca106725 1845 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1846 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1847 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1848 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1849 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1850 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 122:f9eeca106725 1851 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1852 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1853 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1854 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1855 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1856
Kojto 122:f9eeca106725 1857 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 122:f9eeca106725 1858 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 122:f9eeca106725 1859 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1860 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1861 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1862 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1863 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1864 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 122:f9eeca106725 1865 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1866 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1867 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1868 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1869 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1870 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 122:f9eeca106725 1871 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1872 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1873 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1874 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1875 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1876 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 122:f9eeca106725 1877 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1878 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1879 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1880 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1881 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1882 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 122:f9eeca106725 1883 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1884 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1885 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1886 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1887 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1888 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 122:f9eeca106725 1889 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1890 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1891 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1892 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1893 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1894
Kojto 122:f9eeca106725 1895 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 122:f9eeca106725 1896 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 122:f9eeca106725 1897 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1898 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1899 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1900 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1901 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1902 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 122:f9eeca106725 1903 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 1904 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 1905 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 1906 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 1907 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
Kojto 122:f9eeca106725 1908 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 122:f9eeca106725 1909 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 1910 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 1911 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1912 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1913 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1914 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 122:f9eeca106725 1915 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1916 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1917 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
Kojto 122:f9eeca106725 1918 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
Kojto 122:f9eeca106725 1919 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
Kojto 122:f9eeca106725 1920 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 122:f9eeca106725 1921 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1922 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1923
Kojto 122:f9eeca106725 1924 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 122:f9eeca106725 1925 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
Kojto 122:f9eeca106725 1926
Kojto 122:f9eeca106725 1927 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 122:f9eeca106725 1928 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
Kojto 122:f9eeca106725 1929
Kojto 122:f9eeca106725 1930 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 122:f9eeca106725 1931 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
Kojto 122:f9eeca106725 1932
Kojto 122:f9eeca106725 1933 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 122:f9eeca106725 1934 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
Kojto 122:f9eeca106725 1935
Kojto 122:f9eeca106725 1936 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 1937 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
Kojto 122:f9eeca106725 1938 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
Kojto 122:f9eeca106725 1939
Kojto 122:f9eeca106725 1940 /******************* Bit definition for ADC_CSR register ********************/
Kojto 122:f9eeca106725 1941 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
Kojto 122:f9eeca106725 1942 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
Kojto 122:f9eeca106725 1943 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
Kojto 122:f9eeca106725 1944 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
Kojto 122:f9eeca106725 1945 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
Kojto 122:f9eeca106725 1946 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 Overrun flag */
Kojto 122:f9eeca106725 1947 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
Kojto 122:f9eeca106725 1948 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
Kojto 122:f9eeca106725 1949 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
Kojto 122:f9eeca106725 1950 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
Kojto 122:f9eeca106725 1951 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
Kojto 122:f9eeca106725 1952 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 Overrun flag */
Kojto 122:f9eeca106725 1953 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
Kojto 122:f9eeca106725 1954 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
Kojto 122:f9eeca106725 1955 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
Kojto 122:f9eeca106725 1956 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
Kojto 122:f9eeca106725 1957 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
Kojto 122:f9eeca106725 1958 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 Overrun flag */
Kojto 122:f9eeca106725 1959
Kojto 122:f9eeca106725 1960 /* Legacy defines */
Kojto 122:f9eeca106725 1961 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
Kojto 122:f9eeca106725 1962 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
Kojto 122:f9eeca106725 1963 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
Kojto 122:f9eeca106725 1964
Kojto 122:f9eeca106725 1965
Kojto 122:f9eeca106725 1966 /******************* Bit definition for ADC_CCR register ********************/
Kojto 122:f9eeca106725 1967 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 122:f9eeca106725 1968 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 1969 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 1970 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 1971 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 1972 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 1973 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 122:f9eeca106725 1974 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 1975 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 1976 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 1977 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 1978 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
Kojto 122:f9eeca106725 1979 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 122:f9eeca106725 1980 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1981 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1982 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 122:f9eeca106725 1983 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 1984 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 1985 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
Kojto 122:f9eeca106725 1986 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
Kojto 122:f9eeca106725 1987
Kojto 122:f9eeca106725 1988 /******************* Bit definition for ADC_CDR register ********************/
Kojto 122:f9eeca106725 1989 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
Kojto 122:f9eeca106725 1990 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
Kojto 122:f9eeca106725 1991
Kojto 122:f9eeca106725 1992 /******************************************************************************/
Kojto 122:f9eeca106725 1993 /* */
Kojto 122:f9eeca106725 1994 /* Controller Area Network */
Kojto 122:f9eeca106725 1995 /* */
Kojto 122:f9eeca106725 1996 /******************************************************************************/
Kojto 122:f9eeca106725 1997 /*!<CAN control and status registers */
Kojto 122:f9eeca106725 1998 /******************* Bit definition for CAN_MCR register ********************/
Kojto 122:f9eeca106725 1999 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
Kojto 122:f9eeca106725 2000 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
Kojto 122:f9eeca106725 2001 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
Kojto 122:f9eeca106725 2002 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
Kojto 122:f9eeca106725 2003 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
Kojto 122:f9eeca106725 2004 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
Kojto 122:f9eeca106725 2005 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
Kojto 122:f9eeca106725 2006 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
Kojto 122:f9eeca106725 2007 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
Kojto 122:f9eeca106725 2008
Kojto 122:f9eeca106725 2009 /******************* Bit definition for CAN_MSR register ********************/
Kojto 122:f9eeca106725 2010 #define CAN_MSR_INAK 0x00000001U /*!<Initialization Acknowledge */
Kojto 122:f9eeca106725 2011 #define CAN_MSR_SLAK 0x00000002U /*!<Sleep Acknowledge */
Kojto 122:f9eeca106725 2012 #define CAN_MSR_ERRI 0x00000004U /*!<Error Interrupt */
Kojto 122:f9eeca106725 2013 #define CAN_MSR_WKUI 0x00000008U /*!<Wakeup Interrupt */
Kojto 122:f9eeca106725 2014 #define CAN_MSR_SLAKI 0x00000010U /*!<Sleep Acknowledge Interrupt */
Kojto 122:f9eeca106725 2015 #define CAN_MSR_TXM 0x00000100U /*!<Transmit Mode */
Kojto 122:f9eeca106725 2016 #define CAN_MSR_RXM 0x00000200U /*!<Receive Mode */
Kojto 122:f9eeca106725 2017 #define CAN_MSR_SAMP 0x00000400U /*!<Last Sample Point */
Kojto 122:f9eeca106725 2018 #define CAN_MSR_RX 0x00000800U /*!<CAN Rx Signal */
Kojto 122:f9eeca106725 2019
Kojto 122:f9eeca106725 2020 /******************* Bit definition for CAN_TSR register ********************/
Kojto 122:f9eeca106725 2021 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
Kojto 122:f9eeca106725 2022 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
Kojto 122:f9eeca106725 2023 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
Kojto 122:f9eeca106725 2024 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
Kojto 122:f9eeca106725 2025 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
Kojto 122:f9eeca106725 2026 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
Kojto 122:f9eeca106725 2027 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
Kojto 122:f9eeca106725 2028 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
Kojto 122:f9eeca106725 2029 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
Kojto 122:f9eeca106725 2030 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
Kojto 122:f9eeca106725 2031 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
Kojto 122:f9eeca106725 2032 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
Kojto 122:f9eeca106725 2033 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
Kojto 122:f9eeca106725 2034 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
Kojto 122:f9eeca106725 2035 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
Kojto 122:f9eeca106725 2036 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
Kojto 122:f9eeca106725 2037
Kojto 122:f9eeca106725 2038 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
Kojto 122:f9eeca106725 2039 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
Kojto 122:f9eeca106725 2040 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
Kojto 122:f9eeca106725 2041 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
Kojto 122:f9eeca106725 2042
Kojto 122:f9eeca106725 2043 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
Kojto 122:f9eeca106725 2044 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 122:f9eeca106725 2045 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 122:f9eeca106725 2046 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 122:f9eeca106725 2047
Kojto 122:f9eeca106725 2048 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 122:f9eeca106725 2049 #define CAN_RF0R_FMP0 0x00000003U /*!<FIFO 0 Message Pending */
Kojto 122:f9eeca106725 2050 #define CAN_RF0R_FULL0 0x00000008U /*!<FIFO 0 Full */
Kojto 122:f9eeca106725 2051 #define CAN_RF0R_FOVR0 0x00000010U /*!<FIFO 0 Overrun */
Kojto 122:f9eeca106725 2052 #define CAN_RF0R_RFOM0 0x00000020U /*!<Release FIFO 0 Output Mailbox */
Kojto 122:f9eeca106725 2053
Kojto 122:f9eeca106725 2054 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 122:f9eeca106725 2055 #define CAN_RF1R_FMP1 0x00000003U /*!<FIFO 1 Message Pending */
Kojto 122:f9eeca106725 2056 #define CAN_RF1R_FULL1 0x00000008U /*!<FIFO 1 Full */
Kojto 122:f9eeca106725 2057 #define CAN_RF1R_FOVR1 0x00000010U /*!<FIFO 1 Overrun */
Kojto 122:f9eeca106725 2058 #define CAN_RF1R_RFOM1 0x00000020U /*!<Release FIFO 1 Output Mailbox */
Kojto 122:f9eeca106725 2059
Kojto 122:f9eeca106725 2060 /******************** Bit definition for CAN_IER register *******************/
Kojto 122:f9eeca106725 2061 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 122:f9eeca106725 2062 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 2063 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 2064 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 2065 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
Kojto 122:f9eeca106725 2066 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
Kojto 122:f9eeca106725 2067 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
Kojto 122:f9eeca106725 2068 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
Kojto 122:f9eeca106725 2069 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
Kojto 122:f9eeca106725 2070 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
Kojto 122:f9eeca106725 2071 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
Kojto 122:f9eeca106725 2072 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
Kojto 122:f9eeca106725 2073 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
Kojto 122:f9eeca106725 2074 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
Kojto 122:f9eeca106725 2075
Kojto 122:f9eeca106725 2076 /******************** Bit definition for CAN_ESR register *******************/
Kojto 122:f9eeca106725 2077 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
Kojto 122:f9eeca106725 2078 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
Kojto 122:f9eeca106725 2079 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
Kojto 122:f9eeca106725 2080
Kojto 122:f9eeca106725 2081 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
Kojto 122:f9eeca106725 2082 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 2083 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 2084 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 2085
Kojto 122:f9eeca106725 2086 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 122:f9eeca106725 2087 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
Kojto 122:f9eeca106725 2088
Kojto 122:f9eeca106725 2089 /******************* Bit definition for CAN_BTR register ********************/
Kojto 122:f9eeca106725 2090 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
Kojto 122:f9eeca106725 2091 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
Kojto 122:f9eeca106725 2092 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2093 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2094 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 2095 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 2096 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
Kojto 122:f9eeca106725 2097 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2098 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2099 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 2100 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
Kojto 122:f9eeca106725 2101 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 2102 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 2103 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
Kojto 122:f9eeca106725 2104 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
Kojto 122:f9eeca106725 2105
Kojto 122:f9eeca106725 2106 /*!<Mailbox registers */
Kojto 122:f9eeca106725 2107 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 122:f9eeca106725 2108 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2109 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2110 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 2111 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 2112 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2113
Kojto 122:f9eeca106725 2114 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 122:f9eeca106725 2115 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 2116 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2117 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2118
Kojto 122:f9eeca106725 2119 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 122:f9eeca106725 2120 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 2121 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 2122 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 2123 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 122:f9eeca106725 2124
Kojto 122:f9eeca106725 2125 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 122:f9eeca106725 2126 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 2127 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 2128 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 2129 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 122:f9eeca106725 2130
Kojto 122:f9eeca106725 2131 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 122:f9eeca106725 2132 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2133 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2134 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 2135 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 2136 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2137
Kojto 122:f9eeca106725 2138 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 122:f9eeca106725 2139 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 2140 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2141 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2142
Kojto 122:f9eeca106725 2143 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 122:f9eeca106725 2144 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 2145 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 2146 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 2147 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 122:f9eeca106725 2148
Kojto 122:f9eeca106725 2149 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 122:f9eeca106725 2150 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 2151 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 2152 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 2153 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 122:f9eeca106725 2154
Kojto 122:f9eeca106725 2155 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 122:f9eeca106725 2156 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
Kojto 122:f9eeca106725 2157 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2158 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 2159 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
Kojto 122:f9eeca106725 2160 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2161
Kojto 122:f9eeca106725 2162 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 122:f9eeca106725 2163 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 2164 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
Kojto 122:f9eeca106725 2165 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2166
Kojto 122:f9eeca106725 2167 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 122:f9eeca106725 2168 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 2169 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 2170 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 2171 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 122:f9eeca106725 2172
Kojto 122:f9eeca106725 2173 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 122:f9eeca106725 2174 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 2175 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 2176 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 2177 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 122:f9eeca106725 2178
Kojto 122:f9eeca106725 2179 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 122:f9eeca106725 2180 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2181 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 2182 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
Kojto 122:f9eeca106725 2183 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2184
Kojto 122:f9eeca106725 2185 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 122:f9eeca106725 2186 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 2187 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
Kojto 122:f9eeca106725 2188 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2189
Kojto 122:f9eeca106725 2190 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 122:f9eeca106725 2191 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 2192 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 2193 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 2194 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 122:f9eeca106725 2195
Kojto 122:f9eeca106725 2196 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 122:f9eeca106725 2197 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 2198 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 2199 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 2200 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 122:f9eeca106725 2201
Kojto 122:f9eeca106725 2202 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 122:f9eeca106725 2203 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
Kojto 122:f9eeca106725 2204 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
Kojto 122:f9eeca106725 2205 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
Kojto 122:f9eeca106725 2206 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
Kojto 122:f9eeca106725 2207
Kojto 122:f9eeca106725 2208 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 122:f9eeca106725 2209 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
Kojto 122:f9eeca106725 2210 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
Kojto 122:f9eeca106725 2211 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
Kojto 122:f9eeca106725 2212
Kojto 122:f9eeca106725 2213 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 122:f9eeca106725 2214 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
Kojto 122:f9eeca106725 2215 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
Kojto 122:f9eeca106725 2216 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
Kojto 122:f9eeca106725 2217 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
Kojto 122:f9eeca106725 2218
Kojto 122:f9eeca106725 2219 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 122:f9eeca106725 2220 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
Kojto 122:f9eeca106725 2221 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
Kojto 122:f9eeca106725 2222 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
Kojto 122:f9eeca106725 2223 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
Kojto 122:f9eeca106725 2224
Kojto 122:f9eeca106725 2225 /*!<CAN filter registers */
Kojto 122:f9eeca106725 2226 /******************* Bit definition for CAN_FMR register ********************/
Kojto 122:f9eeca106725 2227 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
Kojto 122:f9eeca106725 2228 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
Kojto 122:f9eeca106725 2229
Kojto 122:f9eeca106725 2230 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 122:f9eeca106725 2231 #define CAN_FM1R_FBM 0x3FFFU /*!<Filter Mode */
Kojto 122:f9eeca106725 2232 #define CAN_FM1R_FBM0 0x0001U /*!<Filter Init Mode bit 0 */
Kojto 122:f9eeca106725 2233 #define CAN_FM1R_FBM1 0x0002U /*!<Filter Init Mode bit 1 */
Kojto 122:f9eeca106725 2234 #define CAN_FM1R_FBM2 0x0004U /*!<Filter Init Mode bit 2 */
Kojto 122:f9eeca106725 2235 #define CAN_FM1R_FBM3 0x0008U /*!<Filter Init Mode bit 3 */
Kojto 122:f9eeca106725 2236 #define CAN_FM1R_FBM4 0x0010U /*!<Filter Init Mode bit 4 */
Kojto 122:f9eeca106725 2237 #define CAN_FM1R_FBM5 0x0020U /*!<Filter Init Mode bit 5 */
Kojto 122:f9eeca106725 2238 #define CAN_FM1R_FBM6 0x0040U /*!<Filter Init Mode bit 6 */
Kojto 122:f9eeca106725 2239 #define CAN_FM1R_FBM7 0x0080U /*!<Filter Init Mode bit 7 */
Kojto 122:f9eeca106725 2240 #define CAN_FM1R_FBM8 0x0100U /*!<Filter Init Mode bit 8 */
Kojto 122:f9eeca106725 2241 #define CAN_FM1R_FBM9 0x0200U /*!<Filter Init Mode bit 9 */
Kojto 122:f9eeca106725 2242 #define CAN_FM1R_FBM10 0x0400U /*!<Filter Init Mode bit 10 */
Kojto 122:f9eeca106725 2243 #define CAN_FM1R_FBM11 0x0800U /*!<Filter Init Mode bit 11 */
Kojto 122:f9eeca106725 2244 #define CAN_FM1R_FBM12 0x1000U /*!<Filter Init Mode bit 12 */
Kojto 122:f9eeca106725 2245 #define CAN_FM1R_FBM13 0x2000U /*!<Filter Init Mode bit 13 */
Kojto 122:f9eeca106725 2246
Kojto 122:f9eeca106725 2247 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 122:f9eeca106725 2248 #define CAN_FS1R_FSC 0x00003FFFU /*!<Filter Scale Configuration */
Kojto 122:f9eeca106725 2249 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
Kojto 122:f9eeca106725 2250 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
Kojto 122:f9eeca106725 2251 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
Kojto 122:f9eeca106725 2252 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
Kojto 122:f9eeca106725 2253 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
Kojto 122:f9eeca106725 2254 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
Kojto 122:f9eeca106725 2255 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
Kojto 122:f9eeca106725 2256 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
Kojto 122:f9eeca106725 2257 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
Kojto 122:f9eeca106725 2258 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
Kojto 122:f9eeca106725 2259 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
Kojto 122:f9eeca106725 2260 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
Kojto 122:f9eeca106725 2261 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
Kojto 122:f9eeca106725 2262 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
Kojto 122:f9eeca106725 2263
Kojto 122:f9eeca106725 2264 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 122:f9eeca106725 2265 #define CAN_FFA1R_FFA 0x00003FFFU /*!<Filter FIFO Assignment */
Kojto 122:f9eeca106725 2266 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment for Filter 0 */
Kojto 122:f9eeca106725 2267 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment for Filter 1 */
Kojto 122:f9eeca106725 2268 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment for Filter 2 */
Kojto 122:f9eeca106725 2269 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment for Filter 3 */
Kojto 122:f9eeca106725 2270 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment for Filter 4 */
Kojto 122:f9eeca106725 2271 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment for Filter 5 */
Kojto 122:f9eeca106725 2272 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment for Filter 6 */
Kojto 122:f9eeca106725 2273 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment for Filter 7 */
Kojto 122:f9eeca106725 2274 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment for Filter 8 */
Kojto 122:f9eeca106725 2275 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment for Filter 9 */
Kojto 122:f9eeca106725 2276 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment for Filter 10 */
Kojto 122:f9eeca106725 2277 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment for Filter 11 */
Kojto 122:f9eeca106725 2278 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment for Filter 12 */
Kojto 122:f9eeca106725 2279 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment for Filter 13 */
Kojto 122:f9eeca106725 2280
Kojto 122:f9eeca106725 2281 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 122:f9eeca106725 2282 #define CAN_FA1R_FACT 0x00003FFFU /*!<Filter Active */
Kojto 122:f9eeca106725 2283 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter 0 Active */
Kojto 122:f9eeca106725 2284 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter 1 Active */
Kojto 122:f9eeca106725 2285 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter 2 Active */
Kojto 122:f9eeca106725 2286 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter 3 Active */
Kojto 122:f9eeca106725 2287 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter 4 Active */
Kojto 122:f9eeca106725 2288 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter 5 Active */
Kojto 122:f9eeca106725 2289 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter 6 Active */
Kojto 122:f9eeca106725 2290 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter 7 Active */
Kojto 122:f9eeca106725 2291 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter 8 Active */
Kojto 122:f9eeca106725 2292 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter 9 Active */
Kojto 122:f9eeca106725 2293 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter 10 Active */
Kojto 122:f9eeca106725 2294 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter 11 Active */
Kojto 122:f9eeca106725 2295 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter 12 Active */
Kojto 122:f9eeca106725 2296 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter 13 Active */
Kojto 122:f9eeca106725 2297
Kojto 122:f9eeca106725 2298 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 122:f9eeca106725 2299 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2300 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2301 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2302 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2303 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2304 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2305 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2306 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2307 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2308 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2309 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2310 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2311 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2312 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2313 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2314 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2315 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2316 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2317 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2318 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2319 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2320 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2321 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2322 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2323 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2324 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2325 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2326 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2327 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2328 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2329 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2330 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2331
Kojto 122:f9eeca106725 2332 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 122:f9eeca106725 2333 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2334 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2335 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2336 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2337 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2338 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2339 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2340 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2341 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2342 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2343 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2344 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2345 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2346 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2347 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2348 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2349 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2350 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2351 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2352 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2353 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2354 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2355 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2356 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2357 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2358 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2359 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2360 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2361 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2362 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2363 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2364 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2365
Kojto 122:f9eeca106725 2366 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 122:f9eeca106725 2367 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2368 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2369 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2370 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2371 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2372 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2373 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2374 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2375 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2376 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2377 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2378 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2379 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2380 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2381 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2382 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2383 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2384 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2385 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2386 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2387 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2388 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2389 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2390 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2391 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2392 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2393 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2394 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2395 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2396 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2397 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2398 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2399
Kojto 122:f9eeca106725 2400 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 122:f9eeca106725 2401 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2402 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2403 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2404 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2405 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2406 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2407 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2408 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2409 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2410 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2411 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2412 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2413 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2414 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2415 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2416 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2417 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2418 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2419 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2420 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2421 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2422 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2423 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2424 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2425 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2426 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2427 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2428 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2429 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2430 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2431 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2432 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2433
Kojto 122:f9eeca106725 2434 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 122:f9eeca106725 2435 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2436 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2437 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2438 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2439 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2440 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2441 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2442 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2443 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2444 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2445 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2446 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2447 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2448 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2449 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2450 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2451 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2452 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2453 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2454 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2455 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2456 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2457 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2458 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2459 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2460 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2461 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2462 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2463 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2464 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2465 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2466 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2467
Kojto 122:f9eeca106725 2468 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 122:f9eeca106725 2469 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2470 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2471 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2472 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2473 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2474 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2475 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2476 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2477 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2478 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2479 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2480 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2481 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2482 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2483 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2484 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2485 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2486 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2487 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2488 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2489 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2490 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2491 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2492 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2493 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2494 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2495 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2496 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2497 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2498 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2499 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2500 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2501
Kojto 122:f9eeca106725 2502 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 122:f9eeca106725 2503 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2504 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2505 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2506 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2507 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2508 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2509 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2510 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2511 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2512 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2513 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2514 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2515 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2516 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2517 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2518 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2519 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2520 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2521 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2522 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2523 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2524 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2525 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2526 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2527 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2528 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2529 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2530 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2531 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2532 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2533 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2534 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2535
Kojto 122:f9eeca106725 2536 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 122:f9eeca106725 2537 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2538 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2539 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2540 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2541 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2542 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2543 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2544 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2545 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2546 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2547 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2548 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2549 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2550 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2551 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2552 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2553 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2554 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2555 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2556 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2557 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2558 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2559 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2560 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2561 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2562 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2563 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2564 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2565 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2566 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2567 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2568 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2569
Kojto 122:f9eeca106725 2570 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 122:f9eeca106725 2571 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2572 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2573 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2574 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2575 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2576 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2577 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2578 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2579 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2580 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2581 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2582 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2583 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2584 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2585 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2586 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2587 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2588 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2589 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2590 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2591 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2592 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2593 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2594 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2595 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2596 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2597 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2598 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2599 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2600 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2601 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2602 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2603
Kojto 122:f9eeca106725 2604 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 122:f9eeca106725 2605 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2606 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2607 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2608 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2609 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2610 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2611 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2612 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2613 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2614 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2615 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2616 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2617 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2618 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2619 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2620 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2621 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2622 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2623 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2624 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2625 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2626 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2627 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2628 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2629 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2630 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2631 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2632 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2633 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2634 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2635 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2636 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2637
Kojto 122:f9eeca106725 2638 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 122:f9eeca106725 2639 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2640 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2641 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2642 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2643 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2644 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2645 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2646 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2647 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2648 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2649 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2650 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2651 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2652 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2653 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2654 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2655 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2656 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2657 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2658 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2659 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2660 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2661 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2662 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2663 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2664 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2665 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2666 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2667 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2668 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2669 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2670 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2671
Kojto 122:f9eeca106725 2672 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 122:f9eeca106725 2673 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2674 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2675 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2676 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2677 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2678 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2679 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2680 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2681 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2682 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2683 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2684 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2685 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2686 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2687 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2688 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2689 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2690 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2691 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2692 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2693 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2694 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2695 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2696 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2697 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2698 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2699 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2700 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2701 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2702 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2703 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2704 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2705
Kojto 122:f9eeca106725 2706 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 122:f9eeca106725 2707 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2708 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2709 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2710 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2711 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2712 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2713 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2714 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2715 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2716 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2717 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2718 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2719 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2720 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2721 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2722 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2723 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2724 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2725 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2726 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2727 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2728 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2729 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2730 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2731 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2732 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2733 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2734 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2735 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2736 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2737 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2738 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2739
Kojto 122:f9eeca106725 2740 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 122:f9eeca106725 2741 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2742 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2743 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2744 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2745 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2746 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2747 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2748 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2749 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2750 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2751 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2752 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2753 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2754 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2755 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2756 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2757 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2758 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2759 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2760 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2761 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2762 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2763 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2764 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2765 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2766 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2767 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2768 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2769 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2770 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2771 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2772 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2773
Kojto 122:f9eeca106725 2774 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 122:f9eeca106725 2775 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2776 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2777 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2778 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2779 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2780 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2781 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2782 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2783 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2784 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2785 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2786 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2787 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2788 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2789 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2790 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2791 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2792 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2793 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2794 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2795 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2796 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2797 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2798 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2799 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2800 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2801 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2802 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2803 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2804 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2805 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2806 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2807
Kojto 122:f9eeca106725 2808 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 122:f9eeca106725 2809 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2810 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2811 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2812 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2813 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2814 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2815 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2816 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2817 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2818 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2819 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2820 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2821 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2822 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2823 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2824 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2825 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2826 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2827 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2828 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2829 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2830 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2831 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2832 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2833 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2834 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2835 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2836 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2837 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2838 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2839 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2840 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2841
Kojto 122:f9eeca106725 2842 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 122:f9eeca106725 2843 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2844 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2845 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2846 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2847 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2848 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2849 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2850 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2851 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2852 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2853 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2854 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2855 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2856 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2857 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2858 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2859 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2860 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2861 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2862 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2863 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2864 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2865 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2866 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2867 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2868 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2869 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2870 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2871 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2872 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2873 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2874 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2875
Kojto 122:f9eeca106725 2876 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 122:f9eeca106725 2877 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2878 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2879 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2880 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2881 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2882 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2883 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2884 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2885 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2886 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2887 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2888 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2889 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2890 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2891 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2892 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2893 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2894 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2895 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2896 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2897 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2898 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2899 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2900 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2901 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2902 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2903 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2904 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2905 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2906 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2907 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2908 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2909
Kojto 122:f9eeca106725 2910 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 122:f9eeca106725 2911 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2912 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2913 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2914 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2915 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2916 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2917 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2918 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2919 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2920 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2921 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2922 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2923 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2924 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2925 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2926 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2927 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2928 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2929 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2930 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2931 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2932 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2933 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2934 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2935 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2936 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2937 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2938 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2939 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2940 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2941 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2942 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2943
Kojto 122:f9eeca106725 2944 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 122:f9eeca106725 2945 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2946 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2947 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2948 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2949 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2950 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2951 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2952 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2953 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2954 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2955 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2956 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2957 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2958 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2959 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2960 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2961 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2962 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2963 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2964 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2965 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 2966 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 2967 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 2968 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 2969 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 2970 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 2971 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 2972 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 2973 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 2974 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 2975 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 2976 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 2977
Kojto 122:f9eeca106725 2978 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 122:f9eeca106725 2979 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 2980 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 2981 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 2982 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 2983 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 2984 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 2985 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 2986 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 2987 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 2988 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 2989 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 2990 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 2991 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 2992 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 2993 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 2994 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 2995 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 2996 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 2997 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 2998 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 2999 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3000 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3001 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3002 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3003 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3004 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3005 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3006 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3007 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3008 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3009 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3010 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3011
Kojto 122:f9eeca106725 3012 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 122:f9eeca106725 3013 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3014 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3015 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3016 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3017 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3018 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3019 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3020 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3021 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3022 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3023 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3024 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3025 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3026 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3027 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3028 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3029 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3030 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3031 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3032 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3033 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3034 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3035 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3036 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3037 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3038 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3039 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3040 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3041 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3042 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3043 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3044 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3045
Kojto 122:f9eeca106725 3046 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 122:f9eeca106725 3047 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3048 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3049 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3050 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3051 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3052 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3053 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3054 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3055 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3056 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3057 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3058 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3059 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3060 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3061 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3062 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3063 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3064 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3065 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3066 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3067 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3068 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3069 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3070 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3071 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3072 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3073 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3074 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3075 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3076 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3077 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3078 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3079
Kojto 122:f9eeca106725 3080 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 122:f9eeca106725 3081 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3082 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3083 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3084 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3085 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3086 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3087 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3088 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3089 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3090 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3091 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3092 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3093 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3094 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3095 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3096 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3097 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3098 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3099 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3100 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3101 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3102 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3103 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3104 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3105 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3106 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3107 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3108 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3109 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3110 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3111 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3112 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3113
Kojto 122:f9eeca106725 3114 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 122:f9eeca106725 3115 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3116 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3117 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3118 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3119 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3120 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3121 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3122 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3123 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3124 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3125 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3126 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3127 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3128 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3129 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3130 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3131 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3132 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3133 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3134 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3135 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3136 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3137 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3138 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3139 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3140 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3141 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3142 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3143 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3144 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3145 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3146 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3147
Kojto 122:f9eeca106725 3148 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 122:f9eeca106725 3149 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3150 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3151 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3152 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3153 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3154 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3155 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3156 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3157 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3158 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3159 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3160 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3161 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3162 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3163 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3164 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3165 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3166 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3167 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3168 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3169 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3170 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3171 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3172 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3173 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3174 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3175 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3176 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3177 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3178 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3179 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3180 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3181
Kojto 122:f9eeca106725 3182 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 122:f9eeca106725 3183 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3184 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3185 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3186 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3187 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3188 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3189 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3190 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3191 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3192 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3193 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3194 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3195 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3196 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3197 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3198 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3199 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3200 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3201 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3202 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3203 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3204 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3205 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3206 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3207 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3208 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3209 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3210 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3211 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3212 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3213 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3214 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3215
Kojto 122:f9eeca106725 3216 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 122:f9eeca106725 3217 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
Kojto 122:f9eeca106725 3218 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
Kojto 122:f9eeca106725 3219 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
Kojto 122:f9eeca106725 3220 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
Kojto 122:f9eeca106725 3221 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
Kojto 122:f9eeca106725 3222 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
Kojto 122:f9eeca106725 3223 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
Kojto 122:f9eeca106725 3224 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
Kojto 122:f9eeca106725 3225 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
Kojto 122:f9eeca106725 3226 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
Kojto 122:f9eeca106725 3227 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
Kojto 122:f9eeca106725 3228 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
Kojto 122:f9eeca106725 3229 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
Kojto 122:f9eeca106725 3230 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
Kojto 122:f9eeca106725 3231 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
Kojto 122:f9eeca106725 3232 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
Kojto 122:f9eeca106725 3233 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
Kojto 122:f9eeca106725 3234 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
Kojto 122:f9eeca106725 3235 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
Kojto 122:f9eeca106725 3236 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
Kojto 122:f9eeca106725 3237 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
Kojto 122:f9eeca106725 3238 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
Kojto 122:f9eeca106725 3239 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
Kojto 122:f9eeca106725 3240 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
Kojto 122:f9eeca106725 3241 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
Kojto 122:f9eeca106725 3242 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
Kojto 122:f9eeca106725 3243 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
Kojto 122:f9eeca106725 3244 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
Kojto 122:f9eeca106725 3245 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
Kojto 122:f9eeca106725 3246 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
Kojto 122:f9eeca106725 3247 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
Kojto 122:f9eeca106725 3248 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
Kojto 122:f9eeca106725 3249
Kojto 122:f9eeca106725 3250 /******************************************************************************/
Kojto 122:f9eeca106725 3251 /* */
Kojto 122:f9eeca106725 3252 /* HDMI-CEC (CEC) */
Kojto 122:f9eeca106725 3253 /* */
Kojto 122:f9eeca106725 3254 /******************************************************************************/
Kojto 122:f9eeca106725 3255
Kojto 122:f9eeca106725 3256 /******************* Bit definition for CEC_CR register *********************/
Kojto 122:f9eeca106725 3257 #define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */
Kojto 122:f9eeca106725 3258 #define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */
Kojto 122:f9eeca106725 3259 #define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */
Kojto 122:f9eeca106725 3260
Kojto 122:f9eeca106725 3261 /******************* Bit definition for CEC_CFGR register *******************/
Kojto 122:f9eeca106725 3262 #define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */
Kojto 122:f9eeca106725 3263 #define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */
Kojto 122:f9eeca106725 3264 #define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */
Kojto 122:f9eeca106725 3265 #define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */
Kojto 122:f9eeca106725 3266 #define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Period Error generation */
Kojto 122:f9eeca106725 3267 #define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast no Error generation */
Kojto 122:f9eeca106725 3268 #define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */
Kojto 122:f9eeca106725 3269 #define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */
Kojto 122:f9eeca106725 3270 #define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */
Kojto 122:f9eeca106725 3271
Kojto 122:f9eeca106725 3272 /******************* Bit definition for CEC_TXDR register *******************/
Kojto 122:f9eeca106725 3273 #define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */
Kojto 122:f9eeca106725 3274
Kojto 122:f9eeca106725 3275 /******************* Bit definition for CEC_RXDR register *******************/
Kojto 122:f9eeca106725 3276 #define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */
Kojto 122:f9eeca106725 3277
Kojto 122:f9eeca106725 3278 /******************* Bit definition for CEC_ISR register ********************/
Kojto 122:f9eeca106725 3279 #define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */
Kojto 122:f9eeca106725 3280 #define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */
Kojto 122:f9eeca106725 3281 #define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */
Kojto 122:f9eeca106725 3282 #define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */
Kojto 122:f9eeca106725 3283 #define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */
Kojto 122:f9eeca106725 3284 #define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */
Kojto 122:f9eeca106725 3285 #define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */
Kojto 122:f9eeca106725 3286 #define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */
Kojto 122:f9eeca106725 3287 #define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */
Kojto 122:f9eeca106725 3288 #define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */
Kojto 122:f9eeca106725 3289 #define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */
Kojto 122:f9eeca106725 3290 #define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */
Kojto 122:f9eeca106725 3291 #define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */
Kojto 122:f9eeca106725 3292
Kojto 122:f9eeca106725 3293 /******************* Bit definition for CEC_IER register ********************/
Kojto 122:f9eeca106725 3294 #define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */
Kojto 122:f9eeca106725 3295 #define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */
Kojto 122:f9eeca106725 3296 #define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */
Kojto 122:f9eeca106725 3297 #define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */
Kojto 122:f9eeca106725 3298 #define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable*/
Kojto 122:f9eeca106725 3299 #define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */
Kojto 122:f9eeca106725 3300 #define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */
Kojto 122:f9eeca106725 3301 #define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */
Kojto 122:f9eeca106725 3302 #define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */
Kojto 122:f9eeca106725 3303 #define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */
Kojto 122:f9eeca106725 3304 #define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */
Kojto 122:f9eeca106725 3305 #define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */
Kojto 122:f9eeca106725 3306 #define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */
Kojto 122:f9eeca106725 3307
Kojto 122:f9eeca106725 3308 /******************************************************************************/
Kojto 122:f9eeca106725 3309 /* */
Kojto 122:f9eeca106725 3310 /* CRC calculation unit */
Kojto 122:f9eeca106725 3311 /* */
Kojto 122:f9eeca106725 3312 /******************************************************************************/
Kojto 122:f9eeca106725 3313 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 3314 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
Kojto 122:f9eeca106725 3315
Kojto 122:f9eeca106725 3316 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 3317 #define CRC_IDR_IDR 0x000000FFU /*!< General-purpose 8-bit data register bits */
Kojto 122:f9eeca106725 3318
Kojto 122:f9eeca106725 3319 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 3320 #define CRC_CR_RESET 0x00000001U /*!< RESET the CRC computation unit bit */
Kojto 122:f9eeca106725 3321 #define CRC_CR_POLYSIZE 0x00000018U /*!< Polynomial size bits */
Kojto 122:f9eeca106725 3322 #define CRC_CR_POLYSIZE_0 0x00000008U /*!< Polynomial size bit 0 */
Kojto 122:f9eeca106725 3323 #define CRC_CR_POLYSIZE_1 0x00000010U /*!< Polynomial size bit 1 */
Kojto 122:f9eeca106725 3324 #define CRC_CR_REV_IN 0x00000060U /*!< REV_IN Reverse Input Data bits */
Kojto 122:f9eeca106725 3325 #define CRC_CR_REV_IN_0 0x00000020U /*!< Bit 0 */
Kojto 122:f9eeca106725 3326 #define CRC_CR_REV_IN_1 0x00000040U /*!< Bit 1 */
Kojto 122:f9eeca106725 3327 #define CRC_CR_REV_OUT 0x00000080U /*!< REV_OUT Reverse Output Data bits */
Kojto 122:f9eeca106725 3328
Kojto 122:f9eeca106725 3329 /******************* Bit definition for CRC_INIT register *******************/
Kojto 122:f9eeca106725 3330 #define CRC_INIT_INIT 0xFFFFFFFFU /*!< Initial CRC value bits */
Kojto 122:f9eeca106725 3331
Kojto 122:f9eeca106725 3332 /******************* Bit definition for CRC_POL register ********************/
Kojto 122:f9eeca106725 3333 #define CRC_POL_POL 0xFFFFFFFFU /*!< Coefficients of the polynomial */
Kojto 122:f9eeca106725 3334
Kojto 122:f9eeca106725 3335
Kojto 122:f9eeca106725 3336 /******************************************************************************/
Kojto 122:f9eeca106725 3337 /* */
Kojto 122:f9eeca106725 3338 /* Digital to Analog Converter */
Kojto 122:f9eeca106725 3339 /* */
Kojto 122:f9eeca106725 3340 /******************************************************************************/
Kojto 122:f9eeca106725 3341 /******************** Bit definition for DAC_CR register ********************/
Kojto 122:f9eeca106725 3342 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
Kojto 122:f9eeca106725 3343 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
Kojto 122:f9eeca106725 3344 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
Kojto 122:f9eeca106725 3345 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 122:f9eeca106725 3346 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 3347 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 3348 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 3349 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
Kojto 122:f9eeca106725 3350 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 3351 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 3352 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 3353 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 3354 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 3355 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 3356 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 3357 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
Kojto 122:f9eeca106725 3358 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable */
Kojto 122:f9eeca106725 3359 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
Kojto 122:f9eeca106725 3360 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
Kojto 122:f9eeca106725 3361 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
Kojto 122:f9eeca106725 3362 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 122:f9eeca106725 3363 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3364 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3365 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3366 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 122:f9eeca106725 3367 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3368 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3369 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 122:f9eeca106725 3370 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 3371 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 3372 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 3373 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 3374 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enable */
Kojto 122:f9eeca106725 3375 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable */
Kojto 122:f9eeca106725 3376
Kojto 122:f9eeca106725 3377 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 122:f9eeca106725 3378 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
Kojto 122:f9eeca106725 3379 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
Kojto 122:f9eeca106725 3380
Kojto 122:f9eeca106725 3381 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 122:f9eeca106725 3382 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 3383
Kojto 122:f9eeca106725 3384 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 122:f9eeca106725 3385 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 3386
Kojto 122:f9eeca106725 3387 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 122:f9eeca106725 3388 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 3389
Kojto 122:f9eeca106725 3390 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 122:f9eeca106725 3391 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
Kojto 122:f9eeca106725 3392
Kojto 122:f9eeca106725 3393 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 122:f9eeca106725 3394 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
Kojto 122:f9eeca106725 3395
Kojto 122:f9eeca106725 3396 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 122:f9eeca106725 3397 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
Kojto 122:f9eeca106725 3398
Kojto 122:f9eeca106725 3399 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 122:f9eeca106725 3400 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
Kojto 122:f9eeca106725 3401 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
Kojto 122:f9eeca106725 3402
Kojto 122:f9eeca106725 3403 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 122:f9eeca106725 3404 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
Kojto 122:f9eeca106725 3405 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
Kojto 122:f9eeca106725 3406
Kojto 122:f9eeca106725 3407 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 122:f9eeca106725 3408 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
Kojto 122:f9eeca106725 3409 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
Kojto 122:f9eeca106725 3410
Kojto 122:f9eeca106725 3411 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 122:f9eeca106725 3412 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
Kojto 122:f9eeca106725 3413
Kojto 122:f9eeca106725 3414 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 122:f9eeca106725 3415 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
Kojto 122:f9eeca106725 3416
Kojto 122:f9eeca106725 3417 /******************** Bit definition for DAC_SR register ********************/
Kojto 122:f9eeca106725 3418 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
Kojto 122:f9eeca106725 3419 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
Kojto 122:f9eeca106725 3420
Kojto 122:f9eeca106725 3421 /******************************************************************************/
Kojto 122:f9eeca106725 3422 /* */
Kojto 122:f9eeca106725 3423 /* Digital Filter for Sigma Delta Modulators */
Kojto 122:f9eeca106725 3424 /* */
Kojto 122:f9eeca106725 3425 /******************************************************************************/
Kojto 122:f9eeca106725 3426
Kojto 122:f9eeca106725 3427 /**************** DFSDM channel configuration registers ********************/
Kojto 122:f9eeca106725 3428
Kojto 122:f9eeca106725 3429 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
Kojto 122:f9eeca106725 3430 #define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
Kojto 122:f9eeca106725 3431 #define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
Kojto 122:f9eeca106725 3432 #define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
Kojto 122:f9eeca106725 3433 #define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
Kojto 122:f9eeca106725 3434 #define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
Kojto 122:f9eeca106725 3435 #define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
Kojto 122:f9eeca106725 3436 #define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
Kojto 122:f9eeca106725 3437 #define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
Kojto 122:f9eeca106725 3438 #define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
Kojto 122:f9eeca106725 3439 #define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
Kojto 122:f9eeca106725 3440 #define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
Kojto 122:f9eeca106725 3441 #define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
Kojto 122:f9eeca106725 3442 #define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
Kojto 122:f9eeca106725 3443 #define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
Kojto 122:f9eeca106725 3444 #define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
Kojto 122:f9eeca106725 3445 #define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
Kojto 122:f9eeca106725 3446 #define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
Kojto 122:f9eeca106725 3447 #define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
Kojto 122:f9eeca106725 3448 #define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
Kojto 122:f9eeca106725 3449
Kojto 122:f9eeca106725 3450 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
Kojto 122:f9eeca106725 3451 #define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
Kojto 122:f9eeca106725 3452 #define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
Kojto 122:f9eeca106725 3453
Kojto 122:f9eeca106725 3454 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
Kojto 122:f9eeca106725 3455 #define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
Kojto 122:f9eeca106725 3456 #define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
Kojto 122:f9eeca106725 3457 #define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
Kojto 122:f9eeca106725 3458 #define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
Kojto 122:f9eeca106725 3459 #define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
Kojto 122:f9eeca106725 3460 #define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
Kojto 122:f9eeca106725 3461
Kojto 122:f9eeca106725 3462 /**************** Bit definition for DFSDM_CHWDATR register *******************/
Kojto 122:f9eeca106725 3463 #define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
Kojto 122:f9eeca106725 3464
Kojto 122:f9eeca106725 3465 /**************** Bit definition for DFSDM_CHDATINR register *****************/
Kojto 122:f9eeca106725 3466 #define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
Kojto 122:f9eeca106725 3467 #define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
Kojto 122:f9eeca106725 3468
Kojto 122:f9eeca106725 3469 /************************ DFSDM module registers ****************************/
Kojto 122:f9eeca106725 3470
Kojto 122:f9eeca106725 3471 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
Kojto 122:f9eeca106725 3472 #define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
Kojto 122:f9eeca106725 3473 #define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
Kojto 122:f9eeca106725 3474 #define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
Kojto 122:f9eeca106725 3475 #define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
Kojto 122:f9eeca106725 3476 #define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
Kojto 122:f9eeca106725 3477 #define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
Kojto 122:f9eeca106725 3478 #define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
Kojto 122:f9eeca106725 3479 #define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
Kojto 122:f9eeca106725 3480 #define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
Kojto 122:f9eeca106725 3481 #define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
Kojto 122:f9eeca106725 3482 #define DFSDM_FLTCR1_JEXTSEL 0x00001F00U /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
Kojto 122:f9eeca106725 3483 #define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
Kojto 122:f9eeca106725 3484 #define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
Kojto 122:f9eeca106725 3485 #define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
Kojto 122:f9eeca106725 3486 #define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U /*!< Trigger signal selection for launching injected conversions, Bit 3 */
Kojto 122:f9eeca106725 3487 #define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U /*!< Trigger signal selection for launching injected conversions, Bit 4 */
Kojto 122:f9eeca106725 3488 #define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
Kojto 122:f9eeca106725 3489 #define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
Kojto 122:f9eeca106725 3490 #define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
Kojto 122:f9eeca106725 3491 #define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
Kojto 122:f9eeca106725 3492 #define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
Kojto 122:f9eeca106725 3493
Kojto 122:f9eeca106725 3494 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
Kojto 122:f9eeca106725 3495 #define DFSDM_FLTCR2_AWDCH 0x00FF0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
Kojto 122:f9eeca106725 3496 #define DFSDM_FLTCR2_EXCH 0x0000FF00U /*!< EXCH[7:0] Extreme detector channel selection */
Kojto 122:f9eeca106725 3497 #define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
Kojto 122:f9eeca106725 3498 #define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
Kojto 122:f9eeca106725 3499 #define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
Kojto 122:f9eeca106725 3500 #define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
Kojto 122:f9eeca106725 3501 #define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
Kojto 122:f9eeca106725 3502 #define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
Kojto 122:f9eeca106725 3503 #define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
Kojto 122:f9eeca106725 3504
Kojto 122:f9eeca106725 3505 /******************** Bit definition for DFSDM_FLTISR register *******************/
Kojto 122:f9eeca106725 3506 #define DFSDM_FLTISR_SCDF 0xFF000000U /*!< SCDF[7:0] Short circuit detector flag */
Kojto 122:f9eeca106725 3507 #define DFSDM_FLTISR_CKABF 0x00FF0000U /*!< CKABF[7:0] Clock absence flag */
Kojto 122:f9eeca106725 3508 #define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
Kojto 122:f9eeca106725 3509 #define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
Kojto 122:f9eeca106725 3510 #define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
Kojto 122:f9eeca106725 3511 #define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
Kojto 122:f9eeca106725 3512 #define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
Kojto 122:f9eeca106725 3513 #define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
Kojto 122:f9eeca106725 3514 #define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
Kojto 122:f9eeca106725 3515
Kojto 122:f9eeca106725 3516 /******************** Bit definition for DFSDM_FLTICR register *******************/
Kojto 122:f9eeca106725 3517 #define DFSDM_FLTICR_CLRSCSDF 0xFF000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
Kojto 122:f9eeca106725 3518 #define DFSDM_FLTICR_CLRCKABF 0x00FF0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
Kojto 122:f9eeca106725 3519 #define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
Kojto 122:f9eeca106725 3520 #define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
Kojto 122:f9eeca106725 3521
Kojto 122:f9eeca106725 3522 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
Kojto 122:f9eeca106725 3523 #define DFSDM_FLTJCHGR_JCHG 0x000000FFU /*!< JCHG[7:0] Injected channel group selection */
Kojto 122:f9eeca106725 3524
Kojto 122:f9eeca106725 3525 /******************** Bit definition for DFSDM_FLTFCR register *******************/
Kojto 122:f9eeca106725 3526 #define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
Kojto 122:f9eeca106725 3527 #define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
Kojto 122:f9eeca106725 3528 #define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
Kojto 122:f9eeca106725 3529 #define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
Kojto 122:f9eeca106725 3530 #define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
Kojto 122:f9eeca106725 3531 #define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
Kojto 122:f9eeca106725 3532
Kojto 122:f9eeca106725 3533 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
Kojto 122:f9eeca106725 3534 #define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
Kojto 122:f9eeca106725 3535 #define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
Kojto 122:f9eeca106725 3536
Kojto 122:f9eeca106725 3537 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
Kojto 122:f9eeca106725 3538 #define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
Kojto 122:f9eeca106725 3539 #define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
Kojto 122:f9eeca106725 3540 #define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
Kojto 122:f9eeca106725 3541
Kojto 122:f9eeca106725 3542 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
Kojto 122:f9eeca106725 3543 #define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
Kojto 122:f9eeca106725 3544 #define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
Kojto 122:f9eeca106725 3545
Kojto 122:f9eeca106725 3546 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
Kojto 122:f9eeca106725 3547 #define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
Kojto 122:f9eeca106725 3548 #define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
Kojto 122:f9eeca106725 3549
Kojto 122:f9eeca106725 3550 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
Kojto 122:f9eeca106725 3551 #define DFSDM_FLTAWSR_AWHTF 0x0000FF00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
Kojto 122:f9eeca106725 3552 #define DFSDM_FLTAWSR_AWLTF 0x000000FFU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
Kojto 122:f9eeca106725 3553
Kojto 122:f9eeca106725 3554 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
Kojto 122:f9eeca106725 3555 #define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
Kojto 122:f9eeca106725 3556 #define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
Kojto 122:f9eeca106725 3557
Kojto 122:f9eeca106725 3558 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
Kojto 122:f9eeca106725 3559 #define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
Kojto 122:f9eeca106725 3560 #define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
Kojto 122:f9eeca106725 3561
Kojto 122:f9eeca106725 3562 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
Kojto 122:f9eeca106725 3563 #define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
Kojto 122:f9eeca106725 3564 #define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
Kojto 122:f9eeca106725 3565
Kojto 122:f9eeca106725 3566 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
Kojto 122:f9eeca106725 3567 #define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
Kojto 122:f9eeca106725 3568
Kojto 122:f9eeca106725 3569 /******************************************************************************/
Kojto 122:f9eeca106725 3570 /* */
Kojto 122:f9eeca106725 3571 /* Debug MCU */
Kojto 122:f9eeca106725 3572 /* */
Kojto 122:f9eeca106725 3573 /******************************************************************************/
Kojto 122:f9eeca106725 3574
Kojto 122:f9eeca106725 3575 /******************************************************************************/
Kojto 122:f9eeca106725 3576 /* */
Kojto 122:f9eeca106725 3577 /* DCMI */
Kojto 122:f9eeca106725 3578 /* */
Kojto 122:f9eeca106725 3579 /******************************************************************************/
Kojto 122:f9eeca106725 3580 /******************** Bits definition for DCMI_CR register ******************/
Kojto 122:f9eeca106725 3581 #define DCMI_CR_CAPTURE 0x00000001U
Kojto 122:f9eeca106725 3582 #define DCMI_CR_CM 0x00000002U
Kojto 122:f9eeca106725 3583 #define DCMI_CR_CROP 0x00000004U
Kojto 122:f9eeca106725 3584 #define DCMI_CR_JPEG 0x00000008U
Kojto 122:f9eeca106725 3585 #define DCMI_CR_ESS 0x00000010U
Kojto 122:f9eeca106725 3586 #define DCMI_CR_PCKPOL 0x00000020U
Kojto 122:f9eeca106725 3587 #define DCMI_CR_HSPOL 0x00000040U
Kojto 122:f9eeca106725 3588 #define DCMI_CR_VSPOL 0x00000080U
Kojto 122:f9eeca106725 3589 #define DCMI_CR_FCRC_0 0x00000100U
Kojto 122:f9eeca106725 3590 #define DCMI_CR_FCRC_1 0x00000200U
Kojto 122:f9eeca106725 3591 #define DCMI_CR_EDM_0 0x00000400U
Kojto 122:f9eeca106725 3592 #define DCMI_CR_EDM_1 0x00000800U
Kojto 122:f9eeca106725 3593 #define DCMI_CR_CRE 0x00001000U
Kojto 122:f9eeca106725 3594 #define DCMI_CR_ENABLE 0x00004000U
Kojto 122:f9eeca106725 3595 #define DCMI_CR_BSM 0x00030000U
Kojto 122:f9eeca106725 3596 #define DCMI_CR_BSM_0 0x00010000U
Kojto 122:f9eeca106725 3597 #define DCMI_CR_BSM_1 0x00020000U
Kojto 122:f9eeca106725 3598 #define DCMI_CR_OEBS 0x00040000U
Kojto 122:f9eeca106725 3599 #define DCMI_CR_LSM 0x00080000U
Kojto 122:f9eeca106725 3600 #define DCMI_CR_OELS 0x00100000U
Kojto 122:f9eeca106725 3601
Kojto 122:f9eeca106725 3602 /******************** Bits definition for DCMI_SR register ******************/
Kojto 122:f9eeca106725 3603 #define DCMI_SR_HSYNC 0x00000001U
Kojto 122:f9eeca106725 3604 #define DCMI_SR_VSYNC 0x00000002U
Kojto 122:f9eeca106725 3605 #define DCMI_SR_FNE 0x00000004U
Kojto 122:f9eeca106725 3606
Kojto 122:f9eeca106725 3607 /******************** Bits definition for DCMI_RIS register ****************/
Kojto 122:f9eeca106725 3608 #define DCMI_RIS_FRAME_RIS 0x00000001U
Kojto 122:f9eeca106725 3609 #define DCMI_RIS_OVR_RIS 0x00000002U
Kojto 122:f9eeca106725 3610 #define DCMI_RIS_ERR_RIS 0x00000004U
Kojto 122:f9eeca106725 3611 #define DCMI_RIS_VSYNC_RIS 0x00000008U
Kojto 122:f9eeca106725 3612 #define DCMI_RIS_LINE_RIS 0x00000010U
Kojto 122:f9eeca106725 3613
Kojto 122:f9eeca106725 3614 /* Legacy defines */
Kojto 122:f9eeca106725 3615 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
Kojto 122:f9eeca106725 3616 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
Kojto 122:f9eeca106725 3617 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
Kojto 122:f9eeca106725 3618 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
Kojto 122:f9eeca106725 3619 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
Kojto 122:f9eeca106725 3620
Kojto 122:f9eeca106725 3621 /******************** Bits definition for DCMI_IER register *****************/
Kojto 122:f9eeca106725 3622 #define DCMI_IER_FRAME_IE 0x00000001U
Kojto 122:f9eeca106725 3623 #define DCMI_IER_OVR_IE 0x00000002U
Kojto 122:f9eeca106725 3624 #define DCMI_IER_ERR_IE 0x00000004U
Kojto 122:f9eeca106725 3625 #define DCMI_IER_VSYNC_IE 0x00000008U
Kojto 122:f9eeca106725 3626 #define DCMI_IER_LINE_IE 0x00000010U
Kojto 122:f9eeca106725 3627
Kojto 122:f9eeca106725 3628
Kojto 122:f9eeca106725 3629 /******************** Bits definition for DCMI_MIS register *****************/
Kojto 122:f9eeca106725 3630 #define DCMI_MIS_FRAME_MIS 0x00000001U
Kojto 122:f9eeca106725 3631 #define DCMI_MIS_OVR_MIS 0x00000002U
Kojto 122:f9eeca106725 3632 #define DCMI_MIS_ERR_MIS 0x00000004U
Kojto 122:f9eeca106725 3633 #define DCMI_MIS_VSYNC_MIS 0x00000008U
Kojto 122:f9eeca106725 3634 #define DCMI_MIS_LINE_MIS 0x00000010U
Kojto 122:f9eeca106725 3635
Kojto 122:f9eeca106725 3636
Kojto 122:f9eeca106725 3637 /******************** Bits definition for DCMI_ICR register *****************/
Kojto 122:f9eeca106725 3638 #define DCMI_ICR_FRAME_ISC 0x00000001U
Kojto 122:f9eeca106725 3639 #define DCMI_ICR_OVR_ISC 0x00000002U
Kojto 122:f9eeca106725 3640 #define DCMI_ICR_ERR_ISC 0x00000004U
Kojto 122:f9eeca106725 3641 #define DCMI_ICR_VSYNC_ISC 0x00000008U
Kojto 122:f9eeca106725 3642 #define DCMI_ICR_LINE_ISC 0x00000010U
Kojto 122:f9eeca106725 3643
Kojto 122:f9eeca106725 3644
Kojto 122:f9eeca106725 3645 /******************** Bits definition for DCMI_ESCR register ******************/
Kojto 122:f9eeca106725 3646 #define DCMI_ESCR_FSC 0x000000FFU
Kojto 122:f9eeca106725 3647 #define DCMI_ESCR_LSC 0x0000FF00U
Kojto 122:f9eeca106725 3648 #define DCMI_ESCR_LEC 0x00FF0000U
Kojto 122:f9eeca106725 3649 #define DCMI_ESCR_FEC 0xFF000000U
Kojto 122:f9eeca106725 3650
Kojto 122:f9eeca106725 3651 /******************** Bits definition for DCMI_ESUR register ******************/
Kojto 122:f9eeca106725 3652 #define DCMI_ESUR_FSU 0x000000FFU
Kojto 122:f9eeca106725 3653 #define DCMI_ESUR_LSU 0x0000FF00U
Kojto 122:f9eeca106725 3654 #define DCMI_ESUR_LEU 0x00FF0000U
Kojto 122:f9eeca106725 3655 #define DCMI_ESUR_FEU 0xFF000000U
Kojto 122:f9eeca106725 3656
Kojto 122:f9eeca106725 3657 /******************** Bits definition for DCMI_CWSTRT register ******************/
Kojto 122:f9eeca106725 3658 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
Kojto 122:f9eeca106725 3659 #define DCMI_CWSTRT_VST 0x1FFF0000U
Kojto 122:f9eeca106725 3660
Kojto 122:f9eeca106725 3661 /******************** Bits definition for DCMI_CWSIZE register ******************/
Kojto 122:f9eeca106725 3662 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
Kojto 122:f9eeca106725 3663 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
Kojto 122:f9eeca106725 3664
Kojto 122:f9eeca106725 3665 /******************** Bits definition for DCMI_DR register ******************/
Kojto 122:f9eeca106725 3666 #define DCMI_DR_BYTE0 0x000000FFU
Kojto 122:f9eeca106725 3667 #define DCMI_DR_BYTE1 0x0000FF00U
Kojto 122:f9eeca106725 3668 #define DCMI_DR_BYTE2 0x00FF0000U
Kojto 122:f9eeca106725 3669 #define DCMI_DR_BYTE3 0xFF000000U
Kojto 122:f9eeca106725 3670
Kojto 122:f9eeca106725 3671 /******************************************************************************/
Kojto 122:f9eeca106725 3672 /* */
Kojto 122:f9eeca106725 3673 /* DMA Controller */
Kojto 122:f9eeca106725 3674 /* */
Kojto 122:f9eeca106725 3675 /******************************************************************************/
Kojto 122:f9eeca106725 3676 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 122:f9eeca106725 3677 #define DMA_SxCR_CHSEL 0x1E000000U
Kojto 122:f9eeca106725 3678 #define DMA_SxCR_CHSEL_0 0x02000000U
Kojto 122:f9eeca106725 3679 #define DMA_SxCR_CHSEL_1 0x04000000U
Kojto 122:f9eeca106725 3680 #define DMA_SxCR_CHSEL_2 0x08000000U
Kojto 122:f9eeca106725 3681 #define DMA_SxCR_CHSEL_3 0x10000000U
Kojto 122:f9eeca106725 3682 #define DMA_SxCR_MBURST 0x01800000U
Kojto 122:f9eeca106725 3683 #define DMA_SxCR_MBURST_0 0x00800000U
Kojto 122:f9eeca106725 3684 #define DMA_SxCR_MBURST_1 0x01000000U
Kojto 122:f9eeca106725 3685 #define DMA_SxCR_PBURST 0x00600000U
Kojto 122:f9eeca106725 3686 #define DMA_SxCR_PBURST_0 0x00200000U
Kojto 122:f9eeca106725 3687 #define DMA_SxCR_PBURST_1 0x00400000U
Kojto 122:f9eeca106725 3688 #define DMA_SxCR_CT 0x00080000U
Kojto 122:f9eeca106725 3689 #define DMA_SxCR_DBM 0x00040000U
Kojto 122:f9eeca106725 3690 #define DMA_SxCR_PL 0x00030000U
Kojto 122:f9eeca106725 3691 #define DMA_SxCR_PL_0 0x00010000U
Kojto 122:f9eeca106725 3692 #define DMA_SxCR_PL_1 0x00020000U
Kojto 122:f9eeca106725 3693 #define DMA_SxCR_PINCOS 0x00008000U
Kojto 122:f9eeca106725 3694 #define DMA_SxCR_MSIZE 0x00006000U
Kojto 122:f9eeca106725 3695 #define DMA_SxCR_MSIZE_0 0x00002000U
Kojto 122:f9eeca106725 3696 #define DMA_SxCR_MSIZE_1 0x00004000U
Kojto 122:f9eeca106725 3697 #define DMA_SxCR_PSIZE 0x00001800U
Kojto 122:f9eeca106725 3698 #define DMA_SxCR_PSIZE_0 0x00000800U
Kojto 122:f9eeca106725 3699 #define DMA_SxCR_PSIZE_1 0x00001000U
Kojto 122:f9eeca106725 3700 #define DMA_SxCR_MINC 0x00000400U
Kojto 122:f9eeca106725 3701 #define DMA_SxCR_PINC 0x00000200U
Kojto 122:f9eeca106725 3702 #define DMA_SxCR_CIRC 0x00000100U
Kojto 122:f9eeca106725 3703 #define DMA_SxCR_DIR 0x000000C0U
Kojto 122:f9eeca106725 3704 #define DMA_SxCR_DIR_0 0x00000040U
Kojto 122:f9eeca106725 3705 #define DMA_SxCR_DIR_1 0x00000080U
Kojto 122:f9eeca106725 3706 #define DMA_SxCR_PFCTRL 0x00000020U
Kojto 122:f9eeca106725 3707 #define DMA_SxCR_TCIE 0x00000010U
Kojto 122:f9eeca106725 3708 #define DMA_SxCR_HTIE 0x00000008U
Kojto 122:f9eeca106725 3709 #define DMA_SxCR_TEIE 0x00000004U
Kojto 122:f9eeca106725 3710 #define DMA_SxCR_DMEIE 0x00000002U
Kojto 122:f9eeca106725 3711 #define DMA_SxCR_EN 0x00000001U
Kojto 122:f9eeca106725 3712
Kojto 122:f9eeca106725 3713 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 122:f9eeca106725 3714 #define DMA_SxNDT 0x0000FFFFU
Kojto 122:f9eeca106725 3715 #define DMA_SxNDT_0 0x00000001U
Kojto 122:f9eeca106725 3716 #define DMA_SxNDT_1 0x00000002U
Kojto 122:f9eeca106725 3717 #define DMA_SxNDT_2 0x00000004U
Kojto 122:f9eeca106725 3718 #define DMA_SxNDT_3 0x00000008U
Kojto 122:f9eeca106725 3719 #define DMA_SxNDT_4 0x00000010U
Kojto 122:f9eeca106725 3720 #define DMA_SxNDT_5 0x00000020U
Kojto 122:f9eeca106725 3721 #define DMA_SxNDT_6 0x00000040U
Kojto 122:f9eeca106725 3722 #define DMA_SxNDT_7 0x00000080U
Kojto 122:f9eeca106725 3723 #define DMA_SxNDT_8 0x00000100U
Kojto 122:f9eeca106725 3724 #define DMA_SxNDT_9 0x00000200U
Kojto 122:f9eeca106725 3725 #define DMA_SxNDT_10 0x00000400U
Kojto 122:f9eeca106725 3726 #define DMA_SxNDT_11 0x00000800U
Kojto 122:f9eeca106725 3727 #define DMA_SxNDT_12 0x00001000U
Kojto 122:f9eeca106725 3728 #define DMA_SxNDT_13 0x00002000U
Kojto 122:f9eeca106725 3729 #define DMA_SxNDT_14 0x00004000U
Kojto 122:f9eeca106725 3730 #define DMA_SxNDT_15 0x00008000U
Kojto 122:f9eeca106725 3731
Kojto 122:f9eeca106725 3732 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 122:f9eeca106725 3733 #define DMA_SxFCR_FEIE 0x00000080U
Kojto 122:f9eeca106725 3734 #define DMA_SxFCR_FS 0x00000038U
Kojto 122:f9eeca106725 3735 #define DMA_SxFCR_FS_0 0x00000008U
Kojto 122:f9eeca106725 3736 #define DMA_SxFCR_FS_1 0x00000010U
Kojto 122:f9eeca106725 3737 #define DMA_SxFCR_FS_2 0x00000020U
Kojto 122:f9eeca106725 3738 #define DMA_SxFCR_DMDIS 0x00000004U
Kojto 122:f9eeca106725 3739 #define DMA_SxFCR_FTH 0x00000003U
Kojto 122:f9eeca106725 3740 #define DMA_SxFCR_FTH_0 0x00000001U
Kojto 122:f9eeca106725 3741 #define DMA_SxFCR_FTH_1 0x00000002U
Kojto 122:f9eeca106725 3742
Kojto 122:f9eeca106725 3743 /******************** Bits definition for DMA_LISR register *****************/
Kojto 122:f9eeca106725 3744 #define DMA_LISR_TCIF3 0x08000000U
Kojto 122:f9eeca106725 3745 #define DMA_LISR_HTIF3 0x04000000U
Kojto 122:f9eeca106725 3746 #define DMA_LISR_TEIF3 0x02000000U
Kojto 122:f9eeca106725 3747 #define DMA_LISR_DMEIF3 0x01000000U
Kojto 122:f9eeca106725 3748 #define DMA_LISR_FEIF3 0x00400000U
Kojto 122:f9eeca106725 3749 #define DMA_LISR_TCIF2 0x00200000U
Kojto 122:f9eeca106725 3750 #define DMA_LISR_HTIF2 0x00100000U
Kojto 122:f9eeca106725 3751 #define DMA_LISR_TEIF2 0x00080000U
Kojto 122:f9eeca106725 3752 #define DMA_LISR_DMEIF2 0x00040000U
Kojto 122:f9eeca106725 3753 #define DMA_LISR_FEIF2 0x00010000U
Kojto 122:f9eeca106725 3754 #define DMA_LISR_TCIF1 0x00000800U
Kojto 122:f9eeca106725 3755 #define DMA_LISR_HTIF1 0x00000400U
Kojto 122:f9eeca106725 3756 #define DMA_LISR_TEIF1 0x00000200U
Kojto 122:f9eeca106725 3757 #define DMA_LISR_DMEIF1 0x00000100U
Kojto 122:f9eeca106725 3758 #define DMA_LISR_FEIF1 0x00000040U
Kojto 122:f9eeca106725 3759 #define DMA_LISR_TCIF0 0x00000020U
Kojto 122:f9eeca106725 3760 #define DMA_LISR_HTIF0 0x00000010U
Kojto 122:f9eeca106725 3761 #define DMA_LISR_TEIF0 0x00000008U
Kojto 122:f9eeca106725 3762 #define DMA_LISR_DMEIF0 0x00000004U
Kojto 122:f9eeca106725 3763 #define DMA_LISR_FEIF0 0x00000001U
Kojto 122:f9eeca106725 3764
Kojto 122:f9eeca106725 3765 /******************** Bits definition for DMA_HISR register *****************/
Kojto 122:f9eeca106725 3766 #define DMA_HISR_TCIF7 0x08000000U
Kojto 122:f9eeca106725 3767 #define DMA_HISR_HTIF7 0x04000000U
Kojto 122:f9eeca106725 3768 #define DMA_HISR_TEIF7 0x02000000U
Kojto 122:f9eeca106725 3769 #define DMA_HISR_DMEIF7 0x01000000U
Kojto 122:f9eeca106725 3770 #define DMA_HISR_FEIF7 0x00400000U
Kojto 122:f9eeca106725 3771 #define DMA_HISR_TCIF6 0x00200000U
Kojto 122:f9eeca106725 3772 #define DMA_HISR_HTIF6 0x00100000U
Kojto 122:f9eeca106725 3773 #define DMA_HISR_TEIF6 0x00080000U
Kojto 122:f9eeca106725 3774 #define DMA_HISR_DMEIF6 0x00040000U
Kojto 122:f9eeca106725 3775 #define DMA_HISR_FEIF6 0x00010000U
Kojto 122:f9eeca106725 3776 #define DMA_HISR_TCIF5 0x00000800U
Kojto 122:f9eeca106725 3777 #define DMA_HISR_HTIF5 0x00000400U
Kojto 122:f9eeca106725 3778 #define DMA_HISR_TEIF5 0x00000200U
Kojto 122:f9eeca106725 3779 #define DMA_HISR_DMEIF5 0x00000100U
Kojto 122:f9eeca106725 3780 #define DMA_HISR_FEIF5 0x00000040U
Kojto 122:f9eeca106725 3781 #define DMA_HISR_TCIF4 0x00000020U
Kojto 122:f9eeca106725 3782 #define DMA_HISR_HTIF4 0x00000010U
Kojto 122:f9eeca106725 3783 #define DMA_HISR_TEIF4 0x00000008U
Kojto 122:f9eeca106725 3784 #define DMA_HISR_DMEIF4 0x00000004U
Kojto 122:f9eeca106725 3785 #define DMA_HISR_FEIF4 0x00000001U
Kojto 122:f9eeca106725 3786
Kojto 122:f9eeca106725 3787 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 122:f9eeca106725 3788 #define DMA_LIFCR_CTCIF3 0x08000000U
Kojto 122:f9eeca106725 3789 #define DMA_LIFCR_CHTIF3 0x04000000U
Kojto 122:f9eeca106725 3790 #define DMA_LIFCR_CTEIF3 0x02000000U
Kojto 122:f9eeca106725 3791 #define DMA_LIFCR_CDMEIF3 0x01000000U
Kojto 122:f9eeca106725 3792 #define DMA_LIFCR_CFEIF3 0x00400000U
Kojto 122:f9eeca106725 3793 #define DMA_LIFCR_CTCIF2 0x00200000U
Kojto 122:f9eeca106725 3794 #define DMA_LIFCR_CHTIF2 0x00100000U
Kojto 122:f9eeca106725 3795 #define DMA_LIFCR_CTEIF2 0x00080000U
Kojto 122:f9eeca106725 3796 #define DMA_LIFCR_CDMEIF2 0x00040000U
Kojto 122:f9eeca106725 3797 #define DMA_LIFCR_CFEIF2 0x00010000U
Kojto 122:f9eeca106725 3798 #define DMA_LIFCR_CTCIF1 0x00000800U
Kojto 122:f9eeca106725 3799 #define DMA_LIFCR_CHTIF1 0x00000400U
Kojto 122:f9eeca106725 3800 #define DMA_LIFCR_CTEIF1 0x00000200U
Kojto 122:f9eeca106725 3801 #define DMA_LIFCR_CDMEIF1 0x00000100U
Kojto 122:f9eeca106725 3802 #define DMA_LIFCR_CFEIF1 0x00000040U
Kojto 122:f9eeca106725 3803 #define DMA_LIFCR_CTCIF0 0x00000020U
Kojto 122:f9eeca106725 3804 #define DMA_LIFCR_CHTIF0 0x00000010U
Kojto 122:f9eeca106725 3805 #define DMA_LIFCR_CTEIF0 0x00000008U
Kojto 122:f9eeca106725 3806 #define DMA_LIFCR_CDMEIF0 0x00000004U
Kojto 122:f9eeca106725 3807 #define DMA_LIFCR_CFEIF0 0x00000001U
Kojto 122:f9eeca106725 3808
Kojto 122:f9eeca106725 3809 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 122:f9eeca106725 3810 #define DMA_HIFCR_CTCIF7 0x08000000U
Kojto 122:f9eeca106725 3811 #define DMA_HIFCR_CHTIF7 0x04000000U
Kojto 122:f9eeca106725 3812 #define DMA_HIFCR_CTEIF7 0x02000000U
Kojto 122:f9eeca106725 3813 #define DMA_HIFCR_CDMEIF7 0x01000000U
Kojto 122:f9eeca106725 3814 #define DMA_HIFCR_CFEIF7 0x00400000U
Kojto 122:f9eeca106725 3815 #define DMA_HIFCR_CTCIF6 0x00200000U
Kojto 122:f9eeca106725 3816 #define DMA_HIFCR_CHTIF6 0x00100000U
Kojto 122:f9eeca106725 3817 #define DMA_HIFCR_CTEIF6 0x00080000U
Kojto 122:f9eeca106725 3818 #define DMA_HIFCR_CDMEIF6 0x00040000U
Kojto 122:f9eeca106725 3819 #define DMA_HIFCR_CFEIF6 0x00010000U
Kojto 122:f9eeca106725 3820 #define DMA_HIFCR_CTCIF5 0x00000800U
Kojto 122:f9eeca106725 3821 #define DMA_HIFCR_CHTIF5 0x00000400U
Kojto 122:f9eeca106725 3822 #define DMA_HIFCR_CTEIF5 0x00000200U
Kojto 122:f9eeca106725 3823 #define DMA_HIFCR_CDMEIF5 0x00000100U
Kojto 122:f9eeca106725 3824 #define DMA_HIFCR_CFEIF5 0x00000040U
Kojto 122:f9eeca106725 3825 #define DMA_HIFCR_CTCIF4 0x00000020U
Kojto 122:f9eeca106725 3826 #define DMA_HIFCR_CHTIF4 0x00000010U
Kojto 122:f9eeca106725 3827 #define DMA_HIFCR_CTEIF4 0x00000008U
Kojto 122:f9eeca106725 3828 #define DMA_HIFCR_CDMEIF4 0x00000004U
Kojto 122:f9eeca106725 3829 #define DMA_HIFCR_CFEIF4 0x00000001U
Kojto 122:f9eeca106725 3830
Kojto 122:f9eeca106725 3831 /******************************************************************************/
Kojto 122:f9eeca106725 3832 /* */
Kojto 122:f9eeca106725 3833 /* AHB Master DMA2D Controller (DMA2D) */
Kojto 122:f9eeca106725 3834 /* */
Kojto 122:f9eeca106725 3835 /******************************************************************************/
Kojto 122:f9eeca106725 3836
Kojto 122:f9eeca106725 3837 /******************** Bit definition for DMA2D_CR register ******************/
Kojto 122:f9eeca106725 3838
Kojto 122:f9eeca106725 3839 #define DMA2D_CR_START 0x00000001U /*!< Start transfer */
Kojto 122:f9eeca106725 3840 #define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
Kojto 122:f9eeca106725 3841 #define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
Kojto 122:f9eeca106725 3842 #define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
Kojto 122:f9eeca106725 3843 #define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
Kojto 122:f9eeca106725 3844 #define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
Kojto 122:f9eeca106725 3845 #define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
Kojto 122:f9eeca106725 3846 #define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
Kojto 122:f9eeca106725 3847 #define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
Kojto 122:f9eeca106725 3848 #define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
Kojto 122:f9eeca106725 3849 #define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
Kojto 122:f9eeca106725 3850 #define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
Kojto 122:f9eeca106725 3851
Kojto 122:f9eeca106725 3852 /******************** Bit definition for DMA2D_ISR register *****************/
Kojto 122:f9eeca106725 3853
Kojto 122:f9eeca106725 3854 #define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
Kojto 122:f9eeca106725 3855 #define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
Kojto 122:f9eeca106725 3856 #define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
Kojto 122:f9eeca106725 3857 #define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
Kojto 122:f9eeca106725 3858 #define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
Kojto 122:f9eeca106725 3859 #define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
Kojto 122:f9eeca106725 3860
Kojto 122:f9eeca106725 3861 /******************** Bit definition for DMA2D_IFCR register ****************/
Kojto 122:f9eeca106725 3862
Kojto 122:f9eeca106725 3863 #define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
Kojto 122:f9eeca106725 3864 #define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
Kojto 122:f9eeca106725 3865 #define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
Kojto 122:f9eeca106725 3866 #define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
Kojto 122:f9eeca106725 3867 #define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
Kojto 122:f9eeca106725 3868 #define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
Kojto 122:f9eeca106725 3869
Kojto 122:f9eeca106725 3870 /* Legacy defines */
Kojto 122:f9eeca106725 3871 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
Kojto 122:f9eeca106725 3872 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
Kojto 122:f9eeca106725 3873 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
Kojto 122:f9eeca106725 3874 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
Kojto 122:f9eeca106725 3875 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
Kojto 122:f9eeca106725 3876 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
Kojto 122:f9eeca106725 3877
Kojto 122:f9eeca106725 3878 /******************** Bit definition for DMA2D_FGMAR register ***************/
Kojto 122:f9eeca106725 3879
Kojto 122:f9eeca106725 3880 #define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
Kojto 122:f9eeca106725 3881
Kojto 122:f9eeca106725 3882 /******************** Bit definition for DMA2D_FGOR register ****************/
Kojto 122:f9eeca106725 3883
Kojto 122:f9eeca106725 3884 #define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
Kojto 122:f9eeca106725 3885
Kojto 122:f9eeca106725 3886 /******************** Bit definition for DMA2D_BGMAR register ***************/
Kojto 122:f9eeca106725 3887
Kojto 122:f9eeca106725 3888 #define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
Kojto 122:f9eeca106725 3889
Kojto 122:f9eeca106725 3890 /******************** Bit definition for DMA2D_BGOR register ****************/
Kojto 122:f9eeca106725 3891
Kojto 122:f9eeca106725 3892 #define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
Kojto 122:f9eeca106725 3893
Kojto 122:f9eeca106725 3894 /******************** Bit definition for DMA2D_FGPFCCR register *************/
Kojto 122:f9eeca106725 3895
Kojto 122:f9eeca106725 3896 #define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
Kojto 122:f9eeca106725 3897 #define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
Kojto 122:f9eeca106725 3898 #define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
Kojto 122:f9eeca106725 3899 #define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
Kojto 122:f9eeca106725 3900 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
Kojto 122:f9eeca106725 3901 #define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
Kojto 122:f9eeca106725 3902 #define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
Kojto 122:f9eeca106725 3903 #define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
Kojto 122:f9eeca106725 3904 #define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
Kojto 122:f9eeca106725 3905 #define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
Kojto 122:f9eeca106725 3906 #define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
Kojto 122:f9eeca106725 3907 #define DMA2D_FGPFCCR_AI 0x00100000U /*!< Foreground Input Alpha Inverted */
Kojto 122:f9eeca106725 3908 #define DMA2D_FGPFCCR_RBS 0x00200000U /*!< Foreground Input Red Blue Swap */
Kojto 122:f9eeca106725 3909 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
Kojto 122:f9eeca106725 3910
Kojto 122:f9eeca106725 3911 /******************** Bit definition for DMA2D_FGCOLR register **************/
Kojto 122:f9eeca106725 3912
Kojto 122:f9eeca106725 3913 #define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
Kojto 122:f9eeca106725 3914 #define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
Kojto 122:f9eeca106725 3915 #define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
Kojto 122:f9eeca106725 3916
Kojto 122:f9eeca106725 3917 /******************** Bit definition for DMA2D_BGPFCCR register *************/
Kojto 122:f9eeca106725 3918
Kojto 122:f9eeca106725 3919 #define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
Kojto 122:f9eeca106725 3920 #define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
Kojto 122:f9eeca106725 3921 #define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
Kojto 122:f9eeca106725 3922 #define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
Kojto 122:f9eeca106725 3923 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
Kojto 122:f9eeca106725 3924 #define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
Kojto 122:f9eeca106725 3925 #define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
Kojto 122:f9eeca106725 3926 #define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
Kojto 122:f9eeca106725 3927 #define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
Kojto 122:f9eeca106725 3928 #define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
Kojto 122:f9eeca106725 3929 #define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
Kojto 122:f9eeca106725 3930 #define DMA2D_BGPFCCR_AI 0x00100000U /*!< background Input Alpha Inverted */
Kojto 122:f9eeca106725 3931 #define DMA2D_BGPFCCR_RBS 0x00200000U /*!< Background Input Red Blue Swap */
Kojto 122:f9eeca106725 3932 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
Kojto 122:f9eeca106725 3933
Kojto 122:f9eeca106725 3934 /******************** Bit definition for DMA2D_BGCOLR register **************/
Kojto 122:f9eeca106725 3935
Kojto 122:f9eeca106725 3936 #define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
Kojto 122:f9eeca106725 3937 #define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
Kojto 122:f9eeca106725 3938 #define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
Kojto 122:f9eeca106725 3939
Kojto 122:f9eeca106725 3940 /******************** Bit definition for DMA2D_FGCMAR register **************/
Kojto 122:f9eeca106725 3941
Kojto 122:f9eeca106725 3942 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
Kojto 122:f9eeca106725 3943
Kojto 122:f9eeca106725 3944 /******************** Bit definition for DMA2D_BGCMAR register **************/
Kojto 122:f9eeca106725 3945
Kojto 122:f9eeca106725 3946 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
Kojto 122:f9eeca106725 3947
Kojto 122:f9eeca106725 3948 /******************** Bit definition for DMA2D_OPFCCR register **************/
Kojto 122:f9eeca106725 3949
Kojto 122:f9eeca106725 3950 #define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
Kojto 122:f9eeca106725 3951 #define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
Kojto 122:f9eeca106725 3952 #define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
Kojto 122:f9eeca106725 3953 #define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
Kojto 122:f9eeca106725 3954 #define DMA2D_OPFCCR_AI 0x00100000U /*!< Output Alpha Inverted */
Kojto 122:f9eeca106725 3955 #define DMA2D_OPFCCR_RBS 0x00200000U /*!< Output Red Blue Swap */
Kojto 122:f9eeca106725 3956
Kojto 122:f9eeca106725 3957 /******************** Bit definition for DMA2D_OCOLR register ***************/
Kojto 122:f9eeca106725 3958
Kojto 122:f9eeca106725 3959 /*!<Mode_ARGB8888/RGB888 */
Kojto 122:f9eeca106725 3960
Kojto 122:f9eeca106725 3961 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
Kojto 122:f9eeca106725 3962 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
Kojto 122:f9eeca106725 3963 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
Kojto 122:f9eeca106725 3964 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
Kojto 122:f9eeca106725 3965
Kojto 122:f9eeca106725 3966 /*!<Mode_RGB565 */
Kojto 122:f9eeca106725 3967 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
Kojto 122:f9eeca106725 3968 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
Kojto 122:f9eeca106725 3969 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
Kojto 122:f9eeca106725 3970
Kojto 122:f9eeca106725 3971 /*!<Mode_ARGB1555 */
Kojto 122:f9eeca106725 3972 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
Kojto 122:f9eeca106725 3973 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
Kojto 122:f9eeca106725 3974 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
Kojto 122:f9eeca106725 3975 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
Kojto 122:f9eeca106725 3976
Kojto 122:f9eeca106725 3977 /*!<Mode_ARGB4444 */
Kojto 122:f9eeca106725 3978 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
Kojto 122:f9eeca106725 3979 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
Kojto 122:f9eeca106725 3980 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
Kojto 122:f9eeca106725 3981 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
Kojto 122:f9eeca106725 3982
Kojto 122:f9eeca106725 3983 /******************** Bit definition for DMA2D_OMAR register ****************/
Kojto 122:f9eeca106725 3984
Kojto 122:f9eeca106725 3985 #define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
Kojto 122:f9eeca106725 3986
Kojto 122:f9eeca106725 3987 /******************** Bit definition for DMA2D_OOR register *****************/
Kojto 122:f9eeca106725 3988
Kojto 122:f9eeca106725 3989 #define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
Kojto 122:f9eeca106725 3990
Kojto 122:f9eeca106725 3991 /******************** Bit definition for DMA2D_NLR register *****************/
Kojto 122:f9eeca106725 3992
Kojto 122:f9eeca106725 3993 #define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
Kojto 122:f9eeca106725 3994 #define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
Kojto 122:f9eeca106725 3995
Kojto 122:f9eeca106725 3996 /******************** Bit definition for DMA2D_LWR register *****************/
Kojto 122:f9eeca106725 3997
Kojto 122:f9eeca106725 3998 #define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
Kojto 122:f9eeca106725 3999
Kojto 122:f9eeca106725 4000 /******************** Bit definition for DMA2D_AMTCR register ***************/
Kojto 122:f9eeca106725 4001
Kojto 122:f9eeca106725 4002 #define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
Kojto 122:f9eeca106725 4003 #define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
Kojto 122:f9eeca106725 4004
Kojto 122:f9eeca106725 4005
Kojto 122:f9eeca106725 4006 /******************** Bit definition for DMA2D_FGCLUT register **************/
Kojto 122:f9eeca106725 4007
Kojto 122:f9eeca106725 4008 /******************** Bit definition for DMA2D_BGCLUT register **************/
Kojto 122:f9eeca106725 4009
Kojto 122:f9eeca106725 4010
Kojto 122:f9eeca106725 4011 /******************************************************************************/
Kojto 122:f9eeca106725 4012 /* */
Kojto 122:f9eeca106725 4013 /* External Interrupt/Event Controller */
Kojto 122:f9eeca106725 4014 /* */
Kojto 122:f9eeca106725 4015 /******************************************************************************/
Kojto 122:f9eeca106725 4016 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 122:f9eeca106725 4017 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 4018 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 4019 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 4020 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 4021 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 4022 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 4023 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 4024 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 4025 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 4026 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 4027 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 4028 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 4029 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 4030 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 4031 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 4032 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 4033 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
Kojto 122:f9eeca106725 4034 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 4035 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 4036 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 4037 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
Kojto 122:f9eeca106725 4038 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
Kojto 122:f9eeca106725 4039 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
Kojto 122:f9eeca106725 4040 #define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
Kojto 122:f9eeca106725 4041 #define EXTI_IMR_MR24 0x01000000U /*!< Interrupt Mask on line 24 */
Kojto 122:f9eeca106725 4042
Kojto 122:f9eeca106725 4043 /* Reference Defines */
Kojto 122:f9eeca106725 4044 #define EXTI_IMR_IM0 EXTI_IMR_MR0
Kojto 122:f9eeca106725 4045 #define EXTI_IMR_IM1 EXTI_IMR_MR1
Kojto 122:f9eeca106725 4046 #define EXTI_IMR_IM2 EXTI_IMR_MR2
Kojto 122:f9eeca106725 4047 #define EXTI_IMR_IM3 EXTI_IMR_MR3
Kojto 122:f9eeca106725 4048 #define EXTI_IMR_IM4 EXTI_IMR_MR4
Kojto 122:f9eeca106725 4049 #define EXTI_IMR_IM5 EXTI_IMR_MR5
Kojto 122:f9eeca106725 4050 #define EXTI_IMR_IM6 EXTI_IMR_MR6
Kojto 122:f9eeca106725 4051 #define EXTI_IMR_IM7 EXTI_IMR_MR7
Kojto 122:f9eeca106725 4052 #define EXTI_IMR_IM8 EXTI_IMR_MR8
Kojto 122:f9eeca106725 4053 #define EXTI_IMR_IM9 EXTI_IMR_MR9
Kojto 122:f9eeca106725 4054 #define EXTI_IMR_IM10 EXTI_IMR_MR10
Kojto 122:f9eeca106725 4055 #define EXTI_IMR_IM11 EXTI_IMR_MR11
Kojto 122:f9eeca106725 4056 #define EXTI_IMR_IM12 EXTI_IMR_MR12
Kojto 122:f9eeca106725 4057 #define EXTI_IMR_IM13 EXTI_IMR_MR13
Kojto 122:f9eeca106725 4058 #define EXTI_IMR_IM14 EXTI_IMR_MR14
Kojto 122:f9eeca106725 4059 #define EXTI_IMR_IM15 EXTI_IMR_MR15
Kojto 122:f9eeca106725 4060 #define EXTI_IMR_IM16 EXTI_IMR_MR16
Kojto 122:f9eeca106725 4061 #define EXTI_IMR_IM17 EXTI_IMR_MR17
Kojto 122:f9eeca106725 4062 #define EXTI_IMR_IM18 EXTI_IMR_MR18
Kojto 122:f9eeca106725 4063 #define EXTI_IMR_IM19 EXTI_IMR_MR19
Kojto 122:f9eeca106725 4064 #define EXTI_IMR_IM20 EXTI_IMR_MR20
Kojto 122:f9eeca106725 4065 #define EXTI_IMR_IM21 EXTI_IMR_MR21
Kojto 122:f9eeca106725 4066 #define EXTI_IMR_IM22 EXTI_IMR_MR22
Kojto 122:f9eeca106725 4067 #define EXTI_IMR_IM23 EXTI_IMR_MR23
Kojto 122:f9eeca106725 4068 #define EXTI_IMR_IM24 EXTI_IMR_MR24
Kojto 122:f9eeca106725 4069
Kojto 122:f9eeca106725 4070 #define EXTI_IMR_IM 0x01FFFFFFU /*!< Interrupt Mask All */
Kojto 122:f9eeca106725 4071
Kojto 122:f9eeca106725 4072 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 122:f9eeca106725 4073 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 4074 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 4075 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 4076 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 4077 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 4078 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 4079 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 4080 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 4081 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 4082 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 4083 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 4084 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 4085 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 4086 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 4087 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 4088 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 4089 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
Kojto 122:f9eeca106725 4090 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 4091 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 4092 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 4093 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
Kojto 122:f9eeca106725 4094 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
Kojto 122:f9eeca106725 4095 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
Kojto 122:f9eeca106725 4096 #define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
Kojto 122:f9eeca106725 4097 #define EXTI_EMR_MR24 0x01000000U /*!< Event Mask on line 24 */
Kojto 122:f9eeca106725 4098
Kojto 122:f9eeca106725 4099 /* Reference Defines */
Kojto 122:f9eeca106725 4100 #define EXTI_EMR_EM0 EXTI_EMR_MR0
Kojto 122:f9eeca106725 4101 #define EXTI_EMR_EM1 EXTI_EMR_MR1
Kojto 122:f9eeca106725 4102 #define EXTI_EMR_EM2 EXTI_EMR_MR2
Kojto 122:f9eeca106725 4103 #define EXTI_EMR_EM3 EXTI_EMR_MR3
Kojto 122:f9eeca106725 4104 #define EXTI_EMR_EM4 EXTI_EMR_MR4
Kojto 122:f9eeca106725 4105 #define EXTI_EMR_EM5 EXTI_EMR_MR5
Kojto 122:f9eeca106725 4106 #define EXTI_EMR_EM6 EXTI_EMR_MR6
Kojto 122:f9eeca106725 4107 #define EXTI_EMR_EM7 EXTI_EMR_MR7
Kojto 122:f9eeca106725 4108 #define EXTI_EMR_EM8 EXTI_EMR_MR8
Kojto 122:f9eeca106725 4109 #define EXTI_EMR_EM9 EXTI_EMR_MR9
Kojto 122:f9eeca106725 4110 #define EXTI_EMR_EM10 EXTI_EMR_MR10
Kojto 122:f9eeca106725 4111 #define EXTI_EMR_EM11 EXTI_EMR_MR11
Kojto 122:f9eeca106725 4112 #define EXTI_EMR_EM12 EXTI_EMR_MR12
Kojto 122:f9eeca106725 4113 #define EXTI_EMR_EM13 EXTI_EMR_MR13
Kojto 122:f9eeca106725 4114 #define EXTI_EMR_EM14 EXTI_EMR_MR14
Kojto 122:f9eeca106725 4115 #define EXTI_EMR_EM15 EXTI_EMR_MR15
Kojto 122:f9eeca106725 4116 #define EXTI_EMR_EM16 EXTI_EMR_MR16
Kojto 122:f9eeca106725 4117 #define EXTI_EMR_EM17 EXTI_EMR_MR17
Kojto 122:f9eeca106725 4118 #define EXTI_EMR_EM18 EXTI_EMR_MR18
Kojto 122:f9eeca106725 4119 #define EXTI_EMR_EM19 EXTI_EMR_MR19
Kojto 122:f9eeca106725 4120 #define EXTI_EMR_EM20 EXTI_EMR_MR20
Kojto 122:f9eeca106725 4121 #define EXTI_EMR_EM21 EXTI_EMR_MR21
Kojto 122:f9eeca106725 4122 #define EXTI_EMR_EM22 EXTI_EMR_MR22
Kojto 122:f9eeca106725 4123 #define EXTI_EMR_EM23 EXTI_EMR_MR23
Kojto 122:f9eeca106725 4124 #define EXTI_EMR_EM24 EXTI_EMR_MR24
Kojto 122:f9eeca106725 4125
Kojto 122:f9eeca106725 4126
Kojto 122:f9eeca106725 4127 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 122:f9eeca106725 4128 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 4129 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 4130 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 4131 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 4132 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 4133 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 4134 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 4135 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 4136 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 4137 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 4138 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 4139 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 4140 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 4141 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 4142 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 4143 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 4144 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 4145 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 4146 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 4147 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 4148 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 4149 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 4150 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 4151 #define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
Kojto 122:f9eeca106725 4152 #define EXTI_RTSR_TR24 0x01000000U /*!< Rising trigger event configuration bit of line 24 */
Kojto 122:f9eeca106725 4153
Kojto 122:f9eeca106725 4154 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 122:f9eeca106725 4155 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 4156 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 4157 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 4158 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 4159 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 4160 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 4161 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 4162 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 4163 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 4164 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 4165 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 4166 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 4167 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 4168 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 4169 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 4170 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 4171 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 4172 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 4173 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
Kojto 122:f9eeca106725 4174 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 4175 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
Kojto 122:f9eeca106725 4176 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
Kojto 122:f9eeca106725 4177 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
Kojto 122:f9eeca106725 4178 #define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
Kojto 122:f9eeca106725 4179 #define EXTI_FTSR_TR24 0x01000000U /*!< Falling trigger event configuration bit of line 24 */
Kojto 122:f9eeca106725 4180
Kojto 122:f9eeca106725 4181 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 122:f9eeca106725 4182 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 4183 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 4184 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 4185 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 4186 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 4187 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 4188 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 4189 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 4190 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 4191 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 4192 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 4193 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 4194 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 4195 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 4196 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 4197 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 4198 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 4199 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
Kojto 122:f9eeca106725 4200 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
Kojto 122:f9eeca106725 4201 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 4202 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
Kojto 122:f9eeca106725 4203 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
Kojto 122:f9eeca106725 4204 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
Kojto 122:f9eeca106725 4205 #define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
Kojto 122:f9eeca106725 4206 #define EXTI_SWIER_SWIER24 0x01000000U /*!< Software Interrupt on line 24 */
Kojto 122:f9eeca106725 4207
Kojto 122:f9eeca106725 4208 /******************* Bit definition for EXTI_PR register ********************/
Kojto 122:f9eeca106725 4209 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
Kojto 122:f9eeca106725 4210 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
Kojto 122:f9eeca106725 4211 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
Kojto 122:f9eeca106725 4212 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
Kojto 122:f9eeca106725 4213 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
Kojto 122:f9eeca106725 4214 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
Kojto 122:f9eeca106725 4215 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
Kojto 122:f9eeca106725 4216 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
Kojto 122:f9eeca106725 4217 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
Kojto 122:f9eeca106725 4218 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
Kojto 122:f9eeca106725 4219 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
Kojto 122:f9eeca106725 4220 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
Kojto 122:f9eeca106725 4221 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
Kojto 122:f9eeca106725 4222 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
Kojto 122:f9eeca106725 4223 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
Kojto 122:f9eeca106725 4224 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
Kojto 122:f9eeca106725 4225 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
Kojto 122:f9eeca106725 4226 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
Kojto 122:f9eeca106725 4227 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
Kojto 122:f9eeca106725 4228 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
Kojto 122:f9eeca106725 4229 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
Kojto 122:f9eeca106725 4230 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
Kojto 122:f9eeca106725 4231 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
Kojto 122:f9eeca106725 4232 #define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
Kojto 122:f9eeca106725 4233 #define EXTI_PR_PR24 0x01000000U /*!< Pending bit for line 24 */
Kojto 122:f9eeca106725 4234
Kojto 122:f9eeca106725 4235 /******************************************************************************/
Kojto 122:f9eeca106725 4236 /* */
Kojto 122:f9eeca106725 4237 /* FLASH */
Kojto 122:f9eeca106725 4238 /* */
Kojto 122:f9eeca106725 4239 /******************************************************************************/
Kojto 122:f9eeca106725 4240 /*
Kojto 122:f9eeca106725 4241 * @brief FLASH Total Sectors Number
Kojto 122:f9eeca106725 4242 */
Kojto 122:f9eeca106725 4243 #define FLASH_SECTOR_TOTAL 24
Kojto 122:f9eeca106725 4244
Kojto 122:f9eeca106725 4245 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 122:f9eeca106725 4246 #define FLASH_ACR_LATENCY 0x0000000FU
Kojto 122:f9eeca106725 4247 #define FLASH_ACR_LATENCY_0WS 0x00000000U
Kojto 122:f9eeca106725 4248 #define FLASH_ACR_LATENCY_1WS 0x00000001U
Kojto 122:f9eeca106725 4249 #define FLASH_ACR_LATENCY_2WS 0x00000002U
Kojto 122:f9eeca106725 4250 #define FLASH_ACR_LATENCY_3WS 0x00000003U
Kojto 122:f9eeca106725 4251 #define FLASH_ACR_LATENCY_4WS 0x00000004U
Kojto 122:f9eeca106725 4252 #define FLASH_ACR_LATENCY_5WS 0x00000005U
Kojto 122:f9eeca106725 4253 #define FLASH_ACR_LATENCY_6WS 0x00000006U
Kojto 122:f9eeca106725 4254 #define FLASH_ACR_LATENCY_7WS 0x00000007U
Kojto 122:f9eeca106725 4255 #define FLASH_ACR_LATENCY_8WS 0x00000008U
Kojto 122:f9eeca106725 4256 #define FLASH_ACR_LATENCY_9WS 0x00000009U
Kojto 122:f9eeca106725 4257 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
Kojto 122:f9eeca106725 4258 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
Kojto 122:f9eeca106725 4259 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
Kojto 122:f9eeca106725 4260 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
Kojto 122:f9eeca106725 4261 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
Kojto 122:f9eeca106725 4262 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
Kojto 122:f9eeca106725 4263 #define FLASH_ACR_PRFTEN 0x00000100U
Kojto 122:f9eeca106725 4264 #define FLASH_ACR_ARTEN 0x00000200U
Kojto 122:f9eeca106725 4265 #define FLASH_ACR_ARTRST 0x00000800U
Kojto 122:f9eeca106725 4266
Kojto 122:f9eeca106725 4267 /******************* Bits definition for FLASH_SR register ******************/
Kojto 122:f9eeca106725 4268 #define FLASH_SR_EOP 0x00000001U
Kojto 122:f9eeca106725 4269 #define FLASH_SR_OPERR 0x00000002U
Kojto 122:f9eeca106725 4270 #define FLASH_SR_WRPERR 0x00000010U
Kojto 122:f9eeca106725 4271 #define FLASH_SR_PGAERR 0x00000020U
Kojto 122:f9eeca106725 4272 #define FLASH_SR_PGPERR 0x00000040U
Kojto 122:f9eeca106725 4273 #define FLASH_SR_ERSERR 0x00000080U
Kojto 122:f9eeca106725 4274 #define FLASH_SR_BSY 0x00010000U
Kojto 122:f9eeca106725 4275
Kojto 122:f9eeca106725 4276 /******************* Bits definition for FLASH_CR register ******************/
Kojto 122:f9eeca106725 4277 #define FLASH_CR_PG 0x00000001U
Kojto 122:f9eeca106725 4278 #define FLASH_CR_SER 0x00000002U
Kojto 122:f9eeca106725 4279 #define FLASH_CR_MER 0x00000004U
Kojto 122:f9eeca106725 4280 #define FLASH_CR_MER1 FLASH_CR_MER
Kojto 122:f9eeca106725 4281 #define FLASH_CR_SNB 0x000000F8U
Kojto 122:f9eeca106725 4282 #define FLASH_CR_SNB_0 0x00000008U
Kojto 122:f9eeca106725 4283 #define FLASH_CR_SNB_1 0x00000010U
Kojto 122:f9eeca106725 4284 #define FLASH_CR_SNB_2 0x00000020U
Kojto 122:f9eeca106725 4285 #define FLASH_CR_SNB_3 0x00000040U
Kojto 122:f9eeca106725 4286 #define FLASH_CR_SNB_4 0x00000080U
Kojto 122:f9eeca106725 4287 #define FLASH_CR_PSIZE 0x00000300U
Kojto 122:f9eeca106725 4288 #define FLASH_CR_PSIZE_0 0x00000100U
Kojto 122:f9eeca106725 4289 #define FLASH_CR_PSIZE_1 0x00000200U
Kojto 122:f9eeca106725 4290 #define FLASH_CR_MER2 0x00008000U
Kojto 122:f9eeca106725 4291 #define FLASH_CR_STRT 0x00010000U
Kojto 122:f9eeca106725 4292 #define FLASH_CR_EOPIE 0x01000000U
Kojto 122:f9eeca106725 4293 #define FLASH_CR_ERRIE 0x02000000U
Kojto 122:f9eeca106725 4294 #define FLASH_CR_LOCK 0x80000000U
Kojto 122:f9eeca106725 4295
Kojto 122:f9eeca106725 4296 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 122:f9eeca106725 4297 #define FLASH_OPTCR_OPTLOCK 0x00000001U
Kojto 122:f9eeca106725 4298 #define FLASH_OPTCR_OPTSTRT 0x00000002U
Kojto 122:f9eeca106725 4299 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
Kojto 122:f9eeca106725 4300 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
Kojto 122:f9eeca106725 4301 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
Kojto 122:f9eeca106725 4302 #define FLASH_OPTCR_WWDG_SW 0x00000010U
Kojto 122:f9eeca106725 4303 #define FLASH_OPTCR_IWDG_SW 0x00000020U
Kojto 122:f9eeca106725 4304 #define FLASH_OPTCR_nRST_STOP 0x00000040U
Kojto 122:f9eeca106725 4305 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
Kojto 122:f9eeca106725 4306 #define FLASH_OPTCR_RDP 0x0000FF00U
Kojto 122:f9eeca106725 4307 #define FLASH_OPTCR_RDP_0 0x00000100U
Kojto 122:f9eeca106725 4308 #define FLASH_OPTCR_RDP_1 0x00000200U
Kojto 122:f9eeca106725 4309 #define FLASH_OPTCR_RDP_2 0x00000400U
Kojto 122:f9eeca106725 4310 #define FLASH_OPTCR_RDP_3 0x00000800U
Kojto 122:f9eeca106725 4311 #define FLASH_OPTCR_RDP_4 0x00001000U
Kojto 122:f9eeca106725 4312 #define FLASH_OPTCR_RDP_5 0x00002000U
Kojto 122:f9eeca106725 4313 #define FLASH_OPTCR_RDP_6 0x00004000U
Kojto 122:f9eeca106725 4314 #define FLASH_OPTCR_RDP_7 0x00008000U
Kojto 122:f9eeca106725 4315 #define FLASH_OPTCR_nWRP 0x0FFF0000U
Kojto 122:f9eeca106725 4316 #define FLASH_OPTCR_nWRP_0 0x00010000U
Kojto 122:f9eeca106725 4317 #define FLASH_OPTCR_nWRP_1 0x00020000U
Kojto 122:f9eeca106725 4318 #define FLASH_OPTCR_nWRP_2 0x00040000U
Kojto 122:f9eeca106725 4319 #define FLASH_OPTCR_nWRP_3 0x00080000U
Kojto 122:f9eeca106725 4320 #define FLASH_OPTCR_nWRP_4 0x00100000U
Kojto 122:f9eeca106725 4321 #define FLASH_OPTCR_nWRP_5 0x00200000U
Kojto 122:f9eeca106725 4322 #define FLASH_OPTCR_nWRP_6 0x00400000U
Kojto 122:f9eeca106725 4323 #define FLASH_OPTCR_nWRP_7 0x00800000U
Kojto 122:f9eeca106725 4324 #define FLASH_OPTCR_nWRP_8 0x01000000U
Kojto 122:f9eeca106725 4325 #define FLASH_OPTCR_nWRP_9 0x02000000U
Kojto 122:f9eeca106725 4326 #define FLASH_OPTCR_nWRP_10 0x04000000U
Kojto 122:f9eeca106725 4327 #define FLASH_OPTCR_nWRP_11 0x08000000U
Kojto 122:f9eeca106725 4328 #define FLASH_OPTCR_nDBOOT 0x10000000U
Kojto 122:f9eeca106725 4329 #define FLASH_OPTCR_nDBANK 0x20000000U
Kojto 122:f9eeca106725 4330 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
Kojto 122:f9eeca106725 4331 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
Kojto 122:f9eeca106725 4332
Kojto 122:f9eeca106725 4333 /******************* Bits definition for FLASH_OPTCR1 register ***************/
Kojto 122:f9eeca106725 4334 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
Kojto 122:f9eeca106725 4335 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
Kojto 122:f9eeca106725 4336
Kojto 122:f9eeca106725 4337 /******************************************************************************/
Kojto 122:f9eeca106725 4338 /* */
Kojto 122:f9eeca106725 4339 /* Flexible Memory Controller */
Kojto 122:f9eeca106725 4340 /* */
Kojto 122:f9eeca106725 4341 /******************************************************************************/
Kojto 122:f9eeca106725 4342 /****************** Bit definition for FMC_BCR1 register *******************/
Kojto 122:f9eeca106725 4343 #define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 4344 #define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 4345 #define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 4346 #define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4347 #define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4348 #define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 4349 #define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4350 #define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4351 #define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 4352 #define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 4353 #define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 4354 #define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
Kojto 122:f9eeca106725 4355 #define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 4356 #define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 4357 #define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 4358 #define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 4359 #define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 4360 #define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 4361 #define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4362 #define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4363 #define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4364 #define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
Kojto 122:f9eeca106725 4365 #define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
Kojto 122:f9eeca106725 4366 #define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
Kojto 122:f9eeca106725 4367
Kojto 122:f9eeca106725 4368 /****************** Bit definition for FMC_BCR2 register *******************/
Kojto 122:f9eeca106725 4369 #define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 4370 #define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 4371 #define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 4372 #define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4373 #define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4374 #define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 4375 #define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4376 #define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4377 #define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 4378 #define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 4379 #define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 4380 #define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
Kojto 122:f9eeca106725 4381 #define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 4382 #define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 4383 #define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 4384 #define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 4385 #define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 4386 #define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 4387 #define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4388 #define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4389 #define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4390 #define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
Kojto 122:f9eeca106725 4391
Kojto 122:f9eeca106725 4392 /****************** Bit definition for FMC_BCR3 register *******************/
Kojto 122:f9eeca106725 4393 #define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 4394 #define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 4395 #define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 4396 #define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4397 #define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4398 #define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 4399 #define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4400 #define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4401 #define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 4402 #define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 4403 #define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 4404 #define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
Kojto 122:f9eeca106725 4405 #define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 4406 #define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 4407 #define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 4408 #define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 4409 #define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 4410 #define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 4411 #define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4412 #define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4413 #define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4414 #define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
Kojto 122:f9eeca106725 4415
Kojto 122:f9eeca106725 4416 /****************** Bit definition for FMC_BCR4 register *******************/
Kojto 122:f9eeca106725 4417 #define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
Kojto 122:f9eeca106725 4418 #define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
Kojto 122:f9eeca106725 4419 #define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
Kojto 122:f9eeca106725 4420 #define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4421 #define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4422 #define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 122:f9eeca106725 4423 #define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4424 #define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4425 #define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
Kojto 122:f9eeca106725 4426 #define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
Kojto 122:f9eeca106725 4427 #define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
Kojto 122:f9eeca106725 4428 #define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
Kojto 122:f9eeca106725 4429 #define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
Kojto 122:f9eeca106725 4430 #define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
Kojto 122:f9eeca106725 4431 #define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
Kojto 122:f9eeca106725 4432 #define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
Kojto 122:f9eeca106725 4433 #define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
Kojto 122:f9eeca106725 4434 #define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
Kojto 122:f9eeca106725 4435 #define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4436 #define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4437 #define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4438 #define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
Kojto 122:f9eeca106725 4439
Kojto 122:f9eeca106725 4440 /****************** Bit definition for FMC_BTR1 register ******************/
Kojto 122:f9eeca106725 4441 #define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 4442 #define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4443 #define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4444 #define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4445 #define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4446 #define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 4447 #define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4448 #define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4449 #define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4450 #define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4451 #define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 4452 #define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4453 #define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4454 #define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4455 #define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4456 #define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4457 #define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4458 #define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4459 #define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4460 #define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 4461 #define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4462 #define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4463 #define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4464 #define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4465 #define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 4466 #define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4467 #define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4468 #define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4469 #define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4470 #define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 4471 #define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4472 #define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4473 #define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4474 #define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4475 #define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 4476 #define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4477 #define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4478
Kojto 122:f9eeca106725 4479 /****************** Bit definition for FMC_BTR2 register *******************/
Kojto 122:f9eeca106725 4480 #define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 4481 #define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4482 #define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4483 #define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4484 #define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4485 #define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 4486 #define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4487 #define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4488 #define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4489 #define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4490 #define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 4491 #define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4492 #define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4493 #define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4494 #define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4495 #define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4496 #define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4497 #define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4498 #define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4499 #define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 4500 #define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4501 #define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4502 #define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4503 #define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4504 #define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 4505 #define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4506 #define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4507 #define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4508 #define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4509 #define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 4510 #define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4511 #define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4512 #define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4513 #define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4514 #define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 4515 #define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4516 #define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4517
Kojto 122:f9eeca106725 4518 /******************* Bit definition for FMC_BTR3 register *******************/
Kojto 122:f9eeca106725 4519 #define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 4520 #define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4521 #define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4522 #define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4523 #define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4524 #define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 4525 #define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4526 #define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4527 #define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4528 #define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4529 #define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 4530 #define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4531 #define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4532 #define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4533 #define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4534 #define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4535 #define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4536 #define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4537 #define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4538 #define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 4539 #define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4540 #define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4541 #define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4542 #define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4543 #define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 4544 #define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4545 #define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4546 #define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4547 #define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4548 #define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 4549 #define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4550 #define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4551 #define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4552 #define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4553 #define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 4554 #define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4555 #define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4556
Kojto 122:f9eeca106725 4557 /****************** Bit definition for FMC_BTR4 register *******************/
Kojto 122:f9eeca106725 4558 #define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 4559 #define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4560 #define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4561 #define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4562 #define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4563 #define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 4564 #define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4565 #define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4566 #define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4567 #define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4568 #define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 4569 #define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4570 #define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4571 #define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4572 #define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4573 #define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4574 #define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4575 #define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4576 #define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4577 #define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 4578 #define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4579 #define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4580 #define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4581 #define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4582 #define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 122:f9eeca106725 4583 #define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4584 #define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4585 #define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4586 #define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4587 #define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
Kojto 122:f9eeca106725 4588 #define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4589 #define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4590 #define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4591 #define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4592 #define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 4593 #define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4594 #define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4595
Kojto 122:f9eeca106725 4596 /****************** Bit definition for FMC_BWTR1 register ******************/
Kojto 122:f9eeca106725 4597 #define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 4598 #define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4599 #define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4600 #define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4601 #define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4602 #define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 4603 #define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4604 #define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4605 #define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4606 #define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4607 #define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 4608 #define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4609 #define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4610 #define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4611 #define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4612 #define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4613 #define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4614 #define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4615 #define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4616 #define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 4617 #define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4618 #define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4619 #define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4620 #define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4621 #define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 4622 #define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4623 #define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4624
Kojto 122:f9eeca106725 4625 /****************** Bit definition for FMC_BWTR2 register ******************/
Kojto 122:f9eeca106725 4626 #define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 4627 #define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4628 #define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4629 #define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4630 #define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4631 #define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 4632 #define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4633 #define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4634 #define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4635 #define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4636 #define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 4637 #define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4638 #define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4639 #define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4640 #define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4641 #define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4642 #define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4643 #define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4644 #define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4645 #define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 4646 #define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4647 #define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4648 #define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4649 #define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4650 #define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 4651 #define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4652 #define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4653
Kojto 122:f9eeca106725 4654 /****************** Bit definition for FMC_BWTR3 register ******************/
Kojto 122:f9eeca106725 4655 #define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 4656 #define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4657 #define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4658 #define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4659 #define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4660 #define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 4661 #define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4662 #define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4663 #define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4664 #define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4665 #define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 4666 #define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4667 #define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4668 #define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4669 #define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4670 #define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4671 #define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4672 #define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4673 #define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4674 #define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 4675 #define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4676 #define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4677 #define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4678 #define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4679 #define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 4680 #define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4681 #define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4682
Kojto 122:f9eeca106725 4683 /****************** Bit definition for FMC_BWTR4 register ******************/
Kojto 122:f9eeca106725 4684 #define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 122:f9eeca106725 4685 #define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4686 #define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4687 #define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4688 #define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4689 #define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 122:f9eeca106725 4690 #define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4691 #define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4692 #define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4693 #define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4694 #define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 122:f9eeca106725 4695 #define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4696 #define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4697 #define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4698 #define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4699 #define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4700 #define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4701 #define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4702 #define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4703 #define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 122:f9eeca106725 4704 #define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4705 #define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4706 #define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4707 #define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4708 #define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 122:f9eeca106725 4709 #define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4710 #define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4711
Kojto 122:f9eeca106725 4712 /****************** Bit definition for FMC_PCR register *******************/
Kojto 122:f9eeca106725 4713 #define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
Kojto 122:f9eeca106725 4714 #define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
Kojto 122:f9eeca106725 4715 #define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
Kojto 122:f9eeca106725 4716 #define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
Kojto 122:f9eeca106725 4717 #define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4718 #define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4719 #define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
Kojto 122:f9eeca106725 4720 #define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
Kojto 122:f9eeca106725 4721 #define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
Kojto 122:f9eeca106725 4722 #define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
Kojto 122:f9eeca106725 4723 #define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
Kojto 122:f9eeca106725 4724 #define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4725 #define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
Kojto 122:f9eeca106725 4726 #define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4727 #define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4728 #define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4729 #define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4730 #define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
Kojto 122:f9eeca106725 4731 #define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4732 #define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4733 #define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4734
Kojto 122:f9eeca106725 4735 /******************* Bit definition for FMC_SR register *******************/
Kojto 122:f9eeca106725 4736 #define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
Kojto 122:f9eeca106725 4737 #define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
Kojto 122:f9eeca106725 4738 #define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
Kojto 122:f9eeca106725 4739 #define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
Kojto 122:f9eeca106725 4740 #define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
Kojto 122:f9eeca106725 4741 #define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
Kojto 122:f9eeca106725 4742 #define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
Kojto 122:f9eeca106725 4743
Kojto 122:f9eeca106725 4744 /****************** Bit definition for FMC_PMEM register ******************/
Kojto 122:f9eeca106725 4745 #define FMC_PMEM_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
Kojto 122:f9eeca106725 4746 #define FMC_PMEM_MEMSET3_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4747 #define FMC_PMEM_MEMSET3_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4748 #define FMC_PMEM_MEMSET3_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4749 #define FMC_PMEM_MEMSET3_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4750 #define FMC_PMEM_MEMSET3_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4751 #define FMC_PMEM_MEMSET3_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4752 #define FMC_PMEM_MEMSET3_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4753 #define FMC_PMEM_MEMSET3_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4754 #define FMC_PMEM_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
Kojto 122:f9eeca106725 4755 #define FMC_PMEM_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4756 #define FMC_PMEM_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4757 #define FMC_PMEM_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4758 #define FMC_PMEM_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4759 #define FMC_PMEM_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4760 #define FMC_PMEM_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4761 #define FMC_PMEM_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4762 #define FMC_PMEM_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4763 #define FMC_PMEM_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
Kojto 122:f9eeca106725 4764 #define FMC_PMEM_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4765 #define FMC_PMEM_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4766 #define FMC_PMEM_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4767 #define FMC_PMEM_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4768 #define FMC_PMEM_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4769 #define FMC_PMEM_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4770 #define FMC_PMEM_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4771 #define FMC_PMEM_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4772 #define FMC_PMEM_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
Kojto 122:f9eeca106725 4773 #define FMC_PMEM_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4774 #define FMC_PMEM_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4775 #define FMC_PMEM_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4776 #define FMC_PMEM_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4777 #define FMC_PMEM_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4778 #define FMC_PMEM_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4779 #define FMC_PMEM_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4780 #define FMC_PMEM_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4781
Kojto 122:f9eeca106725 4782 /****************** Bit definition for FMC_PATT register ******************/
Kojto 122:f9eeca106725 4783 #define FMC_PATT_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
Kojto 122:f9eeca106725 4784 #define FMC_PATT_ATTSET3_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4785 #define FMC_PATT_ATTSET3_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4786 #define FMC_PATT_ATTSET3_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4787 #define FMC_PATT_ATTSET3_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4788 #define FMC_PATT_ATTSET3_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 4789 #define FMC_PATT_ATTSET3_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 4790 #define FMC_PATT_ATTSET3_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 4791 #define FMC_PATT_ATTSET3_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 4792 #define FMC_PATT_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
Kojto 122:f9eeca106725 4793 #define FMC_PATT_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4794 #define FMC_PATT_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4795 #define FMC_PATT_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4796 #define FMC_PATT_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4797 #define FMC_PATT_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4798 #define FMC_PATT_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4799 #define FMC_PATT_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4800 #define FMC_PATT_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4801 #define FMC_PATT_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
Kojto 122:f9eeca106725 4802 #define FMC_PATT_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4803 #define FMC_PATT_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4804 #define FMC_PATT_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4805 #define FMC_PATT_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4806 #define FMC_PATT_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4807 #define FMC_PATT_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4808 #define FMC_PATT_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4809 #define FMC_PATT_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4810 #define FMC_PATT_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
Kojto 122:f9eeca106725 4811 #define FMC_PATT_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4812 #define FMC_PATT_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4813 #define FMC_PATT_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4814 #define FMC_PATT_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 4815 #define FMC_PATT_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 4816 #define FMC_PATT_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 4817 #define FMC_PATT_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 4818 #define FMC_PATT_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
Kojto 122:f9eeca106725 4819
Kojto 122:f9eeca106725 4820 /****************** Bit definition for FMC_ECCR register ******************/
Kojto 122:f9eeca106725 4821 #define FMC_ECCR_ECC3 0xFFFFFFFFU /*!<ECC result */
Kojto 122:f9eeca106725 4822
Kojto 122:f9eeca106725 4823 /****************** Bit definition for FMC_SDCR1 register ******************/
Kojto 122:f9eeca106725 4824 #define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
Kojto 122:f9eeca106725 4825 #define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4826 #define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4827 #define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
Kojto 122:f9eeca106725 4828 #define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4829 #define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4830 #define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
Kojto 122:f9eeca106725 4831 #define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4832 #define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4833 #define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
Kojto 122:f9eeca106725 4834 #define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
Kojto 122:f9eeca106725 4835 #define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 4836 #define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 4837 #define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
Kojto 122:f9eeca106725 4838 #define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
Kojto 122:f9eeca106725 4839 #define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 4840 #define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 4841 #define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
Kojto 122:f9eeca106725 4842 #define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
Kojto 122:f9eeca106725 4843 #define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4844 #define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4845
Kojto 122:f9eeca106725 4846 /****************** Bit definition for FMC_SDCR2 register ******************/
Kojto 122:f9eeca106725 4847 #define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
Kojto 122:f9eeca106725 4848 #define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4849 #define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4850 #define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
Kojto 122:f9eeca106725 4851 #define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 4852 #define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 4853 #define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
Kojto 122:f9eeca106725 4854 #define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4855 #define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4856 #define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
Kojto 122:f9eeca106725 4857 #define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
Kojto 122:f9eeca106725 4858 #define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 4859 #define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 4860 #define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
Kojto 122:f9eeca106725 4861 #define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
Kojto 122:f9eeca106725 4862 #define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 4863 #define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 4864 #define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
Kojto 122:f9eeca106725 4865 #define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
Kojto 122:f9eeca106725 4866 #define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4867 #define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4868
Kojto 122:f9eeca106725 4869 /****************** Bit definition for FMC_SDTR1 register ******************/
Kojto 122:f9eeca106725 4870 #define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 122:f9eeca106725 4871 #define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4872 #define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4873 #define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4874 #define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4875 #define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 122:f9eeca106725 4876 #define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4877 #define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4878 #define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4879 #define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4880 #define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 122:f9eeca106725 4881 #define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4882 #define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4883 #define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4884 #define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4885 #define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 122:f9eeca106725 4886 #define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4887 #define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4888 #define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4889 #define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 122:f9eeca106725 4890 #define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4891 #define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4892 #define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4893 #define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 122:f9eeca106725 4894 #define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4895 #define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4896 #define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4897 #define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
Kojto 122:f9eeca106725 4898 #define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4899 #define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4900 #define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4901
Kojto 122:f9eeca106725 4902 /****************** Bit definition for FMC_SDTR2 register ******************/
Kojto 122:f9eeca106725 4903 #define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 122:f9eeca106725 4904 #define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4905 #define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4906 #define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 4907 #define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 4908 #define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 122:f9eeca106725 4909 #define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 4910 #define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 4911 #define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 4912 #define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 4913 #define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 122:f9eeca106725 4914 #define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 4915 #define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 4916 #define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 4917 #define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 4918 #define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 122:f9eeca106725 4919 #define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4920 #define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4921 #define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4922 #define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 122:f9eeca106725 4923 #define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4924 #define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4925 #define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4926 #define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 122:f9eeca106725 4927 #define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4928 #define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4929 #define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4930 #define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
Kojto 122:f9eeca106725 4931 #define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 4932 #define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 4933 #define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 4934
Kojto 122:f9eeca106725 4935 /****************** Bit definition for FMC_SDCMR register ******************/
Kojto 122:f9eeca106725 4936 #define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
Kojto 122:f9eeca106725 4937 #define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 4938 #define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 4939 #define FMC_SDCMR_MODE_2 0x00000003U /*!<Bit 2 */
Kojto 122:f9eeca106725 4940 #define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
Kojto 122:f9eeca106725 4941 #define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
Kojto 122:f9eeca106725 4942 #define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
Kojto 122:f9eeca106725 4943 #define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 4944 #define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 4945 #define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 4946 #define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
Kojto 122:f9eeca106725 4947 #define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
Kojto 122:f9eeca106725 4948
Kojto 122:f9eeca106725 4949 /****************** Bit definition for FMC_SDRTR register ******************/
Kojto 122:f9eeca106725 4950 #define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
Kojto 122:f9eeca106725 4951 #define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
Kojto 122:f9eeca106725 4952 #define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
Kojto 122:f9eeca106725 4953
Kojto 122:f9eeca106725 4954 /****************** Bit definition for FMC_SDSR register ******************/
Kojto 122:f9eeca106725 4955 #define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
Kojto 122:f9eeca106725 4956 #define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
Kojto 122:f9eeca106725 4957 #define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 4958 #define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 4959 #define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
Kojto 122:f9eeca106725 4960 #define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 4961 #define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 4962 #define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
Kojto 122:f9eeca106725 4963
Kojto 122:f9eeca106725 4964 /******************************************************************************/
Kojto 122:f9eeca106725 4965 /* */
Kojto 122:f9eeca106725 4966 /* General Purpose I/O */
Kojto 122:f9eeca106725 4967 /* */
Kojto 122:f9eeca106725 4968 /******************************************************************************/
Kojto 122:f9eeca106725 4969 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 4970 #define GPIO_MODER_MODER0 0x00000003U
Kojto 122:f9eeca106725 4971 #define GPIO_MODER_MODER0_0 0x00000001U
Kojto 122:f9eeca106725 4972 #define GPIO_MODER_MODER0_1 0x00000002U
Kojto 122:f9eeca106725 4973 #define GPIO_MODER_MODER1 0x0000000CU
Kojto 122:f9eeca106725 4974 #define GPIO_MODER_MODER1_0 0x00000004U
Kojto 122:f9eeca106725 4975 #define GPIO_MODER_MODER1_1 0x00000008U
Kojto 122:f9eeca106725 4976 #define GPIO_MODER_MODER2 0x00000030U
Kojto 122:f9eeca106725 4977 #define GPIO_MODER_MODER2_0 0x00000010U
Kojto 122:f9eeca106725 4978 #define GPIO_MODER_MODER2_1 0x00000020U
Kojto 122:f9eeca106725 4979 #define GPIO_MODER_MODER3 0x000000C0U
Kojto 122:f9eeca106725 4980 #define GPIO_MODER_MODER3_0 0x00000040U
Kojto 122:f9eeca106725 4981 #define GPIO_MODER_MODER3_1 0x00000080U
Kojto 122:f9eeca106725 4982 #define GPIO_MODER_MODER4 0x00000300U
Kojto 122:f9eeca106725 4983 #define GPIO_MODER_MODER4_0 0x00000100U
Kojto 122:f9eeca106725 4984 #define GPIO_MODER_MODER4_1 0x00000200U
Kojto 122:f9eeca106725 4985 #define GPIO_MODER_MODER5 0x00000C00U
Kojto 122:f9eeca106725 4986 #define GPIO_MODER_MODER5_0 0x00000400U
Kojto 122:f9eeca106725 4987 #define GPIO_MODER_MODER5_1 0x00000800U
Kojto 122:f9eeca106725 4988 #define GPIO_MODER_MODER6 0x00003000U
Kojto 122:f9eeca106725 4989 #define GPIO_MODER_MODER6_0 0x00001000U
Kojto 122:f9eeca106725 4990 #define GPIO_MODER_MODER6_1 0x00002000U
Kojto 122:f9eeca106725 4991 #define GPIO_MODER_MODER7 0x0000C000U
Kojto 122:f9eeca106725 4992 #define GPIO_MODER_MODER7_0 0x00004000U
Kojto 122:f9eeca106725 4993 #define GPIO_MODER_MODER7_1 0x00008000U
Kojto 122:f9eeca106725 4994 #define GPIO_MODER_MODER8 0x00030000U
Kojto 122:f9eeca106725 4995 #define GPIO_MODER_MODER8_0 0x00010000U
Kojto 122:f9eeca106725 4996 #define GPIO_MODER_MODER8_1 0x00020000U
Kojto 122:f9eeca106725 4997 #define GPIO_MODER_MODER9 0x000C0000U
Kojto 122:f9eeca106725 4998 #define GPIO_MODER_MODER9_0 0x00040000U
Kojto 122:f9eeca106725 4999 #define GPIO_MODER_MODER9_1 0x00080000U
Kojto 122:f9eeca106725 5000 #define GPIO_MODER_MODER10 0x00300000U
Kojto 122:f9eeca106725 5001 #define GPIO_MODER_MODER10_0 0x00100000U
Kojto 122:f9eeca106725 5002 #define GPIO_MODER_MODER10_1 0x00200000U
Kojto 122:f9eeca106725 5003 #define GPIO_MODER_MODER11 0x00C00000U
Kojto 122:f9eeca106725 5004 #define GPIO_MODER_MODER11_0 0x00400000U
Kojto 122:f9eeca106725 5005 #define GPIO_MODER_MODER11_1 0x00800000U
Kojto 122:f9eeca106725 5006 #define GPIO_MODER_MODER12 0x03000000U
Kojto 122:f9eeca106725 5007 #define GPIO_MODER_MODER12_0 0x01000000U
Kojto 122:f9eeca106725 5008 #define GPIO_MODER_MODER12_1 0x02000000U
Kojto 122:f9eeca106725 5009 #define GPIO_MODER_MODER13 0x0C000000U
Kojto 122:f9eeca106725 5010 #define GPIO_MODER_MODER13_0 0x04000000U
Kojto 122:f9eeca106725 5011 #define GPIO_MODER_MODER13_1 0x08000000U
Kojto 122:f9eeca106725 5012 #define GPIO_MODER_MODER14 0x30000000U
Kojto 122:f9eeca106725 5013 #define GPIO_MODER_MODER14_0 0x10000000U
Kojto 122:f9eeca106725 5014 #define GPIO_MODER_MODER14_1 0x20000000U
Kojto 122:f9eeca106725 5015 #define GPIO_MODER_MODER15 0xC0000000U
Kojto 122:f9eeca106725 5016 #define GPIO_MODER_MODER15_0 0x40000000U
Kojto 122:f9eeca106725 5017 #define GPIO_MODER_MODER15_1 0x80000000U
Kojto 122:f9eeca106725 5018
Kojto 122:f9eeca106725 5019 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 122:f9eeca106725 5020 #define GPIO_OTYPER_OT_0 0x00000001U
Kojto 122:f9eeca106725 5021 #define GPIO_OTYPER_OT_1 0x00000002U
Kojto 122:f9eeca106725 5022 #define GPIO_OTYPER_OT_2 0x00000004U
Kojto 122:f9eeca106725 5023 #define GPIO_OTYPER_OT_3 0x00000008U
Kojto 122:f9eeca106725 5024 #define GPIO_OTYPER_OT_4 0x00000010U
Kojto 122:f9eeca106725 5025 #define GPIO_OTYPER_OT_5 0x00000020U
Kojto 122:f9eeca106725 5026 #define GPIO_OTYPER_OT_6 0x00000040U
Kojto 122:f9eeca106725 5027 #define GPIO_OTYPER_OT_7 0x00000080U
Kojto 122:f9eeca106725 5028 #define GPIO_OTYPER_OT_8 0x00000100U
Kojto 122:f9eeca106725 5029 #define GPIO_OTYPER_OT_9 0x00000200U
Kojto 122:f9eeca106725 5030 #define GPIO_OTYPER_OT_10 0x00000400U
Kojto 122:f9eeca106725 5031 #define GPIO_OTYPER_OT_11 0x00000800U
Kojto 122:f9eeca106725 5032 #define GPIO_OTYPER_OT_12 0x00001000U
Kojto 122:f9eeca106725 5033 #define GPIO_OTYPER_OT_13 0x00002000U
Kojto 122:f9eeca106725 5034 #define GPIO_OTYPER_OT_14 0x00004000U
Kojto 122:f9eeca106725 5035 #define GPIO_OTYPER_OT_15 0x00008000U
Kojto 122:f9eeca106725 5036
Kojto 122:f9eeca106725 5037 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 122:f9eeca106725 5038 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
Kojto 122:f9eeca106725 5039 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
Kojto 122:f9eeca106725 5040 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
Kojto 122:f9eeca106725 5041 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
Kojto 122:f9eeca106725 5042 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
Kojto 122:f9eeca106725 5043 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
Kojto 122:f9eeca106725 5044 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
Kojto 122:f9eeca106725 5045 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
Kojto 122:f9eeca106725 5046 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
Kojto 122:f9eeca106725 5047 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
Kojto 122:f9eeca106725 5048 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
Kojto 122:f9eeca106725 5049 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
Kojto 122:f9eeca106725 5050 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
Kojto 122:f9eeca106725 5051 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
Kojto 122:f9eeca106725 5052 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
Kojto 122:f9eeca106725 5053 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
Kojto 122:f9eeca106725 5054 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
Kojto 122:f9eeca106725 5055 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
Kojto 122:f9eeca106725 5056 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
Kojto 122:f9eeca106725 5057 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
Kojto 122:f9eeca106725 5058 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
Kojto 122:f9eeca106725 5059 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
Kojto 122:f9eeca106725 5060 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
Kojto 122:f9eeca106725 5061 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
Kojto 122:f9eeca106725 5062 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
Kojto 122:f9eeca106725 5063 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
Kojto 122:f9eeca106725 5064 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
Kojto 122:f9eeca106725 5065 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
Kojto 122:f9eeca106725 5066 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
Kojto 122:f9eeca106725 5067 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
Kojto 122:f9eeca106725 5068 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
Kojto 122:f9eeca106725 5069 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
Kojto 122:f9eeca106725 5070 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
Kojto 122:f9eeca106725 5071 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
Kojto 122:f9eeca106725 5072 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
Kojto 122:f9eeca106725 5073 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
Kojto 122:f9eeca106725 5074 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
Kojto 122:f9eeca106725 5075 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
Kojto 122:f9eeca106725 5076 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
Kojto 122:f9eeca106725 5077 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
Kojto 122:f9eeca106725 5078 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
Kojto 122:f9eeca106725 5079 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
Kojto 122:f9eeca106725 5080 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
Kojto 122:f9eeca106725 5081 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
Kojto 122:f9eeca106725 5082 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
Kojto 122:f9eeca106725 5083 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
Kojto 122:f9eeca106725 5084 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
Kojto 122:f9eeca106725 5085 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
Kojto 122:f9eeca106725 5086
Kojto 122:f9eeca106725 5087 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 122:f9eeca106725 5088 #define GPIO_PUPDR_PUPDR0 0x00000003U
Kojto 122:f9eeca106725 5089 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
Kojto 122:f9eeca106725 5090 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
Kojto 122:f9eeca106725 5091 #define GPIO_PUPDR_PUPDR1 0x0000000CU
Kojto 122:f9eeca106725 5092 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
Kojto 122:f9eeca106725 5093 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
Kojto 122:f9eeca106725 5094 #define GPIO_PUPDR_PUPDR2 0x00000030U
Kojto 122:f9eeca106725 5095 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
Kojto 122:f9eeca106725 5096 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
Kojto 122:f9eeca106725 5097 #define GPIO_PUPDR_PUPDR3 0x000000C0U
Kojto 122:f9eeca106725 5098 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
Kojto 122:f9eeca106725 5099 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
Kojto 122:f9eeca106725 5100 #define GPIO_PUPDR_PUPDR4 0x00000300U
Kojto 122:f9eeca106725 5101 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
Kojto 122:f9eeca106725 5102 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
Kojto 122:f9eeca106725 5103 #define GPIO_PUPDR_PUPDR5 0x00000C00U
Kojto 122:f9eeca106725 5104 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
Kojto 122:f9eeca106725 5105 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
Kojto 122:f9eeca106725 5106 #define GPIO_PUPDR_PUPDR6 0x00003000U
Kojto 122:f9eeca106725 5107 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
Kojto 122:f9eeca106725 5108 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
Kojto 122:f9eeca106725 5109 #define GPIO_PUPDR_PUPDR7 0x0000C000U
Kojto 122:f9eeca106725 5110 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
Kojto 122:f9eeca106725 5111 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
Kojto 122:f9eeca106725 5112 #define GPIO_PUPDR_PUPDR8 0x00030000U
Kojto 122:f9eeca106725 5113 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
Kojto 122:f9eeca106725 5114 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
Kojto 122:f9eeca106725 5115 #define GPIO_PUPDR_PUPDR9 0x000C0000U
Kojto 122:f9eeca106725 5116 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
Kojto 122:f9eeca106725 5117 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
Kojto 122:f9eeca106725 5118 #define GPIO_PUPDR_PUPDR10 0x00300000U
Kojto 122:f9eeca106725 5119 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
Kojto 122:f9eeca106725 5120 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
Kojto 122:f9eeca106725 5121 #define GPIO_PUPDR_PUPDR11 0x00C00000U
Kojto 122:f9eeca106725 5122 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
Kojto 122:f9eeca106725 5123 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
Kojto 122:f9eeca106725 5124 #define GPIO_PUPDR_PUPDR12 0x03000000U
Kojto 122:f9eeca106725 5125 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
Kojto 122:f9eeca106725 5126 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
Kojto 122:f9eeca106725 5127 #define GPIO_PUPDR_PUPDR13 0x0C000000U
Kojto 122:f9eeca106725 5128 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
Kojto 122:f9eeca106725 5129 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
Kojto 122:f9eeca106725 5130 #define GPIO_PUPDR_PUPDR14 0x30000000U
Kojto 122:f9eeca106725 5131 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
Kojto 122:f9eeca106725 5132 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
Kojto 122:f9eeca106725 5133 #define GPIO_PUPDR_PUPDR15 0xC0000000U
Kojto 122:f9eeca106725 5134 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
Kojto 122:f9eeca106725 5135 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
Kojto 122:f9eeca106725 5136
Kojto 122:f9eeca106725 5137 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 5138 #define GPIO_IDR_IDR_0 0x00000001U
Kojto 122:f9eeca106725 5139 #define GPIO_IDR_IDR_1 0x00000002U
Kojto 122:f9eeca106725 5140 #define GPIO_IDR_IDR_2 0x00000004U
Kojto 122:f9eeca106725 5141 #define GPIO_IDR_IDR_3 0x00000008U
Kojto 122:f9eeca106725 5142 #define GPIO_IDR_IDR_4 0x00000010U
Kojto 122:f9eeca106725 5143 #define GPIO_IDR_IDR_5 0x00000020U
Kojto 122:f9eeca106725 5144 #define GPIO_IDR_IDR_6 0x00000040U
Kojto 122:f9eeca106725 5145 #define GPIO_IDR_IDR_7 0x00000080U
Kojto 122:f9eeca106725 5146 #define GPIO_IDR_IDR_8 0x00000100U
Kojto 122:f9eeca106725 5147 #define GPIO_IDR_IDR_9 0x00000200U
Kojto 122:f9eeca106725 5148 #define GPIO_IDR_IDR_10 0x00000400U
Kojto 122:f9eeca106725 5149 #define GPIO_IDR_IDR_11 0x00000800U
Kojto 122:f9eeca106725 5150 #define GPIO_IDR_IDR_12 0x00001000U
Kojto 122:f9eeca106725 5151 #define GPIO_IDR_IDR_13 0x00002000U
Kojto 122:f9eeca106725 5152 #define GPIO_IDR_IDR_14 0x00004000U
Kojto 122:f9eeca106725 5153 #define GPIO_IDR_IDR_15 0x00008000U
Kojto 122:f9eeca106725 5154
Kojto 122:f9eeca106725 5155 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 122:f9eeca106725 5156 #define GPIO_ODR_ODR_0 0x00000001U
Kojto 122:f9eeca106725 5157 #define GPIO_ODR_ODR_1 0x00000002U
Kojto 122:f9eeca106725 5158 #define GPIO_ODR_ODR_2 0x00000004U
Kojto 122:f9eeca106725 5159 #define GPIO_ODR_ODR_3 0x00000008U
Kojto 122:f9eeca106725 5160 #define GPIO_ODR_ODR_4 0x00000010U
Kojto 122:f9eeca106725 5161 #define GPIO_ODR_ODR_5 0x00000020U
Kojto 122:f9eeca106725 5162 #define GPIO_ODR_ODR_6 0x00000040U
Kojto 122:f9eeca106725 5163 #define GPIO_ODR_ODR_7 0x00000080U
Kojto 122:f9eeca106725 5164 #define GPIO_ODR_ODR_8 0x00000100U
Kojto 122:f9eeca106725 5165 #define GPIO_ODR_ODR_9 0x00000200U
Kojto 122:f9eeca106725 5166 #define GPIO_ODR_ODR_10 0x00000400U
Kojto 122:f9eeca106725 5167 #define GPIO_ODR_ODR_11 0x00000800U
Kojto 122:f9eeca106725 5168 #define GPIO_ODR_ODR_12 0x00001000U
Kojto 122:f9eeca106725 5169 #define GPIO_ODR_ODR_13 0x00002000U
Kojto 122:f9eeca106725 5170 #define GPIO_ODR_ODR_14 0x00004000U
Kojto 122:f9eeca106725 5171 #define GPIO_ODR_ODR_15 0x00008000U
Kojto 122:f9eeca106725 5172
Kojto 122:f9eeca106725 5173 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 122:f9eeca106725 5174 #define GPIO_BSRR_BS_0 0x00000001U
Kojto 122:f9eeca106725 5175 #define GPIO_BSRR_BS_1 0x00000002U
Kojto 122:f9eeca106725 5176 #define GPIO_BSRR_BS_2 0x00000004U
Kojto 122:f9eeca106725 5177 #define GPIO_BSRR_BS_3 0x00000008U
Kojto 122:f9eeca106725 5178 #define GPIO_BSRR_BS_4 0x00000010U
Kojto 122:f9eeca106725 5179 #define GPIO_BSRR_BS_5 0x00000020U
Kojto 122:f9eeca106725 5180 #define GPIO_BSRR_BS_6 0x00000040U
Kojto 122:f9eeca106725 5181 #define GPIO_BSRR_BS_7 0x00000080U
Kojto 122:f9eeca106725 5182 #define GPIO_BSRR_BS_8 0x00000100U
Kojto 122:f9eeca106725 5183 #define GPIO_BSRR_BS_9 0x00000200U
Kojto 122:f9eeca106725 5184 #define GPIO_BSRR_BS_10 0x00000400U
Kojto 122:f9eeca106725 5185 #define GPIO_BSRR_BS_11 0x00000800U
Kojto 122:f9eeca106725 5186 #define GPIO_BSRR_BS_12 0x00001000U
Kojto 122:f9eeca106725 5187 #define GPIO_BSRR_BS_13 0x00002000U
Kojto 122:f9eeca106725 5188 #define GPIO_BSRR_BS_14 0x00004000U
Kojto 122:f9eeca106725 5189 #define GPIO_BSRR_BS_15 0x00008000U
Kojto 122:f9eeca106725 5190 #define GPIO_BSRR_BR_0 0x00010000U
Kojto 122:f9eeca106725 5191 #define GPIO_BSRR_BR_1 0x00020000U
Kojto 122:f9eeca106725 5192 #define GPIO_BSRR_BR_2 0x00040000U
Kojto 122:f9eeca106725 5193 #define GPIO_BSRR_BR_3 0x00080000U
Kojto 122:f9eeca106725 5194 #define GPIO_BSRR_BR_4 0x00100000U
Kojto 122:f9eeca106725 5195 #define GPIO_BSRR_BR_5 0x00200000U
Kojto 122:f9eeca106725 5196 #define GPIO_BSRR_BR_6 0x00400000U
Kojto 122:f9eeca106725 5197 #define GPIO_BSRR_BR_7 0x00800000U
Kojto 122:f9eeca106725 5198 #define GPIO_BSRR_BR_8 0x01000000U
Kojto 122:f9eeca106725 5199 #define GPIO_BSRR_BR_9 0x02000000U
Kojto 122:f9eeca106725 5200 #define GPIO_BSRR_BR_10 0x04000000U
Kojto 122:f9eeca106725 5201 #define GPIO_BSRR_BR_11 0x08000000U
Kojto 122:f9eeca106725 5202 #define GPIO_BSRR_BR_12 0x10000000U
Kojto 122:f9eeca106725 5203 #define GPIO_BSRR_BR_13 0x20000000U
Kojto 122:f9eeca106725 5204 #define GPIO_BSRR_BR_14 0x40000000U
Kojto 122:f9eeca106725 5205 #define GPIO_BSRR_BR_15 0x80000000U
Kojto 122:f9eeca106725 5206
Kojto 122:f9eeca106725 5207 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 122:f9eeca106725 5208 #define GPIO_LCKR_LCK0 0x00000001U
Kojto 122:f9eeca106725 5209 #define GPIO_LCKR_LCK1 0x00000002U
Kojto 122:f9eeca106725 5210 #define GPIO_LCKR_LCK2 0x00000004U
Kojto 122:f9eeca106725 5211 #define GPIO_LCKR_LCK3 0x00000008U
Kojto 122:f9eeca106725 5212 #define GPIO_LCKR_LCK4 0x00000010U
Kojto 122:f9eeca106725 5213 #define GPIO_LCKR_LCK5 0x00000020U
Kojto 122:f9eeca106725 5214 #define GPIO_LCKR_LCK6 0x00000040U
Kojto 122:f9eeca106725 5215 #define GPIO_LCKR_LCK7 0x00000080U
Kojto 122:f9eeca106725 5216 #define GPIO_LCKR_LCK8 0x00000100U
Kojto 122:f9eeca106725 5217 #define GPIO_LCKR_LCK9 0x00000200U
Kojto 122:f9eeca106725 5218 #define GPIO_LCKR_LCK10 0x00000400U
Kojto 122:f9eeca106725 5219 #define GPIO_LCKR_LCK11 0x00000800U
Kojto 122:f9eeca106725 5220 #define GPIO_LCKR_LCK12 0x00001000U
Kojto 122:f9eeca106725 5221 #define GPIO_LCKR_LCK13 0x00002000U
Kojto 122:f9eeca106725 5222 #define GPIO_LCKR_LCK14 0x00004000U
Kojto 122:f9eeca106725 5223 #define GPIO_LCKR_LCK15 0x00008000U
Kojto 122:f9eeca106725 5224 #define GPIO_LCKR_LCKK 0x00010000U
Kojto 122:f9eeca106725 5225
Kojto 122:f9eeca106725 5226
Kojto 122:f9eeca106725 5227 /******************************************************************************/
Kojto 122:f9eeca106725 5228 /* */
Kojto 122:f9eeca106725 5229 /* Inter-integrated Circuit Interface (I2C) */
Kojto 122:f9eeca106725 5230 /* */
Kojto 122:f9eeca106725 5231 /******************************************************************************/
Kojto 122:f9eeca106725 5232 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 122:f9eeca106725 5233 #define I2C_CR1_PE 0x00000001U /*!< Peripheral enable */
Kojto 122:f9eeca106725 5234 #define I2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
Kojto 122:f9eeca106725 5235 #define I2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
Kojto 122:f9eeca106725 5236 #define I2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
Kojto 122:f9eeca106725 5237 #define I2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
Kojto 122:f9eeca106725 5238 #define I2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
Kojto 122:f9eeca106725 5239 #define I2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 5240 #define I2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
Kojto 122:f9eeca106725 5241 #define I2C_CR1_DNF 0x00000F00U /*!< Digital noise filter */
Kojto 122:f9eeca106725 5242 #define I2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
Kojto 122:f9eeca106725 5243 #define I2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
Kojto 122:f9eeca106725 5244 #define I2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
Kojto 122:f9eeca106725 5245 #define I2C_CR1_SBC 0x00010000U /*!< Slave byte control */
Kojto 122:f9eeca106725 5246 #define I2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
Kojto 122:f9eeca106725 5247 #define I2C_CR1_GCEN 0x00080000U /*!< General call enable */
Kojto 122:f9eeca106725 5248 #define I2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
Kojto 122:f9eeca106725 5249 #define I2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
Kojto 122:f9eeca106725 5250 #define I2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
Kojto 122:f9eeca106725 5251 #define I2C_CR1_PECEN 0x00800000U /*!< PEC enable */
Kojto 122:f9eeca106725 5252
Kojto 122:f9eeca106725 5253
Kojto 122:f9eeca106725 5254 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 5255 #define I2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
Kojto 122:f9eeca106725 5256 #define I2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
Kojto 122:f9eeca106725 5257 #define I2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
Kojto 122:f9eeca106725 5258 #define I2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
Kojto 122:f9eeca106725 5259 #define I2C_CR2_START 0x00002000U /*!< START generation */
Kojto 122:f9eeca106725 5260 #define I2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
Kojto 122:f9eeca106725 5261 #define I2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
Kojto 122:f9eeca106725 5262 #define I2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
Kojto 122:f9eeca106725 5263 #define I2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
Kojto 122:f9eeca106725 5264 #define I2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
Kojto 122:f9eeca106725 5265 #define I2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
Kojto 122:f9eeca106725 5266
Kojto 122:f9eeca106725 5267 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 122:f9eeca106725 5268 #define I2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
Kojto 122:f9eeca106725 5269 #define I2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
Kojto 122:f9eeca106725 5270 #define I2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
Kojto 122:f9eeca106725 5271
Kojto 122:f9eeca106725 5272 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 122:f9eeca106725 5273 #define I2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
Kojto 122:f9eeca106725 5274 #define I2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
Kojto 122:f9eeca106725 5275 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
Kojto 122:f9eeca106725 5276 #define I2C_OAR2_OA2MASK01 0x00000100U /*!< OA2[1] is masked, Only OA2[7:2] are compared */
Kojto 122:f9eeca106725 5277 #define I2C_OAR2_OA2MASK02 0x00000200U /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
Kojto 122:f9eeca106725 5278 #define I2C_OAR2_OA2MASK03 0x00000300U /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
Kojto 122:f9eeca106725 5279 #define I2C_OAR2_OA2MASK04 0x00000400U /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
Kojto 122:f9eeca106725 5280 #define I2C_OAR2_OA2MASK05 0x00000500U /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
Kojto 122:f9eeca106725 5281 #define I2C_OAR2_OA2MASK06 0x00000600U /*!< OA2[6:1] is masked, Only OA2[7] are compared */
Kojto 122:f9eeca106725 5282 #define I2C_OAR2_OA2MASK07 0x00000700U /*!< OA2[7:1] is masked, No comparison is done */
Kojto 122:f9eeca106725 5283 #define I2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
Kojto 122:f9eeca106725 5284
Kojto 122:f9eeca106725 5285 /******************* Bit definition for I2C_TIMINGR register *******************/
Kojto 122:f9eeca106725 5286 #define I2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
Kojto 122:f9eeca106725 5287 #define I2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
Kojto 122:f9eeca106725 5288 #define I2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
Kojto 122:f9eeca106725 5289 #define I2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
Kojto 122:f9eeca106725 5290 #define I2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
Kojto 122:f9eeca106725 5291
Kojto 122:f9eeca106725 5292 /******************* Bit definition for I2C_TIMEOUTR register *******************/
Kojto 122:f9eeca106725 5293 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
Kojto 122:f9eeca106725 5294 #define I2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
Kojto 122:f9eeca106725 5295 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
Kojto 122:f9eeca106725 5296 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
Kojto 122:f9eeca106725 5297 #define I2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
Kojto 122:f9eeca106725 5298
Kojto 122:f9eeca106725 5299 /****************** Bit definition for I2C_ISR register *********************/
Kojto 122:f9eeca106725 5300 #define I2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
Kojto 122:f9eeca106725 5301 #define I2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
Kojto 122:f9eeca106725 5302 #define I2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
Kojto 122:f9eeca106725 5303 #define I2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
Kojto 122:f9eeca106725 5304 #define I2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
Kojto 122:f9eeca106725 5305 #define I2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
Kojto 122:f9eeca106725 5306 #define I2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
Kojto 122:f9eeca106725 5307 #define I2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
Kojto 122:f9eeca106725 5308 #define I2C_ISR_BERR 0x00000100U /*!< Bus error */
Kojto 122:f9eeca106725 5309 #define I2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
Kojto 122:f9eeca106725 5310 #define I2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
Kojto 122:f9eeca106725 5311 #define I2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
Kojto 122:f9eeca106725 5312 #define I2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
Kojto 122:f9eeca106725 5313 #define I2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
Kojto 122:f9eeca106725 5314 #define I2C_ISR_BUSY 0x00008000U /*!< Bus busy */
Kojto 122:f9eeca106725 5315 #define I2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
Kojto 122:f9eeca106725 5316 #define I2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
Kojto 122:f9eeca106725 5317
Kojto 122:f9eeca106725 5318 /****************** Bit definition for I2C_ICR register *********************/
Kojto 122:f9eeca106725 5319 #define I2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
Kojto 122:f9eeca106725 5320 #define I2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
Kojto 122:f9eeca106725 5321 #define I2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
Kojto 122:f9eeca106725 5322 #define I2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
Kojto 122:f9eeca106725 5323 #define I2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
Kojto 122:f9eeca106725 5324 #define I2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
Kojto 122:f9eeca106725 5325 #define I2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
Kojto 122:f9eeca106725 5326 #define I2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
Kojto 122:f9eeca106725 5327 #define I2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
Kojto 122:f9eeca106725 5328
Kojto 122:f9eeca106725 5329 /****************** Bit definition for I2C_PECR register *********************/
Kojto 122:f9eeca106725 5330 #define I2C_PECR_PEC 0x000000FFU /*!< PEC register */
Kojto 122:f9eeca106725 5331
Kojto 122:f9eeca106725 5332 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 122:f9eeca106725 5333 #define I2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
Kojto 122:f9eeca106725 5334
Kojto 122:f9eeca106725 5335 /****************** Bit definition for I2C_TXDR register *********************/
Kojto 122:f9eeca106725 5336 #define I2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
Kojto 122:f9eeca106725 5337
Kojto 122:f9eeca106725 5338
Kojto 122:f9eeca106725 5339 /******************************************************************************/
Kojto 122:f9eeca106725 5340 /* */
Kojto 122:f9eeca106725 5341 /* Independent WATCHDOG */
Kojto 122:f9eeca106725 5342 /* */
Kojto 122:f9eeca106725 5343 /******************************************************************************/
Kojto 122:f9eeca106725 5344 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 5345 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
Kojto 122:f9eeca106725 5346
Kojto 122:f9eeca106725 5347 /******************* Bit definition for IWDG_PR register ********************/
Kojto 122:f9eeca106725 5348 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 5349 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 5350 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 5351 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
Kojto 122:f9eeca106725 5352
Kojto 122:f9eeca106725 5353 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 122:f9eeca106725 5354 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
Kojto 122:f9eeca106725 5355
Kojto 122:f9eeca106725 5356 /******************* Bit definition for IWDG_SR register ********************/
Kojto 122:f9eeca106725 5357 #define IWDG_SR_PVU 0x01U /*!< Watchdog prescaler value update */
Kojto 122:f9eeca106725 5358 #define IWDG_SR_RVU 0x02U /*!< Watchdog counter reload value update */
Kojto 122:f9eeca106725 5359 #define IWDG_SR_WVU 0x04U /*!< Watchdog counter window value update */
Kojto 122:f9eeca106725 5360
Kojto 122:f9eeca106725 5361 /******************* Bit definition for IWDG_KR register ********************/
Kojto 122:f9eeca106725 5362 #define IWDG_WINR_WIN 0x0FFFU /*!< Watchdog counter window value */
Kojto 122:f9eeca106725 5363
Kojto 122:f9eeca106725 5364 /******************************************************************************/
Kojto 122:f9eeca106725 5365 /* */
Kojto 122:f9eeca106725 5366 /* LCD-TFT Display Controller (LTDC) */
Kojto 122:f9eeca106725 5367 /* */
Kojto 122:f9eeca106725 5368 /******************************************************************************/
Kojto 122:f9eeca106725 5369
Kojto 122:f9eeca106725 5370 /******************** Bit definition for LTDC_SSCR register *****************/
Kojto 122:f9eeca106725 5371
Kojto 122:f9eeca106725 5372 #define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
Kojto 122:f9eeca106725 5373 #define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
Kojto 122:f9eeca106725 5374
Kojto 122:f9eeca106725 5375 /******************** Bit definition for LTDC_BPCR register *****************/
Kojto 122:f9eeca106725 5376
Kojto 122:f9eeca106725 5377 #define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
Kojto 122:f9eeca106725 5378 #define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
Kojto 122:f9eeca106725 5379
Kojto 122:f9eeca106725 5380 /******************** Bit definition for LTDC_AWCR register *****************/
Kojto 122:f9eeca106725 5381
Kojto 122:f9eeca106725 5382 #define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
Kojto 122:f9eeca106725 5383 #define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
Kojto 122:f9eeca106725 5384
Kojto 122:f9eeca106725 5385 /******************** Bit definition for LTDC_TWCR register *****************/
Kojto 122:f9eeca106725 5386
Kojto 122:f9eeca106725 5387 #define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
Kojto 122:f9eeca106725 5388 #define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
Kojto 122:f9eeca106725 5389
Kojto 122:f9eeca106725 5390 /******************** Bit definition for LTDC_GCR register ******************/
Kojto 122:f9eeca106725 5391
Kojto 122:f9eeca106725 5392 #define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
Kojto 122:f9eeca106725 5393 #define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
Kojto 122:f9eeca106725 5394 #define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
Kojto 122:f9eeca106725 5395 #define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
Kojto 122:f9eeca106725 5396 #define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
Kojto 122:f9eeca106725 5397 #define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
Kojto 122:f9eeca106725 5398 #define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
Kojto 122:f9eeca106725 5399 #define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
Kojto 122:f9eeca106725 5400 #define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
Kojto 122:f9eeca106725 5401
Kojto 122:f9eeca106725 5402
Kojto 122:f9eeca106725 5403 /******************** Bit definition for LTDC_SRCR register *****************/
Kojto 122:f9eeca106725 5404
Kojto 122:f9eeca106725 5405 #define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
Kojto 122:f9eeca106725 5406 #define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
Kojto 122:f9eeca106725 5407
Kojto 122:f9eeca106725 5408 /******************** Bit definition for LTDC_BCCR register *****************/
Kojto 122:f9eeca106725 5409
Kojto 122:f9eeca106725 5410 #define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
Kojto 122:f9eeca106725 5411 #define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
Kojto 122:f9eeca106725 5412 #define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
Kojto 122:f9eeca106725 5413
Kojto 122:f9eeca106725 5414 /******************** Bit definition for LTDC_IER register ******************/
Kojto 122:f9eeca106725 5415
Kojto 122:f9eeca106725 5416 #define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
Kojto 122:f9eeca106725 5417 #define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
Kojto 122:f9eeca106725 5418 #define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
Kojto 122:f9eeca106725 5419 #define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
Kojto 122:f9eeca106725 5420
Kojto 122:f9eeca106725 5421 /******************** Bit definition for LTDC_ISR register ******************/
Kojto 122:f9eeca106725 5422
Kojto 122:f9eeca106725 5423 #define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
Kojto 122:f9eeca106725 5424 #define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
Kojto 122:f9eeca106725 5425 #define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
Kojto 122:f9eeca106725 5426 #define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
Kojto 122:f9eeca106725 5427
Kojto 122:f9eeca106725 5428 /******************** Bit definition for LTDC_ICR register ******************/
Kojto 122:f9eeca106725 5429
Kojto 122:f9eeca106725 5430 #define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
Kojto 122:f9eeca106725 5431 #define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
Kojto 122:f9eeca106725 5432 #define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
Kojto 122:f9eeca106725 5433 #define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
Kojto 122:f9eeca106725 5434
Kojto 122:f9eeca106725 5435 /******************** Bit definition for LTDC_LIPCR register ****************/
Kojto 122:f9eeca106725 5436
Kojto 122:f9eeca106725 5437 #define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
Kojto 122:f9eeca106725 5438
Kojto 122:f9eeca106725 5439 /******************** Bit definition for LTDC_CPSR register *****************/
Kojto 122:f9eeca106725 5440
Kojto 122:f9eeca106725 5441 #define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
Kojto 122:f9eeca106725 5442 #define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
Kojto 122:f9eeca106725 5443
Kojto 122:f9eeca106725 5444 /******************** Bit definition for LTDC_CDSR register *****************/
Kojto 122:f9eeca106725 5445
Kojto 122:f9eeca106725 5446 #define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
Kojto 122:f9eeca106725 5447 #define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
Kojto 122:f9eeca106725 5448 #define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
Kojto 122:f9eeca106725 5449 #define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
Kojto 122:f9eeca106725 5450
Kojto 122:f9eeca106725 5451 /******************** Bit definition for LTDC_LxCR register *****************/
Kojto 122:f9eeca106725 5452
Kojto 122:f9eeca106725 5453 #define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
Kojto 122:f9eeca106725 5454 #define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
Kojto 122:f9eeca106725 5455 #define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
Kojto 122:f9eeca106725 5456
Kojto 122:f9eeca106725 5457 /******************** Bit definition for LTDC_LxWHPCR register **************/
Kojto 122:f9eeca106725 5458
Kojto 122:f9eeca106725 5459 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
Kojto 122:f9eeca106725 5460 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
Kojto 122:f9eeca106725 5461
Kojto 122:f9eeca106725 5462 /******************** Bit definition for LTDC_LxWVPCR register **************/
Kojto 122:f9eeca106725 5463
Kojto 122:f9eeca106725 5464 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
Kojto 122:f9eeca106725 5465 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
Kojto 122:f9eeca106725 5466
Kojto 122:f9eeca106725 5467 /******************** Bit definition for LTDC_LxCKCR register ***************/
Kojto 122:f9eeca106725 5468
Kojto 122:f9eeca106725 5469 #define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
Kojto 122:f9eeca106725 5470 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
Kojto 122:f9eeca106725 5471 #define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
Kojto 122:f9eeca106725 5472
Kojto 122:f9eeca106725 5473 /******************** Bit definition for LTDC_LxPFCR register ***************/
Kojto 122:f9eeca106725 5474
Kojto 122:f9eeca106725 5475 #define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
Kojto 122:f9eeca106725 5476
Kojto 122:f9eeca106725 5477 /******************** Bit definition for LTDC_LxCACR register ***************/
Kojto 122:f9eeca106725 5478
Kojto 122:f9eeca106725 5479 #define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
Kojto 122:f9eeca106725 5480
Kojto 122:f9eeca106725 5481 /******************** Bit definition for LTDC_LxDCCR register ***************/
Kojto 122:f9eeca106725 5482
Kojto 122:f9eeca106725 5483 #define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
Kojto 122:f9eeca106725 5484 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
Kojto 122:f9eeca106725 5485 #define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
Kojto 122:f9eeca106725 5486 #define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
Kojto 122:f9eeca106725 5487
Kojto 122:f9eeca106725 5488 /******************** Bit definition for LTDC_LxBFCR register ***************/
Kojto 122:f9eeca106725 5489
Kojto 122:f9eeca106725 5490 #define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
Kojto 122:f9eeca106725 5491 #define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
Kojto 122:f9eeca106725 5492
Kojto 122:f9eeca106725 5493 /******************** Bit definition for LTDC_LxCFBAR register **************/
Kojto 122:f9eeca106725 5494
Kojto 122:f9eeca106725 5495 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
Kojto 122:f9eeca106725 5496
Kojto 122:f9eeca106725 5497 /******************** Bit definition for LTDC_LxCFBLR register **************/
Kojto 122:f9eeca106725 5498
Kojto 122:f9eeca106725 5499 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
Kojto 122:f9eeca106725 5500 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
Kojto 122:f9eeca106725 5501
Kojto 122:f9eeca106725 5502 /******************** Bit definition for LTDC_LxCFBLNR register *************/
Kojto 122:f9eeca106725 5503
Kojto 122:f9eeca106725 5504 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
Kojto 122:f9eeca106725 5505
Kojto 122:f9eeca106725 5506 /******************** Bit definition for LTDC_LxCLUTWR register *************/
Kojto 122:f9eeca106725 5507
Kojto 122:f9eeca106725 5508 #define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
Kojto 122:f9eeca106725 5509 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
Kojto 122:f9eeca106725 5510 #define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
Kojto 122:f9eeca106725 5511 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
Kojto 122:f9eeca106725 5512
Kojto 122:f9eeca106725 5513 /******************************************************************************/
Kojto 122:f9eeca106725 5514 /* */
Kojto 122:f9eeca106725 5515 /* Power Control */
Kojto 122:f9eeca106725 5516 /* */
Kojto 122:f9eeca106725 5517 /******************************************************************************/
Kojto 122:f9eeca106725 5518 /******************** Bit definition for PWR_CR1 register ********************/
Kojto 122:f9eeca106725 5519 #define PWR_CR1_LPDS 0x00000001U /*!< Low-Power Deepsleep */
Kojto 122:f9eeca106725 5520 #define PWR_CR1_PDDS 0x00000002U /*!< Power Down Deepsleep */
Kojto 122:f9eeca106725 5521 #define PWR_CR1_CSBF 0x00000008U /*!< Clear Standby Flag */
Kojto 122:f9eeca106725 5522 #define PWR_CR1_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
Kojto 122:f9eeca106725 5523 #define PWR_CR1_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 122:f9eeca106725 5524 #define PWR_CR1_PLS_0 0x00000020U /*!< Bit 0 */
Kojto 122:f9eeca106725 5525 #define PWR_CR1_PLS_1 0x00000040U /*!< Bit 1 */
Kojto 122:f9eeca106725 5526 #define PWR_CR1_PLS_2 0x00000080U /*!< Bit 2 */
Kojto 122:f9eeca106725 5527
Kojto 122:f9eeca106725 5528 /*!< PVD level configuration */
Kojto 122:f9eeca106725 5529 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
Kojto 122:f9eeca106725 5530 #define PWR_CR1_PLS_LEV1 0x00000020U /*!< PVD level 1 */
Kojto 122:f9eeca106725 5531 #define PWR_CR1_PLS_LEV2 0x00000040U /*!< PVD level 2 */
Kojto 122:f9eeca106725 5532 #define PWR_CR1_PLS_LEV3 0x00000060U /*!< PVD level 3 */
Kojto 122:f9eeca106725 5533 #define PWR_CR1_PLS_LEV4 0x00000080U /*!< PVD level 4 */
Kojto 122:f9eeca106725 5534 #define PWR_CR1_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
Kojto 122:f9eeca106725 5535 #define PWR_CR1_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
Kojto 122:f9eeca106725 5536 #define PWR_CR1_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
Kojto 122:f9eeca106725 5537 #define PWR_CR1_DBP 0x00000100U /*!< Disable Backup Domain write protection */
Kojto 122:f9eeca106725 5538 #define PWR_CR1_FPDS 0x00000200U /*!< Flash power down in Stop mode */
Kojto 122:f9eeca106725 5539 #define PWR_CR1_LPUDS 0x00000400U /*!< Low-power regulator in deepsleep under-drive mode */
Kojto 122:f9eeca106725 5540 #define PWR_CR1_MRUDS 0x00000800U /*!< Main regulator in deepsleep under-drive mode */
Kojto 122:f9eeca106725 5541 #define PWR_CR1_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 5542 #define PWR_CR1_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 122:f9eeca106725 5543 #define PWR_CR1_VOS_0 0x00004000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5544 #define PWR_CR1_VOS_1 0x00008000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5545 #define PWR_CR1_ODEN 0x00010000U /*!< Over Drive enable */
Kojto 122:f9eeca106725 5546 #define PWR_CR1_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
Kojto 122:f9eeca106725 5547 #define PWR_CR1_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
Kojto 122:f9eeca106725 5548 #define PWR_CR1_UDEN_0 0x00040000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5549 #define PWR_CR1_UDEN_1 0x00080000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5550
Kojto 122:f9eeca106725 5551 /******************* Bit definition for PWR_CSR1 register ********************/
Kojto 122:f9eeca106725 5552 #define PWR_CSR1_WUIF 0x00000001U /*!< Wake up internal Flag */
Kojto 122:f9eeca106725 5553 #define PWR_CSR1_SBF 0x00000002U /*!< Standby Flag */
Kojto 122:f9eeca106725 5554 #define PWR_CSR1_PVDO 0x00000004U /*!< PVD Output */
Kojto 122:f9eeca106725 5555 #define PWR_CSR1_BRR 0x00000008U /*!< Backup regulator ready */
Kojto 122:f9eeca106725 5556 #define PWR_CSR1_EIWUP 0x00000100U /*!< Enable internal wakeup */
Kojto 122:f9eeca106725 5557 #define PWR_CSR1_BRE 0x00000200U /*!< Backup regulator enable */
Kojto 122:f9eeca106725 5558 #define PWR_CSR1_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
Kojto 122:f9eeca106725 5559 #define PWR_CSR1_ODRDY 0x00010000U /*!< Over Drive generator ready */
Kojto 122:f9eeca106725 5560 #define PWR_CSR1_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
Kojto 122:f9eeca106725 5561 #define PWR_CSR1_UDRDY 0x000C0000U /*!< Under Drive ready */
Kojto 122:f9eeca106725 5562
Kojto 122:f9eeca106725 5563
Kojto 122:f9eeca106725 5564 /******************** Bit definition for PWR_CR2 register ********************/
Kojto 122:f9eeca106725 5565 #define PWR_CR2_CWUPF1 0x00000001U /*!< Clear Wakeup Pin Flag for PA0 */
Kojto 122:f9eeca106725 5566 #define PWR_CR2_CWUPF2 0x00000002U /*!< Clear Wakeup Pin Flag for PA2 */
Kojto 122:f9eeca106725 5567 #define PWR_CR2_CWUPF3 0x00000004U /*!< Clear Wakeup Pin Flag for PC1 */
Kojto 122:f9eeca106725 5568 #define PWR_CR2_CWUPF4 0x00000008U /*!< Clear Wakeup Pin Flag for PC13 */
Kojto 122:f9eeca106725 5569 #define PWR_CR2_CWUPF5 0x00000010U /*!< Clear Wakeup Pin Flag for PI8 */
Kojto 122:f9eeca106725 5570 #define PWR_CR2_CWUPF6 0x00000020U /*!< Clear Wakeup Pin Flag for PI11 */
Kojto 122:f9eeca106725 5571 #define PWR_CR2_WUPP1 0x00000100U /*!< Wakeup Pin Polarity bit for PA0 */
Kojto 122:f9eeca106725 5572 #define PWR_CR2_WUPP2 0x00000200U /*!< Wakeup Pin Polarity bit for PA2 */
Kojto 122:f9eeca106725 5573 #define PWR_CR2_WUPP3 0x00000400U /*!< Wakeup Pin Polarity bit for PC1 */
Kojto 122:f9eeca106725 5574 #define PWR_CR2_WUPP4 0x00000800U /*!< Wakeup Pin Polarity bit for PC13 */
Kojto 122:f9eeca106725 5575 #define PWR_CR2_WUPP5 0x00001000U /*!< Wakeup Pin Polarity bit for PI8 */
Kojto 122:f9eeca106725 5576 #define PWR_CR2_WUPP6 0x00002000U /*!< Wakeup Pin Polarity bit for PI11 */
Kojto 122:f9eeca106725 5577
Kojto 122:f9eeca106725 5578 /******************* Bit definition for PWR_CSR2 register ********************/
Kojto 122:f9eeca106725 5579 #define PWR_CSR2_WUPF1 0x00000001U /*!< Wakeup Pin Flag for PA0 */
Kojto 122:f9eeca106725 5580 #define PWR_CSR2_WUPF2 0x00000002U /*!< Wakeup Pin Flag for PA2 */
Kojto 122:f9eeca106725 5581 #define PWR_CSR2_WUPF3 0x00000004U /*!< Wakeup Pin Flag for PC1 */
Kojto 122:f9eeca106725 5582 #define PWR_CSR2_WUPF4 0x00000008U /*!< Wakeup Pin Flag for PC13 */
Kojto 122:f9eeca106725 5583 #define PWR_CSR2_WUPF5 0x00000010U /*!< Wakeup Pin Flag for PI8 */
Kojto 122:f9eeca106725 5584 #define PWR_CSR2_WUPF6 0x00000020U /*!< Wakeup Pin Flag for PI11 */
Kojto 122:f9eeca106725 5585 #define PWR_CSR2_EWUP1 0x00000100U /*!< Enable Wakeup Pin PA0 */
Kojto 122:f9eeca106725 5586 #define PWR_CSR2_EWUP2 0x00000200U /*!< Enable Wakeup Pin PA2 */
Kojto 122:f9eeca106725 5587 #define PWR_CSR2_EWUP3 0x00000400U /*!< Enable Wakeup Pin PC1 */
Kojto 122:f9eeca106725 5588 #define PWR_CSR2_EWUP4 0x00000800U /*!< Enable Wakeup Pin PC13 */
Kojto 122:f9eeca106725 5589 #define PWR_CSR2_EWUP5 0x00001000U /*!< Enable Wakeup Pin PI8 */
Kojto 122:f9eeca106725 5590 #define PWR_CSR2_EWUP6 0x00002000U /*!< Enable Wakeup Pin PI11 */
Kojto 122:f9eeca106725 5591
Kojto 122:f9eeca106725 5592 /******************************************************************************/
Kojto 122:f9eeca106725 5593 /* */
Kojto 122:f9eeca106725 5594 /* QUADSPI */
Kojto 122:f9eeca106725 5595 /* */
Kojto 122:f9eeca106725 5596 /******************************************************************************/
Kojto 122:f9eeca106725 5597 /***************** Bit definition for QUADSPI_CR register *******************/
Kojto 122:f9eeca106725 5598 #define QUADSPI_CR_EN 0x00000001U /*!< Enable */
Kojto 122:f9eeca106725 5599 #define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
Kojto 122:f9eeca106725 5600 #define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
Kojto 122:f9eeca106725 5601 #define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
Kojto 122:f9eeca106725 5602 #define QUADSPI_CR_SSHIFT 0x00000010U /*!< Sample Shift */
Kojto 122:f9eeca106725 5603 #define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
Kojto 122:f9eeca106725 5604 #define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
Kojto 122:f9eeca106725 5605 #define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[4:0] FIFO Level */
Kojto 122:f9eeca106725 5606 #define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 5607 #define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 5608 #define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
Kojto 122:f9eeca106725 5609 #define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
Kojto 122:f9eeca106725 5610 #define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
Kojto 122:f9eeca106725 5611 #define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
Kojto 122:f9eeca106725 5612 #define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
Kojto 122:f9eeca106725 5613 #define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
Kojto 122:f9eeca106725 5614 #define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
Kojto 122:f9eeca106725 5615 #define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 5616 #define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5617 #define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
Kojto 122:f9eeca106725 5618 #define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
Kojto 122:f9eeca106725 5619 #define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5620 #define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5621 #define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
Kojto 122:f9eeca106725 5622 #define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
Kojto 122:f9eeca106725 5623 #define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
Kojto 122:f9eeca106725 5624 #define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
Kojto 122:f9eeca106725 5625 #define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
Kojto 122:f9eeca106725 5626 #define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
Kojto 122:f9eeca106725 5627
Kojto 122:f9eeca106725 5628 /***************** Bit definition for QUADSPI_DCR register ******************/
Kojto 122:f9eeca106725 5629 #define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
Kojto 122:f9eeca106725 5630 #define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
Kojto 122:f9eeca106725 5631 #define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 5632 #define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 5633 #define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
Kojto 122:f9eeca106725 5634 #define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
Kojto 122:f9eeca106725 5635 #define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5636 #define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5637 #define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
Kojto 122:f9eeca106725 5638 #define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
Kojto 122:f9eeca106725 5639 #define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
Kojto 122:f9eeca106725 5640
Kojto 122:f9eeca106725 5641 /****************** Bit definition for QUADSPI_SR register *******************/
Kojto 122:f9eeca106725 5642 #define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
Kojto 122:f9eeca106725 5643 #define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
Kojto 122:f9eeca106725 5644 #define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
Kojto 122:f9eeca106725 5645 #define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
Kojto 122:f9eeca106725 5646 #define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
Kojto 122:f9eeca106725 5647 #define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
Kojto 122:f9eeca106725 5648 #define QUADSPI_SR_FLEVEL 0x00001F00U /*!< FIFO Threshlod Flag */
Kojto 122:f9eeca106725 5649 #define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 5650 #define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 5651 #define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
Kojto 122:f9eeca106725 5652 #define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
Kojto 122:f9eeca106725 5653 #define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
Kojto 122:f9eeca106725 5654
Kojto 122:f9eeca106725 5655 /****************** Bit definition for QUADSPI_FCR register ******************/
Kojto 122:f9eeca106725 5656 #define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
Kojto 122:f9eeca106725 5657 #define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
Kojto 122:f9eeca106725 5658 #define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
Kojto 122:f9eeca106725 5659 #define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
Kojto 122:f9eeca106725 5660
Kojto 122:f9eeca106725 5661 /****************** Bit definition for QUADSPI_DLR register ******************/
Kojto 122:f9eeca106725 5662 #define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
Kojto 122:f9eeca106725 5663
Kojto 122:f9eeca106725 5664 /****************** Bit definition for QUADSPI_CCR register ******************/
Kojto 122:f9eeca106725 5665 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
Kojto 122:f9eeca106725 5666 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
Kojto 122:f9eeca106725 5667 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
Kojto 122:f9eeca106725 5668 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
Kojto 122:f9eeca106725 5669 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
Kojto 122:f9eeca106725 5670 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
Kojto 122:f9eeca106725 5671 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
Kojto 122:f9eeca106725 5672 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
Kojto 122:f9eeca106725 5673 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
Kojto 122:f9eeca106725 5674 #define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
Kojto 122:f9eeca106725 5675 #define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 5676 #define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 5677 #define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
Kojto 122:f9eeca106725 5678 #define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
Kojto 122:f9eeca106725 5679 #define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
Kojto 122:f9eeca106725 5680 #define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
Kojto 122:f9eeca106725 5681 #define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5682 #define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5683 #define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
Kojto 122:f9eeca106725 5684 #define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5685 #define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5686 #define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
Kojto 122:f9eeca106725 5687 #define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5688 #define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5689 #define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
Kojto 122:f9eeca106725 5690 #define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5691 #define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5692 #define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
Kojto 122:f9eeca106725 5693 #define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
Kojto 122:f9eeca106725 5694 #define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
Kojto 122:f9eeca106725 5695 #define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
Kojto 122:f9eeca106725 5696 #define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5697 #define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5698 #define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
Kojto 122:f9eeca106725 5699 #define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5700 #define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5701 #define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
Kojto 122:f9eeca106725 5702 #define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
Kojto 122:f9eeca106725 5703 #define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
Kojto 122:f9eeca106725 5704 /****************** Bit definition for QUADSPI_AR register *******************/
Kojto 122:f9eeca106725 5705 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
Kojto 122:f9eeca106725 5706
Kojto 122:f9eeca106725 5707 /****************** Bit definition for QUADSPI_ABR register ******************/
Kojto 122:f9eeca106725 5708 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
Kojto 122:f9eeca106725 5709
Kojto 122:f9eeca106725 5710 /****************** Bit definition for QUADSPI_DR register *******************/
Kojto 122:f9eeca106725 5711 #define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
Kojto 122:f9eeca106725 5712
Kojto 122:f9eeca106725 5713 /****************** Bit definition for QUADSPI_PSMKR register ****************/
Kojto 122:f9eeca106725 5714 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
Kojto 122:f9eeca106725 5715
Kojto 122:f9eeca106725 5716 /****************** Bit definition for QUADSPI_PSMAR register ****************/
Kojto 122:f9eeca106725 5717 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
Kojto 122:f9eeca106725 5718
Kojto 122:f9eeca106725 5719 /****************** Bit definition for QUADSPI_PIR register *****************/
Kojto 122:f9eeca106725 5720 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
Kojto 122:f9eeca106725 5721
Kojto 122:f9eeca106725 5722 /****************** Bit definition for QUADSPI_LPTR register *****************/
Kojto 122:f9eeca106725 5723 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
Kojto 122:f9eeca106725 5724
Kojto 122:f9eeca106725 5725 /******************************************************************************/
Kojto 122:f9eeca106725 5726 /* */
Kojto 122:f9eeca106725 5727 /* Reset and Clock Control */
Kojto 122:f9eeca106725 5728 /* */
Kojto 122:f9eeca106725 5729 /******************************************************************************/
Kojto 122:f9eeca106725 5730 /******************** Bit definition for RCC_CR register ********************/
Kojto 122:f9eeca106725 5731 #define RCC_CR_HSION 0x00000001U
Kojto 122:f9eeca106725 5732 #define RCC_CR_HSIRDY 0x00000002U
Kojto 122:f9eeca106725 5733 #define RCC_CR_HSITRIM 0x000000F8U
Kojto 122:f9eeca106725 5734 #define RCC_CR_HSITRIM_0 0x00000008U /*!<Bit 0 */
Kojto 122:f9eeca106725 5735 #define RCC_CR_HSITRIM_1 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 5736 #define RCC_CR_HSITRIM_2 0x00000020U /*!<Bit 2 */
Kojto 122:f9eeca106725 5737 #define RCC_CR_HSITRIM_3 0x00000040U /*!<Bit 3 */
Kojto 122:f9eeca106725 5738 #define RCC_CR_HSITRIM_4 0x00000080U /*!<Bit 4 */
Kojto 122:f9eeca106725 5739 #define RCC_CR_HSICAL 0x0000FF00U
Kojto 122:f9eeca106725 5740 #define RCC_CR_HSICAL_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 5741 #define RCC_CR_HSICAL_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 5742 #define RCC_CR_HSICAL_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 5743 #define RCC_CR_HSICAL_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 5744 #define RCC_CR_HSICAL_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 5745 #define RCC_CR_HSICAL_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 5746 #define RCC_CR_HSICAL_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 5747 #define RCC_CR_HSICAL_7 0x00008000U /*!<Bit 7 */
Kojto 122:f9eeca106725 5748 #define RCC_CR_HSEON 0x00010000U
Kojto 122:f9eeca106725 5749 #define RCC_CR_HSERDY 0x00020000U
Kojto 122:f9eeca106725 5750 #define RCC_CR_HSEBYP 0x00040000U
Kojto 122:f9eeca106725 5751 #define RCC_CR_CSSON 0x00080000U
Kojto 122:f9eeca106725 5752 #define RCC_CR_PLLON 0x01000000U
Kojto 122:f9eeca106725 5753 #define RCC_CR_PLLRDY 0x02000000U
Kojto 122:f9eeca106725 5754 #define RCC_CR_PLLI2SON 0x04000000U
Kojto 122:f9eeca106725 5755 #define RCC_CR_PLLI2SRDY 0x08000000U
Kojto 122:f9eeca106725 5756 #define RCC_CR_PLLSAION 0x10000000U
Kojto 122:f9eeca106725 5757 #define RCC_CR_PLLSAIRDY 0x20000000U
Kojto 122:f9eeca106725 5758
Kojto 122:f9eeca106725 5759 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 122:f9eeca106725 5760 #define RCC_PLLCFGR_PLLM 0x0000003FU
Kojto 122:f9eeca106725 5761 #define RCC_PLLCFGR_PLLM_0 0x00000001U
Kojto 122:f9eeca106725 5762 #define RCC_PLLCFGR_PLLM_1 0x00000002U
Kojto 122:f9eeca106725 5763 #define RCC_PLLCFGR_PLLM_2 0x00000004U
Kojto 122:f9eeca106725 5764 #define RCC_PLLCFGR_PLLM_3 0x00000008U
Kojto 122:f9eeca106725 5765 #define RCC_PLLCFGR_PLLM_4 0x00000010U
Kojto 122:f9eeca106725 5766 #define RCC_PLLCFGR_PLLM_5 0x00000020U
Kojto 122:f9eeca106725 5767 #define RCC_PLLCFGR_PLLN 0x00007FC0U
Kojto 122:f9eeca106725 5768 #define RCC_PLLCFGR_PLLN_0 0x00000040U
Kojto 122:f9eeca106725 5769 #define RCC_PLLCFGR_PLLN_1 0x00000080U
Kojto 122:f9eeca106725 5770 #define RCC_PLLCFGR_PLLN_2 0x00000100U
Kojto 122:f9eeca106725 5771 #define RCC_PLLCFGR_PLLN_3 0x00000200U
Kojto 122:f9eeca106725 5772 #define RCC_PLLCFGR_PLLN_4 0x00000400U
Kojto 122:f9eeca106725 5773 #define RCC_PLLCFGR_PLLN_5 0x00000800U
Kojto 122:f9eeca106725 5774 #define RCC_PLLCFGR_PLLN_6 0x00001000U
Kojto 122:f9eeca106725 5775 #define RCC_PLLCFGR_PLLN_7 0x00002000U
Kojto 122:f9eeca106725 5776 #define RCC_PLLCFGR_PLLN_8 0x00004000U
Kojto 122:f9eeca106725 5777 #define RCC_PLLCFGR_PLLP 0x00030000U
Kojto 122:f9eeca106725 5778 #define RCC_PLLCFGR_PLLP_0 0x00010000U
Kojto 122:f9eeca106725 5779 #define RCC_PLLCFGR_PLLP_1 0x00020000U
Kojto 122:f9eeca106725 5780 #define RCC_PLLCFGR_PLLSRC 0x00400000U
Kojto 122:f9eeca106725 5781 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
Kojto 122:f9eeca106725 5782 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
Kojto 122:f9eeca106725 5783 #define RCC_PLLCFGR_PLLQ 0x0F000000U
Kojto 122:f9eeca106725 5784 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
Kojto 122:f9eeca106725 5785 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
Kojto 122:f9eeca106725 5786 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
Kojto 122:f9eeca106725 5787 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
Kojto 122:f9eeca106725 5788
Kojto 122:f9eeca106725 5789 #define RCC_PLLCFGR_PLLR 0x70000000U
Kojto 122:f9eeca106725 5790 #define RCC_PLLCFGR_PLLR_0 0x10000000U
Kojto 122:f9eeca106725 5791 #define RCC_PLLCFGR_PLLR_1 0x20000000U
Kojto 122:f9eeca106725 5792 #define RCC_PLLCFGR_PLLR_2 0x40000000U
Kojto 122:f9eeca106725 5793
Kojto 122:f9eeca106725 5794 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 122:f9eeca106725 5795 /*!< SW configuration */
Kojto 122:f9eeca106725 5796 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 5797 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
Kojto 122:f9eeca106725 5798 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
Kojto 122:f9eeca106725 5799 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 5800 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 5801 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
Kojto 122:f9eeca106725 5802
Kojto 122:f9eeca106725 5803 /*!< SWS configuration */
Kojto 122:f9eeca106725 5804 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 5805 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
Kojto 122:f9eeca106725 5806 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
Kojto 122:f9eeca106725 5807 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
Kojto 122:f9eeca106725 5808 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 5809 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
Kojto 122:f9eeca106725 5810
Kojto 122:f9eeca106725 5811 /*!< HPRE configuration */
Kojto 122:f9eeca106725 5812 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 5813 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
Kojto 122:f9eeca106725 5814 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
Kojto 122:f9eeca106725 5815 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
Kojto 122:f9eeca106725 5816 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
Kojto 122:f9eeca106725 5817
Kojto 122:f9eeca106725 5818 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 5819 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 5820 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 5821 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 5822 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 5823 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 5824 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 5825 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 5826 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
Kojto 122:f9eeca106725 5827
Kojto 122:f9eeca106725 5828 /*!< PPRE1 configuration */
Kojto 122:f9eeca106725 5829 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 122:f9eeca106725 5830 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
Kojto 122:f9eeca106725 5831 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
Kojto 122:f9eeca106725 5832 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
Kojto 122:f9eeca106725 5833
Kojto 122:f9eeca106725 5834 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
Kojto 122:f9eeca106725 5835 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 5836 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 5837 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 5838 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 5839
Kojto 122:f9eeca106725 5840 /*!< PPRE2 configuration */
Kojto 122:f9eeca106725 5841 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 122:f9eeca106725 5842 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
Kojto 122:f9eeca106725 5843 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
Kojto 122:f9eeca106725 5844 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
Kojto 122:f9eeca106725 5845
Kojto 122:f9eeca106725 5846 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
Kojto 122:f9eeca106725 5847 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 5848 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 5849 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 5850 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
Kojto 122:f9eeca106725 5851
Kojto 122:f9eeca106725 5852 /*!< RTCPRE configuration */
Kojto 122:f9eeca106725 5853 #define RCC_CFGR_RTCPRE 0x001F0000U
Kojto 122:f9eeca106725 5854 #define RCC_CFGR_RTCPRE_0 0x00010000U
Kojto 122:f9eeca106725 5855 #define RCC_CFGR_RTCPRE_1 0x00020000U
Kojto 122:f9eeca106725 5856 #define RCC_CFGR_RTCPRE_2 0x00040000U
Kojto 122:f9eeca106725 5857 #define RCC_CFGR_RTCPRE_3 0x00080000U
Kojto 122:f9eeca106725 5858 #define RCC_CFGR_RTCPRE_4 0x00100000U
Kojto 122:f9eeca106725 5859
Kojto 122:f9eeca106725 5860 /*!< MCO1 configuration */
Kojto 122:f9eeca106725 5861 #define RCC_CFGR_MCO1 0x00600000U
Kojto 122:f9eeca106725 5862 #define RCC_CFGR_MCO1_0 0x00200000U
Kojto 122:f9eeca106725 5863 #define RCC_CFGR_MCO1_1 0x00400000U
Kojto 122:f9eeca106725 5864
Kojto 122:f9eeca106725 5865 #define RCC_CFGR_I2SSRC 0x00800000U
Kojto 122:f9eeca106725 5866
Kojto 122:f9eeca106725 5867 #define RCC_CFGR_MCO1PRE 0x07000000U
Kojto 122:f9eeca106725 5868 #define RCC_CFGR_MCO1PRE_0 0x01000000U
Kojto 122:f9eeca106725 5869 #define RCC_CFGR_MCO1PRE_1 0x02000000U
Kojto 122:f9eeca106725 5870 #define RCC_CFGR_MCO1PRE_2 0x04000000U
Kojto 122:f9eeca106725 5871
Kojto 122:f9eeca106725 5872 #define RCC_CFGR_MCO2PRE 0x38000000U
Kojto 122:f9eeca106725 5873 #define RCC_CFGR_MCO2PRE_0 0x08000000U
Kojto 122:f9eeca106725 5874 #define RCC_CFGR_MCO2PRE_1 0x10000000U
Kojto 122:f9eeca106725 5875 #define RCC_CFGR_MCO2PRE_2 0x20000000U
Kojto 122:f9eeca106725 5876
Kojto 122:f9eeca106725 5877 #define RCC_CFGR_MCO2 0xC0000000U
Kojto 122:f9eeca106725 5878 #define RCC_CFGR_MCO2_0 0x40000000U
Kojto 122:f9eeca106725 5879 #define RCC_CFGR_MCO2_1 0x80000000U
Kojto 122:f9eeca106725 5880
Kojto 122:f9eeca106725 5881 /******************** Bit definition for RCC_CIR register *******************/
Kojto 122:f9eeca106725 5882 #define RCC_CIR_LSIRDYF 0x00000001U
Kojto 122:f9eeca106725 5883 #define RCC_CIR_LSERDYF 0x00000002U
Kojto 122:f9eeca106725 5884 #define RCC_CIR_HSIRDYF 0x00000004U
Kojto 122:f9eeca106725 5885 #define RCC_CIR_HSERDYF 0x00000008U
Kojto 122:f9eeca106725 5886 #define RCC_CIR_PLLRDYF 0x00000010U
Kojto 122:f9eeca106725 5887 #define RCC_CIR_PLLI2SRDYF 0x00000020U
Kojto 122:f9eeca106725 5888 #define RCC_CIR_PLLSAIRDYF 0x00000040U
Kojto 122:f9eeca106725 5889 #define RCC_CIR_CSSF 0x00000080U
Kojto 122:f9eeca106725 5890 #define RCC_CIR_LSIRDYIE 0x00000100U
Kojto 122:f9eeca106725 5891 #define RCC_CIR_LSERDYIE 0x00000200U
Kojto 122:f9eeca106725 5892 #define RCC_CIR_HSIRDYIE 0x00000400U
Kojto 122:f9eeca106725 5893 #define RCC_CIR_HSERDYIE 0x00000800U
Kojto 122:f9eeca106725 5894 #define RCC_CIR_PLLRDYIE 0x00001000U
Kojto 122:f9eeca106725 5895 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
Kojto 122:f9eeca106725 5896 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
Kojto 122:f9eeca106725 5897 #define RCC_CIR_LSIRDYC 0x00010000U
Kojto 122:f9eeca106725 5898 #define RCC_CIR_LSERDYC 0x00020000U
Kojto 122:f9eeca106725 5899 #define RCC_CIR_HSIRDYC 0x00040000U
Kojto 122:f9eeca106725 5900 #define RCC_CIR_HSERDYC 0x00080000U
Kojto 122:f9eeca106725 5901 #define RCC_CIR_PLLRDYC 0x00100000U
Kojto 122:f9eeca106725 5902 #define RCC_CIR_PLLI2SRDYC 0x00200000U
Kojto 122:f9eeca106725 5903 #define RCC_CIR_PLLSAIRDYC 0x00400000U
Kojto 122:f9eeca106725 5904 #define RCC_CIR_CSSC 0x00800000U
Kojto 122:f9eeca106725 5905
Kojto 122:f9eeca106725 5906 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 122:f9eeca106725 5907 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
Kojto 122:f9eeca106725 5908 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
Kojto 122:f9eeca106725 5909 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
Kojto 122:f9eeca106725 5910 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
Kojto 122:f9eeca106725 5911 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
Kojto 122:f9eeca106725 5912 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
Kojto 122:f9eeca106725 5913 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
Kojto 122:f9eeca106725 5914 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
Kojto 122:f9eeca106725 5915 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
Kojto 122:f9eeca106725 5916 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
Kojto 122:f9eeca106725 5917 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
Kojto 122:f9eeca106725 5918 #define RCC_AHB1RSTR_CRCRST 0x00001000U
Kojto 122:f9eeca106725 5919 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
Kojto 122:f9eeca106725 5920 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
Kojto 122:f9eeca106725 5921 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
Kojto 122:f9eeca106725 5922 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
Kojto 122:f9eeca106725 5923 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
Kojto 122:f9eeca106725 5924
Kojto 122:f9eeca106725 5925 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 122:f9eeca106725 5926 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
Kojto 122:f9eeca106725 5927 #define RCC_AHB2RSTR_JPEGRST 0x00000002U
Kojto 122:f9eeca106725 5928 #define RCC_AHB2RSTR_RNGRST 0x00000040U
Kojto 122:f9eeca106725 5929 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
Kojto 122:f9eeca106725 5930
Kojto 122:f9eeca106725 5931 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 122:f9eeca106725 5932
Kojto 122:f9eeca106725 5933 #define RCC_AHB3RSTR_FMCRST 0x00000001U
Kojto 122:f9eeca106725 5934 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
Kojto 122:f9eeca106725 5935
Kojto 122:f9eeca106725 5936 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 122:f9eeca106725 5937 #define RCC_APB1RSTR_TIM2RST 0x00000001U
Kojto 122:f9eeca106725 5938 #define RCC_APB1RSTR_TIM3RST 0x00000002U
Kojto 122:f9eeca106725 5939 #define RCC_APB1RSTR_TIM4RST 0x00000004U
Kojto 122:f9eeca106725 5940 #define RCC_APB1RSTR_TIM5RST 0x00000008U
Kojto 122:f9eeca106725 5941 #define RCC_APB1RSTR_TIM6RST 0x00000010U
Kojto 122:f9eeca106725 5942 #define RCC_APB1RSTR_TIM7RST 0x00000020U
Kojto 122:f9eeca106725 5943 #define RCC_APB1RSTR_TIM12RST 0x00000040U
Kojto 122:f9eeca106725 5944 #define RCC_APB1RSTR_TIM13RST 0x00000080U
Kojto 122:f9eeca106725 5945 #define RCC_APB1RSTR_TIM14RST 0x00000100U
Kojto 122:f9eeca106725 5946 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
Kojto 122:f9eeca106725 5947 #define RCC_APB1RSTR_WWDGRST 0x00000800U
Kojto 122:f9eeca106725 5948 #define RCC_APB1RSTR_CAN3RST 0x00002000U
Kojto 122:f9eeca106725 5949 #define RCC_APB1RSTR_SPI2RST 0x00004000U
Kojto 122:f9eeca106725 5950 #define RCC_APB1RSTR_SPI3RST 0x00008000U
Kojto 122:f9eeca106725 5951 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
Kojto 122:f9eeca106725 5952 #define RCC_APB1RSTR_USART2RST 0x00020000U
Kojto 122:f9eeca106725 5953 #define RCC_APB1RSTR_USART3RST 0x00040000U
Kojto 122:f9eeca106725 5954 #define RCC_APB1RSTR_UART4RST 0x00080000U
Kojto 122:f9eeca106725 5955 #define RCC_APB1RSTR_UART5RST 0x00100000U
Kojto 122:f9eeca106725 5956 #define RCC_APB1RSTR_I2C1RST 0x00200000U
Kojto 122:f9eeca106725 5957 #define RCC_APB1RSTR_I2C2RST 0x00400000U
Kojto 122:f9eeca106725 5958 #define RCC_APB1RSTR_I2C3RST 0x00800000U
Kojto 122:f9eeca106725 5959 #define RCC_APB1RSTR_I2C4RST 0x01000000U
Kojto 122:f9eeca106725 5960 #define RCC_APB1RSTR_CAN1RST 0x02000000U
Kojto 122:f9eeca106725 5961 #define RCC_APB1RSTR_CAN2RST 0x04000000U
Kojto 122:f9eeca106725 5962 #define RCC_APB1RSTR_CECRST 0x08000000U
Kojto 122:f9eeca106725 5963 #define RCC_APB1RSTR_PWRRST 0x10000000U
Kojto 122:f9eeca106725 5964 #define RCC_APB1RSTR_DACRST 0x20000000U
Kojto 122:f9eeca106725 5965 #define RCC_APB1RSTR_UART7RST 0x40000000U
Kojto 122:f9eeca106725 5966 #define RCC_APB1RSTR_UART8RST 0x80000000U
Kojto 122:f9eeca106725 5967
Kojto 122:f9eeca106725 5968 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 122:f9eeca106725 5969 #define RCC_APB2RSTR_TIM1RST 0x00000001U
Kojto 122:f9eeca106725 5970 #define RCC_APB2RSTR_TIM8RST 0x00000002U
Kojto 122:f9eeca106725 5971 #define RCC_APB2RSTR_USART1RST 0x00000010U
Kojto 122:f9eeca106725 5972 #define RCC_APB2RSTR_USART6RST 0x00000020U
Kojto 122:f9eeca106725 5973 #define RCC_APB2RSTR_SDMMC2RST 0x00000080U
Kojto 122:f9eeca106725 5974 #define RCC_APB2RSTR_ADCRST 0x00000100U
Kojto 122:f9eeca106725 5975 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
Kojto 122:f9eeca106725 5976 #define RCC_APB2RSTR_SPI1RST 0x00001000U
Kojto 122:f9eeca106725 5977 #define RCC_APB2RSTR_SPI4RST 0x00002000U
Kojto 122:f9eeca106725 5978 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
Kojto 122:f9eeca106725 5979 #define RCC_APB2RSTR_TIM9RST 0x00010000U
Kojto 122:f9eeca106725 5980 #define RCC_APB2RSTR_TIM10RST 0x00020000U
Kojto 122:f9eeca106725 5981 #define RCC_APB2RSTR_TIM11RST 0x00040000U
Kojto 122:f9eeca106725 5982 #define RCC_APB2RSTR_SPI5RST 0x00100000U
Kojto 122:f9eeca106725 5983 #define RCC_APB2RSTR_SPI6RST 0x00200000U
Kojto 122:f9eeca106725 5984 #define RCC_APB2RSTR_SAI1RST 0x00400000U
Kojto 122:f9eeca106725 5985 #define RCC_APB2RSTR_SAI2RST 0x00800000U
Kojto 122:f9eeca106725 5986 #define RCC_APB2RSTR_LTDCRST 0x04000000U
Kojto 122:f9eeca106725 5987 #define RCC_APB2RSTR_DFSDM1RST 0x20000000U
Kojto 122:f9eeca106725 5988 #define RCC_APB2RSTR_MDIORST 0x40000000U
Kojto 122:f9eeca106725 5989
Kojto 122:f9eeca106725 5990 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 122:f9eeca106725 5991 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
Kojto 122:f9eeca106725 5992 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
Kojto 122:f9eeca106725 5993 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
Kojto 122:f9eeca106725 5994 #define RCC_AHB1ENR_GPIODEN 0x00000008U
Kojto 122:f9eeca106725 5995 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
Kojto 122:f9eeca106725 5996 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
Kojto 122:f9eeca106725 5997 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
Kojto 122:f9eeca106725 5998 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
Kojto 122:f9eeca106725 5999 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
Kojto 122:f9eeca106725 6000 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
Kojto 122:f9eeca106725 6001 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
Kojto 122:f9eeca106725 6002 #define RCC_AHB1ENR_CRCEN 0x00001000U
Kojto 122:f9eeca106725 6003 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
Kojto 122:f9eeca106725 6004 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
Kojto 122:f9eeca106725 6005 #define RCC_AHB1ENR_DMA1EN 0x00200000U
Kojto 122:f9eeca106725 6006 #define RCC_AHB1ENR_DMA2EN 0x00400000U
Kojto 122:f9eeca106725 6007 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
Kojto 122:f9eeca106725 6008 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
Kojto 122:f9eeca106725 6009 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
Kojto 122:f9eeca106725 6010 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
Kojto 122:f9eeca106725 6011 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
Kojto 122:f9eeca106725 6012 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
Kojto 122:f9eeca106725 6013 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
Kojto 122:f9eeca106725 6014
Kojto 122:f9eeca106725 6015 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 122:f9eeca106725 6016 #define RCC_AHB2ENR_DCMIEN 0x00000001U
Kojto 122:f9eeca106725 6017 #define RCC_AHB2ENR_JPEGEN 0x00000002U
Kojto 122:f9eeca106725 6018 #define RCC_AHB2ENR_RNGEN 0x00000040U
Kojto 122:f9eeca106725 6019 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
Kojto 122:f9eeca106725 6020
Kojto 122:f9eeca106725 6021 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 122:f9eeca106725 6022 #define RCC_AHB3ENR_FMCEN 0x00000001U
Kojto 122:f9eeca106725 6023 #define RCC_AHB3ENR_QSPIEN 0x00000002U
Kojto 122:f9eeca106725 6024
Kojto 122:f9eeca106725 6025 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 122:f9eeca106725 6026 #define RCC_APB1ENR_TIM2EN 0x00000001U
Kojto 122:f9eeca106725 6027 #define RCC_APB1ENR_TIM3EN 0x00000002U
Kojto 122:f9eeca106725 6028 #define RCC_APB1ENR_TIM4EN 0x00000004U
Kojto 122:f9eeca106725 6029 #define RCC_APB1ENR_TIM5EN 0x00000008U
Kojto 122:f9eeca106725 6030 #define RCC_APB1ENR_TIM6EN 0x00000010U
Kojto 122:f9eeca106725 6031 #define RCC_APB1ENR_TIM7EN 0x00000020U
Kojto 122:f9eeca106725 6032 #define RCC_APB1ENR_TIM12EN 0x00000040U
Kojto 122:f9eeca106725 6033 #define RCC_APB1ENR_TIM13EN 0x00000080U
Kojto 122:f9eeca106725 6034 #define RCC_APB1ENR_TIM14EN 0x00000100U
Kojto 122:f9eeca106725 6035 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
Kojto 122:f9eeca106725 6036 #define RCC_APB1ENR_RTCEN 0x00000400U
Kojto 122:f9eeca106725 6037 #define RCC_APB1ENR_WWDGEN 0x00000800U
Kojto 122:f9eeca106725 6038 #define RCC_APB1ENR_CAN3EN 0x00002000U
Kojto 122:f9eeca106725 6039 #define RCC_APB1ENR_SPI2EN 0x00004000U
Kojto 122:f9eeca106725 6040 #define RCC_APB1ENR_SPI3EN 0x00008000U
Kojto 122:f9eeca106725 6041 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
Kojto 122:f9eeca106725 6042 #define RCC_APB1ENR_USART2EN 0x00020000U
Kojto 122:f9eeca106725 6043 #define RCC_APB1ENR_USART3EN 0x00040000U
Kojto 122:f9eeca106725 6044 #define RCC_APB1ENR_UART4EN 0x00080000U
Kojto 122:f9eeca106725 6045 #define RCC_APB1ENR_UART5EN 0x00100000U
Kojto 122:f9eeca106725 6046 #define RCC_APB1ENR_I2C1EN 0x00200000U
Kojto 122:f9eeca106725 6047 #define RCC_APB1ENR_I2C2EN 0x00400000U
Kojto 122:f9eeca106725 6048 #define RCC_APB1ENR_I2C3EN 0x00800000U
Kojto 122:f9eeca106725 6049 #define RCC_APB1ENR_I2C4EN 0x01000000U
Kojto 122:f9eeca106725 6050 #define RCC_APB1ENR_CAN1EN 0x02000000U
Kojto 122:f9eeca106725 6051 #define RCC_APB1ENR_CAN2EN 0x04000000U
Kojto 122:f9eeca106725 6052 #define RCC_APB1ENR_CECEN 0x08000000U
Kojto 122:f9eeca106725 6053 #define RCC_APB1ENR_PWREN 0x10000000U
Kojto 122:f9eeca106725 6054 #define RCC_APB1ENR_DACEN 0x20000000U
Kojto 122:f9eeca106725 6055 #define RCC_APB1ENR_UART7EN 0x40000000U
Kojto 122:f9eeca106725 6056 #define RCC_APB1ENR_UART8EN 0x80000000U
Kojto 122:f9eeca106725 6057
Kojto 122:f9eeca106725 6058 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 122:f9eeca106725 6059 #define RCC_APB2ENR_TIM1EN 0x00000001U
Kojto 122:f9eeca106725 6060 #define RCC_APB2ENR_TIM8EN 0x00000002U
Kojto 122:f9eeca106725 6061 #define RCC_APB2ENR_USART1EN 0x00000010U
Kojto 122:f9eeca106725 6062 #define RCC_APB2ENR_USART6EN 0x00000020U
Kojto 122:f9eeca106725 6063 #define RCC_APB2ENR_SDMMC2EN 0x00000080U
Kojto 122:f9eeca106725 6064 #define RCC_APB2ENR_ADC1EN 0x00000100U
Kojto 122:f9eeca106725 6065 #define RCC_APB2ENR_ADC2EN 0x00000200U
Kojto 122:f9eeca106725 6066 #define RCC_APB2ENR_ADC3EN 0x00000400U
Kojto 122:f9eeca106725 6067 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
Kojto 122:f9eeca106725 6068 #define RCC_APB2ENR_SPI1EN 0x00001000U
Kojto 122:f9eeca106725 6069 #define RCC_APB2ENR_SPI4EN 0x00002000U
Kojto 122:f9eeca106725 6070 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
Kojto 122:f9eeca106725 6071 #define RCC_APB2ENR_TIM9EN 0x00010000U
Kojto 122:f9eeca106725 6072 #define RCC_APB2ENR_TIM10EN 0x00020000U
Kojto 122:f9eeca106725 6073 #define RCC_APB2ENR_TIM11EN 0x00040000U
Kojto 122:f9eeca106725 6074 #define RCC_APB2ENR_SPI5EN 0x00100000U
Kojto 122:f9eeca106725 6075 #define RCC_APB2ENR_SPI6EN 0x00200000U
Kojto 122:f9eeca106725 6076 #define RCC_APB2ENR_SAI1EN 0x00400000U
Kojto 122:f9eeca106725 6077 #define RCC_APB2ENR_SAI2EN 0x00800000U
Kojto 122:f9eeca106725 6078 #define RCC_APB2ENR_LTDCEN 0x04000000U
Kojto 122:f9eeca106725 6079 #define RCC_APB2ENR_DFSDM1EN 0x20000000U
Kojto 122:f9eeca106725 6080 #define RCC_APB2ENR_MDIOEN 0x40000000U
Kojto 122:f9eeca106725 6081
Kojto 122:f9eeca106725 6082 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 122:f9eeca106725 6083 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
Kojto 122:f9eeca106725 6084 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
Kojto 122:f9eeca106725 6085 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
Kojto 122:f9eeca106725 6086 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
Kojto 122:f9eeca106725 6087 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
Kojto 122:f9eeca106725 6088 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
Kojto 122:f9eeca106725 6089 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
Kojto 122:f9eeca106725 6090 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
Kojto 122:f9eeca106725 6091 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
Kojto 122:f9eeca106725 6092 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
Kojto 122:f9eeca106725 6093 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
Kojto 122:f9eeca106725 6094 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
Kojto 122:f9eeca106725 6095 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
Kojto 122:f9eeca106725 6096 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
Kojto 122:f9eeca106725 6097 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
Kojto 122:f9eeca106725 6098 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
Kojto 122:f9eeca106725 6099 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
Kojto 122:f9eeca106725 6100 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
Kojto 122:f9eeca106725 6101 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
Kojto 122:f9eeca106725 6102 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
Kojto 122:f9eeca106725 6103 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
Kojto 122:f9eeca106725 6104 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
Kojto 122:f9eeca106725 6105 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
Kojto 122:f9eeca106725 6106 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
Kojto 122:f9eeca106725 6107 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
Kojto 122:f9eeca106725 6108 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
Kojto 122:f9eeca106725 6109 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
Kojto 122:f9eeca106725 6110
Kojto 122:f9eeca106725 6111 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 122:f9eeca106725 6112 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
Kojto 122:f9eeca106725 6113 #define RCC_AHB2LPENR_JPEGLPEN 0x00000002U
Kojto 122:f9eeca106725 6114 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
Kojto 122:f9eeca106725 6115 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
Kojto 122:f9eeca106725 6116
Kojto 122:f9eeca106725 6117 /******************** Bit definition for RCC_AHB3LPENR register *************/
Kojto 122:f9eeca106725 6118 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
Kojto 122:f9eeca106725 6119 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
Kojto 122:f9eeca106725 6120 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 122:f9eeca106725 6121 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
Kojto 122:f9eeca106725 6122 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
Kojto 122:f9eeca106725 6123 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
Kojto 122:f9eeca106725 6124 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
Kojto 122:f9eeca106725 6125 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
Kojto 122:f9eeca106725 6126 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
Kojto 122:f9eeca106725 6127 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
Kojto 122:f9eeca106725 6128 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
Kojto 122:f9eeca106725 6129 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
Kojto 122:f9eeca106725 6130 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
Kojto 122:f9eeca106725 6131 #define RCC_APB1LPENR_RTCLPEN 0x00000400U
Kojto 122:f9eeca106725 6132 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
Kojto 122:f9eeca106725 6133 #define RCC_APB1LPENR_CAN3LPEN 0x00002000U
Kojto 122:f9eeca106725 6134 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
Kojto 122:f9eeca106725 6135 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
Kojto 122:f9eeca106725 6136 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
Kojto 122:f9eeca106725 6137 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
Kojto 122:f9eeca106725 6138 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
Kojto 122:f9eeca106725 6139 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
Kojto 122:f9eeca106725 6140 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
Kojto 122:f9eeca106725 6141 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
Kojto 122:f9eeca106725 6142 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
Kojto 122:f9eeca106725 6143 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
Kojto 122:f9eeca106725 6144 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
Kojto 122:f9eeca106725 6145 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
Kojto 122:f9eeca106725 6146 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
Kojto 122:f9eeca106725 6147 #define RCC_APB1LPENR_CECLPEN 0x08000000U
Kojto 122:f9eeca106725 6148 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
Kojto 122:f9eeca106725 6149 #define RCC_APB1LPENR_DACLPEN 0x20000000U
Kojto 122:f9eeca106725 6150 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
Kojto 122:f9eeca106725 6151 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
Kojto 122:f9eeca106725 6152
Kojto 122:f9eeca106725 6153 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 122:f9eeca106725 6154 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
Kojto 122:f9eeca106725 6155 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
Kojto 122:f9eeca106725 6156 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
Kojto 122:f9eeca106725 6157 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
Kojto 122:f9eeca106725 6158 #define RCC_APB2LPENR_SDMMC2LPEN 0x00000080U
Kojto 122:f9eeca106725 6159 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
Kojto 122:f9eeca106725 6160 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
Kojto 122:f9eeca106725 6161 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
Kojto 122:f9eeca106725 6162 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
Kojto 122:f9eeca106725 6163 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
Kojto 122:f9eeca106725 6164 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
Kojto 122:f9eeca106725 6165 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
Kojto 122:f9eeca106725 6166 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
Kojto 122:f9eeca106725 6167 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
Kojto 122:f9eeca106725 6168 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
Kojto 122:f9eeca106725 6169 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
Kojto 122:f9eeca106725 6170 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
Kojto 122:f9eeca106725 6171 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
Kojto 122:f9eeca106725 6172 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
Kojto 122:f9eeca106725 6173 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
Kojto 122:f9eeca106725 6174 #define RCC_APB2LPENR_DFSDM1LPEN 0x20000000U
Kojto 122:f9eeca106725 6175 #define RCC_APB2LPENR_MDIOLPEN 0x40000000U
Kojto 122:f9eeca106725 6176
Kojto 122:f9eeca106725 6177 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 122:f9eeca106725 6178 #define RCC_BDCR_LSEON 0x00000001U
Kojto 122:f9eeca106725 6179 #define RCC_BDCR_LSERDY 0x00000002U
Kojto 122:f9eeca106725 6180 #define RCC_BDCR_LSEBYP 0x00000004U
Kojto 122:f9eeca106725 6181 #define RCC_BDCR_LSEDRV 0x00000018U
Kojto 122:f9eeca106725 6182 #define RCC_BDCR_LSEDRV_0 0x00000008U
Kojto 122:f9eeca106725 6183 #define RCC_BDCR_LSEDRV_1 0x00000010U
Kojto 122:f9eeca106725 6184 #define RCC_BDCR_RTCSEL 0x00000300U
Kojto 122:f9eeca106725 6185 #define RCC_BDCR_RTCSEL_0 0x00000100U
Kojto 122:f9eeca106725 6186 #define RCC_BDCR_RTCSEL_1 0x00000200U
Kojto 122:f9eeca106725 6187 #define RCC_BDCR_RTCEN 0x00008000U
Kojto 122:f9eeca106725 6188 #define RCC_BDCR_BDRST 0x00010000U
Kojto 122:f9eeca106725 6189
Kojto 122:f9eeca106725 6190 /******************** Bit definition for RCC_CSR register *******************/
Kojto 122:f9eeca106725 6191 #define RCC_CSR_LSION 0x00000001U
Kojto 122:f9eeca106725 6192 #define RCC_CSR_LSIRDY 0x00000002U
Kojto 122:f9eeca106725 6193 #define RCC_CSR_RMVF 0x01000000U
Kojto 122:f9eeca106725 6194 #define RCC_CSR_BORRSTF 0x02000000U
Kojto 122:f9eeca106725 6195 #define RCC_CSR_PINRSTF 0x04000000U
Kojto 122:f9eeca106725 6196 #define RCC_CSR_PORRSTF 0x08000000U
Kojto 122:f9eeca106725 6197 #define RCC_CSR_SFTRSTF 0x10000000U
Kojto 122:f9eeca106725 6198 #define RCC_CSR_IWDGRSTF 0x20000000U
Kojto 122:f9eeca106725 6199 #define RCC_CSR_WWDGRSTF 0x40000000U
Kojto 122:f9eeca106725 6200 #define RCC_CSR_LPWRRSTF 0x80000000U
Kojto 122:f9eeca106725 6201
Kojto 122:f9eeca106725 6202 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 122:f9eeca106725 6203 #define RCC_SSCGR_MODPER 0x00001FFFU
Kojto 122:f9eeca106725 6204 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
Kojto 122:f9eeca106725 6205 #define RCC_SSCGR_SPREADSEL 0x40000000U
Kojto 122:f9eeca106725 6206 #define RCC_SSCGR_SSCGEN 0x80000000U
Kojto 122:f9eeca106725 6207
Kojto 122:f9eeca106725 6208 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 122:f9eeca106725 6209 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
Kojto 122:f9eeca106725 6210 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
Kojto 122:f9eeca106725 6211 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
Kojto 122:f9eeca106725 6212 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
Kojto 122:f9eeca106725 6213 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
Kojto 122:f9eeca106725 6214 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
Kojto 122:f9eeca106725 6215 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
Kojto 122:f9eeca106725 6216 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
Kojto 122:f9eeca106725 6217 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
Kojto 122:f9eeca106725 6218 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
Kojto 122:f9eeca106725 6219 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
Kojto 122:f9eeca106725 6220 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
Kojto 122:f9eeca106725 6221 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
Kojto 122:f9eeca106725 6222 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
Kojto 122:f9eeca106725 6223 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
Kojto 122:f9eeca106725 6224 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
Kojto 122:f9eeca106725 6225 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
Kojto 122:f9eeca106725 6226 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
Kojto 122:f9eeca106725 6227 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
Kojto 122:f9eeca106725 6228 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
Kojto 122:f9eeca106725 6229 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
Kojto 122:f9eeca106725 6230 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
Kojto 122:f9eeca106725 6231
Kojto 122:f9eeca106725 6232 /******************** Bit definition for RCC_PLLSAICFGR register ************/
Kojto 122:f9eeca106725 6233 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
Kojto 122:f9eeca106725 6234 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
Kojto 122:f9eeca106725 6235 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
Kojto 122:f9eeca106725 6236 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
Kojto 122:f9eeca106725 6237 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
Kojto 122:f9eeca106725 6238 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
Kojto 122:f9eeca106725 6239 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
Kojto 122:f9eeca106725 6240 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
Kojto 122:f9eeca106725 6241 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
Kojto 122:f9eeca106725 6242 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
Kojto 122:f9eeca106725 6243 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
Kojto 122:f9eeca106725 6244 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
Kojto 122:f9eeca106725 6245 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
Kojto 122:f9eeca106725 6246 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
Kojto 122:f9eeca106725 6247 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
Kojto 122:f9eeca106725 6248 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
Kojto 122:f9eeca106725 6249 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
Kojto 122:f9eeca106725 6250 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
Kojto 122:f9eeca106725 6251 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
Kojto 122:f9eeca106725 6252 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
Kojto 122:f9eeca106725 6253 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
Kojto 122:f9eeca106725 6254 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
Kojto 122:f9eeca106725 6255
Kojto 122:f9eeca106725 6256 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
Kojto 122:f9eeca106725 6257 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
Kojto 122:f9eeca106725 6258 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
Kojto 122:f9eeca106725 6259 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
Kojto 122:f9eeca106725 6260 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
Kojto 122:f9eeca106725 6261 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
Kojto 122:f9eeca106725 6262 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
Kojto 122:f9eeca106725 6263
Kojto 122:f9eeca106725 6264 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
Kojto 122:f9eeca106725 6265 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
Kojto 122:f9eeca106725 6266 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
Kojto 122:f9eeca106725 6267 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
Kojto 122:f9eeca106725 6268 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
Kojto 122:f9eeca106725 6269 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
Kojto 122:f9eeca106725 6270
Kojto 122:f9eeca106725 6271 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
Kojto 122:f9eeca106725 6272 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
Kojto 122:f9eeca106725 6273 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
Kojto 122:f9eeca106725 6274
Kojto 122:f9eeca106725 6275 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
Kojto 122:f9eeca106725 6276 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
Kojto 122:f9eeca106725 6277 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
Kojto 122:f9eeca106725 6278
Kojto 122:f9eeca106725 6279 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
Kojto 122:f9eeca106725 6280 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
Kojto 122:f9eeca106725 6281 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
Kojto 122:f9eeca106725 6282
Kojto 122:f9eeca106725 6283 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
Kojto 122:f9eeca106725 6284 #define RCC_DCKCFGR1_DFSDM1SEL 0x02000000U
Kojto 122:f9eeca106725 6285 #define RCC_DCKCFGR1_ADFSDM1SEL 0x04000000U
Kojto 122:f9eeca106725 6286
Kojto 122:f9eeca106725 6287 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
Kojto 122:f9eeca106725 6288 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
Kojto 122:f9eeca106725 6289 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
Kojto 122:f9eeca106725 6290 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
Kojto 122:f9eeca106725 6291 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
Kojto 122:f9eeca106725 6292 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
Kojto 122:f9eeca106725 6293 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
Kojto 122:f9eeca106725 6294 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
Kojto 122:f9eeca106725 6295 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
Kojto 122:f9eeca106725 6296 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
Kojto 122:f9eeca106725 6297 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
Kojto 122:f9eeca106725 6298 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
Kojto 122:f9eeca106725 6299 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
Kojto 122:f9eeca106725 6300 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
Kojto 122:f9eeca106725 6301 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
Kojto 122:f9eeca106725 6302 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
Kojto 122:f9eeca106725 6303 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
Kojto 122:f9eeca106725 6304 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
Kojto 122:f9eeca106725 6305 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
Kojto 122:f9eeca106725 6306 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
Kojto 122:f9eeca106725 6307 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
Kojto 122:f9eeca106725 6308 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
Kojto 122:f9eeca106725 6309 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
Kojto 122:f9eeca106725 6310 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
Kojto 122:f9eeca106725 6311 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
Kojto 122:f9eeca106725 6312 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
Kojto 122:f9eeca106725 6313 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
Kojto 122:f9eeca106725 6314 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
Kojto 122:f9eeca106725 6315 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
Kojto 122:f9eeca106725 6316 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
Kojto 122:f9eeca106725 6317 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
Kojto 122:f9eeca106725 6318 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
Kojto 122:f9eeca106725 6319 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
Kojto 122:f9eeca106725 6320 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
Kojto 122:f9eeca106725 6321 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
Kojto 122:f9eeca106725 6322 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
Kojto 122:f9eeca106725 6323 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
Kojto 122:f9eeca106725 6324 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
Kojto 122:f9eeca106725 6325 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
Kojto 122:f9eeca106725 6326 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
Kojto 122:f9eeca106725 6327 #define RCC_DCKCFGR2_CECSEL 0x04000000U
Kojto 122:f9eeca106725 6328 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
Kojto 122:f9eeca106725 6329 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
Kojto 122:f9eeca106725 6330 #define RCC_DCKCFGR2_SDMMC2SEL 0x20000000U
Kojto 122:f9eeca106725 6331
Kojto 122:f9eeca106725 6332 /******************************************************************************/
Kojto 122:f9eeca106725 6333 /* */
Kojto 122:f9eeca106725 6334 /* RNG */
Kojto 122:f9eeca106725 6335 /* */
Kojto 122:f9eeca106725 6336 /******************************************************************************/
Kojto 122:f9eeca106725 6337 /******************** Bits definition for RNG_CR register *******************/
Kojto 122:f9eeca106725 6338 #define RNG_CR_RNGEN 0x00000004U
Kojto 122:f9eeca106725 6339 #define RNG_CR_IE 0x00000008U
Kojto 122:f9eeca106725 6340
Kojto 122:f9eeca106725 6341 /******************** Bits definition for RNG_SR register *******************/
Kojto 122:f9eeca106725 6342 #define RNG_SR_DRDY 0x00000001U
Kojto 122:f9eeca106725 6343 #define RNG_SR_CECS 0x00000002U
Kojto 122:f9eeca106725 6344 #define RNG_SR_SECS 0x00000004U
Kojto 122:f9eeca106725 6345 #define RNG_SR_CEIS 0x00000020U
Kojto 122:f9eeca106725 6346 #define RNG_SR_SEIS 0x00000040U
Kojto 122:f9eeca106725 6347
Kojto 122:f9eeca106725 6348 /******************************************************************************/
Kojto 122:f9eeca106725 6349 /* */
Kojto 122:f9eeca106725 6350 /* Real-Time Clock (RTC) */
Kojto 122:f9eeca106725 6351 /* */
Kojto 122:f9eeca106725 6352 /******************************************************************************/
Kojto 122:f9eeca106725 6353 /******************** Bits definition for RTC_TR register *******************/
Kojto 122:f9eeca106725 6354 #define RTC_TR_PM 0x00400000U
Kojto 122:f9eeca106725 6355 #define RTC_TR_HT 0x00300000U
Kojto 122:f9eeca106725 6356 #define RTC_TR_HT_0 0x00100000U
Kojto 122:f9eeca106725 6357 #define RTC_TR_HT_1 0x00200000U
Kojto 122:f9eeca106725 6358 #define RTC_TR_HU 0x000F0000U
Kojto 122:f9eeca106725 6359 #define RTC_TR_HU_0 0x00010000U
Kojto 122:f9eeca106725 6360 #define RTC_TR_HU_1 0x00020000U
Kojto 122:f9eeca106725 6361 #define RTC_TR_HU_2 0x00040000U
Kojto 122:f9eeca106725 6362 #define RTC_TR_HU_3 0x00080000U
Kojto 122:f9eeca106725 6363 #define RTC_TR_MNT 0x00007000U
Kojto 122:f9eeca106725 6364 #define RTC_TR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 6365 #define RTC_TR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 6366 #define RTC_TR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 6367 #define RTC_TR_MNU 0x00000F00U
Kojto 122:f9eeca106725 6368 #define RTC_TR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 6369 #define RTC_TR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 6370 #define RTC_TR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 6371 #define RTC_TR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 6372 #define RTC_TR_ST 0x00000070U
Kojto 122:f9eeca106725 6373 #define RTC_TR_ST_0 0x00000010U
Kojto 122:f9eeca106725 6374 #define RTC_TR_ST_1 0x00000020U
Kojto 122:f9eeca106725 6375 #define RTC_TR_ST_2 0x00000040U
Kojto 122:f9eeca106725 6376 #define RTC_TR_SU 0x0000000FU
Kojto 122:f9eeca106725 6377 #define RTC_TR_SU_0 0x00000001U
Kojto 122:f9eeca106725 6378 #define RTC_TR_SU_1 0x00000002U
Kojto 122:f9eeca106725 6379 #define RTC_TR_SU_2 0x00000004U
Kojto 122:f9eeca106725 6380 #define RTC_TR_SU_3 0x00000008U
Kojto 122:f9eeca106725 6381
Kojto 122:f9eeca106725 6382 /******************** Bits definition for RTC_DR register *******************/
Kojto 122:f9eeca106725 6383 #define RTC_DR_YT 0x00F00000U
Kojto 122:f9eeca106725 6384 #define RTC_DR_YT_0 0x00100000U
Kojto 122:f9eeca106725 6385 #define RTC_DR_YT_1 0x00200000U
Kojto 122:f9eeca106725 6386 #define RTC_DR_YT_2 0x00400000U
Kojto 122:f9eeca106725 6387 #define RTC_DR_YT_3 0x00800000U
Kojto 122:f9eeca106725 6388 #define RTC_DR_YU 0x000F0000U
Kojto 122:f9eeca106725 6389 #define RTC_DR_YU_0 0x00010000U
Kojto 122:f9eeca106725 6390 #define RTC_DR_YU_1 0x00020000U
Kojto 122:f9eeca106725 6391 #define RTC_DR_YU_2 0x00040000U
Kojto 122:f9eeca106725 6392 #define RTC_DR_YU_3 0x00080000U
Kojto 122:f9eeca106725 6393 #define RTC_DR_WDU 0x0000E000U
Kojto 122:f9eeca106725 6394 #define RTC_DR_WDU_0 0x00002000U
Kojto 122:f9eeca106725 6395 #define RTC_DR_WDU_1 0x00004000U
Kojto 122:f9eeca106725 6396 #define RTC_DR_WDU_2 0x00008000U
Kojto 122:f9eeca106725 6397 #define RTC_DR_MT 0x00001000U
Kojto 122:f9eeca106725 6398 #define RTC_DR_MU 0x00000F00U
Kojto 122:f9eeca106725 6399 #define RTC_DR_MU_0 0x00000100U
Kojto 122:f9eeca106725 6400 #define RTC_DR_MU_1 0x00000200U
Kojto 122:f9eeca106725 6401 #define RTC_DR_MU_2 0x00000400U
Kojto 122:f9eeca106725 6402 #define RTC_DR_MU_3 0x00000800U
Kojto 122:f9eeca106725 6403 #define RTC_DR_DT 0x00000030U
Kojto 122:f9eeca106725 6404 #define RTC_DR_DT_0 0x00000010U
Kojto 122:f9eeca106725 6405 #define RTC_DR_DT_1 0x00000020U
Kojto 122:f9eeca106725 6406 #define RTC_DR_DU 0x0000000FU
Kojto 122:f9eeca106725 6407 #define RTC_DR_DU_0 0x00000001U
Kojto 122:f9eeca106725 6408 #define RTC_DR_DU_1 0x00000002U
Kojto 122:f9eeca106725 6409 #define RTC_DR_DU_2 0x00000004U
Kojto 122:f9eeca106725 6410 #define RTC_DR_DU_3 0x00000008U
Kojto 122:f9eeca106725 6411
Kojto 122:f9eeca106725 6412 /******************** Bits definition for RTC_CR register *******************/
Kojto 122:f9eeca106725 6413 #define RTC_CR_ITSE 0x01000000U
Kojto 122:f9eeca106725 6414 #define RTC_CR_COE 0x00800000U
Kojto 122:f9eeca106725 6415 #define RTC_CR_OSEL 0x00600000U
Kojto 122:f9eeca106725 6416 #define RTC_CR_OSEL_0 0x00200000U
Kojto 122:f9eeca106725 6417 #define RTC_CR_OSEL_1 0x00400000U
Kojto 122:f9eeca106725 6418 #define RTC_CR_POL 0x00100000U
Kojto 122:f9eeca106725 6419 #define RTC_CR_COSEL 0x00080000U
Kojto 122:f9eeca106725 6420 #define RTC_CR_BCK 0x00040000U
Kojto 122:f9eeca106725 6421 #define RTC_CR_SUB1H 0x00020000U
Kojto 122:f9eeca106725 6422 #define RTC_CR_ADD1H 0x00010000U
Kojto 122:f9eeca106725 6423 #define RTC_CR_TSIE 0x00008000U
Kojto 122:f9eeca106725 6424 #define RTC_CR_WUTIE 0x00004000U
Kojto 122:f9eeca106725 6425 #define RTC_CR_ALRBIE 0x00002000U
Kojto 122:f9eeca106725 6426 #define RTC_CR_ALRAIE 0x00001000U
Kojto 122:f9eeca106725 6427 #define RTC_CR_TSE 0x00000800U
Kojto 122:f9eeca106725 6428 #define RTC_CR_WUTE 0x00000400U
Kojto 122:f9eeca106725 6429 #define RTC_CR_ALRBE 0x00000200U
Kojto 122:f9eeca106725 6430 #define RTC_CR_ALRAE 0x00000100U
Kojto 122:f9eeca106725 6431 #define RTC_CR_FMT 0x00000040U
Kojto 122:f9eeca106725 6432 #define RTC_CR_BYPSHAD 0x00000020U
Kojto 122:f9eeca106725 6433 #define RTC_CR_REFCKON 0x00000010U
Kojto 122:f9eeca106725 6434 #define RTC_CR_TSEDGE 0x00000008U
Kojto 122:f9eeca106725 6435 #define RTC_CR_WUCKSEL 0x00000007U
Kojto 122:f9eeca106725 6436 #define RTC_CR_WUCKSEL_0 0x00000001U
Kojto 122:f9eeca106725 6437 #define RTC_CR_WUCKSEL_1 0x00000002U
Kojto 122:f9eeca106725 6438 #define RTC_CR_WUCKSEL_2 0x00000004U
Kojto 122:f9eeca106725 6439
Kojto 122:f9eeca106725 6440 /******************** Bits definition for RTC_ISR register ******************/
Kojto 122:f9eeca106725 6441 #define RTC_ISR_ITSF 0x00020000U
Kojto 122:f9eeca106725 6442 #define RTC_ISR_RECALPF 0x00010000U
Kojto 122:f9eeca106725 6443 #define RTC_ISR_TAMP3F 0x00008000U
Kojto 122:f9eeca106725 6444 #define RTC_ISR_TAMP2F 0x00004000U
Kojto 122:f9eeca106725 6445 #define RTC_ISR_TAMP1F 0x00002000U
Kojto 122:f9eeca106725 6446 #define RTC_ISR_TSOVF 0x00001000U
Kojto 122:f9eeca106725 6447 #define RTC_ISR_TSF 0x00000800U
Kojto 122:f9eeca106725 6448 #define RTC_ISR_WUTF 0x00000400U
Kojto 122:f9eeca106725 6449 #define RTC_ISR_ALRBF 0x00000200U
Kojto 122:f9eeca106725 6450 #define RTC_ISR_ALRAF 0x00000100U
Kojto 122:f9eeca106725 6451 #define RTC_ISR_INIT 0x00000080U
Kojto 122:f9eeca106725 6452 #define RTC_ISR_INITF 0x00000040U
Kojto 122:f9eeca106725 6453 #define RTC_ISR_RSF 0x00000020U
Kojto 122:f9eeca106725 6454 #define RTC_ISR_INITS 0x00000010U
Kojto 122:f9eeca106725 6455 #define RTC_ISR_SHPF 0x00000008U
Kojto 122:f9eeca106725 6456 #define RTC_ISR_WUTWF 0x00000004U
Kojto 122:f9eeca106725 6457 #define RTC_ISR_ALRBWF 0x00000002U
Kojto 122:f9eeca106725 6458 #define RTC_ISR_ALRAWF 0x00000001U
Kojto 122:f9eeca106725 6459
Kojto 122:f9eeca106725 6460 /******************** Bits definition for RTC_PRER register *****************/
Kojto 122:f9eeca106725 6461 #define RTC_PRER_PREDIV_A 0x007F0000U
Kojto 122:f9eeca106725 6462 #define RTC_PRER_PREDIV_S 0x00007FFFU
Kojto 122:f9eeca106725 6463
Kojto 122:f9eeca106725 6464 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 122:f9eeca106725 6465 #define RTC_WUTR_WUT 0x0000FFFFU
Kojto 122:f9eeca106725 6466
Kojto 122:f9eeca106725 6467 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 122:f9eeca106725 6468 #define RTC_ALRMAR_MSK4 0x80000000U
Kojto 122:f9eeca106725 6469 #define RTC_ALRMAR_WDSEL 0x40000000U
Kojto 122:f9eeca106725 6470 #define RTC_ALRMAR_DT 0x30000000U
Kojto 122:f9eeca106725 6471 #define RTC_ALRMAR_DT_0 0x10000000U
Kojto 122:f9eeca106725 6472 #define RTC_ALRMAR_DT_1 0x20000000U
Kojto 122:f9eeca106725 6473 #define RTC_ALRMAR_DU 0x0F000000U
Kojto 122:f9eeca106725 6474 #define RTC_ALRMAR_DU_0 0x01000000U
Kojto 122:f9eeca106725 6475 #define RTC_ALRMAR_DU_1 0x02000000U
Kojto 122:f9eeca106725 6476 #define RTC_ALRMAR_DU_2 0x04000000U
Kojto 122:f9eeca106725 6477 #define RTC_ALRMAR_DU_3 0x08000000U
Kojto 122:f9eeca106725 6478 #define RTC_ALRMAR_MSK3 0x00800000U
Kojto 122:f9eeca106725 6479 #define RTC_ALRMAR_PM 0x00400000U
Kojto 122:f9eeca106725 6480 #define RTC_ALRMAR_HT 0x00300000U
Kojto 122:f9eeca106725 6481 #define RTC_ALRMAR_HT_0 0x00100000U
Kojto 122:f9eeca106725 6482 #define RTC_ALRMAR_HT_1 0x00200000U
Kojto 122:f9eeca106725 6483 #define RTC_ALRMAR_HU 0x000F0000U
Kojto 122:f9eeca106725 6484 #define RTC_ALRMAR_HU_0 0x00010000U
Kojto 122:f9eeca106725 6485 #define RTC_ALRMAR_HU_1 0x00020000U
Kojto 122:f9eeca106725 6486 #define RTC_ALRMAR_HU_2 0x00040000U
Kojto 122:f9eeca106725 6487 #define RTC_ALRMAR_HU_3 0x00080000U
Kojto 122:f9eeca106725 6488 #define RTC_ALRMAR_MSK2 0x00008000U
Kojto 122:f9eeca106725 6489 #define RTC_ALRMAR_MNT 0x00007000U
Kojto 122:f9eeca106725 6490 #define RTC_ALRMAR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 6491 #define RTC_ALRMAR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 6492 #define RTC_ALRMAR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 6493 #define RTC_ALRMAR_MNU 0x00000F00U
Kojto 122:f9eeca106725 6494 #define RTC_ALRMAR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 6495 #define RTC_ALRMAR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 6496 #define RTC_ALRMAR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 6497 #define RTC_ALRMAR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 6498 #define RTC_ALRMAR_MSK1 0x00000080U
Kojto 122:f9eeca106725 6499 #define RTC_ALRMAR_ST 0x00000070U
Kojto 122:f9eeca106725 6500 #define RTC_ALRMAR_ST_0 0x00000010U
Kojto 122:f9eeca106725 6501 #define RTC_ALRMAR_ST_1 0x00000020U
Kojto 122:f9eeca106725 6502 #define RTC_ALRMAR_ST_2 0x00000040U
Kojto 122:f9eeca106725 6503 #define RTC_ALRMAR_SU 0x0000000FU
Kojto 122:f9eeca106725 6504 #define RTC_ALRMAR_SU_0 0x00000001U
Kojto 122:f9eeca106725 6505 #define RTC_ALRMAR_SU_1 0x00000002U
Kojto 122:f9eeca106725 6506 #define RTC_ALRMAR_SU_2 0x00000004U
Kojto 122:f9eeca106725 6507 #define RTC_ALRMAR_SU_3 0x00000008U
Kojto 122:f9eeca106725 6508
Kojto 122:f9eeca106725 6509 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 122:f9eeca106725 6510 #define RTC_ALRMBR_MSK4 0x80000000U
Kojto 122:f9eeca106725 6511 #define RTC_ALRMBR_WDSEL 0x40000000U
Kojto 122:f9eeca106725 6512 #define RTC_ALRMBR_DT 0x30000000U
Kojto 122:f9eeca106725 6513 #define RTC_ALRMBR_DT_0 0x10000000U
Kojto 122:f9eeca106725 6514 #define RTC_ALRMBR_DT_1 0x20000000U
Kojto 122:f9eeca106725 6515 #define RTC_ALRMBR_DU 0x0F000000U
Kojto 122:f9eeca106725 6516 #define RTC_ALRMBR_DU_0 0x01000000U
Kojto 122:f9eeca106725 6517 #define RTC_ALRMBR_DU_1 0x02000000U
Kojto 122:f9eeca106725 6518 #define RTC_ALRMBR_DU_2 0x04000000U
Kojto 122:f9eeca106725 6519 #define RTC_ALRMBR_DU_3 0x08000000U
Kojto 122:f9eeca106725 6520 #define RTC_ALRMBR_MSK3 0x00800000U
Kojto 122:f9eeca106725 6521 #define RTC_ALRMBR_PM 0x00400000U
Kojto 122:f9eeca106725 6522 #define RTC_ALRMBR_HT 0x00300000U
Kojto 122:f9eeca106725 6523 #define RTC_ALRMBR_HT_0 0x00100000U
Kojto 122:f9eeca106725 6524 #define RTC_ALRMBR_HT_1 0x00200000U
Kojto 122:f9eeca106725 6525 #define RTC_ALRMBR_HU 0x000F0000U
Kojto 122:f9eeca106725 6526 #define RTC_ALRMBR_HU_0 0x00010000U
Kojto 122:f9eeca106725 6527 #define RTC_ALRMBR_HU_1 0x00020000U
Kojto 122:f9eeca106725 6528 #define RTC_ALRMBR_HU_2 0x00040000U
Kojto 122:f9eeca106725 6529 #define RTC_ALRMBR_HU_3 0x00080000U
Kojto 122:f9eeca106725 6530 #define RTC_ALRMBR_MSK2 0x00008000U
Kojto 122:f9eeca106725 6531 #define RTC_ALRMBR_MNT 0x00007000U
Kojto 122:f9eeca106725 6532 #define RTC_ALRMBR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 6533 #define RTC_ALRMBR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 6534 #define RTC_ALRMBR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 6535 #define RTC_ALRMBR_MNU 0x00000F00U
Kojto 122:f9eeca106725 6536 #define RTC_ALRMBR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 6537 #define RTC_ALRMBR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 6538 #define RTC_ALRMBR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 6539 #define RTC_ALRMBR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 6540 #define RTC_ALRMBR_MSK1 0x00000080U
Kojto 122:f9eeca106725 6541 #define RTC_ALRMBR_ST 0x00000070U
Kojto 122:f9eeca106725 6542 #define RTC_ALRMBR_ST_0 0x00000010U
Kojto 122:f9eeca106725 6543 #define RTC_ALRMBR_ST_1 0x00000020U
Kojto 122:f9eeca106725 6544 #define RTC_ALRMBR_ST_2 0x00000040U
Kojto 122:f9eeca106725 6545 #define RTC_ALRMBR_SU 0x0000000FU
Kojto 122:f9eeca106725 6546 #define RTC_ALRMBR_SU_0 0x00000001U
Kojto 122:f9eeca106725 6547 #define RTC_ALRMBR_SU_1 0x00000002U
Kojto 122:f9eeca106725 6548 #define RTC_ALRMBR_SU_2 0x00000004U
Kojto 122:f9eeca106725 6549 #define RTC_ALRMBR_SU_3 0x00000008U
Kojto 122:f9eeca106725 6550
Kojto 122:f9eeca106725 6551 /******************** Bits definition for RTC_WPR register ******************/
Kojto 122:f9eeca106725 6552 #define RTC_WPR_KEY 0x000000FFU
Kojto 122:f9eeca106725 6553
Kojto 122:f9eeca106725 6554 /******************** Bits definition for RTC_SSR register ******************/
Kojto 122:f9eeca106725 6555 #define RTC_SSR_SS 0x0000FFFFU
Kojto 122:f9eeca106725 6556
Kojto 122:f9eeca106725 6557 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 122:f9eeca106725 6558 #define RTC_SHIFTR_SUBFS 0x00007FFFU
Kojto 122:f9eeca106725 6559 #define RTC_SHIFTR_ADD1S 0x80000000U
Kojto 122:f9eeca106725 6560
Kojto 122:f9eeca106725 6561 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 122:f9eeca106725 6562 #define RTC_TSTR_PM 0x00400000U
Kojto 122:f9eeca106725 6563 #define RTC_TSTR_HT 0x00300000U
Kojto 122:f9eeca106725 6564 #define RTC_TSTR_HT_0 0x00100000U
Kojto 122:f9eeca106725 6565 #define RTC_TSTR_HT_1 0x00200000U
Kojto 122:f9eeca106725 6566 #define RTC_TSTR_HU 0x000F0000U
Kojto 122:f9eeca106725 6567 #define RTC_TSTR_HU_0 0x00010000U
Kojto 122:f9eeca106725 6568 #define RTC_TSTR_HU_1 0x00020000U
Kojto 122:f9eeca106725 6569 #define RTC_TSTR_HU_2 0x00040000U
Kojto 122:f9eeca106725 6570 #define RTC_TSTR_HU_3 0x00080000U
Kojto 122:f9eeca106725 6571 #define RTC_TSTR_MNT 0x00007000U
Kojto 122:f9eeca106725 6572 #define RTC_TSTR_MNT_0 0x00001000U
Kojto 122:f9eeca106725 6573 #define RTC_TSTR_MNT_1 0x00002000U
Kojto 122:f9eeca106725 6574 #define RTC_TSTR_MNT_2 0x00004000U
Kojto 122:f9eeca106725 6575 #define RTC_TSTR_MNU 0x00000F00U
Kojto 122:f9eeca106725 6576 #define RTC_TSTR_MNU_0 0x00000100U
Kojto 122:f9eeca106725 6577 #define RTC_TSTR_MNU_1 0x00000200U
Kojto 122:f9eeca106725 6578 #define RTC_TSTR_MNU_2 0x00000400U
Kojto 122:f9eeca106725 6579 #define RTC_TSTR_MNU_3 0x00000800U
Kojto 122:f9eeca106725 6580 #define RTC_TSTR_ST 0x00000070U
Kojto 122:f9eeca106725 6581 #define RTC_TSTR_ST_0 0x00000010U
Kojto 122:f9eeca106725 6582 #define RTC_TSTR_ST_1 0x00000020U
Kojto 122:f9eeca106725 6583 #define RTC_TSTR_ST_2 0x00000040U
Kojto 122:f9eeca106725 6584 #define RTC_TSTR_SU 0x0000000FU
Kojto 122:f9eeca106725 6585 #define RTC_TSTR_SU_0 0x00000001U
Kojto 122:f9eeca106725 6586 #define RTC_TSTR_SU_1 0x00000002U
Kojto 122:f9eeca106725 6587 #define RTC_TSTR_SU_2 0x00000004U
Kojto 122:f9eeca106725 6588 #define RTC_TSTR_SU_3 0x00000008U
Kojto 122:f9eeca106725 6589
Kojto 122:f9eeca106725 6590 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 122:f9eeca106725 6591 #define RTC_TSDR_WDU 0x0000E000U
Kojto 122:f9eeca106725 6592 #define RTC_TSDR_WDU_0 0x00002000U
Kojto 122:f9eeca106725 6593 #define RTC_TSDR_WDU_1 0x00004000U
Kojto 122:f9eeca106725 6594 #define RTC_TSDR_WDU_2 0x00008000U
Kojto 122:f9eeca106725 6595 #define RTC_TSDR_MT 0x00001000U
Kojto 122:f9eeca106725 6596 #define RTC_TSDR_MU 0x00000F00U
Kojto 122:f9eeca106725 6597 #define RTC_TSDR_MU_0 0x00000100U
Kojto 122:f9eeca106725 6598 #define RTC_TSDR_MU_1 0x00000200U
Kojto 122:f9eeca106725 6599 #define RTC_TSDR_MU_2 0x00000400U
Kojto 122:f9eeca106725 6600 #define RTC_TSDR_MU_3 0x00000800U
Kojto 122:f9eeca106725 6601 #define RTC_TSDR_DT 0x00000030U
Kojto 122:f9eeca106725 6602 #define RTC_TSDR_DT_0 0x00000010U
Kojto 122:f9eeca106725 6603 #define RTC_TSDR_DT_1 0x00000020U
Kojto 122:f9eeca106725 6604 #define RTC_TSDR_DU 0x0000000FU
Kojto 122:f9eeca106725 6605 #define RTC_TSDR_DU_0 0x00000001U
Kojto 122:f9eeca106725 6606 #define RTC_TSDR_DU_1 0x00000002U
Kojto 122:f9eeca106725 6607 #define RTC_TSDR_DU_2 0x00000004U
Kojto 122:f9eeca106725 6608 #define RTC_TSDR_DU_3 0x00000008U
Kojto 122:f9eeca106725 6609
Kojto 122:f9eeca106725 6610 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 122:f9eeca106725 6611 #define RTC_TSSSR_SS 0x0000FFFFU
Kojto 122:f9eeca106725 6612
Kojto 122:f9eeca106725 6613 /******************** Bits definition for RTC_CAL register *****************/
Kojto 122:f9eeca106725 6614 #define RTC_CALR_CALP 0x00008000U
Kojto 122:f9eeca106725 6615 #define RTC_CALR_CALW8 0x00004000U
Kojto 122:f9eeca106725 6616 #define RTC_CALR_CALW16 0x00002000U
Kojto 122:f9eeca106725 6617 #define RTC_CALR_CALM 0x000001FFU
Kojto 122:f9eeca106725 6618 #define RTC_CALR_CALM_0 0x00000001U
Kojto 122:f9eeca106725 6619 #define RTC_CALR_CALM_1 0x00000002U
Kojto 122:f9eeca106725 6620 #define RTC_CALR_CALM_2 0x00000004U
Kojto 122:f9eeca106725 6621 #define RTC_CALR_CALM_3 0x00000008U
Kojto 122:f9eeca106725 6622 #define RTC_CALR_CALM_4 0x00000010U
Kojto 122:f9eeca106725 6623 #define RTC_CALR_CALM_5 0x00000020U
Kojto 122:f9eeca106725 6624 #define RTC_CALR_CALM_6 0x00000040U
Kojto 122:f9eeca106725 6625 #define RTC_CALR_CALM_7 0x00000080U
Kojto 122:f9eeca106725 6626 #define RTC_CALR_CALM_8 0x00000100U
Kojto 122:f9eeca106725 6627
Kojto 122:f9eeca106725 6628 /******************** Bits definition for RTC_TAMPCR register ****************/
Kojto 122:f9eeca106725 6629 #define RTC_TAMPCR_TAMP3MF 0x01000000U
Kojto 122:f9eeca106725 6630 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
Kojto 122:f9eeca106725 6631 #define RTC_TAMPCR_TAMP3IE 0x00400000U
Kojto 122:f9eeca106725 6632 #define RTC_TAMPCR_TAMP2MF 0x00200000U
Kojto 122:f9eeca106725 6633 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
Kojto 122:f9eeca106725 6634 #define RTC_TAMPCR_TAMP2IE 0x00080000U
Kojto 122:f9eeca106725 6635 #define RTC_TAMPCR_TAMP1MF 0x00040000U
Kojto 122:f9eeca106725 6636 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
Kojto 122:f9eeca106725 6637 #define RTC_TAMPCR_TAMP1IE 0x00010000U
Kojto 122:f9eeca106725 6638 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
Kojto 122:f9eeca106725 6639 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
Kojto 122:f9eeca106725 6640 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
Kojto 122:f9eeca106725 6641 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
Kojto 122:f9eeca106725 6642 #define RTC_TAMPCR_TAMPFLT 0x00001800U
Kojto 122:f9eeca106725 6643 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
Kojto 122:f9eeca106725 6644 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
Kojto 122:f9eeca106725 6645 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
Kojto 122:f9eeca106725 6646 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
Kojto 122:f9eeca106725 6647 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
Kojto 122:f9eeca106725 6648 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
Kojto 122:f9eeca106725 6649 #define RTC_TAMPCR_TAMPTS 0x00000080U
Kojto 122:f9eeca106725 6650 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
Kojto 122:f9eeca106725 6651 #define RTC_TAMPCR_TAMP3E 0x00000020U
Kojto 122:f9eeca106725 6652 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
Kojto 122:f9eeca106725 6653 #define RTC_TAMPCR_TAMP2E 0x00000008U
Kojto 122:f9eeca106725 6654 #define RTC_TAMPCR_TAMPIE 0x00000004U
Kojto 122:f9eeca106725 6655 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
Kojto 122:f9eeca106725 6656 #define RTC_TAMPCR_TAMP1E 0x00000001U
Kojto 122:f9eeca106725 6657
Kojto 122:f9eeca106725 6658
Kojto 122:f9eeca106725 6659 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 122:f9eeca106725 6660 #define RTC_ALRMASSR_MASKSS 0x0F000000U
Kojto 122:f9eeca106725 6661 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
Kojto 122:f9eeca106725 6662 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
Kojto 122:f9eeca106725 6663 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
Kojto 122:f9eeca106725 6664 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
Kojto 122:f9eeca106725 6665 #define RTC_ALRMASSR_SS 0x00007FFFU
Kojto 122:f9eeca106725 6666
Kojto 122:f9eeca106725 6667 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 122:f9eeca106725 6668 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
Kojto 122:f9eeca106725 6669 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
Kojto 122:f9eeca106725 6670 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
Kojto 122:f9eeca106725 6671 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
Kojto 122:f9eeca106725 6672 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
Kojto 122:f9eeca106725 6673 #define RTC_ALRMBSSR_SS 0x00007FFFU
Kojto 122:f9eeca106725 6674
Kojto 122:f9eeca106725 6675 /******************** Bits definition for RTC_OR register ****************/
Kojto 122:f9eeca106725 6676 #define RTC_OR_TSINSEL 0x00000006U
Kojto 122:f9eeca106725 6677 #define RTC_OR_TSINSEL_0 0x00000002U
Kojto 122:f9eeca106725 6678 #define RTC_OR_TSINSEL_1 0x00000004U
Kojto 122:f9eeca106725 6679 #define RTC_OR_ALARMTYPE 0x00000008U
Kojto 122:f9eeca106725 6680
Kojto 122:f9eeca106725 6681 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 122:f9eeca106725 6682 #define RTC_BKP0R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6683
Kojto 122:f9eeca106725 6684 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 122:f9eeca106725 6685 #define RTC_BKP1R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6686
Kojto 122:f9eeca106725 6687 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 122:f9eeca106725 6688 #define RTC_BKP2R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6689
Kojto 122:f9eeca106725 6690 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 122:f9eeca106725 6691 #define RTC_BKP3R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6692
Kojto 122:f9eeca106725 6693 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 122:f9eeca106725 6694 #define RTC_BKP4R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6695
Kojto 122:f9eeca106725 6696 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 122:f9eeca106725 6697 #define RTC_BKP5R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6698
Kojto 122:f9eeca106725 6699 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 122:f9eeca106725 6700 #define RTC_BKP6R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6701
Kojto 122:f9eeca106725 6702 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 122:f9eeca106725 6703 #define RTC_BKP7R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6704
Kojto 122:f9eeca106725 6705 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 122:f9eeca106725 6706 #define RTC_BKP8R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6707
Kojto 122:f9eeca106725 6708 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 122:f9eeca106725 6709 #define RTC_BKP9R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6710
Kojto 122:f9eeca106725 6711 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 122:f9eeca106725 6712 #define RTC_BKP10R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6713
Kojto 122:f9eeca106725 6714 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 122:f9eeca106725 6715 #define RTC_BKP11R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6716
Kojto 122:f9eeca106725 6717 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 122:f9eeca106725 6718 #define RTC_BKP12R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6719
Kojto 122:f9eeca106725 6720 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 122:f9eeca106725 6721 #define RTC_BKP13R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6722
Kojto 122:f9eeca106725 6723 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 122:f9eeca106725 6724 #define RTC_BKP14R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6725
Kojto 122:f9eeca106725 6726 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 122:f9eeca106725 6727 #define RTC_BKP15R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6728
Kojto 122:f9eeca106725 6729 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 122:f9eeca106725 6730 #define RTC_BKP16R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6731
Kojto 122:f9eeca106725 6732 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 122:f9eeca106725 6733 #define RTC_BKP17R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6734
Kojto 122:f9eeca106725 6735 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 122:f9eeca106725 6736 #define RTC_BKP18R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6737
Kojto 122:f9eeca106725 6738 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 122:f9eeca106725 6739 #define RTC_BKP19R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6740
Kojto 122:f9eeca106725 6741 /******************** Bits definition for RTC_BKP20R register ***************/
Kojto 122:f9eeca106725 6742 #define RTC_BKP20R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6743
Kojto 122:f9eeca106725 6744 /******************** Bits definition for RTC_BKP21R register ***************/
Kojto 122:f9eeca106725 6745 #define RTC_BKP21R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6746
Kojto 122:f9eeca106725 6747 /******************** Bits definition for RTC_BKP22R register ***************/
Kojto 122:f9eeca106725 6748 #define RTC_BKP22R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6749
Kojto 122:f9eeca106725 6750 /******************** Bits definition for RTC_BKP23R register ***************/
Kojto 122:f9eeca106725 6751 #define RTC_BKP23R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6752
Kojto 122:f9eeca106725 6753 /******************** Bits definition for RTC_BKP24R register ***************/
Kojto 122:f9eeca106725 6754 #define RTC_BKP24R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6755
Kojto 122:f9eeca106725 6756 /******************** Bits definition for RTC_BKP25R register ***************/
Kojto 122:f9eeca106725 6757 #define RTC_BKP25R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6758
Kojto 122:f9eeca106725 6759 /******************** Bits definition for RTC_BKP26R register ***************/
Kojto 122:f9eeca106725 6760 #define RTC_BKP26R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6761
Kojto 122:f9eeca106725 6762 /******************** Bits definition for RTC_BKP27R register ***************/
Kojto 122:f9eeca106725 6763 #define RTC_BKP27R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6764
Kojto 122:f9eeca106725 6765 /******************** Bits definition for RTC_BKP28R register ***************/
Kojto 122:f9eeca106725 6766 #define RTC_BKP28R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6767
Kojto 122:f9eeca106725 6768 /******************** Bits definition for RTC_BKP29R register ***************/
Kojto 122:f9eeca106725 6769 #define RTC_BKP29R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6770
Kojto 122:f9eeca106725 6771 /******************** Bits definition for RTC_BKP30R register ***************/
Kojto 122:f9eeca106725 6772 #define RTC_BKP30R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6773
Kojto 122:f9eeca106725 6774 /******************** Bits definition for RTC_BKP31R register ***************/
Kojto 122:f9eeca106725 6775 #define RTC_BKP31R 0xFFFFFFFFU
Kojto 122:f9eeca106725 6776
Kojto 122:f9eeca106725 6777 /******************** Number of backup registers ******************************/
Kojto 122:f9eeca106725 6778 #define RTC_BKP_NUMBER 0x00000020U
Kojto 122:f9eeca106725 6779
Kojto 122:f9eeca106725 6780
Kojto 122:f9eeca106725 6781 /******************************************************************************/
Kojto 122:f9eeca106725 6782 /* */
Kojto 122:f9eeca106725 6783 /* Serial Audio Interface */
Kojto 122:f9eeca106725 6784 /* */
Kojto 122:f9eeca106725 6785 /******************************************************************************/
Kojto 122:f9eeca106725 6786 /******************** Bit definition for SAI_GCR register *******************/
Kojto 122:f9eeca106725 6787 #define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
Kojto 122:f9eeca106725 6788 #define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6789 #define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6790
Kojto 122:f9eeca106725 6791 #define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
Kojto 122:f9eeca106725 6792 #define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 6793 #define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 6794
Kojto 122:f9eeca106725 6795 /******************* Bit definition for SAI_xCR1 register *******************/
Kojto 122:f9eeca106725 6796 #define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
Kojto 122:f9eeca106725 6797 #define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6798 #define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6799
Kojto 122:f9eeca106725 6800 #define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
Kojto 122:f9eeca106725 6801 #define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 6802 #define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 6803
Kojto 122:f9eeca106725 6804 #define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
Kojto 122:f9eeca106725 6805 #define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
Kojto 122:f9eeca106725 6806 #define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
Kojto 122:f9eeca106725 6807 #define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
Kojto 122:f9eeca106725 6808
Kojto 122:f9eeca106725 6809 #define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
Kojto 122:f9eeca106725 6810 #define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
Kojto 122:f9eeca106725 6811
Kojto 122:f9eeca106725 6812 #define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
Kojto 122:f9eeca106725 6813 #define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 6814 #define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 6815
Kojto 122:f9eeca106725 6816 #define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
Kojto 122:f9eeca106725 6817 #define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
Kojto 122:f9eeca106725 6818 #define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
Kojto 122:f9eeca106725 6819 #define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
Kojto 122:f9eeca106725 6820 #define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
Kojto 122:f9eeca106725 6821
Kojto 122:f9eeca106725 6822 #define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
Kojto 122:f9eeca106725 6823 #define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6824 #define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6825 #define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6826 #define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
Kojto 122:f9eeca106725 6827
Kojto 122:f9eeca106725 6828 /******************* Bit definition for SAI_xCR2 register *******************/
Kojto 122:f9eeca106725 6829 #define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
Kojto 122:f9eeca106725 6830 #define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6831 #define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6832 #define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6833
Kojto 122:f9eeca106725 6834 #define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
Kojto 122:f9eeca106725 6835 #define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
Kojto 122:f9eeca106725 6836 #define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
Kojto 122:f9eeca106725 6837 #define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
Kojto 122:f9eeca106725 6838
Kojto 122:f9eeca106725 6839 #define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
Kojto 122:f9eeca106725 6840 #define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 6841 #define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 6842 #define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
Kojto 122:f9eeca106725 6843 #define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
Kojto 122:f9eeca106725 6844 #define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
Kojto 122:f9eeca106725 6845 #define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6846
Kojto 122:f9eeca106725 6847 #define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
Kojto 122:f9eeca106725 6848
Kojto 122:f9eeca106725 6849 #define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
Kojto 122:f9eeca106725 6850 #define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6851 #define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6852
Kojto 122:f9eeca106725 6853 /****************** Bit definition for SAI_xFRCR register *******************/
Kojto 122:f9eeca106725 6854 #define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
Kojto 122:f9eeca106725 6855 #define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6856 #define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6857 #define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6858 #define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6859 #define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6860 #define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 6861 #define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 6862 #define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 6863
Kojto 122:f9eeca106725 6864 #define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
Kojto 122:f9eeca106725 6865 #define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6866 #define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6867 #define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 6868 #define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 6869 #define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 6870 #define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
Kojto 122:f9eeca106725 6871 #define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
Kojto 122:f9eeca106725 6872
Kojto 122:f9eeca106725 6873 #define SAI_xFRCR_FSDEF 0x00010000U /*!<Frame Synchronization Definition */
Kojto 122:f9eeca106725 6874 #define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
Kojto 122:f9eeca106725 6875 #define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
Kojto 122:f9eeca106725 6876
Kojto 122:f9eeca106725 6877 /* Legacy define */
Kojto 122:f9eeca106725 6878 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
Kojto 122:f9eeca106725 6879
Kojto 122:f9eeca106725 6880 /****************** Bit definition for SAI_xSLOTR register *******************/
Kojto 122:f9eeca106725 6881 #define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
Kojto 122:f9eeca106725 6882 #define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 6883 #define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 6884 #define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 6885 #define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 6886 #define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 6887
Kojto 122:f9eeca106725 6888 #define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
Kojto 122:f9eeca106725 6889 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 6890 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 6891
Kojto 122:f9eeca106725 6892 #define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
Kojto 122:f9eeca106725 6893 #define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 6894 #define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 6895 #define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 6896 #define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 6897
Kojto 122:f9eeca106725 6898 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
Kojto 122:f9eeca106725 6899
Kojto 122:f9eeca106725 6900 /******************* Bit definition for SAI_xIMR register *******************/
Kojto 122:f9eeca106725 6901 #define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
Kojto 122:f9eeca106725 6902 #define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
Kojto 122:f9eeca106725 6903 #define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
Kojto 122:f9eeca106725 6904 #define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
Kojto 122:f9eeca106725 6905 #define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
Kojto 122:f9eeca106725 6906 #define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
Kojto 122:f9eeca106725 6907 #define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
Kojto 122:f9eeca106725 6908
Kojto 122:f9eeca106725 6909 /******************** Bit definition for SAI_xSR register *******************/
Kojto 122:f9eeca106725 6910 #define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
Kojto 122:f9eeca106725 6911 #define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
Kojto 122:f9eeca106725 6912 #define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
Kojto 122:f9eeca106725 6913 #define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
Kojto 122:f9eeca106725 6914 #define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
Kojto 122:f9eeca106725 6915 #define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
Kojto 122:f9eeca106725 6916 #define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
Kojto 122:f9eeca106725 6917
Kojto 122:f9eeca106725 6918 #define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
Kojto 122:f9eeca106725 6919 #define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 6920 #define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 6921 #define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 6922
Kojto 122:f9eeca106725 6923 /****************** Bit definition for SAI_xCLRFR register ******************/
Kojto 122:f9eeca106725 6924 #define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
Kojto 122:f9eeca106725 6925 #define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
Kojto 122:f9eeca106725 6926 #define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
Kojto 122:f9eeca106725 6927 #define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
Kojto 122:f9eeca106725 6928 #define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
Kojto 122:f9eeca106725 6929 #define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
Kojto 122:f9eeca106725 6930 #define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
Kojto 122:f9eeca106725 6931
Kojto 122:f9eeca106725 6932 /****************** Bit definition for SAI_xDR register *********************/
Kojto 122:f9eeca106725 6933 #define SAI_xDR_DATA 0xFFFFFFFFU
Kojto 122:f9eeca106725 6934
Kojto 122:f9eeca106725 6935 /******************************************************************************/
Kojto 122:f9eeca106725 6936 /* */
Kojto 122:f9eeca106725 6937 /* SPDIF-RX Interface */
Kojto 122:f9eeca106725 6938 /* */
Kojto 122:f9eeca106725 6939 /******************************************************************************/
Kojto 122:f9eeca106725 6940 /******************** Bit definition for SPDIF_CR register *******************/
Kojto 122:f9eeca106725 6941 #define SPDIFRX_CR_SPDIFEN 0x00000003U /*!<Peripheral Block Enable */
Kojto 122:f9eeca106725 6942 #define SPDIFRX_CR_RXDMAEN 0x00000004U /*!<Receiver DMA Enable for data flow */
Kojto 122:f9eeca106725 6943 #define SPDIFRX_CR_RXSTEO 0x00000008U /*!<Stereo Mode */
Kojto 122:f9eeca106725 6944 #define SPDIFRX_CR_DRFMT 0x00000030U /*!<RX Data format */
Kojto 122:f9eeca106725 6945 #define SPDIFRX_CR_PMSK 0x00000040U /*!<Mask Parity error bit */
Kojto 122:f9eeca106725 6946 #define SPDIFRX_CR_VMSK 0x00000080U /*!<Mask of Validity bit */
Kojto 122:f9eeca106725 6947 #define SPDIFRX_CR_CUMSK 0x00000100U /*!<Mask of channel status and user bits */
Kojto 122:f9eeca106725 6948 #define SPDIFRX_CR_PTMSK 0x00000200U /*!<Mask of Preamble Type bits */
Kojto 122:f9eeca106725 6949 #define SPDIFRX_CR_CBDMAEN 0x00000400U /*!<Control Buffer DMA ENable for control flow */
Kojto 122:f9eeca106725 6950 #define SPDIFRX_CR_CHSEL 0x00000800U /*!<Channel Selection */
Kojto 122:f9eeca106725 6951 #define SPDIFRX_CR_NBTR 0x00003000U /*!<Maximum allowed re-tries during synchronization phase */
Kojto 122:f9eeca106725 6952 #define SPDIFRX_CR_WFA 0x00004000U /*!<Wait For Activity */
Kojto 122:f9eeca106725 6953 #define SPDIFRX_CR_INSEL 0x00070000U /*!<SPDIF input selection */
Kojto 122:f9eeca106725 6954
Kojto 122:f9eeca106725 6955 /******************* Bit definition for SPDIFRX_IMR register *******************/
Kojto 122:f9eeca106725 6956 #define SPDIFRX_IMR_RXNEIE 0x00000001U /*!<RXNE interrupt enable */
Kojto 122:f9eeca106725 6957 #define SPDIFRX_IMR_CSRNEIE 0x00000002U /*!<Control Buffer Ready Interrupt Enable */
Kojto 122:f9eeca106725 6958 #define SPDIFRX_IMR_PERRIE 0x00000004U /*!<Parity error interrupt enable */
Kojto 122:f9eeca106725 6959 #define SPDIFRX_IMR_OVRIE 0x00000008U /*!<Overrun error Interrupt Enable */
Kojto 122:f9eeca106725 6960 #define SPDIFRX_IMR_SBLKIE 0x00000010U /*!<Synchronization Block Detected Interrupt Enable */
Kojto 122:f9eeca106725 6961 #define SPDIFRX_IMR_SYNCDIE 0x00000020U /*!<Synchronization Done */
Kojto 122:f9eeca106725 6962 #define SPDIFRX_IMR_IFEIE 0x00000040U /*!<Serial Interface Error Interrupt Enable */
Kojto 122:f9eeca106725 6963
Kojto 122:f9eeca106725 6964 /******************* Bit definition for SPDIFRX_SR register *******************/
Kojto 122:f9eeca106725 6965 #define SPDIFRX_SR_RXNE 0x00000001U /*!<Read data register not empty */
Kojto 122:f9eeca106725 6966 #define SPDIFRX_SR_CSRNE 0x00000002U /*!<The Control Buffer register is not empty */
Kojto 122:f9eeca106725 6967 #define SPDIFRX_SR_PERR 0x00000004U /*!<Parity error */
Kojto 122:f9eeca106725 6968 #define SPDIFRX_SR_OVR 0x00000008U /*!<Overrun error */
Kojto 122:f9eeca106725 6969 #define SPDIFRX_SR_SBD 0x00000010U /*!<Synchronization Block Detected */
Kojto 122:f9eeca106725 6970 #define SPDIFRX_SR_SYNCD 0x00000020U /*!<Synchronization Done */
Kojto 122:f9eeca106725 6971 #define SPDIFRX_SR_FERR 0x00000040U /*!<Framing error */
Kojto 122:f9eeca106725 6972 #define SPDIFRX_SR_SERR 0x00000080U /*!<Synchronization error */
Kojto 122:f9eeca106725 6973 #define SPDIFRX_SR_TERR 0x00000100U /*!<Time-out error */
Kojto 122:f9eeca106725 6974 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U /*!<Duration of 5 symbols counted with spdif_clk */
Kojto 122:f9eeca106725 6975
Kojto 122:f9eeca106725 6976 /******************* Bit definition for SPDIFRX_IFCR register *******************/
Kojto 122:f9eeca106725 6977 #define SPDIFRX_IFCR_PERRCF 0x00000004U /*!<Clears the Parity error flag */
Kojto 122:f9eeca106725 6978 #define SPDIFRX_IFCR_OVRCF 0x00000008U /*!<Clears the Overrun error flag */
Kojto 122:f9eeca106725 6979 #define SPDIFRX_IFCR_SBDCF 0x00000010U /*!<Clears the Synchronization Block Detected flag */
Kojto 122:f9eeca106725 6980 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U /*!<Clears the Synchronization Done flag */
Kojto 122:f9eeca106725 6981
Kojto 122:f9eeca106725 6982 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
Kojto 122:f9eeca106725 6983 #define SPDIFRX_DR0_DR 0x00FFFFFFU /*!<Data value */
Kojto 122:f9eeca106725 6984 #define SPDIFRX_DR0_PE 0x01000000U /*!<Parity Error bit */
Kojto 122:f9eeca106725 6985 #define SPDIFRX_DR0_V 0x02000000U /*!<Validity bit */
Kojto 122:f9eeca106725 6986 #define SPDIFRX_DR0_U 0x04000000U /*!<User bit */
Kojto 122:f9eeca106725 6987 #define SPDIFRX_DR0_C 0x08000000U /*!<Channel Status bit */
Kojto 122:f9eeca106725 6988 #define SPDIFRX_DR0_PT 0x30000000U /*!<Preamble Type */
Kojto 122:f9eeca106725 6989
Kojto 122:f9eeca106725 6990 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
Kojto 122:f9eeca106725 6991 #define SPDIFRX_DR1_DR 0xFFFFFF00U /*!<Data value */
Kojto 122:f9eeca106725 6992 #define SPDIFRX_DR1_PT 0x00000030U /*!<Preamble Type */
Kojto 122:f9eeca106725 6993 #define SPDIFRX_DR1_C 0x00000008U /*!<Channel Status bit */
Kojto 122:f9eeca106725 6994 #define SPDIFRX_DR1_U 0x00000004U /*!<User bit */
Kojto 122:f9eeca106725 6995 #define SPDIFRX_DR1_V 0x00000002U /*!<Validity bit */
Kojto 122:f9eeca106725 6996 #define SPDIFRX_DR1_PE 0x00000001U /*!<Parity Error bit */
Kojto 122:f9eeca106725 6997
Kojto 122:f9eeca106725 6998 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
Kojto 122:f9eeca106725 6999 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U /*!<Data value Channel B */
Kojto 122:f9eeca106725 7000 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU /*!<Data value Channel A */
Kojto 122:f9eeca106725 7001
Kojto 122:f9eeca106725 7002 /******************* Bit definition for SPDIFRX_CSR register *******************/
Kojto 122:f9eeca106725 7003 #define SPDIFRX_CSR_USR 0x0000FFFFU /*!<User data information */
Kojto 122:f9eeca106725 7004 #define SPDIFRX_CSR_CS 0x00FF0000U /*!<Channel A status information */
Kojto 122:f9eeca106725 7005 #define SPDIFRX_CSR_SOB 0x01000000U /*!<Start Of Block */
Kojto 122:f9eeca106725 7006
Kojto 122:f9eeca106725 7007 /******************* Bit definition for SPDIFRX_DIR register *******************/
Kojto 122:f9eeca106725 7008 #define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
Kojto 122:f9eeca106725 7009 #define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
Kojto 122:f9eeca106725 7010
Kojto 122:f9eeca106725 7011
Kojto 122:f9eeca106725 7012 /******************************************************************************/
Kojto 122:f9eeca106725 7013 /* */
Kojto 122:f9eeca106725 7014 /* SD host Interface */
Kojto 122:f9eeca106725 7015 /* */
Kojto 122:f9eeca106725 7016 /******************************************************************************/
Kojto 122:f9eeca106725 7017 /****************** Bit definition for SDMMC_POWER register ******************/
Kojto 122:f9eeca106725 7018 #define SDMMC_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 122:f9eeca106725 7019 #define SDMMC_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 7020 #define SDMMC_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 7021
Kojto 122:f9eeca106725 7022 /****************** Bit definition for SDMMC_CLKCR register ******************/
Kojto 122:f9eeca106725 7023 #define SDMMC_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
Kojto 122:f9eeca106725 7024 #define SDMMC_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
Kojto 122:f9eeca106725 7025 #define SDMMC_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
Kojto 122:f9eeca106725 7026 #define SDMMC_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
Kojto 122:f9eeca106725 7027
Kojto 122:f9eeca106725 7028 #define SDMMC_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 122:f9eeca106725 7029 #define SDMMC_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
Kojto 122:f9eeca106725 7030 #define SDMMC_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7031
Kojto 122:f9eeca106725 7032 #define SDMMC_CLKCR_NEGEDGE 0x2000U /*!<SDMMC_CK dephasing selection bit */
Kojto 122:f9eeca106725 7033 #define SDMMC_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
Kojto 122:f9eeca106725 7034
Kojto 122:f9eeca106725 7035 /******************* Bit definition for SDMMC_ARG register *******************/
Kojto 122:f9eeca106725 7036 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
Kojto 122:f9eeca106725 7037
Kojto 122:f9eeca106725 7038 /******************* Bit definition for SDMMC_CMD register *******************/
Kojto 122:f9eeca106725 7039 #define SDMMC_CMD_CMDINDEX 0x003FU /*!<Command Index */
Kojto 122:f9eeca106725 7040
Kojto 122:f9eeca106725 7041 #define SDMMC_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 122:f9eeca106725 7042 #define SDMMC_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
Kojto 122:f9eeca106725 7043 #define SDMMC_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
Kojto 122:f9eeca106725 7044
Kojto 122:f9eeca106725 7045 #define SDMMC_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
Kojto 122:f9eeca106725 7046 #define SDMMC_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 122:f9eeca106725 7047 #define SDMMC_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
Kojto 122:f9eeca106725 7048 #define SDMMC_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
Kojto 122:f9eeca106725 7049
Kojto 122:f9eeca106725 7050 /***************** Bit definition for SDMMC_RESPCMD register *****************/
Kojto 122:f9eeca106725 7051 #define SDMMC_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
Kojto 122:f9eeca106725 7052
Kojto 122:f9eeca106725 7053 /****************** Bit definition for SDMMC_RESP0 register ******************/
Kojto 122:f9eeca106725 7054 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
Kojto 122:f9eeca106725 7055
Kojto 122:f9eeca106725 7056 /****************** Bit definition for SDMMC_RESP1 register ******************/
Kojto 122:f9eeca106725 7057 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
Kojto 122:f9eeca106725 7058
Kojto 122:f9eeca106725 7059 /****************** Bit definition for SDMMC_RESP2 register ******************/
Kojto 122:f9eeca106725 7060 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
Kojto 122:f9eeca106725 7061
Kojto 122:f9eeca106725 7062 /****************** Bit definition for SDMMC_RESP3 register ******************/
Kojto 122:f9eeca106725 7063 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
Kojto 122:f9eeca106725 7064
Kojto 122:f9eeca106725 7065 /****************** Bit definition for SDMMC_RESP4 register ******************/
Kojto 122:f9eeca106725 7066 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
Kojto 122:f9eeca106725 7067
Kojto 122:f9eeca106725 7068 /****************** Bit definition for SDMMC_DTIMER register *****************/
Kojto 122:f9eeca106725 7069 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
Kojto 122:f9eeca106725 7070
Kojto 122:f9eeca106725 7071 /****************** Bit definition for SDMMC_DLEN register *******************/
Kojto 122:f9eeca106725 7072 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
Kojto 122:f9eeca106725 7073
Kojto 122:f9eeca106725 7074 /****************** Bit definition for SDMMC_DCTRL register ******************/
Kojto 122:f9eeca106725 7075 #define SDMMC_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
Kojto 122:f9eeca106725 7076 #define SDMMC_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
Kojto 122:f9eeca106725 7077 #define SDMMC_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
Kojto 122:f9eeca106725 7078 #define SDMMC_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
Kojto 122:f9eeca106725 7079
Kojto 122:f9eeca106725 7080 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 122:f9eeca106725 7081 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7082 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7083 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7084 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 7085
Kojto 122:f9eeca106725 7086 #define SDMMC_DCTRL_RWSTART 0x0100U /*!<Read wait start */
Kojto 122:f9eeca106725 7087 #define SDMMC_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
Kojto 122:f9eeca106725 7088 #define SDMMC_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
Kojto 122:f9eeca106725 7089 #define SDMMC_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
Kojto 122:f9eeca106725 7090
Kojto 122:f9eeca106725 7091 /****************** Bit definition for SDMMC_DCOUNT register *****************/
Kojto 122:f9eeca106725 7092 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
Kojto 122:f9eeca106725 7093
Kojto 122:f9eeca106725 7094 /****************** Bit definition for SDMMC_STA registe ********************/
Kojto 122:f9eeca106725 7095 #define SDMMC_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
Kojto 122:f9eeca106725 7096 #define SDMMC_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
Kojto 122:f9eeca106725 7097 #define SDMMC_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
Kojto 122:f9eeca106725 7098 #define SDMMC_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
Kojto 122:f9eeca106725 7099 #define SDMMC_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
Kojto 122:f9eeca106725 7100 #define SDMMC_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
Kojto 122:f9eeca106725 7101 #define SDMMC_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
Kojto 122:f9eeca106725 7102 #define SDMMC_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
Kojto 122:f9eeca106725 7103 #define SDMMC_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 122:f9eeca106725 7104 #define SDMMC_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
Kojto 122:f9eeca106725 7105 #define SDMMC_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
Kojto 122:f9eeca106725 7106 #define SDMMC_STA_TXACT 0x00001000U /*!<Data transmit in progress */
Kojto 122:f9eeca106725 7107 #define SDMMC_STA_RXACT 0x00002000U /*!<Data receive in progress */
Kojto 122:f9eeca106725 7108 #define SDMMC_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 122:f9eeca106725 7109 #define SDMMC_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 122:f9eeca106725 7110 #define SDMMC_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
Kojto 122:f9eeca106725 7111 #define SDMMC_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
Kojto 122:f9eeca106725 7112 #define SDMMC_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
Kojto 122:f9eeca106725 7113 #define SDMMC_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
Kojto 122:f9eeca106725 7114 #define SDMMC_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
Kojto 122:f9eeca106725 7115 #define SDMMC_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
Kojto 122:f9eeca106725 7116 #define SDMMC_STA_SDIOIT 0x00400000U /*!<SDMMC interrupt received */
Kojto 122:f9eeca106725 7117
Kojto 122:f9eeca106725 7118 /******************* Bit definition for SDMMC_ICR register *******************/
Kojto 122:f9eeca106725 7119 #define SDMMC_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
Kojto 122:f9eeca106725 7120 #define SDMMC_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
Kojto 122:f9eeca106725 7121 #define SDMMC_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
Kojto 122:f9eeca106725 7122 #define SDMMC_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
Kojto 122:f9eeca106725 7123 #define SDMMC_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
Kojto 122:f9eeca106725 7124 #define SDMMC_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
Kojto 122:f9eeca106725 7125 #define SDMMC_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
Kojto 122:f9eeca106725 7126 #define SDMMC_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
Kojto 122:f9eeca106725 7127 #define SDMMC_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
Kojto 122:f9eeca106725 7128 #define SDMMC_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
Kojto 122:f9eeca106725 7129 #define SDMMC_ICR_SDIOITC 0x00400000U /*!<SDMMCIT flag clear bit */
Kojto 122:f9eeca106725 7130
Kojto 122:f9eeca106725 7131 /****************** Bit definition for SDMMC_MASK register *******************/
Kojto 122:f9eeca106725 7132 #define SDMMC_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
Kojto 122:f9eeca106725 7133 #define SDMMC_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
Kojto 122:f9eeca106725 7134 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 7135 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
Kojto 122:f9eeca106725 7136 #define SDMMC_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 122:f9eeca106725 7137 #define SDMMC_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 122:f9eeca106725 7138 #define SDMMC_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
Kojto 122:f9eeca106725 7139 #define SDMMC_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
Kojto 122:f9eeca106725 7140 #define SDMMC_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
Kojto 122:f9eeca106725 7141 #define SDMMC_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
Kojto 122:f9eeca106725 7142 #define SDMMC_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
Kojto 122:f9eeca106725 7143 #define SDMMC_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
Kojto 122:f9eeca106725 7144 #define SDMMC_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
Kojto 122:f9eeca106725 7145 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 122:f9eeca106725 7146 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
Kojto 122:f9eeca106725 7147 #define SDMMC_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
Kojto 122:f9eeca106725 7148 #define SDMMC_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
Kojto 122:f9eeca106725 7149 #define SDMMC_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
Kojto 122:f9eeca106725 7150 #define SDMMC_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
Kojto 122:f9eeca106725 7151 #define SDMMC_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
Kojto 122:f9eeca106725 7152 #define SDMMC_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
Kojto 122:f9eeca106725 7153 #define SDMMC_MASK_SDIOITIE 0x00400000U /*!<SDMMC Mode Interrupt Received interrupt Enable */
Kojto 122:f9eeca106725 7154
Kojto 122:f9eeca106725 7155 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
Kojto 122:f9eeca106725 7156 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
Kojto 122:f9eeca106725 7157
Kojto 122:f9eeca106725 7158 /****************** Bit definition for SDMMC_FIFO register *******************/
Kojto 122:f9eeca106725 7159 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
Kojto 122:f9eeca106725 7160
Kojto 122:f9eeca106725 7161 /******************************************************************************/
Kojto 122:f9eeca106725 7162 /* */
Kojto 122:f9eeca106725 7163 /* Serial Peripheral Interface (SPI) */
Kojto 122:f9eeca106725 7164 /* */
Kojto 122:f9eeca106725 7165 /******************************************************************************/
Kojto 122:f9eeca106725 7166 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 122:f9eeca106725 7167 #define SPI_CR1_CPHA 0x00000001U /*!< Clock Phase */
Kojto 122:f9eeca106725 7168 #define SPI_CR1_CPOL 0x00000002U /*!< Clock Polarity */
Kojto 122:f9eeca106725 7169 #define SPI_CR1_MSTR 0x00000004U /*!< Master Selection */
Kojto 122:f9eeca106725 7170 #define SPI_CR1_BR 0x00000038U /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 7171 #define SPI_CR1_BR_0 0x00000008U /*!< Bit 0 */
Kojto 122:f9eeca106725 7172 #define SPI_CR1_BR_1 0x00000010U /*!< Bit 1 */
Kojto 122:f9eeca106725 7173 #define SPI_CR1_BR_2 0x00000020U /*!< Bit 2 */
Kojto 122:f9eeca106725 7174 #define SPI_CR1_SPE 0x00000040U /*!< SPI Enable */
Kojto 122:f9eeca106725 7175 #define SPI_CR1_LSBFIRST 0x00000080U /*!< Frame Format */
Kojto 122:f9eeca106725 7176 #define SPI_CR1_SSI 0x00000100U /*!< Internal slave select */
Kojto 122:f9eeca106725 7177 #define SPI_CR1_SSM 0x00000200U /*!< Software slave management */
Kojto 122:f9eeca106725 7178 #define SPI_CR1_RXONLY 0x00000400U /*!< Receive only */
Kojto 122:f9eeca106725 7179 #define SPI_CR1_CRCL 0x00000800U /*!< CRC Length */
Kojto 122:f9eeca106725 7180 #define SPI_CR1_CRCNEXT 0x00001000U /*!< Transmit CRC next */
Kojto 122:f9eeca106725 7181 #define SPI_CR1_CRCEN 0x00002000U /*!< Hardware CRC calculation enable */
Kojto 122:f9eeca106725 7182 #define SPI_CR1_BIDIOE 0x00004000U /*!< Output enable in bidirectional mode */
Kojto 122:f9eeca106725 7183 #define SPI_CR1_BIDIMODE 0x00008000U /*!< Bidirectional data mode enable */
Kojto 122:f9eeca106725 7184
Kojto 122:f9eeca106725 7185 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 122:f9eeca106725 7186 #define SPI_CR2_RXDMAEN 0x00000001U /*!< Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 7187 #define SPI_CR2_TXDMAEN 0x00000002U /*!< Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 7188 #define SPI_CR2_SSOE 0x00000004U /*!< SS Output Enable */
Kojto 122:f9eeca106725 7189 #define SPI_CR2_NSSP 0x00000008U /*!< NSS pulse management Enable */
Kojto 122:f9eeca106725 7190 #define SPI_CR2_FRF 0x00000010U /*!< Frame Format Enable */
Kojto 122:f9eeca106725 7191 #define SPI_CR2_ERRIE 0x00000020U /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 7192 #define SPI_CR2_RXNEIE 0x00000040U /*!< RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 7193 #define SPI_CR2_TXEIE 0x00000080U /*!< Tx buffer Empty Interrupt Enable */
Kojto 122:f9eeca106725 7194 #define SPI_CR2_DS 0x00000F00U /*!< DS[3:0] Data Size */
Kojto 122:f9eeca106725 7195 #define SPI_CR2_DS_0 0x00000100U /*!< Bit 0 */
Kojto 122:f9eeca106725 7196 #define SPI_CR2_DS_1 0x00000200U /*!< Bit 1 */
Kojto 122:f9eeca106725 7197 #define SPI_CR2_DS_2 0x00000400U /*!< Bit 2 */
Kojto 122:f9eeca106725 7198 #define SPI_CR2_DS_3 0x00000800U /*!< Bit 3 */
Kojto 122:f9eeca106725 7199 #define SPI_CR2_FRXTH 0x00001000U /*!< FIFO reception Threshold */
Kojto 122:f9eeca106725 7200 #define SPI_CR2_LDMARX 0x00002000U /*!< Last DMA transfer for reception */
Kojto 122:f9eeca106725 7201 #define SPI_CR2_LDMATX 0x00004000U /*!< Last DMA transfer for transmission */
Kojto 122:f9eeca106725 7202
Kojto 122:f9eeca106725 7203 /******************** Bit definition for SPI_SR register ********************/
Kojto 122:f9eeca106725 7204 #define SPI_SR_RXNE 0x00000001U /*!< Receive buffer Not Empty */
Kojto 122:f9eeca106725 7205 #define SPI_SR_TXE 0x00000002U /*!< Transmit buffer Empty */
Kojto 122:f9eeca106725 7206 #define SPI_SR_CHSIDE 0x00000004U /*!< Channel side */
Kojto 122:f9eeca106725 7207 #define SPI_SR_UDR 0x00000008U /*!< Underrun flag */
Kojto 122:f9eeca106725 7208 #define SPI_SR_CRCERR 0x00000010U /*!< CRC Error flag */
Kojto 122:f9eeca106725 7209 #define SPI_SR_MODF 0x00000020U /*!< Mode fault */
Kojto 122:f9eeca106725 7210 #define SPI_SR_OVR 0x00000040U /*!< Overrun flag */
Kojto 122:f9eeca106725 7211 #define SPI_SR_BSY 0x00000080U /*!< Busy flag */
Kojto 122:f9eeca106725 7212 #define SPI_SR_FRE 0x00000100U /*!< TI frame format error */
Kojto 122:f9eeca106725 7213 #define SPI_SR_FRLVL 0x00000600U /*!< FIFO Reception Level */
Kojto 122:f9eeca106725 7214 #define SPI_SR_FRLVL_0 0x00000200U /*!< Bit 0 */
Kojto 122:f9eeca106725 7215 #define SPI_SR_FRLVL_1 0x00000400U /*!< Bit 1 */
Kojto 122:f9eeca106725 7216 #define SPI_SR_FTLVL 0x00001800U /*!< FIFO Transmission Level */
Kojto 122:f9eeca106725 7217 #define SPI_SR_FTLVL_0 0x00000800U /*!< Bit 0 */
Kojto 122:f9eeca106725 7218 #define SPI_SR_FTLVL_1 0x00001000U /*!< Bit 1 */
Kojto 122:f9eeca106725 7219
Kojto 122:f9eeca106725 7220 /******************** Bit definition for SPI_DR register ********************/
Kojto 122:f9eeca106725 7221 #define SPI_DR_DR 0xFFFFU /*!< Data Register */
Kojto 122:f9eeca106725 7222
Kojto 122:f9eeca106725 7223 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 122:f9eeca106725 7224 #define SPI_CRCPR_CRCPOLY 0xFFFFU /*!< CRC polynomial register */
Kojto 122:f9eeca106725 7225
Kojto 122:f9eeca106725 7226 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 122:f9eeca106725 7227 #define SPI_RXCRCR_RXCRC 0xFFFFU /*!< Rx CRC Register */
Kojto 122:f9eeca106725 7228
Kojto 122:f9eeca106725 7229 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 122:f9eeca106725 7230 #define SPI_TXCRCR_TXCRC 0xFFFFU /*!< Tx CRC Register */
Kojto 122:f9eeca106725 7231
Kojto 122:f9eeca106725 7232 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 122:f9eeca106725 7233 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
Kojto 122:f9eeca106725 7234 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 122:f9eeca106725 7235 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 7236 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 7237 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
Kojto 122:f9eeca106725 7238 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 122:f9eeca106725 7239 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7240 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7241 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
Kojto 122:f9eeca106725 7242 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 122:f9eeca106725 7243 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 7244 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7245 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
Kojto 122:f9eeca106725 7246 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
Kojto 122:f9eeca106725 7247 #define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
Kojto 122:f9eeca106725 7248
Kojto 122:f9eeca106725 7249 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 122:f9eeca106725 7250 #define SPI_I2SPR_I2SDIV 0x00FFU /*!<I2S Linear prescaler */
Kojto 122:f9eeca106725 7251 #define SPI_I2SPR_ODD 0x0100U /*!<Odd factor for the prescaler */
Kojto 122:f9eeca106725 7252 #define SPI_I2SPR_MCKOE 0x0200U /*!<Master Clock Output Enable */
Kojto 122:f9eeca106725 7253
Kojto 122:f9eeca106725 7254
Kojto 122:f9eeca106725 7255 /******************************************************************************/
Kojto 122:f9eeca106725 7256 /* */
Kojto 122:f9eeca106725 7257 /* SYSCFG */
Kojto 122:f9eeca106725 7258 /* */
Kojto 122:f9eeca106725 7259 /******************************************************************************/
Kojto 122:f9eeca106725 7260 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 122:f9eeca106725 7261 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U /*!< Boot information after Reset */
Kojto 122:f9eeca106725 7262
Kojto 122:f9eeca106725 7263 #define SYSCFG_MEMRMP_SWP_FB 0x00000100U /*!< User Flash Bank swap */
Kojto 122:f9eeca106725 7264
Kojto 122:f9eeca106725 7265 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U /*!< FMC Memory Mapping swapping */
Kojto 122:f9eeca106725 7266 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
Kojto 122:f9eeca106725 7267 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
Kojto 122:f9eeca106725 7268
Kojto 122:f9eeca106725 7269 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 122:f9eeca106725 7270 #define SYSCFG_PMC_I2C1_FMP 0x00000001U /*!< I2C1_FMP I2C1 Fast Mode + Enable */
Kojto 122:f9eeca106725 7271 #define SYSCFG_PMC_I2C2_FMP 0x00000002U /*!< I2C2_FMP I2C2 Fast Mode + Enable */
Kojto 122:f9eeca106725 7272 #define SYSCFG_PMC_I2C3_FMP 0x00000004U /*!< I2C3_FMP I2C3 Fast Mode + Enable */
Kojto 122:f9eeca106725 7273 #define SYSCFG_PMC_I2C4_FMP 0x00000008U /*!< I2C4_FMP I2C4 Fast Mode + Enable */
Kojto 122:f9eeca106725 7274 #define SYSCFG_PMC_I2C_PB6_FMP 0x00000010U /*!< PB6_FMP Fast Mode + Enable */
Kojto 122:f9eeca106725 7275 #define SYSCFG_PMC_I2C_PB7_FMP 0x00000020U /*!< PB7_FMP Fast Mode + Enable */
Kojto 122:f9eeca106725 7276 #define SYSCFG_PMC_I2C_PB8_FMP 0x00000040U /*!< PB8_FMP Fast Mode + Enable */
Kojto 122:f9eeca106725 7277 #define SYSCFG_PMC_I2C_PB9_FMP 0x00000080U /*!< PB9_FMP Fast Mode + Enable */
Kojto 122:f9eeca106725 7278
Kojto 122:f9eeca106725 7279 #define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 7280 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 7281 #define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 7282 #define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
Kojto 122:f9eeca106725 7283
Kojto 122:f9eeca106725 7284 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
Kojto 122:f9eeca106725 7285
Kojto 122:f9eeca106725 7286 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 122:f9eeca106725 7287 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
Kojto 122:f9eeca106725 7288 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
Kojto 122:f9eeca106725 7289 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
Kojto 122:f9eeca106725 7290 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
Kojto 122:f9eeca106725 7291 /**
Kojto 122:f9eeca106725 7292 * @brief EXTI0 configuration
Kojto 122:f9eeca106725 7293 */
Kojto 122:f9eeca106725 7294 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
Kojto 122:f9eeca106725 7295 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
Kojto 122:f9eeca106725 7296 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
Kojto 122:f9eeca106725 7297 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
Kojto 122:f9eeca106725 7298 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
Kojto 122:f9eeca106725 7299 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
Kojto 122:f9eeca106725 7300 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
Kojto 122:f9eeca106725 7301 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
Kojto 122:f9eeca106725 7302 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
Kojto 122:f9eeca106725 7303 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
Kojto 122:f9eeca106725 7304 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
Kojto 122:f9eeca106725 7305
Kojto 122:f9eeca106725 7306 /**
Kojto 122:f9eeca106725 7307 * @brief EXTI1 configuration
Kojto 122:f9eeca106725 7308 */
Kojto 122:f9eeca106725 7309 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
Kojto 122:f9eeca106725 7310 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
Kojto 122:f9eeca106725 7311 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
Kojto 122:f9eeca106725 7312 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
Kojto 122:f9eeca106725 7313 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
Kojto 122:f9eeca106725 7314 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
Kojto 122:f9eeca106725 7315 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
Kojto 122:f9eeca106725 7316 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
Kojto 122:f9eeca106725 7317 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
Kojto 122:f9eeca106725 7318 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
Kojto 122:f9eeca106725 7319 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
Kojto 122:f9eeca106725 7320
Kojto 122:f9eeca106725 7321 /**
Kojto 122:f9eeca106725 7322 * @brief EXTI2 configuration
Kojto 122:f9eeca106725 7323 */
Kojto 122:f9eeca106725 7324 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
Kojto 122:f9eeca106725 7325 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
Kojto 122:f9eeca106725 7326 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
Kojto 122:f9eeca106725 7327 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
Kojto 122:f9eeca106725 7328 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
Kojto 122:f9eeca106725 7329 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
Kojto 122:f9eeca106725 7330 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
Kojto 122:f9eeca106725 7331 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
Kojto 122:f9eeca106725 7332 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
Kojto 122:f9eeca106725 7333 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
Kojto 122:f9eeca106725 7334 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
Kojto 122:f9eeca106725 7335
Kojto 122:f9eeca106725 7336 /**
Kojto 122:f9eeca106725 7337 * @brief EXTI3 configuration
Kojto 122:f9eeca106725 7338 */
Kojto 122:f9eeca106725 7339 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
Kojto 122:f9eeca106725 7340 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
Kojto 122:f9eeca106725 7341 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
Kojto 122:f9eeca106725 7342 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
Kojto 122:f9eeca106725 7343 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
Kojto 122:f9eeca106725 7344 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
Kojto 122:f9eeca106725 7345 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
Kojto 122:f9eeca106725 7346 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
Kojto 122:f9eeca106725 7347 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
Kojto 122:f9eeca106725 7348 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
Kojto 122:f9eeca106725 7349 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
Kojto 122:f9eeca106725 7350
Kojto 122:f9eeca106725 7351 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 122:f9eeca106725 7352 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
Kojto 122:f9eeca106725 7353 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
Kojto 122:f9eeca106725 7354 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
Kojto 122:f9eeca106725 7355 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
Kojto 122:f9eeca106725 7356 /**
Kojto 122:f9eeca106725 7357 * @brief EXTI4 configuration
Kojto 122:f9eeca106725 7358 */
Kojto 122:f9eeca106725 7359 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
Kojto 122:f9eeca106725 7360 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
Kojto 122:f9eeca106725 7361 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
Kojto 122:f9eeca106725 7362 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
Kojto 122:f9eeca106725 7363 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
Kojto 122:f9eeca106725 7364 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
Kojto 122:f9eeca106725 7365 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
Kojto 122:f9eeca106725 7366 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
Kojto 122:f9eeca106725 7367 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
Kojto 122:f9eeca106725 7368 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
Kojto 122:f9eeca106725 7369 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
Kojto 122:f9eeca106725 7370
Kojto 122:f9eeca106725 7371 /**
Kojto 122:f9eeca106725 7372 * @brief EXTI5 configuration
Kojto 122:f9eeca106725 7373 */
Kojto 122:f9eeca106725 7374 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
Kojto 122:f9eeca106725 7375 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
Kojto 122:f9eeca106725 7376 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
Kojto 122:f9eeca106725 7377 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
Kojto 122:f9eeca106725 7378 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
Kojto 122:f9eeca106725 7379 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
Kojto 122:f9eeca106725 7380 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
Kojto 122:f9eeca106725 7381 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
Kojto 122:f9eeca106725 7382 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
Kojto 122:f9eeca106725 7383 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
Kojto 122:f9eeca106725 7384 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
Kojto 122:f9eeca106725 7385
Kojto 122:f9eeca106725 7386 /**
Kojto 122:f9eeca106725 7387 * @brief EXTI6 configuration
Kojto 122:f9eeca106725 7388 */
Kojto 122:f9eeca106725 7389 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
Kojto 122:f9eeca106725 7390 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
Kojto 122:f9eeca106725 7391 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
Kojto 122:f9eeca106725 7392 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
Kojto 122:f9eeca106725 7393 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
Kojto 122:f9eeca106725 7394 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
Kojto 122:f9eeca106725 7395 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
Kojto 122:f9eeca106725 7396 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
Kojto 122:f9eeca106725 7397 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
Kojto 122:f9eeca106725 7398 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
Kojto 122:f9eeca106725 7399 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
Kojto 122:f9eeca106725 7400
Kojto 122:f9eeca106725 7401 /**
Kojto 122:f9eeca106725 7402 * @brief EXTI7 configuration
Kojto 122:f9eeca106725 7403 */
Kojto 122:f9eeca106725 7404 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
Kojto 122:f9eeca106725 7405 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
Kojto 122:f9eeca106725 7406 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
Kojto 122:f9eeca106725 7407 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
Kojto 122:f9eeca106725 7408 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
Kojto 122:f9eeca106725 7409 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
Kojto 122:f9eeca106725 7410 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
Kojto 122:f9eeca106725 7411 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
Kojto 122:f9eeca106725 7412 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
Kojto 122:f9eeca106725 7413 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
Kojto 122:f9eeca106725 7414 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
Kojto 122:f9eeca106725 7415
Kojto 122:f9eeca106725 7416 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 122:f9eeca106725 7417 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
Kojto 122:f9eeca106725 7418 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
Kojto 122:f9eeca106725 7419 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
Kojto 122:f9eeca106725 7420 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
Kojto 122:f9eeca106725 7421
Kojto 122:f9eeca106725 7422 /**
Kojto 122:f9eeca106725 7423 * @brief EXTI8 configuration
Kojto 122:f9eeca106725 7424 */
Kojto 122:f9eeca106725 7425 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
Kojto 122:f9eeca106725 7426 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
Kojto 122:f9eeca106725 7427 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
Kojto 122:f9eeca106725 7428 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
Kojto 122:f9eeca106725 7429 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
Kojto 122:f9eeca106725 7430 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
Kojto 122:f9eeca106725 7431 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
Kojto 122:f9eeca106725 7432 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
Kojto 122:f9eeca106725 7433 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
Kojto 122:f9eeca106725 7434 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
Kojto 122:f9eeca106725 7435
Kojto 122:f9eeca106725 7436 /**
Kojto 122:f9eeca106725 7437 * @brief EXTI9 configuration
Kojto 122:f9eeca106725 7438 */
Kojto 122:f9eeca106725 7439 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
Kojto 122:f9eeca106725 7440 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
Kojto 122:f9eeca106725 7441 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
Kojto 122:f9eeca106725 7442 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
Kojto 122:f9eeca106725 7443 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
Kojto 122:f9eeca106725 7444 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
Kojto 122:f9eeca106725 7445 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
Kojto 122:f9eeca106725 7446 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
Kojto 122:f9eeca106725 7447 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
Kojto 122:f9eeca106725 7448 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
Kojto 122:f9eeca106725 7449
Kojto 122:f9eeca106725 7450 /**
Kojto 122:f9eeca106725 7451 * @brief EXTI10 configuration
Kojto 122:f9eeca106725 7452 */
Kojto 122:f9eeca106725 7453 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
Kojto 122:f9eeca106725 7454 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
Kojto 122:f9eeca106725 7455 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
Kojto 122:f9eeca106725 7456 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
Kojto 122:f9eeca106725 7457 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
Kojto 122:f9eeca106725 7458 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
Kojto 122:f9eeca106725 7459 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
Kojto 122:f9eeca106725 7460 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
Kojto 122:f9eeca106725 7461 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
Kojto 122:f9eeca106725 7462 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
Kojto 122:f9eeca106725 7463
Kojto 122:f9eeca106725 7464 /**
Kojto 122:f9eeca106725 7465 * @brief EXTI11 configuration
Kojto 122:f9eeca106725 7466 */
Kojto 122:f9eeca106725 7467 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
Kojto 122:f9eeca106725 7468 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
Kojto 122:f9eeca106725 7469 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
Kojto 122:f9eeca106725 7470 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
Kojto 122:f9eeca106725 7471 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
Kojto 122:f9eeca106725 7472 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
Kojto 122:f9eeca106725 7473 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
Kojto 122:f9eeca106725 7474 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
Kojto 122:f9eeca106725 7475 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
Kojto 122:f9eeca106725 7476 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
Kojto 122:f9eeca106725 7477
Kojto 122:f9eeca106725 7478
Kojto 122:f9eeca106725 7479 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 122:f9eeca106725 7480 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
Kojto 122:f9eeca106725 7481 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
Kojto 122:f9eeca106725 7482 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
Kojto 122:f9eeca106725 7483 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
Kojto 122:f9eeca106725 7484 /**
Kojto 122:f9eeca106725 7485 * @brief EXTI12 configuration
Kojto 122:f9eeca106725 7486 */
Kojto 122:f9eeca106725 7487 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
Kojto 122:f9eeca106725 7488 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
Kojto 122:f9eeca106725 7489 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
Kojto 122:f9eeca106725 7490 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
Kojto 122:f9eeca106725 7491 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
Kojto 122:f9eeca106725 7492 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
Kojto 122:f9eeca106725 7493 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
Kojto 122:f9eeca106725 7494 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
Kojto 122:f9eeca106725 7495 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
Kojto 122:f9eeca106725 7496 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
Kojto 122:f9eeca106725 7497
Kojto 122:f9eeca106725 7498 /**
Kojto 122:f9eeca106725 7499 * @brief EXTI13 configuration
Kojto 122:f9eeca106725 7500 */
Kojto 122:f9eeca106725 7501 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
Kojto 122:f9eeca106725 7502 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
Kojto 122:f9eeca106725 7503 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
Kojto 122:f9eeca106725 7504 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
Kojto 122:f9eeca106725 7505 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
Kojto 122:f9eeca106725 7506 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
Kojto 122:f9eeca106725 7507 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
Kojto 122:f9eeca106725 7508 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
Kojto 122:f9eeca106725 7509 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
Kojto 122:f9eeca106725 7510 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
Kojto 122:f9eeca106725 7511
Kojto 122:f9eeca106725 7512 /**
Kojto 122:f9eeca106725 7513 * @brief EXTI14 configuration
Kojto 122:f9eeca106725 7514 */
Kojto 122:f9eeca106725 7515 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
Kojto 122:f9eeca106725 7516 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
Kojto 122:f9eeca106725 7517 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
Kojto 122:f9eeca106725 7518 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
Kojto 122:f9eeca106725 7519 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
Kojto 122:f9eeca106725 7520 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
Kojto 122:f9eeca106725 7521 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
Kojto 122:f9eeca106725 7522 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
Kojto 122:f9eeca106725 7523 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
Kojto 122:f9eeca106725 7524 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
Kojto 122:f9eeca106725 7525
Kojto 122:f9eeca106725 7526 /**
Kojto 122:f9eeca106725 7527 * @brief EXTI15 configuration
Kojto 122:f9eeca106725 7528 */
Kojto 122:f9eeca106725 7529 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
Kojto 122:f9eeca106725 7530 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
Kojto 122:f9eeca106725 7531 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
Kojto 122:f9eeca106725 7532 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
Kojto 122:f9eeca106725 7533 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
Kojto 122:f9eeca106725 7534 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
Kojto 122:f9eeca106725 7535 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
Kojto 122:f9eeca106725 7536 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
Kojto 122:f9eeca106725 7537 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
Kojto 122:f9eeca106725 7538 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
Kojto 122:f9eeca106725 7539
Kojto 122:f9eeca106725 7540 /****************** Bit definition for SYSCFG_CBR register ******************/
Kojto 122:f9eeca106725 7541 #define SYSCFG_CBR_CLL 0x00000001U /*!<Core Lockup Lock */
Kojto 122:f9eeca106725 7542 #define SYSCFG_CBR_PVDL 0x00000004U /*!<PVD Lock */
Kojto 122:f9eeca106725 7543
Kojto 122:f9eeca106725 7544 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 122:f9eeca106725 7545 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell power-down */
Kojto 122:f9eeca106725 7546 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell ready flag */
Kojto 122:f9eeca106725 7547
Kojto 122:f9eeca106725 7548 /******************************************************************************/
Kojto 122:f9eeca106725 7549 /* */
Kojto 122:f9eeca106725 7550 /* TIM */
Kojto 122:f9eeca106725 7551 /* */
Kojto 122:f9eeca106725 7552 /******************************************************************************/
Kojto 122:f9eeca106725 7553 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 122:f9eeca106725 7554 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
Kojto 122:f9eeca106725 7555 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
Kojto 122:f9eeca106725 7556 #define TIM_CR1_URS 0x0004U /*!<Update request source */
Kojto 122:f9eeca106725 7557 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
Kojto 122:f9eeca106725 7558 #define TIM_CR1_DIR 0x0010U /*!<Direction */
Kojto 122:f9eeca106725 7559
Kojto 122:f9eeca106725 7560 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 7561 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
Kojto 122:f9eeca106725 7562 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
Kojto 122:f9eeca106725 7563
Kojto 122:f9eeca106725 7564 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 7565
Kojto 122:f9eeca106725 7566 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 7567 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 7568 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7569 #define TIM_CR1_UIFREMAP 0x0800U /*!<UIF status bit */
Kojto 122:f9eeca106725 7570
Kojto 122:f9eeca106725 7571 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 122:f9eeca106725 7572 #define TIM_CR2_CCPC 0x00000001U /*!<Capture/Compare Preloaded Control */
Kojto 122:f9eeca106725 7573 #define TIM_CR2_CCUS 0x00000004U /*!<Capture/Compare Control Update Selection */
Kojto 122:f9eeca106725 7574 #define TIM_CR2_CCDS 0x00000008U /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 7575
Kojto 122:f9eeca106725 7576 #define TIM_CR2_OIS5 0x00010000U /*!<Output Idle state 4 (OC4 output) */
Kojto 122:f9eeca106725 7577 #define TIM_CR2_OIS6 0x00040000U /*!<Output Idle state 4 (OC4 output) */
Kojto 122:f9eeca106725 7578
Kojto 122:f9eeca106725 7579 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 7580 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7581 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7582 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7583
Kojto 122:f9eeca106725 7584 #define TIM_CR2_MMS2 0x00F00000U /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 7585 #define TIM_CR2_MMS2_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7586 #define TIM_CR2_MMS2_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7587 #define TIM_CR2_MMS2_2 0x00400000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7588 #define TIM_CR2_MMS2_3 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7589
Kojto 122:f9eeca106725 7590 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
Kojto 122:f9eeca106725 7591 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
Kojto 122:f9eeca106725 7592 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
Kojto 122:f9eeca106725 7593 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
Kojto 122:f9eeca106725 7594 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
Kojto 122:f9eeca106725 7595 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
Kojto 122:f9eeca106725 7596 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
Kojto 122:f9eeca106725 7597 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
Kojto 122:f9eeca106725 7598
Kojto 122:f9eeca106725 7599 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 122:f9eeca106725 7600 #define TIM_SMCR_SMS 0x00010007U /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 7601 #define TIM_SMCR_SMS_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7602 #define TIM_SMCR_SMS_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7603 #define TIM_SMCR_SMS_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7604 #define TIM_SMCR_SMS_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7605 #define TIM_SMCR_OCCS 0x00000008U /*!< OCREF clear selection */
Kojto 122:f9eeca106725 7606
Kojto 122:f9eeca106725 7607 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 7608 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7609 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7610 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7611
Kojto 122:f9eeca106725 7612 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
Kojto 122:f9eeca106725 7613
Kojto 122:f9eeca106725 7614 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 7615 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 7616 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7617 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
Kojto 122:f9eeca106725 7618 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
Kojto 122:f9eeca106725 7619
Kojto 122:f9eeca106725 7620 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 7621 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7622 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7623
Kojto 122:f9eeca106725 7624 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
Kojto 122:f9eeca106725 7625 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
Kojto 122:f9eeca106725 7626
Kojto 122:f9eeca106725 7627 /******************* Bit definition for TIM_DIER register *******************/
Kojto 122:f9eeca106725 7628 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
Kojto 122:f9eeca106725 7629 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 7630 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 7631 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 7632 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 7633 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
Kojto 122:f9eeca106725 7634 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 7635 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
Kojto 122:f9eeca106725 7636 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
Kojto 122:f9eeca106725 7637 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 7638 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 7639 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 7640 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 7641 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
Kojto 122:f9eeca106725 7642 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
Kojto 122:f9eeca106725 7643
Kojto 122:f9eeca106725 7644 /******************** Bit definition for TIM_SR register ********************/
Kojto 122:f9eeca106725 7645 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 7646 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 7647 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 7648 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 7649 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 7650 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
Kojto 122:f9eeca106725 7651 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 7652 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
Kojto 122:f9eeca106725 7653 #define TIM_SR_B2IF 0x0100U /*!<Break2 interrupt Flag */
Kojto 122:f9eeca106725 7654 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 7655 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 7656 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 7657 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
Kojto 122:f9eeca106725 7658
Kojto 122:f9eeca106725 7659 /******************* Bit definition for TIM_EGR register ********************/
Kojto 122:f9eeca106725 7660 #define TIM_EGR_UG 0x00000001U /*!<Update Generation */
Kojto 122:f9eeca106725 7661 #define TIM_EGR_CC1G 0x00000002U /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 7662 #define TIM_EGR_CC2G 0x00000004U /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 7663 #define TIM_EGR_CC3G 0x00000008U /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 7664 #define TIM_EGR_CC4G 0x00000010U /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 7665 #define TIM_EGR_COMG 0x00000020U /*!<Capture/Compare Control Update Generation */
Kojto 122:f9eeca106725 7666 #define TIM_EGR_TG 0x00000040U /*!<Trigger Generation */
Kojto 122:f9eeca106725 7667 #define TIM_EGR_BG 0x00000080U /*!<Break Generation */
Kojto 122:f9eeca106725 7668 #define TIM_EGR_B2G 0x00000100U /*!<Break2 Generation */
Kojto 122:f9eeca106725 7669
Kojto 122:f9eeca106725 7670 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 122:f9eeca106725 7671 #define TIM_CCMR1_CC1S 0x00000003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 7672 #define TIM_CCMR1_CC1S_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7673 #define TIM_CCMR1_CC1S_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7674
Kojto 122:f9eeca106725 7675 #define TIM_CCMR1_OC1FE 0x00000004U /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 7676 #define TIM_CCMR1_OC1PE 0x00000008U /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 7677
Kojto 122:f9eeca106725 7678 #define TIM_CCMR1_OC1M 0x00010070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 7679 #define TIM_CCMR1_OC1M_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7680 #define TIM_CCMR1_OC1M_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7681 #define TIM_CCMR1_OC1M_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7682 #define TIM_CCMR1_OC1M_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7683
Kojto 122:f9eeca106725 7684 #define TIM_CCMR1_OC1CE 0x00000080U /*!<Output Compare 1Clear Enable */
Kojto 122:f9eeca106725 7685
Kojto 122:f9eeca106725 7686 #define TIM_CCMR1_CC2S 0x00000300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 7687 #define TIM_CCMR1_CC2S_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 7688 #define TIM_CCMR1_CC2S_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7689
Kojto 122:f9eeca106725 7690 #define TIM_CCMR1_OC2FE 0x00000400U /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 7691 #define TIM_CCMR1_OC2PE 0x00000800U /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 7692
Kojto 122:f9eeca106725 7693 #define TIM_CCMR1_OC2M 0x01007000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 7694 #define TIM_CCMR1_OC2M_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7695 #define TIM_CCMR1_OC2M_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7696 #define TIM_CCMR1_OC2M_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7697 #define TIM_CCMR1_OC2M_3 0x01000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7698
Kojto 122:f9eeca106725 7699 #define TIM_CCMR1_OC2CE 0x00008000U /*!<Output Compare 2 Clear Enable */
Kojto 122:f9eeca106725 7700
Kojto 122:f9eeca106725 7701 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 7702
Kojto 122:f9eeca106725 7703 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 7704 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
Kojto 122:f9eeca106725 7705 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
Kojto 122:f9eeca106725 7706
Kojto 122:f9eeca106725 7707 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 7708 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7709 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7710 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7711 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 7712
Kojto 122:f9eeca106725 7713 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 7714 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 7715 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 7716
Kojto 122:f9eeca106725 7717 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 7718 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7719 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7720 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7721 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7722
Kojto 122:f9eeca106725 7723 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 122:f9eeca106725 7724 #define TIM_CCMR2_CC3S 0x00000003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 7725 #define TIM_CCMR2_CC3S_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7726 #define TIM_CCMR2_CC3S_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7727
Kojto 122:f9eeca106725 7728 #define TIM_CCMR2_OC3FE 0x00000004U /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 7729 #define TIM_CCMR2_OC3PE 0x00000008U /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 7730
Kojto 122:f9eeca106725 7731 #define TIM_CCMR2_OC3M 0x00010070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 7732 #define TIM_CCMR2_OC3M_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7733 #define TIM_CCMR2_OC3M_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7734 #define TIM_CCMR2_OC3M_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7735 #define TIM_CCMR2_OC3M_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7736
Kojto 122:f9eeca106725 7737
Kojto 122:f9eeca106725 7738
Kojto 122:f9eeca106725 7739 #define TIM_CCMR2_OC3CE 0x00000080U /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 7740
Kojto 122:f9eeca106725 7741 #define TIM_CCMR2_CC4S 0x00000300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 7742 #define TIM_CCMR2_CC4S_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 7743 #define TIM_CCMR2_CC4S_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7744
Kojto 122:f9eeca106725 7745 #define TIM_CCMR2_OC4FE 0x00000400U /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 7746 #define TIM_CCMR2_OC4PE 0x00000800U /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 7747
Kojto 122:f9eeca106725 7748 #define TIM_CCMR2_OC4M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 7749 #define TIM_CCMR2_OC4M_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7750 #define TIM_CCMR2_OC4M_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7751 #define TIM_CCMR2_OC4M_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7752 #define TIM_CCMR2_OC4M_3 0x01000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7753
Kojto 122:f9eeca106725 7754 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
Kojto 122:f9eeca106725 7755
Kojto 122:f9eeca106725 7756 /*----------------------------------------------------------------------------*/
Kojto 122:f9eeca106725 7757
Kojto 122:f9eeca106725 7758 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 7759 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
Kojto 122:f9eeca106725 7760 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
Kojto 122:f9eeca106725 7761
Kojto 122:f9eeca106725 7762 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 7763 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7764 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7765 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7766 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
Kojto 122:f9eeca106725 7767
Kojto 122:f9eeca106725 7768 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 7769 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 7770 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 7771
Kojto 122:f9eeca106725 7772 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 7773 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7774 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7775 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7776 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7777
Kojto 122:f9eeca106725 7778 /******************* Bit definition for TIM_CCER register *******************/
Kojto 122:f9eeca106725 7779 #define TIM_CCER_CC1E 0x00000001U /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 7780 #define TIM_CCER_CC1P 0x00000002U /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 7781 #define TIM_CCER_CC1NE 0x00000004U /*!<Capture/Compare 1 Complementary output enable */
Kojto 122:f9eeca106725 7782 #define TIM_CCER_CC1NP 0x00000008U /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 7783 #define TIM_CCER_CC2E 0x00000010U /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 7784 #define TIM_CCER_CC2P 0x00000020U /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 7785 #define TIM_CCER_CC2NE 0x00000040U /*!<Capture/Compare 2 Complementary output enable */
Kojto 122:f9eeca106725 7786 #define TIM_CCER_CC2NP 0x00000080U /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 7787 #define TIM_CCER_CC3E 0x00000100U /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 7788 #define TIM_CCER_CC3P 0x00000200U /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 7789 #define TIM_CCER_CC3NE 0x00000400U /*!<Capture/Compare 3 Complementary output enable */
Kojto 122:f9eeca106725 7790 #define TIM_CCER_CC3NP 0x00000800U /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 7791 #define TIM_CCER_CC4E 0x00001000U /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 7792 #define TIM_CCER_CC4P 0x00002000U /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 7793 #define TIM_CCER_CC4NP 0x00008000U /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 122:f9eeca106725 7794 #define TIM_CCER_CC5E 0x00010000U /*!<Capture/Compare 5 output enable */
Kojto 122:f9eeca106725 7795 #define TIM_CCER_CC5P 0x00020000U /*!<Capture/Compare 5 output Polarity */
Kojto 122:f9eeca106725 7796 #define TIM_CCER_CC6E 0x00100000U /*!<Capture/Compare 6 output enable */
Kojto 122:f9eeca106725 7797 #define TIM_CCER_CC6P 0x00200000U /*!<Capture/Compare 6 output Polarity */
Kojto 122:f9eeca106725 7798
Kojto 122:f9eeca106725 7799
Kojto 122:f9eeca106725 7800 /******************* Bit definition for TIM_CNT register ********************/
Kojto 122:f9eeca106725 7801 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
Kojto 122:f9eeca106725 7802
Kojto 122:f9eeca106725 7803 /******************* Bit definition for TIM_PSC register ********************/
Kojto 122:f9eeca106725 7804 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
Kojto 122:f9eeca106725 7805
Kojto 122:f9eeca106725 7806 /******************* Bit definition for TIM_ARR register ********************/
Kojto 122:f9eeca106725 7807 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
Kojto 122:f9eeca106725 7808
Kojto 122:f9eeca106725 7809 /******************* Bit definition for TIM_RCR register ********************/
Kojto 122:f9eeca106725 7810 #define TIM_RCR_REP ((uint8_t)0xFFU) /*!<Repetition Counter Value */
Kojto 122:f9eeca106725 7811
Kojto 122:f9eeca106725 7812 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 122:f9eeca106725 7813 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
Kojto 122:f9eeca106725 7814
Kojto 122:f9eeca106725 7815 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 122:f9eeca106725 7816 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
Kojto 122:f9eeca106725 7817
Kojto 122:f9eeca106725 7818 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 122:f9eeca106725 7819 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
Kojto 122:f9eeca106725 7820
Kojto 122:f9eeca106725 7821 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 122:f9eeca106725 7822 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
Kojto 122:f9eeca106725 7823
Kojto 122:f9eeca106725 7824 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 122:f9eeca106725 7825 #define TIM_BDTR_DTG 0x000000FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 122:f9eeca106725 7826 #define TIM_BDTR_DTG_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7827 #define TIM_BDTR_DTG_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7828 #define TIM_BDTR_DTG_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7829 #define TIM_BDTR_DTG_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7830 #define TIM_BDTR_DTG_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 7831 #define TIM_BDTR_DTG_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 7832 #define TIM_BDTR_DTG_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 7833 #define TIM_BDTR_DTG_7 0x00000080U /*!<Bit 7 */
Kojto 122:f9eeca106725 7834
Kojto 122:f9eeca106725 7835 #define TIM_BDTR_LOCK 0x00000300U /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 122:f9eeca106725 7836 #define TIM_BDTR_LOCK_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 7837 #define TIM_BDTR_LOCK_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7838
Kojto 122:f9eeca106725 7839 #define TIM_BDTR_OSSI 0x00000400U /*!<Off-State Selection for Idle mode */
Kojto 122:f9eeca106725 7840 #define TIM_BDTR_OSSR 0x00000800U /*!<Off-State Selection for Run mode */
Kojto 122:f9eeca106725 7841 #define TIM_BDTR_BKE 0x00001000U /*!<Break enable */
Kojto 122:f9eeca106725 7842 #define TIM_BDTR_BKP 0x00002000U /*!<Break Polarity */
Kojto 122:f9eeca106725 7843 #define TIM_BDTR_AOE 0x00004000U /*!<Automatic Output enable */
Kojto 122:f9eeca106725 7844 #define TIM_BDTR_MOE 0x00008000U /*!<Main Output enable */
Kojto 122:f9eeca106725 7845 #define TIM_BDTR_BKF 0x000F0000U /*!<Break Filter for Break1 */
Kojto 122:f9eeca106725 7846 #define TIM_BDTR_BK2F 0x00F00000U /*!<Break Filter for Break2 */
Kojto 122:f9eeca106725 7847 #define TIM_BDTR_BK2E 0x01000000U /*!<Break enable for Break2 */
Kojto 122:f9eeca106725 7848 #define TIM_BDTR_BK2P 0x02000000U /*!<Break Polarity for Break2 */
Kojto 122:f9eeca106725 7849
Kojto 122:f9eeca106725 7850 /******************* Bit definition for TIM_DCR register ********************/
Kojto 122:f9eeca106725 7851 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 7852 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 7853 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 7854 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 7855 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 7856 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 7857
Kojto 122:f9eeca106725 7858 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 7859 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
Kojto 122:f9eeca106725 7860 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
Kojto 122:f9eeca106725 7861 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
Kojto 122:f9eeca106725 7862 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
Kojto 122:f9eeca106725 7863 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
Kojto 122:f9eeca106725 7864
Kojto 122:f9eeca106725 7865 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 122:f9eeca106725 7866 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
Kojto 122:f9eeca106725 7867
Kojto 122:f9eeca106725 7868 /******************* Bit definition for TIM_OR regiter *********************/
Kojto 122:f9eeca106725 7869 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 122:f9eeca106725 7870 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
Kojto 122:f9eeca106725 7871 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
Kojto 122:f9eeca106725 7872 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 122:f9eeca106725 7873 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
Kojto 122:f9eeca106725 7874 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
Kojto 122:f9eeca106725 7875
Kojto 122:f9eeca106725 7876 /****************** Bit definition for TIM_CCMR3 register *******************/
Kojto 122:f9eeca106725 7877 #define TIM_CCMR3_OC5FE 0x00000004U /*!<Output Compare 5 Fast enable */
Kojto 122:f9eeca106725 7878 #define TIM_CCMR3_OC5PE 0x00000008U /*!<Output Compare 5 Preload enable */
Kojto 122:f9eeca106725 7879
Kojto 122:f9eeca106725 7880 #define TIM_CCMR3_OC5M 0x00010070U /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
Kojto 122:f9eeca106725 7881 #define TIM_CCMR3_OC5M_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 7882 #define TIM_CCMR3_OC5M_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 7883 #define TIM_CCMR3_OC5M_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 7884 #define TIM_CCMR3_OC5M_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7885
Kojto 122:f9eeca106725 7886 #define TIM_CCMR3_OC5CE 0x00000080U /*!<Output Compare 5 Clear Enable */
Kojto 122:f9eeca106725 7887
Kojto 122:f9eeca106725 7888 #define TIM_CCMR3_OC6FE 0x00000400U /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 7889 #define TIM_CCMR3_OC6PE 0x00000800U /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 7890
Kojto 122:f9eeca106725 7891 #define TIM_CCMR3_OC6M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 7892 #define TIM_CCMR3_OC6M_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 7893 #define TIM_CCMR3_OC6M_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 7894 #define TIM_CCMR3_OC6M_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 7895 #define TIM_CCMR3_OC6M_3 0x01000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 7896
Kojto 122:f9eeca106725 7897 #define TIM_CCMR3_OC6CE 0x00008000U /*!<Output Compare 4 Clear Enable */
Kojto 122:f9eeca106725 7898
Kojto 122:f9eeca106725 7899 /******************* Bit definition for TIM_CCR5 register *******************/
Kojto 122:f9eeca106725 7900 #define TIM_CCR5_CCR5 0xFFFFFFFFU /*!<Capture/Compare 5 Value */
Kojto 122:f9eeca106725 7901 #define TIM_CCR5_GC5C1 0x20000000U /*!<Group Channel 5 and Channel 1 */
Kojto 122:f9eeca106725 7902 #define TIM_CCR5_GC5C2 0x40000000U /*!<Group Channel 5 and Channel 2 */
Kojto 122:f9eeca106725 7903 #define TIM_CCR5_GC5C3 0x80000000U /*!<Group Channel 5 and Channel 3 */
Kojto 122:f9eeca106725 7904
Kojto 122:f9eeca106725 7905 /******************* Bit definition for TIM_CCR6 register *******************/
Kojto 122:f9eeca106725 7906 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
Kojto 122:f9eeca106725 7907
Kojto 122:f9eeca106725 7908 /******************* Bit definition for TIM1_AF1 register *******************/
Kojto 122:f9eeca106725 7909 #define TIM1_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */
Kojto 122:f9eeca106725 7910 #define TIM1_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */
Kojto 122:f9eeca106725 7911
Kojto 122:f9eeca106725 7912 /******************* Bit definition for TIM1_AF2 register *******************/
Kojto 122:f9eeca106725 7913 #define TIM1_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN input enable */
Kojto 122:f9eeca106725 7914 #define TIM1_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */
Kojto 122:f9eeca106725 7915
Kojto 122:f9eeca106725 7916 /******************* Bit definition for TIM8_AF1 register *******************/
Kojto 122:f9eeca106725 7917 #define TIM8_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */
Kojto 122:f9eeca106725 7918 #define TIM8_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */
Kojto 122:f9eeca106725 7919
Kojto 122:f9eeca106725 7920 /******************* Bit definition for TIM8_AF2 register *******************/
Kojto 122:f9eeca106725 7921 #define TIM8_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN2 input enable */
Kojto 122:f9eeca106725 7922 #define TIM8_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */
Kojto 122:f9eeca106725 7923
Kojto 122:f9eeca106725 7924 /******************************************************************************/
Kojto 122:f9eeca106725 7925 /* */
Kojto 122:f9eeca106725 7926 /* Low Power Timer (LPTIM) */
Kojto 122:f9eeca106725 7927 /* */
Kojto 122:f9eeca106725 7928 /******************************************************************************/
Kojto 122:f9eeca106725 7929 /****************** Bit definition for LPTIM_ISR register *******************/
Kojto 122:f9eeca106725 7930 #define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
Kojto 122:f9eeca106725 7931 #define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
Kojto 122:f9eeca106725 7932 #define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
Kojto 122:f9eeca106725 7933 #define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
Kojto 122:f9eeca106725 7934 #define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
Kojto 122:f9eeca106725 7935 #define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
Kojto 122:f9eeca106725 7936 #define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
Kojto 122:f9eeca106725 7937
Kojto 122:f9eeca106725 7938 /****************** Bit definition for LPTIM_ICR register *******************/
Kojto 122:f9eeca106725 7939 #define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
Kojto 122:f9eeca106725 7940 #define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
Kojto 122:f9eeca106725 7941 #define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
Kojto 122:f9eeca106725 7942 #define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
Kojto 122:f9eeca106725 7943 #define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
Kojto 122:f9eeca106725 7944 #define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
Kojto 122:f9eeca106725 7945 #define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
Kojto 122:f9eeca106725 7946
Kojto 122:f9eeca106725 7947 /****************** Bit definition for LPTIM_IER register *******************/
Kojto 122:f9eeca106725 7948 #define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
Kojto 122:f9eeca106725 7949 #define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
Kojto 122:f9eeca106725 7950 #define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
Kojto 122:f9eeca106725 7951 #define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
Kojto 122:f9eeca106725 7952 #define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
Kojto 122:f9eeca106725 7953 #define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
Kojto 122:f9eeca106725 7954 #define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
Kojto 122:f9eeca106725 7955
Kojto 122:f9eeca106725 7956 /****************** Bit definition for LPTIM_CFGR register*******************/
Kojto 122:f9eeca106725 7957 #define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
Kojto 122:f9eeca106725 7958
Kojto 122:f9eeca106725 7959 #define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
Kojto 122:f9eeca106725 7960 #define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
Kojto 122:f9eeca106725 7961 #define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
Kojto 122:f9eeca106725 7962
Kojto 122:f9eeca106725 7963 #define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
Kojto 122:f9eeca106725 7964 #define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
Kojto 122:f9eeca106725 7965 #define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
Kojto 122:f9eeca106725 7966
Kojto 122:f9eeca106725 7967 #define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
Kojto 122:f9eeca106725 7968 #define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
Kojto 122:f9eeca106725 7969 #define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
Kojto 122:f9eeca106725 7970
Kojto 122:f9eeca106725 7971 #define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
Kojto 122:f9eeca106725 7972 #define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
Kojto 122:f9eeca106725 7973 #define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
Kojto 122:f9eeca106725 7974 #define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
Kojto 122:f9eeca106725 7975
Kojto 122:f9eeca106725 7976 #define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
Kojto 122:f9eeca106725 7977 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
Kojto 122:f9eeca106725 7978 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
Kojto 122:f9eeca106725 7979 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
Kojto 122:f9eeca106725 7980
Kojto 122:f9eeca106725 7981 #define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
Kojto 122:f9eeca106725 7982 #define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
Kojto 122:f9eeca106725 7983 #define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
Kojto 122:f9eeca106725 7984
Kojto 122:f9eeca106725 7985 #define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
Kojto 122:f9eeca106725 7986 #define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
Kojto 122:f9eeca106725 7987 #define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
Kojto 122:f9eeca106725 7988 #define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
Kojto 122:f9eeca106725 7989 #define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
Kojto 122:f9eeca106725 7990 #define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
Kojto 122:f9eeca106725 7991
Kojto 122:f9eeca106725 7992 /****************** Bit definition for LPTIM_CR register ********************/
Kojto 122:f9eeca106725 7993 #define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
Kojto 122:f9eeca106725 7994 #define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
Kojto 122:f9eeca106725 7995 #define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
Kojto 122:f9eeca106725 7996
Kojto 122:f9eeca106725 7997 /****************** Bit definition for LPTIM_CMP register *******************/
Kojto 122:f9eeca106725 7998 #define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
Kojto 122:f9eeca106725 7999
Kojto 122:f9eeca106725 8000 /****************** Bit definition for LPTIM_ARR register *******************/
Kojto 122:f9eeca106725 8001 #define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
Kojto 122:f9eeca106725 8002
Kojto 122:f9eeca106725 8003 /****************** Bit definition for LPTIM_CNT register *******************/
Kojto 122:f9eeca106725 8004 #define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
Kojto 122:f9eeca106725 8005 /******************************************************************************/
Kojto 122:f9eeca106725 8006 /* */
Kojto 122:f9eeca106725 8007 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 122:f9eeca106725 8008 /* */
Kojto 122:f9eeca106725 8009 /******************************************************************************/
Kojto 122:f9eeca106725 8010 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 8011 #define USART_CR1_UE 0x00000001U /*!< USART Enable */
Kojto 122:f9eeca106725 8012 #define USART_CR1_RE 0x00000004U /*!< Receiver Enable */
Kojto 122:f9eeca106725 8013 #define USART_CR1_TE 0x00000008U /*!< Transmitter Enable */
Kojto 122:f9eeca106725 8014 #define USART_CR1_IDLEIE 0x00000010U /*!< IDLE Interrupt Enable */
Kojto 122:f9eeca106725 8015 #define USART_CR1_RXNEIE 0x00000020U /*!< RXNE Interrupt Enable */
Kojto 122:f9eeca106725 8016 #define USART_CR1_TCIE 0x00000040U /*!< Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 8017 #define USART_CR1_TXEIE 0x00000080U /*!< TXE Interrupt Enable */
Kojto 122:f9eeca106725 8018 #define USART_CR1_PEIE 0x00000100U /*!< PE Interrupt Enable */
Kojto 122:f9eeca106725 8019 #define USART_CR1_PS 0x00000200U /*!< Parity Selection */
Kojto 122:f9eeca106725 8020 #define USART_CR1_PCE 0x00000400U /*!< Parity Control Enable */
Kojto 122:f9eeca106725 8021 #define USART_CR1_WAKE 0x00000800U /*!< Receiver Wakeup method */
Kojto 122:f9eeca106725 8022 #define USART_CR1_M 0x10001000U /*!< Word length */
Kojto 122:f9eeca106725 8023 #define USART_CR1_M_0 0x00001000U /*!< Word length - Bit 0 */
Kojto 122:f9eeca106725 8024 #define USART_CR1_MME 0x00002000U /*!< Mute Mode Enable */
Kojto 122:f9eeca106725 8025 #define USART_CR1_CMIE 0x00004000U /*!< Character match interrupt enable */
Kojto 122:f9eeca106725 8026 #define USART_CR1_OVER8 0x00008000U /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 122:f9eeca106725 8027 #define USART_CR1_DEDT 0x001F0000U /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 122:f9eeca106725 8028 #define USART_CR1_DEDT_0 0x00010000U /*!< Bit 0 */
Kojto 122:f9eeca106725 8029 #define USART_CR1_DEDT_1 0x00020000U /*!< Bit 1 */
Kojto 122:f9eeca106725 8030 #define USART_CR1_DEDT_2 0x00040000U /*!< Bit 2 */
Kojto 122:f9eeca106725 8031 #define USART_CR1_DEDT_3 0x00080000U /*!< Bit 3 */
Kojto 122:f9eeca106725 8032 #define USART_CR1_DEDT_4 0x00100000U /*!< Bit 4 */
Kojto 122:f9eeca106725 8033 #define USART_CR1_DEAT 0x03E00000U /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 122:f9eeca106725 8034 #define USART_CR1_DEAT_0 0x00200000U /*!< Bit 0 */
Kojto 122:f9eeca106725 8035 #define USART_CR1_DEAT_1 0x00400000U /*!< Bit 1 */
Kojto 122:f9eeca106725 8036 #define USART_CR1_DEAT_2 0x00800000U /*!< Bit 2 */
Kojto 122:f9eeca106725 8037 #define USART_CR1_DEAT_3 0x01000000U /*!< Bit 3 */
Kojto 122:f9eeca106725 8038 #define USART_CR1_DEAT_4 0x02000000U /*!< Bit 4 */
Kojto 122:f9eeca106725 8039 #define USART_CR1_RTOIE 0x04000000U /*!< Receive Time Out interrupt enable */
Kojto 122:f9eeca106725 8040 #define USART_CR1_EOBIE 0x08000000U /*!< End of Block interrupt enable */
Kojto 122:f9eeca106725 8041 #define USART_CR1_M_1 0x10000000U /*!< Word length - Bit 1 */
Kojto 122:f9eeca106725 8042
Kojto 122:f9eeca106725 8043 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 8044 #define USART_CR2_ADDM7 0x00000010U /*!< 7-bit or 4-bit Address Detection */
Kojto 122:f9eeca106725 8045 #define USART_CR2_LBDL 0x00000020U /*!< LIN Break Detection Length */
Kojto 122:f9eeca106725 8046 #define USART_CR2_LBDIE 0x00000040U /*!< LIN Break Detection Interrupt Enable */
Kojto 122:f9eeca106725 8047 #define USART_CR2_LBCL 0x00000100U /*!< Last Bit Clock pulse */
Kojto 122:f9eeca106725 8048 #define USART_CR2_CPHA 0x00000200U /*!< Clock Phase */
Kojto 122:f9eeca106725 8049 #define USART_CR2_CPOL 0x00000400U /*!< Clock Polarity */
Kojto 122:f9eeca106725 8050 #define USART_CR2_CLKEN 0x00000800U /*!< Clock Enable */
Kojto 122:f9eeca106725 8051 #define USART_CR2_STOP 0x00003000U /*!< STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 8052 #define USART_CR2_STOP_0 0x00001000U /*!< Bit 0 */
Kojto 122:f9eeca106725 8053 #define USART_CR2_STOP_1 0x00002000U /*!< Bit 1 */
Kojto 122:f9eeca106725 8054 #define USART_CR2_LINEN 0x00004000U /*!< LIN mode enable */
Kojto 122:f9eeca106725 8055 #define USART_CR2_SWAP 0x00008000U /*!< SWAP TX/RX pins */
Kojto 122:f9eeca106725 8056 #define USART_CR2_RXINV 0x00010000U /*!< RX pin active level inversion */
Kojto 122:f9eeca106725 8057 #define USART_CR2_TXINV 0x00020000U /*!< TX pin active level inversion */
Kojto 122:f9eeca106725 8058 #define USART_CR2_DATAINV 0x00040000U /*!< Binary data inversion */
Kojto 122:f9eeca106725 8059 #define USART_CR2_MSBFIRST 0x00080000U /*!< Most Significant Bit First */
Kojto 122:f9eeca106725 8060 #define USART_CR2_ABREN 0x00100000U /*!< Auto Baud-Rate Enable */
Kojto 122:f9eeca106725 8061 #define USART_CR2_ABRMODE 0x00600000U /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 122:f9eeca106725 8062 #define USART_CR2_ABRMODE_0 0x00200000U /*!< Bit 0 */
Kojto 122:f9eeca106725 8063 #define USART_CR2_ABRMODE_1 0x00400000U /*!< Bit 1 */
Kojto 122:f9eeca106725 8064 #define USART_CR2_RTOEN 0x00800000U /*!< Receiver Time-Out enable */
Kojto 122:f9eeca106725 8065 #define USART_CR2_ADD 0xFF000000U /*!< Address of the USART node */
Kojto 122:f9eeca106725 8066
Kojto 122:f9eeca106725 8067 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 8068 #define USART_CR3_EIE 0x00000001U /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 8069 #define USART_CR3_IREN 0x00000002U /*!< IrDA mode Enable */
Kojto 122:f9eeca106725 8070 #define USART_CR3_IRLP 0x00000004U /*!< IrDA Low-Power */
Kojto 122:f9eeca106725 8071 #define USART_CR3_HDSEL 0x00000008U /*!< Half-Duplex Selection */
Kojto 122:f9eeca106725 8072 #define USART_CR3_NACK 0x00000010U /*!< SmartCard NACK enable */
Kojto 122:f9eeca106725 8073 #define USART_CR3_SCEN 0x00000020U /*!< SmartCard mode enable */
Kojto 122:f9eeca106725 8074 #define USART_CR3_DMAR 0x00000040U /*!< DMA Enable Receiver */
Kojto 122:f9eeca106725 8075 #define USART_CR3_DMAT 0x00000080U /*!< DMA Enable Transmitter */
Kojto 122:f9eeca106725 8076 #define USART_CR3_RTSE 0x00000100U /*!< RTS Enable */
Kojto 122:f9eeca106725 8077 #define USART_CR3_CTSE 0x00000200U /*!< CTS Enable */
Kojto 122:f9eeca106725 8078 #define USART_CR3_CTSIE 0x00000400U /*!< CTS Interrupt Enable */
Kojto 122:f9eeca106725 8079 #define USART_CR3_ONEBIT 0x00000800U /*!< One sample bit method enable */
Kojto 122:f9eeca106725 8080 #define USART_CR3_OVRDIS 0x00001000U /*!< Overrun Disable */
Kojto 122:f9eeca106725 8081 #define USART_CR3_DDRE 0x00002000U /*!< DMA Disable on Reception Error */
Kojto 122:f9eeca106725 8082 #define USART_CR3_DEM 0x00004000U /*!< Driver Enable Mode */
Kojto 122:f9eeca106725 8083 #define USART_CR3_DEP 0x00008000U /*!< Driver Enable Polarity Selection */
Kojto 122:f9eeca106725 8084 #define USART_CR3_SCARCNT 0x000E0000U /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 122:f9eeca106725 8085 #define USART_CR3_SCARCNT_0 0x00020000U /*!< Bit 0 */
Kojto 122:f9eeca106725 8086 #define USART_CR3_SCARCNT_1 0x00040000U /*!< Bit 1 */
Kojto 122:f9eeca106725 8087 #define USART_CR3_SCARCNT_2 0x00080000U /*!< Bit 2 */
Kojto 122:f9eeca106725 8088
Kojto 122:f9eeca106725 8089
Kojto 122:f9eeca106725 8090 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 8091 #define USART_BRR_DIV_FRACTION 0x000FU /*!< Fraction of USARTDIV */
Kojto 122:f9eeca106725 8092 #define USART_BRR_DIV_MANTISSA 0xFFF0U /*!< Mantissa of USARTDIV */
Kojto 122:f9eeca106725 8093
Kojto 122:f9eeca106725 8094 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 8095 #define USART_GTPR_PSC 0x00FFU /*!< PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 8096 #define USART_GTPR_GT 0xFF00U /*!< GT[7:0] bits (Guard time value) */
Kojto 122:f9eeca106725 8097
Kojto 122:f9eeca106725 8098
Kojto 122:f9eeca106725 8099 /******************* Bit definition for USART_RTOR register *****************/
Kojto 122:f9eeca106725 8100 #define USART_RTOR_RTO 0x00FFFFFFU /*!< Receiver Time Out Value */
Kojto 122:f9eeca106725 8101 #define USART_RTOR_BLEN 0xFF000000U /*!< Block Length */
Kojto 122:f9eeca106725 8102
Kojto 122:f9eeca106725 8103 /******************* Bit definition for USART_RQR register ******************/
Kojto 122:f9eeca106725 8104 #define USART_RQR_ABRRQ 0x0001U /*!< Auto-Baud Rate Request */
Kojto 122:f9eeca106725 8105 #define USART_RQR_SBKRQ 0x0002U /*!< Send Break Request */
Kojto 122:f9eeca106725 8106 #define USART_RQR_MMRQ 0x0004U /*!< Mute Mode Request */
Kojto 122:f9eeca106725 8107 #define USART_RQR_RXFRQ 0x0008U /*!< Receive Data flush Request */
Kojto 122:f9eeca106725 8108 #define USART_RQR_TXFRQ 0x0010U /*!< Transmit data flush Request */
Kojto 122:f9eeca106725 8109
Kojto 122:f9eeca106725 8110 /******************* Bit definition for USART_ISR register ******************/
Kojto 122:f9eeca106725 8111 #define USART_ISR_PE 0x00000001U /*!< Parity Error */
Kojto 122:f9eeca106725 8112 #define USART_ISR_FE 0x00000002U /*!< Framing Error */
Kojto 122:f9eeca106725 8113 #define USART_ISR_NE 0x00000004U /*!< Noise detected Flag */
Kojto 122:f9eeca106725 8114 #define USART_ISR_ORE 0x00000008U /*!< OverRun Error */
Kojto 122:f9eeca106725 8115 #define USART_ISR_IDLE 0x00000010U /*!< IDLE line detected */
Kojto 122:f9eeca106725 8116 #define USART_ISR_RXNE 0x00000020U /*!< Read Data Register Not Empty */
Kojto 122:f9eeca106725 8117 #define USART_ISR_TC 0x00000040U /*!< Transmission Complete */
Kojto 122:f9eeca106725 8118 #define USART_ISR_TXE 0x00000080U /*!< Transmit Data Register Empty */
Kojto 122:f9eeca106725 8119 #define USART_ISR_LBDF 0x00000100U /*!< LIN Break Detection Flag */
Kojto 122:f9eeca106725 8120 #define USART_ISR_CTSIF 0x00000200U /*!< CTS interrupt flag */
Kojto 122:f9eeca106725 8121 #define USART_ISR_CTS 0x00000400U /*!< CTS flag */
Kojto 122:f9eeca106725 8122 #define USART_ISR_RTOF 0x00000800U /*!< Receiver Time Out */
Kojto 122:f9eeca106725 8123 #define USART_ISR_EOBF 0x00001000U /*!< End Of Block Flag */
Kojto 122:f9eeca106725 8124 #define USART_ISR_ABRE 0x00004000U /*!< Auto-Baud Rate Error */
Kojto 122:f9eeca106725 8125 #define USART_ISR_ABRF 0x00008000U /*!< Auto-Baud Rate Flag */
Kojto 122:f9eeca106725 8126 #define USART_ISR_BUSY 0x00010000U /*!< Busy Flag */
Kojto 122:f9eeca106725 8127 #define USART_ISR_CMF 0x00020000U /*!< Character Match Flag */
Kojto 122:f9eeca106725 8128 #define USART_ISR_SBKF 0x00040000U /*!< Send Break Flag */
Kojto 122:f9eeca106725 8129 #define USART_ISR_RWU 0x00080000U /*!< Receive Wake Up from mute mode Flag */
Kojto 122:f9eeca106725 8130 #define USART_ISR_WUF 0x00100000U /*!< Wake Up from stop mode Flag */
Kojto 122:f9eeca106725 8131 #define USART_ISR_TEACK 0x00200000U /*!< Transmit Enable Acknowledge Flag */
Kojto 122:f9eeca106725 8132 #define USART_ISR_REACK 0x00400000U /*!< Receive Enable Acknowledge Flag */
Kojto 122:f9eeca106725 8133
Kojto 122:f9eeca106725 8134
Kojto 122:f9eeca106725 8135 /******************* Bit definition for USART_ICR register ******************/
Kojto 122:f9eeca106725 8136 #define USART_ICR_PECF 0x00000001U /*!< Parity Error Clear Flag */
Kojto 122:f9eeca106725 8137 #define USART_ICR_FECF 0x00000002U /*!< Framing Error Clear Flag */
Kojto 122:f9eeca106725 8138 #define USART_ICR_NCF 0x00000004U /*!< Noise detected Clear Flag */
Kojto 122:f9eeca106725 8139 #define USART_ICR_ORECF 0x00000008U /*!< OverRun Error Clear Flag */
Kojto 122:f9eeca106725 8140 #define USART_ICR_IDLECF 0x00000010U /*!< IDLE line detected Clear Flag */
Kojto 122:f9eeca106725 8141 #define USART_ICR_TCCF 0x00000040U /*!< Transmission Complete Clear Flag */
Kojto 122:f9eeca106725 8142 #define USART_ICR_LBDCF 0x00000100U /*!< LIN Break Detection Clear Flag */
Kojto 122:f9eeca106725 8143 #define USART_ICR_CTSCF 0x00000200U /*!< CTS Interrupt Clear Flag */
Kojto 122:f9eeca106725 8144 #define USART_ICR_RTOCF 0x00000800U /*!< Receiver Time Out Clear Flag */
Kojto 122:f9eeca106725 8145 #define USART_ICR_EOBCF 0x00001000U /*!< End Of Block Clear Flag */
Kojto 122:f9eeca106725 8146 #define USART_ICR_CMCF 0x00020000U /*!< Character Match Clear Flag */
Kojto 122:f9eeca106725 8147 #define USART_ICR_WUCF 0x00100000U /*!< Wake Up from stop mode Clear Flag */
Kojto 122:f9eeca106725 8148
Kojto 122:f9eeca106725 8149 /******************* Bit definition for USART_RDR register ******************/
Kojto 122:f9eeca106725 8150 #define USART_RDR_RDR 0x01FFU /*!< RDR[8:0] bits (Receive Data value) */
Kojto 122:f9eeca106725 8151
Kojto 122:f9eeca106725 8152 /******************* Bit definition for USART_TDR register ******************/
Kojto 122:f9eeca106725 8153 #define USART_TDR_TDR 0x01FFU /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 122:f9eeca106725 8154
Kojto 122:f9eeca106725 8155 /******************************************************************************/
Kojto 122:f9eeca106725 8156 /* */
Kojto 122:f9eeca106725 8157 /* Window WATCHDOG */
Kojto 122:f9eeca106725 8158 /* */
Kojto 122:f9eeca106725 8159 /******************************************************************************/
Kojto 122:f9eeca106725 8160 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 8161 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 8162 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
Kojto 122:f9eeca106725 8163 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
Kojto 122:f9eeca106725 8164 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
Kojto 122:f9eeca106725 8165 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
Kojto 122:f9eeca106725 8166 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
Kojto 122:f9eeca106725 8167 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
Kojto 122:f9eeca106725 8168 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
Kojto 122:f9eeca106725 8169
Kojto 122:f9eeca106725 8170
Kojto 122:f9eeca106725 8171 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
Kojto 122:f9eeca106725 8172
Kojto 122:f9eeca106725 8173 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 8174 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 8175 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
Kojto 122:f9eeca106725 8176 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
Kojto 122:f9eeca106725 8177 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
Kojto 122:f9eeca106725 8178 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
Kojto 122:f9eeca106725 8179 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
Kojto 122:f9eeca106725 8180 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
Kojto 122:f9eeca106725 8181 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
Kojto 122:f9eeca106725 8182
Kojto 122:f9eeca106725 8183
Kojto 122:f9eeca106725 8184 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 8185 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
Kojto 122:f9eeca106725 8186 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
Kojto 122:f9eeca106725 8187
Kojto 122:f9eeca106725 8188
Kojto 122:f9eeca106725 8189 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
Kojto 122:f9eeca106725 8190
Kojto 122:f9eeca106725 8191 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 8192 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
Kojto 122:f9eeca106725 8193
Kojto 122:f9eeca106725 8194 /******************************************************************************/
Kojto 122:f9eeca106725 8195 /* */
Kojto 122:f9eeca106725 8196 /* DBG */
Kojto 122:f9eeca106725 8197 /* */
Kojto 122:f9eeca106725 8198 /******************************************************************************/
Kojto 122:f9eeca106725 8199 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 122:f9eeca106725 8200 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
Kojto 122:f9eeca106725 8201 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
Kojto 122:f9eeca106725 8202
Kojto 122:f9eeca106725 8203 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 122:f9eeca106725 8204 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
Kojto 122:f9eeca106725 8205 #define DBGMCU_CR_DBG_STOP 0x00000002U
Kojto 122:f9eeca106725 8206 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
Kojto 122:f9eeca106725 8207 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
Kojto 122:f9eeca106725 8208
Kojto 122:f9eeca106725 8209 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
Kojto 122:f9eeca106725 8210 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 8211 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 8212
Kojto 122:f9eeca106725 8213 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 122:f9eeca106725 8214 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
Kojto 122:f9eeca106725 8215 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
Kojto 122:f9eeca106725 8216 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
Kojto 122:f9eeca106725 8217 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
Kojto 122:f9eeca106725 8218 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
Kojto 122:f9eeca106725 8219 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
Kojto 122:f9eeca106725 8220 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
Kojto 122:f9eeca106725 8221 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
Kojto 122:f9eeca106725 8222 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
Kojto 122:f9eeca106725 8223 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
Kojto 122:f9eeca106725 8224 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
Kojto 122:f9eeca106725 8225 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
Kojto 122:f9eeca106725 8226 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP 0x00002000U
Kojto 122:f9eeca106725 8227 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
Kojto 122:f9eeca106725 8228 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
Kojto 122:f9eeca106725 8229 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
Kojto 122:f9eeca106725 8230 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
Kojto 122:f9eeca106725 8231 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
Kojto 122:f9eeca106725 8232
Kojto 122:f9eeca106725 8233 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 122:f9eeca106725 8234 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
Kojto 122:f9eeca106725 8235 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
Kojto 122:f9eeca106725 8236 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
Kojto 122:f9eeca106725 8237 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
Kojto 122:f9eeca106725 8238 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
Kojto 122:f9eeca106725 8239
Kojto 122:f9eeca106725 8240 /******************************************************************************/
Kojto 122:f9eeca106725 8241 /* */
Kojto 122:f9eeca106725 8242 /* Ethernet MAC Registers bits definitions */
Kojto 122:f9eeca106725 8243 /* */
Kojto 122:f9eeca106725 8244 /******************************************************************************/
Kojto 122:f9eeca106725 8245 /* Bit definition for Ethernet MAC Control Register register */
Kojto 122:f9eeca106725 8246 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
Kojto 122:f9eeca106725 8247 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
Kojto 122:f9eeca106725 8248 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
Kojto 122:f9eeca106725 8249 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
Kojto 122:f9eeca106725 8250 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
Kojto 122:f9eeca106725 8251 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
Kojto 122:f9eeca106725 8252 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
Kojto 122:f9eeca106725 8253 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
Kojto 122:f9eeca106725 8254 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
Kojto 122:f9eeca106725 8255 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
Kojto 122:f9eeca106725 8256 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
Kojto 122:f9eeca106725 8257 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
Kojto 122:f9eeca106725 8258 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
Kojto 122:f9eeca106725 8259 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
Kojto 122:f9eeca106725 8260 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
Kojto 122:f9eeca106725 8261 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
Kojto 122:f9eeca106725 8262 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
Kojto 122:f9eeca106725 8263 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
Kojto 122:f9eeca106725 8264 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
Kojto 122:f9eeca106725 8265 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
Kojto 122:f9eeca106725 8266 a transmission attempt during retries after a collision: 0 =< r <2^k */
Kojto 122:f9eeca106725 8267 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
Kojto 122:f9eeca106725 8268 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
Kojto 122:f9eeca106725 8269 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
Kojto 122:f9eeca106725 8270 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
Kojto 122:f9eeca106725 8271 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
Kojto 122:f9eeca106725 8272 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
Kojto 122:f9eeca106725 8273 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
Kojto 122:f9eeca106725 8274
Kojto 122:f9eeca106725 8275 /* Bit definition for Ethernet MAC Frame Filter Register */
Kojto 122:f9eeca106725 8276 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
Kojto 122:f9eeca106725 8277 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
Kojto 122:f9eeca106725 8278 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
Kojto 122:f9eeca106725 8279 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
Kojto 122:f9eeca106725 8280 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
Kojto 122:f9eeca106725 8281 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
Kojto 122:f9eeca106725 8282 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
Kojto 122:f9eeca106725 8283 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
Kojto 122:f9eeca106725 8284 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
Kojto 122:f9eeca106725 8285 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
Kojto 122:f9eeca106725 8286 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
Kojto 122:f9eeca106725 8287 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
Kojto 122:f9eeca106725 8288 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
Kojto 122:f9eeca106725 8289 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
Kojto 122:f9eeca106725 8290
Kojto 122:f9eeca106725 8291 /* Bit definition for Ethernet MAC Hash Table High Register */
Kojto 122:f9eeca106725 8292 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
Kojto 122:f9eeca106725 8293
Kojto 122:f9eeca106725 8294 /* Bit definition for Ethernet MAC Hash Table Low Register */
Kojto 122:f9eeca106725 8295 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
Kojto 122:f9eeca106725 8296
Kojto 122:f9eeca106725 8297 /* Bit definition for Ethernet MAC MII Address Register */
Kojto 122:f9eeca106725 8298 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
Kojto 122:f9eeca106725 8299 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
Kojto 122:f9eeca106725 8300 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
Kojto 122:f9eeca106725 8301 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
Kojto 122:f9eeca106725 8302 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
Kojto 122:f9eeca106725 8303 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
Kojto 122:f9eeca106725 8304 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
Kojto 122:f9eeca106725 8305 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
Kojto 122:f9eeca106725 8306 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
Kojto 122:f9eeca106725 8307 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
Kojto 122:f9eeca106725 8308
Kojto 122:f9eeca106725 8309 /* Bit definition for Ethernet MAC MII Data Register */
Kojto 122:f9eeca106725 8310 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
Kojto 122:f9eeca106725 8311
Kojto 122:f9eeca106725 8312 /* Bit definition for Ethernet MAC Flow Control Register */
Kojto 122:f9eeca106725 8313 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
Kojto 122:f9eeca106725 8314 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
Kojto 122:f9eeca106725 8315 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
Kojto 122:f9eeca106725 8316 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
Kojto 122:f9eeca106725 8317 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
Kojto 122:f9eeca106725 8318 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
Kojto 122:f9eeca106725 8319 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
Kojto 122:f9eeca106725 8320 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
Kojto 122:f9eeca106725 8321 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
Kojto 122:f9eeca106725 8322 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
Kojto 122:f9eeca106725 8323 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
Kojto 122:f9eeca106725 8324
Kojto 122:f9eeca106725 8325 /* Bit definition for Ethernet MAC VLAN Tag Register */
Kojto 122:f9eeca106725 8326 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
Kojto 122:f9eeca106725 8327 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
Kojto 122:f9eeca106725 8328
Kojto 122:f9eeca106725 8329 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
Kojto 122:f9eeca106725 8330 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
Kojto 122:f9eeca106725 8331 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Kojto 122:f9eeca106725 8332 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
Kojto 122:f9eeca106725 8333 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Kojto 122:f9eeca106725 8334 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Kojto 122:f9eeca106725 8335 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Kojto 122:f9eeca106725 8336 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Kojto 122:f9eeca106725 8337 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
Kojto 122:f9eeca106725 8338 RSVD - Filter1 Command - RSVD - Filter0 Command
Kojto 122:f9eeca106725 8339 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Kojto 122:f9eeca106725 8340 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Kojto 122:f9eeca106725 8341 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
Kojto 122:f9eeca106725 8342
Kojto 122:f9eeca106725 8343 /* Bit definition for Ethernet MAC PMT Control and Status Register */
Kojto 122:f9eeca106725 8344 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
Kojto 122:f9eeca106725 8345 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
Kojto 122:f9eeca106725 8346 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
Kojto 122:f9eeca106725 8347 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
Kojto 122:f9eeca106725 8348 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
Kojto 122:f9eeca106725 8349 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
Kojto 122:f9eeca106725 8350 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
Kojto 122:f9eeca106725 8351
Kojto 122:f9eeca106725 8352 /* Bit definition for Ethernet MAC Status Register */
Kojto 122:f9eeca106725 8353 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
Kojto 122:f9eeca106725 8354 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
Kojto 122:f9eeca106725 8355 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
Kojto 122:f9eeca106725 8356 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
Kojto 122:f9eeca106725 8357 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
Kojto 122:f9eeca106725 8358
Kojto 122:f9eeca106725 8359 /* Bit definition for Ethernet MAC Interrupt Mask Register */
Kojto 122:f9eeca106725 8360 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
Kojto 122:f9eeca106725 8361 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
Kojto 122:f9eeca106725 8362
Kojto 122:f9eeca106725 8363 /* Bit definition for Ethernet MAC Address0 High Register */
Kojto 122:f9eeca106725 8364 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
Kojto 122:f9eeca106725 8365
Kojto 122:f9eeca106725 8366 /* Bit definition for Ethernet MAC Address0 Low Register */
Kojto 122:f9eeca106725 8367 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
Kojto 122:f9eeca106725 8368
Kojto 122:f9eeca106725 8369 /* Bit definition for Ethernet MAC Address1 High Register */
Kojto 122:f9eeca106725 8370 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
Kojto 122:f9eeca106725 8371 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
Kojto 122:f9eeca106725 8372 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
Kojto 122:f9eeca106725 8373 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto 122:f9eeca106725 8374 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto 122:f9eeca106725 8375 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto 122:f9eeca106725 8376 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto 122:f9eeca106725 8377 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto 122:f9eeca106725 8378 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
Kojto 122:f9eeca106725 8379 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
Kojto 122:f9eeca106725 8380
Kojto 122:f9eeca106725 8381 /* Bit definition for Ethernet MAC Address1 Low Register */
Kojto 122:f9eeca106725 8382 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
Kojto 122:f9eeca106725 8383
Kojto 122:f9eeca106725 8384 /* Bit definition for Ethernet MAC Address2 High Register */
Kojto 122:f9eeca106725 8385 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
Kojto 122:f9eeca106725 8386 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
Kojto 122:f9eeca106725 8387 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
Kojto 122:f9eeca106725 8388 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto 122:f9eeca106725 8389 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto 122:f9eeca106725 8390 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto 122:f9eeca106725 8391 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto 122:f9eeca106725 8392 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto 122:f9eeca106725 8393 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
Kojto 122:f9eeca106725 8394 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
Kojto 122:f9eeca106725 8395
Kojto 122:f9eeca106725 8396 /* Bit definition for Ethernet MAC Address2 Low Register */
Kojto 122:f9eeca106725 8397 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
Kojto 122:f9eeca106725 8398
Kojto 122:f9eeca106725 8399 /* Bit definition for Ethernet MAC Address3 High Register */
Kojto 122:f9eeca106725 8400 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
Kojto 122:f9eeca106725 8401 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
Kojto 122:f9eeca106725 8402 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
Kojto 122:f9eeca106725 8403 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto 122:f9eeca106725 8404 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto 122:f9eeca106725 8405 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto 122:f9eeca106725 8406 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto 122:f9eeca106725 8407 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto 122:f9eeca106725 8408 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
Kojto 122:f9eeca106725 8409 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
Kojto 122:f9eeca106725 8410
Kojto 122:f9eeca106725 8411 /* Bit definition for Ethernet MAC Address3 Low Register */
Kojto 122:f9eeca106725 8412 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
Kojto 122:f9eeca106725 8413
Kojto 122:f9eeca106725 8414 /******************************************************************************/
Kojto 122:f9eeca106725 8415 /* Ethernet MMC Registers bits definition */
Kojto 122:f9eeca106725 8416 /******************************************************************************/
Kojto 122:f9eeca106725 8417
Kojto 122:f9eeca106725 8418 /* Bit definition for Ethernet MMC Contol Register */
Kojto 122:f9eeca106725 8419 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
Kojto 122:f9eeca106725 8420 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
Kojto 122:f9eeca106725 8421 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
Kojto 122:f9eeca106725 8422 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
Kojto 122:f9eeca106725 8423 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
Kojto 122:f9eeca106725 8424 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
Kojto 122:f9eeca106725 8425
Kojto 122:f9eeca106725 8426 /* Bit definition for Ethernet MMC Receive Interrupt Register */
Kojto 122:f9eeca106725 8427 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
Kojto 122:f9eeca106725 8428 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
Kojto 122:f9eeca106725 8429 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
Kojto 122:f9eeca106725 8430
Kojto 122:f9eeca106725 8431 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
Kojto 122:f9eeca106725 8432 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
Kojto 122:f9eeca106725 8433 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
Kojto 122:f9eeca106725 8434 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
Kojto 122:f9eeca106725 8435
Kojto 122:f9eeca106725 8436 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
Kojto 122:f9eeca106725 8437 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
Kojto 122:f9eeca106725 8438 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
Kojto 122:f9eeca106725 8439 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
Kojto 122:f9eeca106725 8440
Kojto 122:f9eeca106725 8441 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
Kojto 122:f9eeca106725 8442 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
Kojto 122:f9eeca106725 8443 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
Kojto 122:f9eeca106725 8444 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
Kojto 122:f9eeca106725 8445
Kojto 122:f9eeca106725 8446 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
Kojto 122:f9eeca106725 8447 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
Kojto 122:f9eeca106725 8448
Kojto 122:f9eeca106725 8449 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
Kojto 122:f9eeca106725 8450 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
Kojto 122:f9eeca106725 8451
Kojto 122:f9eeca106725 8452 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
Kojto 122:f9eeca106725 8453 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
Kojto 122:f9eeca106725 8454
Kojto 122:f9eeca106725 8455 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
Kojto 122:f9eeca106725 8456 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
Kojto 122:f9eeca106725 8457
Kojto 122:f9eeca106725 8458 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
Kojto 122:f9eeca106725 8459 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
Kojto 122:f9eeca106725 8460
Kojto 122:f9eeca106725 8461 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
Kojto 122:f9eeca106725 8462 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
Kojto 122:f9eeca106725 8463
Kojto 122:f9eeca106725 8464 /******************************************************************************/
Kojto 122:f9eeca106725 8465 /* Ethernet PTP Registers bits definition */
Kojto 122:f9eeca106725 8466 /******************************************************************************/
Kojto 122:f9eeca106725 8467
Kojto 122:f9eeca106725 8468 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
Kojto 122:f9eeca106725 8469 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
Kojto 122:f9eeca106725 8470 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
Kojto 122:f9eeca106725 8471 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
Kojto 122:f9eeca106725 8472 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
Kojto 122:f9eeca106725 8473 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
Kojto 122:f9eeca106725 8474 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
Kojto 122:f9eeca106725 8475 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
Kojto 122:f9eeca106725 8476 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
Kojto 122:f9eeca106725 8477 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
Kojto 122:f9eeca106725 8478
Kojto 122:f9eeca106725 8479 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
Kojto 122:f9eeca106725 8480 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
Kojto 122:f9eeca106725 8481 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
Kojto 122:f9eeca106725 8482 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
Kojto 122:f9eeca106725 8483 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
Kojto 122:f9eeca106725 8484 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
Kojto 122:f9eeca106725 8485
Kojto 122:f9eeca106725 8486 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
Kojto 122:f9eeca106725 8487 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
Kojto 122:f9eeca106725 8488
Kojto 122:f9eeca106725 8489 /* Bit definition for Ethernet PTP Time Stamp High Register */
Kojto 122:f9eeca106725 8490 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
Kojto 122:f9eeca106725 8491
Kojto 122:f9eeca106725 8492 /* Bit definition for Ethernet PTP Time Stamp Low Register */
Kojto 122:f9eeca106725 8493 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
Kojto 122:f9eeca106725 8494 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
Kojto 122:f9eeca106725 8495
Kojto 122:f9eeca106725 8496 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
Kojto 122:f9eeca106725 8497 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
Kojto 122:f9eeca106725 8498
Kojto 122:f9eeca106725 8499 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
Kojto 122:f9eeca106725 8500 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
Kojto 122:f9eeca106725 8501 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
Kojto 122:f9eeca106725 8502
Kojto 122:f9eeca106725 8503 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
Kojto 122:f9eeca106725 8504 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
Kojto 122:f9eeca106725 8505
Kojto 122:f9eeca106725 8506 /* Bit definition for Ethernet PTP Target Time High Register */
Kojto 122:f9eeca106725 8507 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
Kojto 122:f9eeca106725 8508
Kojto 122:f9eeca106725 8509 /* Bit definition for Ethernet PTP Target Time Low Register */
Kojto 122:f9eeca106725 8510 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
Kojto 122:f9eeca106725 8511
Kojto 122:f9eeca106725 8512 /* Bit definition for Ethernet PTP Time Stamp Status Register */
Kojto 122:f9eeca106725 8513 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
Kojto 122:f9eeca106725 8514 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
Kojto 122:f9eeca106725 8515
Kojto 122:f9eeca106725 8516 /******************************************************************************/
Kojto 122:f9eeca106725 8517 /* Ethernet DMA Registers bits definition */
Kojto 122:f9eeca106725 8518 /******************************************************************************/
Kojto 122:f9eeca106725 8519
Kojto 122:f9eeca106725 8520 /* Bit definition for Ethernet DMA Bus Mode Register */
Kojto 122:f9eeca106725 8521 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
Kojto 122:f9eeca106725 8522 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
Kojto 122:f9eeca106725 8523 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
Kojto 122:f9eeca106725 8524 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
Kojto 122:f9eeca106725 8525 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
Kojto 122:f9eeca106725 8526 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
Kojto 122:f9eeca106725 8527 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 122:f9eeca106725 8528 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 122:f9eeca106725 8529 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 122:f9eeca106725 8530 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 122:f9eeca106725 8531 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 122:f9eeca106725 8532 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 122:f9eeca106725 8533 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 122:f9eeca106725 8534 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 122:f9eeca106725 8535 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
Kojto 122:f9eeca106725 8536 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
Kojto 122:f9eeca106725 8537 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
Kojto 122:f9eeca106725 8538 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
Kojto 122:f9eeca106725 8539 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
Kojto 122:f9eeca106725 8540 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
Kojto 122:f9eeca106725 8541 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
Kojto 122:f9eeca106725 8542 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
Kojto 122:f9eeca106725 8543 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
Kojto 122:f9eeca106725 8544 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Kojto 122:f9eeca106725 8545 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Kojto 122:f9eeca106725 8546 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 122:f9eeca106725 8547 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 122:f9eeca106725 8548 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 122:f9eeca106725 8549 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 122:f9eeca106725 8550 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 122:f9eeca106725 8551 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 122:f9eeca106725 8552 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 122:f9eeca106725 8553 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 122:f9eeca106725 8554 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Kojto 122:f9eeca106725 8555 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto 122:f9eeca106725 8556 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
Kojto 122:f9eeca106725 8557 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
Kojto 122:f9eeca106725 8558 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
Kojto 122:f9eeca106725 8559 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
Kojto 122:f9eeca106725 8560
Kojto 122:f9eeca106725 8561 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
Kojto 122:f9eeca106725 8562 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
Kojto 122:f9eeca106725 8563
Kojto 122:f9eeca106725 8564 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
Kojto 122:f9eeca106725 8565 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
Kojto 122:f9eeca106725 8566
Kojto 122:f9eeca106725 8567 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
Kojto 122:f9eeca106725 8568 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
Kojto 122:f9eeca106725 8569
Kojto 122:f9eeca106725 8570 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
Kojto 122:f9eeca106725 8571 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
Kojto 122:f9eeca106725 8572
Kojto 122:f9eeca106725 8573 /* Bit definition for Ethernet DMA Status Register */
Kojto 122:f9eeca106725 8574 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
Kojto 122:f9eeca106725 8575 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
Kojto 122:f9eeca106725 8576 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
Kojto 122:f9eeca106725 8577 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
Kojto 122:f9eeca106725 8578 /* combination with EBS[2:0] for GetFlagStatus function */
Kojto 122:f9eeca106725 8579 #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
Kojto 122:f9eeca106725 8580 #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
Kojto 122:f9eeca106725 8581 #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
Kojto 122:f9eeca106725 8582 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
Kojto 122:f9eeca106725 8583 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
Kojto 122:f9eeca106725 8584 #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
Kojto 122:f9eeca106725 8585 #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
Kojto 122:f9eeca106725 8586 #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
Kojto 122:f9eeca106725 8587 #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
Kojto 122:f9eeca106725 8588 #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
Kojto 122:f9eeca106725 8589 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
Kojto 122:f9eeca106725 8590 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
Kojto 122:f9eeca106725 8591 #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
Kojto 122:f9eeca106725 8592 #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
Kojto 122:f9eeca106725 8593 #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
Kojto 122:f9eeca106725 8594 #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
Kojto 122:f9eeca106725 8595 #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
Kojto 122:f9eeca106725 8596 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
Kojto 122:f9eeca106725 8597 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
Kojto 122:f9eeca106725 8598 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
Kojto 122:f9eeca106725 8599 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
Kojto 122:f9eeca106725 8600 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
Kojto 122:f9eeca106725 8601 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
Kojto 122:f9eeca106725 8602 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
Kojto 122:f9eeca106725 8603 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
Kojto 122:f9eeca106725 8604 #define ETH_DMASR_RS 0x00000040U /* Receive status */
Kojto 122:f9eeca106725 8605 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
Kojto 122:f9eeca106725 8606 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
Kojto 122:f9eeca106725 8607 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
Kojto 122:f9eeca106725 8608 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
Kojto 122:f9eeca106725 8609 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
Kojto 122:f9eeca106725 8610 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
Kojto 122:f9eeca106725 8611
Kojto 122:f9eeca106725 8612 /* Bit definition for Ethernet DMA Operation Mode Register */
Kojto 122:f9eeca106725 8613 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
Kojto 122:f9eeca106725 8614 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
Kojto 122:f9eeca106725 8615 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
Kojto 122:f9eeca106725 8616 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
Kojto 122:f9eeca106725 8617 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
Kojto 122:f9eeca106725 8618 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
Kojto 122:f9eeca106725 8619 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
Kojto 122:f9eeca106725 8620 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
Kojto 122:f9eeca106725 8621 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
Kojto 122:f9eeca106725 8622 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
Kojto 122:f9eeca106725 8623 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
Kojto 122:f9eeca106725 8624 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
Kojto 122:f9eeca106725 8625 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
Kojto 122:f9eeca106725 8626 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
Kojto 122:f9eeca106725 8627 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
Kojto 122:f9eeca106725 8628 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
Kojto 122:f9eeca106725 8629 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
Kojto 122:f9eeca106725 8630 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
Kojto 122:f9eeca106725 8631 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
Kojto 122:f9eeca106725 8632 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
Kojto 122:f9eeca106725 8633 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
Kojto 122:f9eeca106725 8634 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
Kojto 122:f9eeca106725 8635 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
Kojto 122:f9eeca106725 8636 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
Kojto 122:f9eeca106725 8637
Kojto 122:f9eeca106725 8638 /* Bit definition for Ethernet DMA Interrupt Enable Register */
Kojto 122:f9eeca106725 8639 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
Kojto 122:f9eeca106725 8640 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
Kojto 122:f9eeca106725 8641 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
Kojto 122:f9eeca106725 8642 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
Kojto 122:f9eeca106725 8643 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
Kojto 122:f9eeca106725 8644 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
Kojto 122:f9eeca106725 8645 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
Kojto 122:f9eeca106725 8646 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
Kojto 122:f9eeca106725 8647 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
Kojto 122:f9eeca106725 8648 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
Kojto 122:f9eeca106725 8649 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
Kojto 122:f9eeca106725 8650 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
Kojto 122:f9eeca106725 8651 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
Kojto 122:f9eeca106725 8652 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
Kojto 122:f9eeca106725 8653 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
Kojto 122:f9eeca106725 8654
Kojto 122:f9eeca106725 8655 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
Kojto 122:f9eeca106725 8656 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
Kojto 122:f9eeca106725 8657 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
Kojto 122:f9eeca106725 8658 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
Kojto 122:f9eeca106725 8659 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
Kojto 122:f9eeca106725 8660
Kojto 122:f9eeca106725 8661 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
Kojto 122:f9eeca106725 8662 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
Kojto 122:f9eeca106725 8663
Kojto 122:f9eeca106725 8664 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
Kojto 122:f9eeca106725 8665 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
Kojto 122:f9eeca106725 8666
Kojto 122:f9eeca106725 8667 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
Kojto 122:f9eeca106725 8668 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
Kojto 122:f9eeca106725 8669
Kojto 122:f9eeca106725 8670 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
Kojto 122:f9eeca106725 8671 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
Kojto 122:f9eeca106725 8672
Kojto 122:f9eeca106725 8673 /******************************************************************************/
Kojto 122:f9eeca106725 8674 /* */
Kojto 122:f9eeca106725 8675 /* USB_OTG */
Kojto 122:f9eeca106725 8676 /* */
Kojto 122:f9eeca106725 8677 /******************************************************************************/
Kojto 122:f9eeca106725 8678 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
Kojto 122:f9eeca106725 8679 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
Kojto 122:f9eeca106725 8680 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
Kojto 122:f9eeca106725 8681 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
Kojto 122:f9eeca106725 8682 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
Kojto 122:f9eeca106725 8683 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
Kojto 122:f9eeca106725 8684 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
Kojto 122:f9eeca106725 8685 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
Kojto 122:f9eeca106725 8686 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
Kojto 122:f9eeca106725 8687 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
Kojto 122:f9eeca106725 8688 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
Kojto 122:f9eeca106725 8689 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
Kojto 122:f9eeca106725 8690 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
Kojto 122:f9eeca106725 8691 #define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
Kojto 122:f9eeca106725 8692 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
Kojto 122:f9eeca106725 8693 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
Kojto 122:f9eeca106725 8694 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
Kojto 122:f9eeca106725 8695 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
Kojto 122:f9eeca106725 8696 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
Kojto 122:f9eeca106725 8697
Kojto 122:f9eeca106725 8698 /******************** Bit definition for USB_OTG_HCFG register ********************/
Kojto 122:f9eeca106725 8699 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
Kojto 122:f9eeca106725 8700 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 8701 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 8702 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
Kojto 122:f9eeca106725 8703
Kojto 122:f9eeca106725 8704 /******************** Bit definition for USB_OTG_DCFG register ********************/
Kojto 122:f9eeca106725 8705 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
Kojto 122:f9eeca106725 8706 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 8707 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 8708 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
Kojto 122:f9eeca106725 8709
Kojto 122:f9eeca106725 8710 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
Kojto 122:f9eeca106725 8711 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 8712 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 8713 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 8714 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 8715 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
Kojto 122:f9eeca106725 8716 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
Kojto 122:f9eeca106725 8717 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
Kojto 122:f9eeca106725 8718
Kojto 122:f9eeca106725 8719 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
Kojto 122:f9eeca106725 8720 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
Kojto 122:f9eeca106725 8721 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8722
Kojto 122:f9eeca106725 8723 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
Kojto 122:f9eeca106725 8724 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 8725 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8726
Kojto 122:f9eeca106725 8727 /******************** Bit definition for USB_OTG_PCGCR register ********************/
Kojto 122:f9eeca106725 8728 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
Kojto 122:f9eeca106725 8729 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
Kojto 122:f9eeca106725 8730 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
Kojto 122:f9eeca106725 8731
Kojto 122:f9eeca106725 8732 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
Kojto 122:f9eeca106725 8733 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
Kojto 122:f9eeca106725 8734 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
Kojto 122:f9eeca106725 8735 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
Kojto 122:f9eeca106725 8736 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
Kojto 122:f9eeca106725 8737 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
Kojto 122:f9eeca106725 8738 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
Kojto 122:f9eeca106725 8739 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
Kojto 122:f9eeca106725 8740
Kojto 122:f9eeca106725 8741 /******************** Bit definition for USB_OTG_DCTL register ********************/
Kojto 122:f9eeca106725 8742 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
Kojto 122:f9eeca106725 8743 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
Kojto 122:f9eeca106725 8744 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
Kojto 122:f9eeca106725 8745 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
Kojto 122:f9eeca106725 8746
Kojto 122:f9eeca106725 8747 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
Kojto 122:f9eeca106725 8748 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 8749 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 8750 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 8751 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
Kojto 122:f9eeca106725 8752 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
Kojto 122:f9eeca106725 8753 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
Kojto 122:f9eeca106725 8754 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
Kojto 122:f9eeca106725 8755 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
Kojto 122:f9eeca106725 8756
Kojto 122:f9eeca106725 8757 /******************** Bit definition for USB_OTG_HFIR register ********************/
Kojto 122:f9eeca106725 8758 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
Kojto 122:f9eeca106725 8759
Kojto 122:f9eeca106725 8760 /******************** Bit definition for USB_OTG_HFNUM register ********************/
Kojto 122:f9eeca106725 8761 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
Kojto 122:f9eeca106725 8762 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
Kojto 122:f9eeca106725 8763
Kojto 122:f9eeca106725 8764 /******************** Bit definition for USB_OTG_DSTS register ********************/
Kojto 122:f9eeca106725 8765 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
Kojto 122:f9eeca106725 8766
Kojto 122:f9eeca106725 8767 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
Kojto 122:f9eeca106725 8768 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 8769 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 8770 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
Kojto 122:f9eeca106725 8771 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
Kojto 122:f9eeca106725 8772
Kojto 122:f9eeca106725 8773 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
Kojto 122:f9eeca106725 8774 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
Kojto 122:f9eeca106725 8775 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
Kojto 122:f9eeca106725 8776 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 8777 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
Kojto 122:f9eeca106725 8778 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
Kojto 122:f9eeca106725 8779 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
Kojto 122:f9eeca106725 8780 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
Kojto 122:f9eeca106725 8781 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
Kojto 122:f9eeca106725 8782 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
Kojto 122:f9eeca106725 8783
Kojto 122:f9eeca106725 8784 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
Kojto 122:f9eeca106725 8785 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
Kojto 122:f9eeca106725 8786 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 8787 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 8788 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 8789 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 122:f9eeca106725 8790 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
Kojto 122:f9eeca106725 8791 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
Kojto 122:f9eeca106725 8792 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
Kojto 122:f9eeca106725 8793 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 8794 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 8795 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
Kojto 122:f9eeca106725 8796 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
Kojto 122:f9eeca106725 8797 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
Kojto 122:f9eeca106725 8798 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
Kojto 122:f9eeca106725 8799 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
Kojto 122:f9eeca106725 8800 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
Kojto 122:f9eeca106725 8801 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
Kojto 122:f9eeca106725 8802 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
Kojto 122:f9eeca106725 8803 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
Kojto 122:f9eeca106725 8804 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
Kojto 122:f9eeca106725 8805 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
Kojto 122:f9eeca106725 8806 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
Kojto 122:f9eeca106725 8807 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
Kojto 122:f9eeca106725 8808 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
Kojto 122:f9eeca106725 8809 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
Kojto 122:f9eeca106725 8810
Kojto 122:f9eeca106725 8811 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
Kojto 122:f9eeca106725 8812 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
Kojto 122:f9eeca106725 8813 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
Kojto 122:f9eeca106725 8814 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
Kojto 122:f9eeca106725 8815 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
Kojto 122:f9eeca106725 8816 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
Kojto 122:f9eeca106725 8817 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
Kojto 122:f9eeca106725 8818 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 8819 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 8820 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
Kojto 122:f9eeca106725 8821 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
Kojto 122:f9eeca106725 8822 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
Kojto 122:f9eeca106725 8823 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
Kojto 122:f9eeca106725 8824 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
Kojto 122:f9eeca106725 8825
Kojto 122:f9eeca106725 8826 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
Kojto 122:f9eeca106725 8827 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 8828 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 8829 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 122:f9eeca106725 8830 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 8831 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 8832 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 8833 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
Kojto 122:f9eeca106725 8834 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 8835
Kojto 122:f9eeca106725 8836 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
Kojto 122:f9eeca106725 8837 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
Kojto 122:f9eeca106725 8838 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
Kojto 122:f9eeca106725 8839 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 8840 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8841 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 8842 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 8843 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 8844 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 8845 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 8846 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 8847
Kojto 122:f9eeca106725 8848 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
Kojto 122:f9eeca106725 8849 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 8850 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8851 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 8852 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 8853 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 8854 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 8855 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 8856 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
Kojto 122:f9eeca106725 8857
Kojto 122:f9eeca106725 8858 /******************** Bit definition for USB_OTG_HAINT register ********************/
Kojto 122:f9eeca106725 8859 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
Kojto 122:f9eeca106725 8860
Kojto 122:f9eeca106725 8861 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
Kojto 122:f9eeca106725 8862 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 8863 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 8864 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
Kojto 122:f9eeca106725 8865 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
Kojto 122:f9eeca106725 8866 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
Kojto 122:f9eeca106725 8867 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
Kojto 122:f9eeca106725 8868 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
Kojto 122:f9eeca106725 8869 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 8870
Kojto 122:f9eeca106725 8871 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
Kojto 122:f9eeca106725 8872 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
Kojto 122:f9eeca106725 8873 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
Kojto 122:f9eeca106725 8874 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
Kojto 122:f9eeca106725 8875 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
Kojto 122:f9eeca106725 8876 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
Kojto 122:f9eeca106725 8877 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
Kojto 122:f9eeca106725 8878 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
Kojto 122:f9eeca106725 8879 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
Kojto 122:f9eeca106725 8880 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
Kojto 122:f9eeca106725 8881 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
Kojto 122:f9eeca106725 8882 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
Kojto 122:f9eeca106725 8883 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
Kojto 122:f9eeca106725 8884 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
Kojto 122:f9eeca106725 8885 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
Kojto 122:f9eeca106725 8886 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
Kojto 122:f9eeca106725 8887 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
Kojto 122:f9eeca106725 8888 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
Kojto 122:f9eeca106725 8889 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
Kojto 122:f9eeca106725 8890 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
Kojto 122:f9eeca106725 8891 #define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
Kojto 122:f9eeca106725 8892 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
Kojto 122:f9eeca106725 8893 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
Kojto 122:f9eeca106725 8894 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
Kojto 122:f9eeca106725 8895 #define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
Kojto 122:f9eeca106725 8896 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
Kojto 122:f9eeca106725 8897 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
Kojto 122:f9eeca106725 8898 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
Kojto 122:f9eeca106725 8899 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
Kojto 122:f9eeca106725 8900
Kojto 122:f9eeca106725 8901 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
Kojto 122:f9eeca106725 8902 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
Kojto 122:f9eeca106725 8903 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
Kojto 122:f9eeca106725 8904 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
Kojto 122:f9eeca106725 8905 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
Kojto 122:f9eeca106725 8906 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
Kojto 122:f9eeca106725 8907 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
Kojto 122:f9eeca106725 8908 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
Kojto 122:f9eeca106725 8909 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
Kojto 122:f9eeca106725 8910 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
Kojto 122:f9eeca106725 8911 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
Kojto 122:f9eeca106725 8912 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
Kojto 122:f9eeca106725 8913 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 122:f9eeca106725 8914 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
Kojto 122:f9eeca106725 8915 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
Kojto 122:f9eeca106725 8916 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
Kojto 122:f9eeca106725 8917 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
Kojto 122:f9eeca106725 8918 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
Kojto 122:f9eeca106725 8919 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
Kojto 122:f9eeca106725 8920 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
Kojto 122:f9eeca106725 8921 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
Kojto 122:f9eeca106725 8922 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
Kojto 122:f9eeca106725 8923 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
Kojto 122:f9eeca106725 8924 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
Kojto 122:f9eeca106725 8925 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
Kojto 122:f9eeca106725 8926 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
Kojto 122:f9eeca106725 8927 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
Kojto 122:f9eeca106725 8928 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
Kojto 122:f9eeca106725 8929 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
Kojto 122:f9eeca106725 8930
Kojto 122:f9eeca106725 8931 /******************** Bit definition for USB_OTG_DAINT register ********************/
Kojto 122:f9eeca106725 8932 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
Kojto 122:f9eeca106725 8933 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
Kojto 122:f9eeca106725 8934
Kojto 122:f9eeca106725 8935 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
Kojto 122:f9eeca106725 8936 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
Kojto 122:f9eeca106725 8937
Kojto 122:f9eeca106725 8938 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 122:f9eeca106725 8939 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
Kojto 122:f9eeca106725 8940 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 8941 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 8942 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 8943
Kojto 122:f9eeca106725 8944 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
Kojto 122:f9eeca106725 8945 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
Kojto 122:f9eeca106725 8946 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
Kojto 122:f9eeca106725 8947
Kojto 122:f9eeca106725 8948 /******************** Bit definition for OTG register ********************/
Kojto 122:f9eeca106725 8949
Kojto 122:f9eeca106725 8950 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
Kojto 122:f9eeca106725 8951 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 8952 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 8953 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 8954 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 8955 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
Kojto 122:f9eeca106725 8956
Kojto 122:f9eeca106725 8957 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
Kojto 122:f9eeca106725 8958 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 8959 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8960
Kojto 122:f9eeca106725 8961 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
Kojto 122:f9eeca106725 8962 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 8963 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8964 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 8965 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 8966
Kojto 122:f9eeca106725 8967 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
Kojto 122:f9eeca106725 8968 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 8969 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 8970 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 8971 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 8972
Kojto 122:f9eeca106725 8973 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
Kojto 122:f9eeca106725 8974 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 8975 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8976 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 8977 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 8978
Kojto 122:f9eeca106725 8979 /******************** Bit definition for OTG register ********************/
Kojto 122:f9eeca106725 8980
Kojto 122:f9eeca106725 8981 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
Kojto 122:f9eeca106725 8982 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 8983 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 8984 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 8985 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 8986 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
Kojto 122:f9eeca106725 8987
Kojto 122:f9eeca106725 8988 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
Kojto 122:f9eeca106725 8989 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
Kojto 122:f9eeca106725 8990 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8991
Kojto 122:f9eeca106725 8992 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
Kojto 122:f9eeca106725 8993 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 8994 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 8995 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 8996 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 8997
Kojto 122:f9eeca106725 8998 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
Kojto 122:f9eeca106725 8999 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 9000 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 9001 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 9002 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 9003
Kojto 122:f9eeca106725 9004 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
Kojto 122:f9eeca106725 9005 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9006 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9007 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9008 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9009
Kojto 122:f9eeca106725 9010 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
Kojto 122:f9eeca106725 9011 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
Kojto 122:f9eeca106725 9012
Kojto 122:f9eeca106725 9013 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
Kojto 122:f9eeca106725 9014 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
Kojto 122:f9eeca106725 9015
Kojto 122:f9eeca106725 9016 /******************** Bit definition for OTG register ********************/
Kojto 122:f9eeca106725 9017 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
Kojto 122:f9eeca106725 9018 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
Kojto 122:f9eeca106725 9019 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
Kojto 122:f9eeca106725 9020 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
Kojto 122:f9eeca106725 9021
Kojto 122:f9eeca106725 9022 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
Kojto 122:f9eeca106725 9023 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
Kojto 122:f9eeca106725 9024
Kojto 122:f9eeca106725 9025 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
Kojto 122:f9eeca106725 9026 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
Kojto 122:f9eeca106725 9027
Kojto 122:f9eeca106725 9028 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
Kojto 122:f9eeca106725 9029 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9030 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9031 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9032 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9033 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
Kojto 122:f9eeca106725 9034 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
Kojto 122:f9eeca106725 9035 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
Kojto 122:f9eeca106725 9036 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
Kojto 122:f9eeca106725 9037
Kojto 122:f9eeca106725 9038 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
Kojto 122:f9eeca106725 9039 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9040 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9041 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9042 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9043 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 9044 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 9045 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 9046
Kojto 122:f9eeca106725 9047 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
Kojto 122:f9eeca106725 9048 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
Kojto 122:f9eeca106725 9049 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
Kojto 122:f9eeca106725 9050
Kojto 122:f9eeca106725 9051 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
Kojto 122:f9eeca106725 9052 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 9053 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 9054 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
Kojto 122:f9eeca106725 9055 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
Kojto 122:f9eeca106725 9056 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
Kojto 122:f9eeca106725 9057 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
Kojto 122:f9eeca106725 9058 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
Kojto 122:f9eeca106725 9059 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
Kojto 122:f9eeca106725 9060 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
Kojto 122:f9eeca106725 9061 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
Kojto 122:f9eeca106725 9062
Kojto 122:f9eeca106725 9063 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
Kojto 122:f9eeca106725 9064 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9065 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9066 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9067 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9068 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
Kojto 122:f9eeca106725 9069 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
Kojto 122:f9eeca106725 9070 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
Kojto 122:f9eeca106725 9071 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
Kojto 122:f9eeca106725 9072 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
Kojto 122:f9eeca106725 9073 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
Kojto 122:f9eeca106725 9074
Kojto 122:f9eeca106725 9075 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
Kojto 122:f9eeca106725 9076 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
Kojto 122:f9eeca106725 9077
Kojto 122:f9eeca106725 9078 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
Kojto 122:f9eeca106725 9079 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
Kojto 122:f9eeca106725 9080 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
Kojto 122:f9eeca106725 9081
Kojto 122:f9eeca106725 9082 /******************** Bit definition for USB_OTG_GCCFG register ********************/
Kojto 122:f9eeca106725 9083 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
Kojto 122:f9eeca106725 9084 #define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
Kojto 122:f9eeca106725 9085
Kojto 122:f9eeca106725 9086 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
Kojto 122:f9eeca106725 9087 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U /*!< ADP module enable */
Kojto 122:f9eeca106725 9088 #define USB_OTG_GPWRDN_ADPIF 0x00800000U /*!< ADP Interrupt flag */
Kojto 122:f9eeca106725 9089
Kojto 122:f9eeca106725 9090 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
Kojto 122:f9eeca106725 9091 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
Kojto 122:f9eeca106725 9092 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
Kojto 122:f9eeca106725 9093
Kojto 122:f9eeca106725 9094 /******************** Bit definition for USB_OTG_CID register ********************/
Kojto 122:f9eeca106725 9095 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
Kojto 122:f9eeca106725 9096
Kojto 122:f9eeca106725 9097 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
Kojto 122:f9eeca106725 9098 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
Kojto 122:f9eeca106725 9099 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
Kojto 122:f9eeca106725 9100 #define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
Kojto 122:f9eeca106725 9101 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 122:f9eeca106725 9102 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
Kojto 122:f9eeca106725 9103 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
Kojto 122:f9eeca106725 9104 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
Kojto 122:f9eeca106725 9105 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
Kojto 122:f9eeca106725 9106 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
Kojto 122:f9eeca106725 9107 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
Kojto 122:f9eeca106725 9108 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
Kojto 122:f9eeca106725 9109 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
Kojto 122:f9eeca106725 9110 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
Kojto 122:f9eeca106725 9111 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
Kojto 122:f9eeca106725 9112 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
Kojto 122:f9eeca106725 9113
Kojto 122:f9eeca106725 9114 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
Kojto 122:f9eeca106725 9115 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 9116 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 9117 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 122:f9eeca106725 9118 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 9119 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 9120 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 9121 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
Kojto 122:f9eeca106725 9122 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 9123 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
Kojto 122:f9eeca106725 9124
Kojto 122:f9eeca106725 9125 /******************** Bit definition for USB_OTG_HPRT register ********************/
Kojto 122:f9eeca106725 9126 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
Kojto 122:f9eeca106725 9127 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
Kojto 122:f9eeca106725 9128 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
Kojto 122:f9eeca106725 9129 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
Kojto 122:f9eeca106725 9130 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
Kojto 122:f9eeca106725 9131 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
Kojto 122:f9eeca106725 9132 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
Kojto 122:f9eeca106725 9133 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
Kojto 122:f9eeca106725 9134 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
Kojto 122:f9eeca106725 9135
Kojto 122:f9eeca106725 9136 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
Kojto 122:f9eeca106725 9137 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
Kojto 122:f9eeca106725 9138 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
Kojto 122:f9eeca106725 9139 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
Kojto 122:f9eeca106725 9140
Kojto 122:f9eeca106725 9141 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
Kojto 122:f9eeca106725 9142 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9143 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9144 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9145 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9146
Kojto 122:f9eeca106725 9147 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
Kojto 122:f9eeca106725 9148 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9149 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9150
Kojto 122:f9eeca106725 9151 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
Kojto 122:f9eeca106725 9152 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
Kojto 122:f9eeca106725 9153 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
Kojto 122:f9eeca106725 9154 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
Kojto 122:f9eeca106725 9155 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
Kojto 122:f9eeca106725 9156 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
Kojto 122:f9eeca106725 9157 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
Kojto 122:f9eeca106725 9158 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
Kojto 122:f9eeca106725 9159 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
Kojto 122:f9eeca106725 9160 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
Kojto 122:f9eeca106725 9161 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
Kojto 122:f9eeca106725 9162 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
Kojto 122:f9eeca106725 9163
Kojto 122:f9eeca106725 9164 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
Kojto 122:f9eeca106725 9165 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
Kojto 122:f9eeca106725 9166 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
Kojto 122:f9eeca106725 9167
Kojto 122:f9eeca106725 9168 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
Kojto 122:f9eeca106725 9169 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
Kojto 122:f9eeca106725 9170 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
Kojto 122:f9eeca106725 9171 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
Kojto 122:f9eeca106725 9172 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
Kojto 122:f9eeca106725 9173
Kojto 122:f9eeca106725 9174 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 9175 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9176 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9177 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
Kojto 122:f9eeca106725 9178
Kojto 122:f9eeca106725 9179 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
Kojto 122:f9eeca106725 9180 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9181 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9182 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9183 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9184 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
Kojto 122:f9eeca106725 9185 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
Kojto 122:f9eeca106725 9186 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
Kojto 122:f9eeca106725 9187 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
Kojto 122:f9eeca106725 9188 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
Kojto 122:f9eeca106725 9189 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
Kojto 122:f9eeca106725 9190
Kojto 122:f9eeca106725 9191 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
Kojto 122:f9eeca106725 9192 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
Kojto 122:f9eeca106725 9193
Kojto 122:f9eeca106725 9194 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
Kojto 122:f9eeca106725 9195 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
Kojto 122:f9eeca106725 9196 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9197 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9198 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9199 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
Kojto 122:f9eeca106725 9200 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
Kojto 122:f9eeca106725 9201
Kojto 122:f9eeca106725 9202 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 9203 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9204 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9205
Kojto 122:f9eeca106725 9206 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
Kojto 122:f9eeca106725 9207 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9208 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9209
Kojto 122:f9eeca106725 9210 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
Kojto 122:f9eeca106725 9211 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9212 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9213 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9214 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9215 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
Kojto 122:f9eeca106725 9216 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
Kojto 122:f9eeca106725 9217 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
Kojto 122:f9eeca106725 9218 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
Kojto 122:f9eeca106725 9219 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
Kojto 122:f9eeca106725 9220 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
Kojto 122:f9eeca106725 9221
Kojto 122:f9eeca106725 9222 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
Kojto 122:f9eeca106725 9223
Kojto 122:f9eeca106725 9224 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
Kojto 122:f9eeca106725 9225 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 9226 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 9227 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
Kojto 122:f9eeca106725 9228 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
Kojto 122:f9eeca106725 9229 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
Kojto 122:f9eeca106725 9230 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
Kojto 122:f9eeca106725 9231 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
Kojto 122:f9eeca106725 9232
Kojto 122:f9eeca106725 9233 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
Kojto 122:f9eeca106725 9234 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
Kojto 122:f9eeca106725 9235 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
Kojto 122:f9eeca106725 9236 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
Kojto 122:f9eeca106725 9237 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
Kojto 122:f9eeca106725 9238 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
Kojto 122:f9eeca106725 9239 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
Kojto 122:f9eeca106725 9240 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
Kojto 122:f9eeca106725 9241
Kojto 122:f9eeca106725 9242 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
Kojto 122:f9eeca106725 9243 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9244 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9245 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
Kojto 122:f9eeca106725 9246 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
Kojto 122:f9eeca106725 9247
Kojto 122:f9eeca106725 9248 /******************** Bit definition for USB_OTG_HCINT register ********************/
Kojto 122:f9eeca106725 9249 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
Kojto 122:f9eeca106725 9250 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
Kojto 122:f9eeca106725 9251 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
Kojto 122:f9eeca106725 9252 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
Kojto 122:f9eeca106725 9253 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
Kojto 122:f9eeca106725 9254 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
Kojto 122:f9eeca106725 9255 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
Kojto 122:f9eeca106725 9256 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
Kojto 122:f9eeca106725 9257 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
Kojto 122:f9eeca106725 9258 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
Kojto 122:f9eeca106725 9259 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
Kojto 122:f9eeca106725 9260
Kojto 122:f9eeca106725 9261 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
Kojto 122:f9eeca106725 9262 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
Kojto 122:f9eeca106725 9263 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
Kojto 122:f9eeca106725 9264 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
Kojto 122:f9eeca106725 9265 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
Kojto 122:f9eeca106725 9266 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
Kojto 122:f9eeca106725 9267 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
Kojto 122:f9eeca106725 9268 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
Kojto 122:f9eeca106725 9269 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
Kojto 122:f9eeca106725 9270 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
Kojto 122:f9eeca106725 9271 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
Kojto 122:f9eeca106725 9272 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
Kojto 122:f9eeca106725 9273
Kojto 122:f9eeca106725 9274 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
Kojto 122:f9eeca106725 9275 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
Kojto 122:f9eeca106725 9276 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
Kojto 122:f9eeca106725 9277 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
Kojto 122:f9eeca106725 9278 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
Kojto 122:f9eeca106725 9279 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
Kojto 122:f9eeca106725 9280 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
Kojto 122:f9eeca106725 9281 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
Kojto 122:f9eeca106725 9282 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
Kojto 122:f9eeca106725 9283 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
Kojto 122:f9eeca106725 9284 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
Kojto 122:f9eeca106725 9285 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
Kojto 122:f9eeca106725 9286
Kojto 122:f9eeca106725 9287 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
Kojto 122:f9eeca106725 9288
Kojto 122:f9eeca106725 9289 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 9290 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 9291 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
Kojto 122:f9eeca106725 9292 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
Kojto 122:f9eeca106725 9293 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 9294 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 9295 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
Kojto 122:f9eeca106725 9296 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
Kojto 122:f9eeca106725 9297 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9298 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9299
Kojto 122:f9eeca106725 9300 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
Kojto 122:f9eeca106725 9301 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
Kojto 122:f9eeca106725 9302
Kojto 122:f9eeca106725 9303 /******************** Bit definition for USB_OTG_HCDMA register ********************/
Kojto 122:f9eeca106725 9304 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
Kojto 122:f9eeca106725 9305
Kojto 122:f9eeca106725 9306 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
Kojto 122:f9eeca106725 9307 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
Kojto 122:f9eeca106725 9308
Kojto 122:f9eeca106725 9309 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
Kojto 122:f9eeca106725 9310 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 122:f9eeca106725 9311 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
Kojto 122:f9eeca106725 9312
Kojto 122:f9eeca106725 9313 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
Kojto 122:f9eeca106725 9314 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 122:f9eeca106725 9315 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
Kojto 122:f9eeca106725 9316 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
Kojto 122:f9eeca106725 9317 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
Kojto 122:f9eeca106725 9318 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
Kojto 122:f9eeca106725 9319 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
Kojto 122:f9eeca106725 9320 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9321 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9322 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
Kojto 122:f9eeca106725 9323 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
Kojto 122:f9eeca106725 9324 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
Kojto 122:f9eeca106725 9325 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
Kojto 122:f9eeca106725 9326 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
Kojto 122:f9eeca106725 9327 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
Kojto 122:f9eeca106725 9328
Kojto 122:f9eeca106725 9329 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
Kojto 122:f9eeca106725 9330 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
Kojto 122:f9eeca106725 9331 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
Kojto 122:f9eeca106725 9332 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
Kojto 122:f9eeca106725 9333 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
Kojto 122:f9eeca106725 9334 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
Kojto 122:f9eeca106725 9335 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
Kojto 122:f9eeca106725 9336 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
Kojto 122:f9eeca106725 9337
Kojto 122:f9eeca106725 9338 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
Kojto 122:f9eeca106725 9339 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
Kojto 122:f9eeca106725 9340 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
Kojto 122:f9eeca106725 9341
Kojto 122:f9eeca106725 9342 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
Kojto 122:f9eeca106725 9343 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9344 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9345
Kojto 122:f9eeca106725 9346 /******************** Bit definition for PCGCCTL register ********************/
Kojto 122:f9eeca106725 9347 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
Kojto 122:f9eeca106725 9348 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
Kojto 122:f9eeca106725 9349 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
Kojto 122:f9eeca106725 9350
Kojto 122:f9eeca106725 9351 /******************************************************************************/
Kojto 122:f9eeca106725 9352 /* */
Kojto 122:f9eeca106725 9353 /* JPEG Encoder/Decoder */
Kojto 122:f9eeca106725 9354 /* */
Kojto 122:f9eeca106725 9355 /******************************************************************************/
Kojto 122:f9eeca106725 9356 /******************** Bit definition for CONFR0 register ********************/
Kojto 122:f9eeca106725 9357 #define JPEG_CONFR0_START 0x00000001U /*!<Start/Stop bit */
Kojto 122:f9eeca106725 9358
Kojto 122:f9eeca106725 9359 /******************** Bit definition for CONFR1 register *******************/
Kojto 122:f9eeca106725 9360 #define JPEG_CONFR1_NF 0x00000003U /*!<Number of color components */
Kojto 122:f9eeca106725 9361 #define JPEG_CONFR1_NF_0 0x00000001U /*!<Bit 0 */
Kojto 122:f9eeca106725 9362 #define JPEG_CONFR1_NF_1 0x00000002U /*!<Bit 1 */
Kojto 122:f9eeca106725 9363 #define JPEG_CONFR1_RE 0x00000004U /*!<Restart maker Enable */
Kojto 122:f9eeca106725 9364 #define JPEG_CONFR1_DE 0x00000008U /*!<Decoding Enable */
Kojto 122:f9eeca106725 9365 #define JPEG_CONFR1_COLORSPACE 0x00000030U /*!<Color Space */
Kojto 122:f9eeca106725 9366 #define JPEG_CONFR1_COLORSPACE_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 9367 #define JPEG_CONFR1_COLORSPACE_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 9368 #define JPEG_CONFR1_NS 0x000000C0U /*!<Number of components for Scan */
Kojto 122:f9eeca106725 9369 #define JPEG_CONFR1_NS_0 0x00000040U /*!<Bit 0 */
Kojto 122:f9eeca106725 9370 #define JPEG_CONFR1_NS_1 0x00000080U /*!<Bit 1 */
Kojto 122:f9eeca106725 9371 #define JPEG_CONFR1_HDR 0x00000100U /*!<Header Processing On/Off */
Kojto 122:f9eeca106725 9372 #define JPEG_CONFR1_YSIZE 0xFFFF0000U /*!<Number of lines in source image */
Kojto 122:f9eeca106725 9373
Kojto 122:f9eeca106725 9374 /******************** Bit definition for CONFR2 register *******************/
Kojto 122:f9eeca106725 9375 #define JPEG_CONFR2_NMCU 0x03FFFFFFU /*!<Number of MCU units minus 1 to encode */
Kojto 122:f9eeca106725 9376
Kojto 122:f9eeca106725 9377 /******************** Bit definition for CONFR3 register *******************/
Kojto 122:f9eeca106725 9378 #define JPEG_CONFR3_NRST 0x0000FFFFU /*!<Number of MCU between two restart makers minus 1 */
Kojto 122:f9eeca106725 9379 #define JPEG_CONFR3_XSIZE 0xFFFF0000U /*!<Number of pixels per line */
Kojto 122:f9eeca106725 9380
Kojto 122:f9eeca106725 9381 /******************** Bit definition for CONFR4 register *******************/
Kojto 122:f9eeca106725 9382 #define JPEG_CONFR4_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
Kojto 122:f9eeca106725 9383 #define JPEG_CONFR4_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
Kojto 122:f9eeca106725 9384 #define JPEG_CONFR4_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
Kojto 122:f9eeca106725 9385 #define JPEG_CONFR4_QT_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 9386 #define JPEG_CONFR4_QT_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 9387 #define JPEG_CONFR4_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
Kojto 122:f9eeca106725 9388 #define JPEG_CONFR4_NB_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 9389 #define JPEG_CONFR4_NB_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 9390 #define JPEG_CONFR4_NB_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 9391 #define JPEG_CONFR4_NB_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 9392 #define JPEG_CONFR4_VSF 0x00000F00U /*!<Vertical sampling factor for component 1 */
Kojto 122:f9eeca106725 9393 #define JPEG_CONFR4_VSF_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 9394 #define JPEG_CONFR4_VSF_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 9395 #define JPEG_CONFR4_VSF_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 9396 #define JPEG_CONFR4_VSF_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 9397 #define JPEG_CONFR4_HSF 0x0000F000U /*!<Horizontal sampling factor for component 1 */
Kojto 122:f9eeca106725 9398 #define JPEG_CONFR4_HSF_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9399 #define JPEG_CONFR4_HSF_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9400 #define JPEG_CONFR4_HSF_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9401 #define JPEG_CONFR4_HSF_3 0x00008000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9402
Kojto 122:f9eeca106725 9403 /******************** Bit definition for CONFR5 register *******************/
Kojto 122:f9eeca106725 9404 #define JPEG_CONFR5_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
Kojto 122:f9eeca106725 9405 #define JPEG_CONFR5_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
Kojto 122:f9eeca106725 9406 #define JPEG_CONFR5_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
Kojto 122:f9eeca106725 9407 #define JPEG_CONFR5_QT_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 9408 #define JPEG_CONFR5_QT_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 9409 #define JPEG_CONFR5_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
Kojto 122:f9eeca106725 9410 #define JPEG_CONFR5_NB_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 9411 #define JPEG_CONFR5_NB_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 9412 #define JPEG_CONFR5_NB_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 9413 #define JPEG_CONFR5_NB_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 9414 #define JPEG_CONFR5_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
Kojto 122:f9eeca106725 9415 #define JPEG_CONFR5_VSF_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 9416 #define JPEG_CONFR5_VSF_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 9417 #define JPEG_CONFR5_VSF_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 9418 #define JPEG_CONFR5_VSF_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 9419 #define JPEG_CONFR5_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
Kojto 122:f9eeca106725 9420 #define JPEG_CONFR5_HSF_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9421 #define JPEG_CONFR5_HSF_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9422 #define JPEG_CONFR5_HSF_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9423 #define JPEG_CONFR5_HSF_3 0x00008000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9424
Kojto 122:f9eeca106725 9425 /******************** Bit definition for CONFR6 register *******************/
Kojto 122:f9eeca106725 9426 #define JPEG_CONFR6_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
Kojto 122:f9eeca106725 9427 #define JPEG_CONFR6_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
Kojto 122:f9eeca106725 9428 #define JPEG_CONFR6_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
Kojto 122:f9eeca106725 9429 #define JPEG_CONFR6_QT_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 9430 #define JPEG_CONFR6_QT_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 9431 #define JPEG_CONFR6_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
Kojto 122:f9eeca106725 9432 #define JPEG_CONFR6_NB_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 9433 #define JPEG_CONFR6_NB_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 9434 #define JPEG_CONFR6_NB_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 9435 #define JPEG_CONFR6_NB_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 9436 #define JPEG_CONFR6_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
Kojto 122:f9eeca106725 9437 #define JPEG_CONFR6_VSF_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 9438 #define JPEG_CONFR6_VSF_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 9439 #define JPEG_CONFR6_VSF_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 9440 #define JPEG_CONFR6_VSF_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 9441 #define JPEG_CONFR6_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
Kojto 122:f9eeca106725 9442 #define JPEG_CONFR6_HSF_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9443 #define JPEG_CONFR6_HSF_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9444 #define JPEG_CONFR6_HSF_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9445 #define JPEG_CONFR6_HSF_3 0x00008000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9446
Kojto 122:f9eeca106725 9447 /******************** Bit definition for CONFR7 register *******************/
Kojto 122:f9eeca106725 9448 #define JPEG_CONFR7_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
Kojto 122:f9eeca106725 9449 #define JPEG_CONFR7_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
Kojto 122:f9eeca106725 9450 #define JPEG_CONFR7_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
Kojto 122:f9eeca106725 9451 #define JPEG_CONFR7_QT_0 0x00000004U /*!<Bit 0 */
Kojto 122:f9eeca106725 9452 #define JPEG_CONFR7_QT_1 0x00000008U /*!<Bit 1 */
Kojto 122:f9eeca106725 9453 #define JPEG_CONFR7_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
Kojto 122:f9eeca106725 9454 #define JPEG_CONFR7_NB_0 0x00000010U /*!<Bit 0 */
Kojto 122:f9eeca106725 9455 #define JPEG_CONFR7_NB_1 0x00000020U /*!<Bit 1 */
Kojto 122:f9eeca106725 9456 #define JPEG_CONFR7_NB_2 0x00000040U /*!<Bit 2 */
Kojto 122:f9eeca106725 9457 #define JPEG_CONFR7_NB_3 0x00000080U /*!<Bit 3 */
Kojto 122:f9eeca106725 9458 #define JPEG_CONFR7_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
Kojto 122:f9eeca106725 9459 #define JPEG_CONFR7_VSF_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 9460 #define JPEG_CONFR7_VSF_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 9461 #define JPEG_CONFR7_VSF_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 9462 #define JPEG_CONFR7_VSF_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 9463 #define JPEG_CONFR7_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
Kojto 122:f9eeca106725 9464 #define JPEG_CONFR7_HSF_0 0x00001000U /*!<Bit 0 */
Kojto 122:f9eeca106725 9465 #define JPEG_CONFR7_HSF_1 0x00002000U /*!<Bit 1 */
Kojto 122:f9eeca106725 9466 #define JPEG_CONFR7_HSF_2 0x00004000U /*!<Bit 2 */
Kojto 122:f9eeca106725 9467 #define JPEG_CONFR7_HSF_3 0x00008000U /*!<Bit 3 */
Kojto 122:f9eeca106725 9468
Kojto 122:f9eeca106725 9469 /******************** Bit definition for CR register *******************/
Kojto 122:f9eeca106725 9470 #define JPEG_CR_JCEN 0x00000001U /*!<Enable the JPEG Codec Core */
Kojto 122:f9eeca106725 9471 #define JPEG_CR_IFTIE 0x00000002U /*!<Input FIFO Threshold Interrupt Enable */
Kojto 122:f9eeca106725 9472 #define JPEG_CR_IFNFIE 0x00000004U /*!<Input FIFO Not Full Interrupt Enable */
Kojto 122:f9eeca106725 9473 #define JPEG_CR_OFTIE 0x00000008U /*!<Output FIFO Threshold Interrupt Enable */
Kojto 122:f9eeca106725 9474 #define JPEG_CR_OFNEIE 0x00000010U /*!<Output FIFO Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 9475 #define JPEG_CR_EOCIE 0x00000020U /*!<End of Conversion Interrupt Enable */
Kojto 122:f9eeca106725 9476 #define JPEG_CR_HPDIE 0x00000040U /*!<Header Parsing Done Interrupt Enable */
Kojto 122:f9eeca106725 9477 #define JPEG_CR_IDMAEN 0x00000800U /*!<Enable the DMA request generation for the input FIFO */
Kojto 122:f9eeca106725 9478 #define JPEG_CR_ODMAEN 0x00001000U /*!<Enable the DMA request generation for the output FIFO */
Kojto 122:f9eeca106725 9479 #define JPEG_CR_IFF 0x00002000U /*!<Flush the input FIFO */
Kojto 122:f9eeca106725 9480 #define JPEG_CR_OFF 0x00004000U /*!<Flush the output FIFO */
Kojto 122:f9eeca106725 9481
Kojto 122:f9eeca106725 9482 /******************** Bit definition for SR register *******************/
Kojto 122:f9eeca106725 9483 #define JPEG_SR_IFTF 0x00000002U /*!<Input FIFO is not full and is bellow its threshold flag */
Kojto 122:f9eeca106725 9484 #define JPEG_SR_IFNFF 0x00000004U /*!<Input FIFO Not Full Flag, a data can be written */
Kojto 122:f9eeca106725 9485 #define JPEG_SR_OFTF 0x00000008U /*!<Output FIFO is not empty and has reach its threshold */
Kojto 122:f9eeca106725 9486 #define JPEG_SR_OFNEF 0x000000010U /*!<Output FIFO is not empty, a data is available */
Kojto 122:f9eeca106725 9487 #define JPEG_SR_EOCF 0x000000020U /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
Kojto 122:f9eeca106725 9488 #define JPEG_SR_HPDF 0x000000040U /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
Kojto 122:f9eeca106725 9489 #define JPEG_SR_COF 0x000000080U /*!<JPEG Codec operation on going flag */
Kojto 122:f9eeca106725 9490
Kojto 122:f9eeca106725 9491 /******************** Bit definition for CFR register *******************/
Kojto 122:f9eeca106725 9492 #define JPEG_CFR_CEOCF 0x00000020U /*!<Clear End of Conversion Flag */
Kojto 122:f9eeca106725 9493 #define JPEG_CFR_CHPDF 0x00000040U /*!<Clear Header Parsing Done Flag */
Kojto 122:f9eeca106725 9494
Kojto 122:f9eeca106725 9495 /******************** Bit definition for DIR register ********************/
Kojto 122:f9eeca106725 9496 #define JPEG_DIR_DATAIN 0xFFFFFFFFU /*!<Data Input FIFO */
Kojto 122:f9eeca106725 9497
Kojto 122:f9eeca106725 9498 /******************** Bit definition for DOR register ********************/
Kojto 122:f9eeca106725 9499 #define JPEG_DOR_DATAOUT 0xFFFFFFFFU /*!<Data Output FIFO */
Kojto 122:f9eeca106725 9500
Kojto 122:f9eeca106725 9501 /******************************************************************************/
Kojto 122:f9eeca106725 9502 /* */
Kojto 122:f9eeca106725 9503 /* MDIOS */
Kojto 122:f9eeca106725 9504 /* */
Kojto 122:f9eeca106725 9505 /******************************************************************************/
Kojto 122:f9eeca106725 9506 /******************** Bit definition for MDIOS_CR register *******************/
Kojto 122:f9eeca106725 9507 #define MDIOS_CR_EN 0x00000001U /*!<Peripheral enable */
Kojto 122:f9eeca106725 9508 #define MDIOS_CR_WRIE 0x00000002U /*!<Register write interrupt enable */
Kojto 122:f9eeca106725 9509 #define MDIOS_CR_RDIE 0x00000004U /*!<Register Read Interrupt Enable */
Kojto 122:f9eeca106725 9510 #define MDIOS_CR_EIE 0x00000008U /*!<Error interrupt enable */
Kojto 122:f9eeca106725 9511 #define MDIOS_CR_DPC 0x00000080U /*!<Disable Preamble Check */
Kojto 122:f9eeca106725 9512 #define MDIOS_CR_PORT_ADDRESS 0x00001F00U /*!<PORT_ADDRESS[4:0] bits */
Kojto 122:f9eeca106725 9513 #define MDIOS_CR_PORT_ADDRESS_0 0x00000100U /*!<Bit 0 */
Kojto 122:f9eeca106725 9514 #define MDIOS_CR_PORT_ADDRESS_1 0x00000200U /*!<Bit 1 */
Kojto 122:f9eeca106725 9515 #define MDIOS_CR_PORT_ADDRESS_2 0x00000400U /*!<Bit 2 */
Kojto 122:f9eeca106725 9516 #define MDIOS_CR_PORT_ADDRESS_3 0x00000800U /*!<Bit 3 */
Kojto 122:f9eeca106725 9517 #define MDIOS_CR_PORT_ADDRESS_4 0x00001000U /*!<Bit 4 */
Kojto 122:f9eeca106725 9518
Kojto 122:f9eeca106725 9519 /******************** Bit definition for MDIOS_WRFR register *******************/
Kojto 122:f9eeca106725 9520 #define MDIOS_WRFR_WRF 0xFFFFFFFFU /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
Kojto 122:f9eeca106725 9521
Kojto 122:f9eeca106725 9522 /******************** Bit definition for MDIOS_CWRFR register *******************/
Kojto 122:f9eeca106725 9523 #define MDIOS_CWRFR_CWRF 0xFFFFFFFFU /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
Kojto 122:f9eeca106725 9524
Kojto 122:f9eeca106725 9525 /******************** Bit definition for MDIOS_RDFR register *******************/
Kojto 122:f9eeca106725 9526 #define MDIOS_RDFR_RDF 0xFFFFFFFFU /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
Kojto 122:f9eeca106725 9527
Kojto 122:f9eeca106725 9528 /******************** Bit definition for MDIOS_CRDFR register *******************/
Kojto 122:f9eeca106725 9529 #define MDIOS_CRDFR_CRDF 0xFFFFFFFFU /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
Kojto 122:f9eeca106725 9530
Kojto 122:f9eeca106725 9531 /******************** Bit definition for MDIOS_SR register *******************/
Kojto 122:f9eeca106725 9532 #define MDIOS_SR_PERF 0x00000001U /*!< Preamble error flag */
Kojto 122:f9eeca106725 9533 #define MDIOS_SR_SERF 0x00000002U /*!< Start error flag */
Kojto 122:f9eeca106725 9534 #define MDIOS_SR_TERF 0x00000004U /*!< Turnaround error flag */
Kojto 122:f9eeca106725 9535
Kojto 122:f9eeca106725 9536 /******************** Bit definition for MDIOS_CLRFR register *******************/
Kojto 122:f9eeca106725 9537 #define MDIOS_CLRFR_CPERF 0x00000001U /*!< Clear the preamble error flag */
Kojto 122:f9eeca106725 9538 #define MDIOS_CLRFR_CSERF 0x00000002U /*!< Clear the start error flag */
Kojto 122:f9eeca106725 9539 #define MDIOS_CLRFR_CTERF 0x00000004U /*!< Clear the turnaround error flag */
Kojto 122:f9eeca106725 9540
Kojto 122:f9eeca106725 9541 /**
Kojto 122:f9eeca106725 9542 * @}
Kojto 122:f9eeca106725 9543 */
Kojto 122:f9eeca106725 9544
Kojto 122:f9eeca106725 9545 /**
Kojto 122:f9eeca106725 9546 * @}
Kojto 122:f9eeca106725 9547 */
Kojto 122:f9eeca106725 9548
Kojto 122:f9eeca106725 9549 /** @addtogroup Exported_macros
Kojto 122:f9eeca106725 9550 * @{
Kojto 122:f9eeca106725 9551 */
Kojto 122:f9eeca106725 9552
Kojto 122:f9eeca106725 9553 /******************************* ADC Instances ********************************/
Kojto 122:f9eeca106725 9554 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
Kojto 122:f9eeca106725 9555 ((__INSTANCE__) == ADC2) || \
Kojto 122:f9eeca106725 9556 ((__INSTANCE__) == ADC3))
Kojto 122:f9eeca106725 9557
Kojto 122:f9eeca106725 9558 /******************************* CAN Instances ********************************/
Kojto 122:f9eeca106725 9559 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
Kojto 122:f9eeca106725 9560 ((__INSTANCE__) == CAN2) || \
Kojto 122:f9eeca106725 9561 ((__INSTANCE__) == CAN3))
Kojto 122:f9eeca106725 9562 /******************************* CRC Instances ********************************/
Kojto 122:f9eeca106725 9563 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
Kojto 122:f9eeca106725 9564
Kojto 122:f9eeca106725 9565 /******************************* DAC Instances ********************************/
Kojto 122:f9eeca106725 9566 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
Kojto 122:f9eeca106725 9567
Kojto 122:f9eeca106725 9568 /******************************* DCMI Instances *******************************/
Kojto 122:f9eeca106725 9569 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
Kojto 122:f9eeca106725 9570
Kojto 122:f9eeca106725 9571 /****************************** DFSDM Instances *******************************/
Kojto 122:f9eeca106725 9572 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
Kojto 122:f9eeca106725 9573 ((INSTANCE) == DFSDM1_Filter1) || \
Kojto 122:f9eeca106725 9574 ((INSTANCE) == DFSDM1_Filter2) || \
Kojto 122:f9eeca106725 9575 ((INSTANCE) == DFSDM1_Filter3))
Kojto 122:f9eeca106725 9576
Kojto 122:f9eeca106725 9577 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
Kojto 122:f9eeca106725 9578 ((INSTANCE) == DFSDM1_Channel1) || \
Kojto 122:f9eeca106725 9579 ((INSTANCE) == DFSDM1_Channel2) || \
Kojto 122:f9eeca106725 9580 ((INSTANCE) == DFSDM1_Channel3) || \
Kojto 122:f9eeca106725 9581 ((INSTANCE) == DFSDM1_Channel4) || \
Kojto 122:f9eeca106725 9582 ((INSTANCE) == DFSDM1_Channel5) || \
Kojto 122:f9eeca106725 9583 ((INSTANCE) == DFSDM1_Channel6) || \
Kojto 122:f9eeca106725 9584 ((INSTANCE) == DFSDM1_Channel7))
Kojto 122:f9eeca106725 9585
Kojto 122:f9eeca106725 9586 /******************************* DMA2D Instances *******************************/
Kojto 122:f9eeca106725 9587 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
Kojto 122:f9eeca106725 9588
Kojto 122:f9eeca106725 9589 /******************************** DMA Instances *******************************/
Kojto 122:f9eeca106725 9590 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
Kojto 122:f9eeca106725 9591 ((__INSTANCE__) == DMA1_Stream1) || \
Kojto 122:f9eeca106725 9592 ((__INSTANCE__) == DMA1_Stream2) || \
Kojto 122:f9eeca106725 9593 ((__INSTANCE__) == DMA1_Stream3) || \
Kojto 122:f9eeca106725 9594 ((__INSTANCE__) == DMA1_Stream4) || \
Kojto 122:f9eeca106725 9595 ((__INSTANCE__) == DMA1_Stream5) || \
Kojto 122:f9eeca106725 9596 ((__INSTANCE__) == DMA1_Stream6) || \
Kojto 122:f9eeca106725 9597 ((__INSTANCE__) == DMA1_Stream7) || \
Kojto 122:f9eeca106725 9598 ((__INSTANCE__) == DMA2_Stream0) || \
Kojto 122:f9eeca106725 9599 ((__INSTANCE__) == DMA2_Stream1) || \
Kojto 122:f9eeca106725 9600 ((__INSTANCE__) == DMA2_Stream2) || \
Kojto 122:f9eeca106725 9601 ((__INSTANCE__) == DMA2_Stream3) || \
Kojto 122:f9eeca106725 9602 ((__INSTANCE__) == DMA2_Stream4) || \
Kojto 122:f9eeca106725 9603 ((__INSTANCE__) == DMA2_Stream5) || \
Kojto 122:f9eeca106725 9604 ((__INSTANCE__) == DMA2_Stream6) || \
Kojto 122:f9eeca106725 9605 ((__INSTANCE__) == DMA2_Stream7))
Kojto 122:f9eeca106725 9606
Kojto 122:f9eeca106725 9607 /******************************* GPIO Instances *******************************/
Kojto 122:f9eeca106725 9608 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
Kojto 122:f9eeca106725 9609 ((__INSTANCE__) == GPIOB) || \
Kojto 122:f9eeca106725 9610 ((__INSTANCE__) == GPIOC) || \
Kojto 122:f9eeca106725 9611 ((__INSTANCE__) == GPIOD) || \
Kojto 122:f9eeca106725 9612 ((__INSTANCE__) == GPIOE) || \
Kojto 122:f9eeca106725 9613 ((__INSTANCE__) == GPIOF) || \
Kojto 122:f9eeca106725 9614 ((__INSTANCE__) == GPIOG) || \
Kojto 122:f9eeca106725 9615 ((__INSTANCE__) == GPIOH) || \
Kojto 122:f9eeca106725 9616 ((__INSTANCE__) == GPIOI) || \
Kojto 122:f9eeca106725 9617 ((__INSTANCE__) == GPIOJ) || \
Kojto 122:f9eeca106725 9618 ((__INSTANCE__) == GPIOK))
Kojto 122:f9eeca106725 9619
Kojto 122:f9eeca106725 9620 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
Kojto 122:f9eeca106725 9621 ((__INSTANCE__) == GPIOB) || \
Kojto 122:f9eeca106725 9622 ((__INSTANCE__) == GPIOC) || \
Kojto 122:f9eeca106725 9623 ((__INSTANCE__) == GPIOD) || \
Kojto 122:f9eeca106725 9624 ((__INSTANCE__) == GPIOE) || \
Kojto 122:f9eeca106725 9625 ((__INSTANCE__) == GPIOF) || \
Kojto 122:f9eeca106725 9626 ((__INSTANCE__) == GPIOG) || \
Kojto 122:f9eeca106725 9627 ((__INSTANCE__) == GPIOH) || \
Kojto 122:f9eeca106725 9628 ((__INSTANCE__) == GPIOI) || \
Kojto 122:f9eeca106725 9629 ((__INSTANCE__) == GPIOJ) || \
Kojto 122:f9eeca106725 9630 ((__INSTANCE__) == GPIOK))
Kojto 122:f9eeca106725 9631
Kojto 122:f9eeca106725 9632 /****************************** CEC Instances *********************************/
Kojto 122:f9eeca106725 9633 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
Kojto 122:f9eeca106725 9634
Kojto 122:f9eeca106725 9635 /****************************** QSPI Instances *********************************/
Kojto 122:f9eeca106725 9636 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
Kojto 122:f9eeca106725 9637
Kojto 122:f9eeca106725 9638
Kojto 122:f9eeca106725 9639 /******************************** I2C Instances *******************************/
Kojto 122:f9eeca106725 9640 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
Kojto 122:f9eeca106725 9641 ((__INSTANCE__) == I2C2) || \
Kojto 122:f9eeca106725 9642 ((__INSTANCE__) == I2C3) || \
Kojto 122:f9eeca106725 9643 ((__INSTANCE__) == I2C4))
Kojto 122:f9eeca106725 9644
Kojto 122:f9eeca106725 9645 /******************************** I2S Instances *******************************/
Kojto 122:f9eeca106725 9646 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
Kojto 122:f9eeca106725 9647 ((__INSTANCE__) == SPI2) || \
Kojto 122:f9eeca106725 9648 ((__INSTANCE__) == SPI3))
Kojto 122:f9eeca106725 9649
Kojto 122:f9eeca106725 9650 /******************************* LPTIM Instances ********************************/
Kojto 122:f9eeca106725 9651 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
Kojto 122:f9eeca106725 9652
Kojto 122:f9eeca106725 9653 /****************************** LTDC Instances ********************************/
Kojto 122:f9eeca106725 9654 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
Kojto 122:f9eeca106725 9655
Kojto 122:f9eeca106725 9656 /****************************** MDIOS Instances ********************************/
Kojto 122:f9eeca106725 9657 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
Kojto 122:f9eeca106725 9658
Kojto 122:f9eeca106725 9659 /****************************** MDIOS Instances ********************************/
Kojto 122:f9eeca106725 9660 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
Kojto 122:f9eeca106725 9661
Kojto 122:f9eeca106725 9662 /******************************* RNG Instances ********************************/
Kojto 122:f9eeca106725 9663 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
Kojto 122:f9eeca106725 9664
Kojto 122:f9eeca106725 9665 /****************************** RTC Instances *********************************/
Kojto 122:f9eeca106725 9666 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
Kojto 122:f9eeca106725 9667
Kojto 122:f9eeca106725 9668 /******************************* SAI Instances ********************************/
Kojto 122:f9eeca106725 9669 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
Kojto 122:f9eeca106725 9670 ((__PERIPH__) == SAI1_Block_B) || \
Kojto 122:f9eeca106725 9671 ((__PERIPH__) == SAI2_Block_A) || \
Kojto 122:f9eeca106725 9672 ((__PERIPH__) == SAI2_Block_B))
Kojto 122:f9eeca106725 9673 /* Legacy define */
Kojto 122:f9eeca106725 9674 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
Kojto 122:f9eeca106725 9675
Kojto 122:f9eeca106725 9676 /******************************** SDMMC Instances *******************************/
Kojto 122:f9eeca106725 9677 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
Kojto 122:f9eeca106725 9678 ((__INSTANCE__) == SDMMC2))
Kojto 122:f9eeca106725 9679
Kojto 122:f9eeca106725 9680 /****************************** SPDIFRX Instances *********************************/
Kojto 122:f9eeca106725 9681 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
Kojto 122:f9eeca106725 9682
Kojto 122:f9eeca106725 9683 /******************************** SPI Instances *******************************/
Kojto 122:f9eeca106725 9684 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
Kojto 122:f9eeca106725 9685 ((__INSTANCE__) == SPI2) || \
Kojto 122:f9eeca106725 9686 ((__INSTANCE__) == SPI3) || \
Kojto 122:f9eeca106725 9687 ((__INSTANCE__) == SPI4) || \
Kojto 122:f9eeca106725 9688 ((__INSTANCE__) == SPI5) || \
Kojto 122:f9eeca106725 9689 ((__INSTANCE__) == SPI6))
Kojto 122:f9eeca106725 9690
Kojto 122:f9eeca106725 9691 /****************** TIM Instances : All supported instances *******************/
Kojto 122:f9eeca106725 9692 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9693 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9694 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9695 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9696 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9697 ((__INSTANCE__) == TIM6) || \
Kojto 122:f9eeca106725 9698 ((__INSTANCE__) == TIM7) || \
Kojto 122:f9eeca106725 9699 ((__INSTANCE__) == TIM8) || \
Kojto 122:f9eeca106725 9700 ((__INSTANCE__) == TIM9) || \
Kojto 122:f9eeca106725 9701 ((__INSTANCE__) == TIM10) || \
Kojto 122:f9eeca106725 9702 ((__INSTANCE__) == TIM11) || \
Kojto 122:f9eeca106725 9703 ((__INSTANCE__) == TIM12) || \
Kojto 122:f9eeca106725 9704 ((__INSTANCE__) == TIM13) || \
Kojto 122:f9eeca106725 9705 ((__INSTANCE__) == TIM14))
Kojto 122:f9eeca106725 9706
Kojto 122:f9eeca106725 9707 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 122:f9eeca106725 9708 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9709 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9710 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9711 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9712 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9713 ((__INSTANCE__) == TIM8) || \
Kojto 122:f9eeca106725 9714 ((__INSTANCE__) == TIM9) || \
Kojto 122:f9eeca106725 9715 ((__INSTANCE__) == TIM10) || \
Kojto 122:f9eeca106725 9716 ((__INSTANCE__) == TIM11) || \
Kojto 122:f9eeca106725 9717 ((__INSTANCE__) == TIM12) || \
Kojto 122:f9eeca106725 9718 ((__INSTANCE__) == TIM13) || \
Kojto 122:f9eeca106725 9719 ((__INSTANCE__) == TIM14))
Kojto 122:f9eeca106725 9720
Kojto 122:f9eeca106725 9721 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 122:f9eeca106725 9722 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9723 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9724 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9725 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9726 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9727 ((__INSTANCE__) == TIM8) || \
Kojto 122:f9eeca106725 9728 ((__INSTANCE__) == TIM9) || \
Kojto 122:f9eeca106725 9729 ((__INSTANCE__) == TIM12))
Kojto 122:f9eeca106725 9730
Kojto 122:f9eeca106725 9731 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 122:f9eeca106725 9732 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9733 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9734 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9735 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9736 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9737 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9738
Kojto 122:f9eeca106725 9739 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 122:f9eeca106725 9740 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9741 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9742 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9743 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9744 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9745 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9746
Kojto 122:f9eeca106725 9747 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
Kojto 122:f9eeca106725 9748 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
Kojto 122:f9eeca106725 9749 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9750 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9751
Kojto 122:f9eeca106725 9752 /****************** TIM Instances : supporting OCxREF clear *******************/
Kojto 122:f9eeca106725 9753 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
Kojto 122:f9eeca106725 9754 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9755 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9756 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9757 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9758 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9759
Kojto 122:f9eeca106725 9760 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
Kojto 122:f9eeca106725 9761 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
Kojto 122:f9eeca106725 9762 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9763 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9764 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9765 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9766 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9767 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9768
Kojto 122:f9eeca106725 9769 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
Kojto 122:f9eeca106725 9770 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
Kojto 122:f9eeca106725 9771 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9772 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9773 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9774 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9775 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9776 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9777 /****************** TIM Instances : at least 5 capture/compare channels *******/
Kojto 122:f9eeca106725 9778 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
Kojto 122:f9eeca106725 9779 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9780 ((__INSTANCE__) == TIM8) )
Kojto 122:f9eeca106725 9781
Kojto 122:f9eeca106725 9782 /****************** TIM Instances : at least 6 capture/compare channels *******/
Kojto 122:f9eeca106725 9783 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
Kojto 122:f9eeca106725 9784 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9785 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9786
Kojto 122:f9eeca106725 9787
Kojto 122:f9eeca106725 9788 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 122:f9eeca106725 9789 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9790 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9791
Kojto 122:f9eeca106725 9792 /****************** TIM Instances : supporting 2 break inputs *****************/
Kojto 122:f9eeca106725 9793 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
Kojto 122:f9eeca106725 9794 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9795 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9796
Kojto 122:f9eeca106725 9797 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 122:f9eeca106725 9798 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9799 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9800 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9801 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9802 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9803 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9804
Kojto 122:f9eeca106725 9805 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 122:f9eeca106725 9806 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9807 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9808 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9809 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9810 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9811 ((__INSTANCE__) == TIM6) || \
Kojto 122:f9eeca106725 9812 ((__INSTANCE__) == TIM7) || \
Kojto 122:f9eeca106725 9813 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9814
Kojto 122:f9eeca106725 9815 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 122:f9eeca106725 9816 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9817 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9818 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9819 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9820 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9821 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9822
Kojto 122:f9eeca106725 9823 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 122:f9eeca106725 9824 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9825 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9826 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9827 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9828 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9829 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9830
Kojto 122:f9eeca106725 9831 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 122:f9eeca106725 9832 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9833 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9834 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9835 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9836 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9837 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9838
Kojto 122:f9eeca106725 9839 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 122:f9eeca106725 9840 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9841 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9842 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9843 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9844 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9845 ((__INSTANCE__) == TIM6) || \
Kojto 122:f9eeca106725 9846 ((__INSTANCE__) == TIM7) || \
Kojto 122:f9eeca106725 9847 ((__INSTANCE__) == TIM8) || \
Kojto 122:f9eeca106725 9848 ((__INSTANCE__) == TIM13) || \
Kojto 122:f9eeca106725 9849 ((__INSTANCE__) == TIM14))
Kojto 122:f9eeca106725 9850
Kojto 122:f9eeca106725 9851 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 122:f9eeca106725 9852 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9853 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9854 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9855 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9856 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9857 ((__INSTANCE__) == TIM8) || \
Kojto 122:f9eeca106725 9858 ((__INSTANCE__) == TIM9) || \
Kojto 122:f9eeca106725 9859 ((__INSTANCE__) == TIM12))
Kojto 122:f9eeca106725 9860
Kojto 122:f9eeca106725 9861 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 122:f9eeca106725 9862 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9863 ((__INSTANCE__) == TIM5))
Kojto 122:f9eeca106725 9864
Kojto 122:f9eeca106725 9865 /***************** TIM Instances : external trigger input available ************/
Kojto 122:f9eeca106725 9866 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9867 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9868 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9869 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9870 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9871 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9872
Kojto 122:f9eeca106725 9873 /****************** TIM Instances : remapping capability **********************/
Kojto 122:f9eeca106725 9874 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9875 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9876 ((__INSTANCE__) == TIM11))
Kojto 122:f9eeca106725 9877
Kojto 122:f9eeca106725 9878 /******************* TIM Instances : output(s) available **********************/
Kojto 122:f9eeca106725 9879 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
Kojto 122:f9eeca106725 9880 ((((__INSTANCE__) == TIM1) && \
Kojto 122:f9eeca106725 9881 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9882 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 9883 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 122:f9eeca106725 9884 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 122:f9eeca106725 9885 || \
Kojto 122:f9eeca106725 9886 (((__INSTANCE__) == TIM2) && \
Kojto 122:f9eeca106725 9887 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9888 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 9889 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 122:f9eeca106725 9890 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 122:f9eeca106725 9891 || \
Kojto 122:f9eeca106725 9892 (((__INSTANCE__) == TIM3) && \
Kojto 122:f9eeca106725 9893 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9894 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 9895 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 122:f9eeca106725 9896 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 122:f9eeca106725 9897 || \
Kojto 122:f9eeca106725 9898 (((__INSTANCE__) == TIM4) && \
Kojto 122:f9eeca106725 9899 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9900 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 9901 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 122:f9eeca106725 9902 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 122:f9eeca106725 9903 || \
Kojto 122:f9eeca106725 9904 (((__INSTANCE__) == TIM5) && \
Kojto 122:f9eeca106725 9905 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9906 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 9907 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 122:f9eeca106725 9908 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 122:f9eeca106725 9909 || \
Kojto 122:f9eeca106725 9910 (((__INSTANCE__) == TIM8) && \
Kojto 122:f9eeca106725 9911 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9912 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 9913 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 122:f9eeca106725 9914 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 122:f9eeca106725 9915 || \
Kojto 122:f9eeca106725 9916 (((__INSTANCE__) == TIM9) && \
Kojto 122:f9eeca106725 9917 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9918 ((__CHANNEL__) == TIM_CHANNEL_2))) \
Kojto 122:f9eeca106725 9919 || \
Kojto 122:f9eeca106725 9920 (((__INSTANCE__) == TIM10) && \
Kojto 122:f9eeca106725 9921 (((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto 122:f9eeca106725 9922 || \
Kojto 122:f9eeca106725 9923 (((__INSTANCE__) == TIM11) && \
Kojto 122:f9eeca106725 9924 (((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto 122:f9eeca106725 9925 || \
Kojto 122:f9eeca106725 9926 (((__INSTANCE__) == TIM12) && \
Kojto 122:f9eeca106725 9927 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9928 ((__CHANNEL__) == TIM_CHANNEL_2))) \
Kojto 122:f9eeca106725 9929 || \
Kojto 122:f9eeca106725 9930 (((__INSTANCE__) == TIM13) && \
Kojto 122:f9eeca106725 9931 (((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto 122:f9eeca106725 9932 || \
Kojto 122:f9eeca106725 9933 (((__INSTANCE__) == TIM14) && \
Kojto 122:f9eeca106725 9934 (((__CHANNEL__) == TIM_CHANNEL_1))))
Kojto 122:f9eeca106725 9935
Kojto 122:f9eeca106725 9936 /************ TIM Instances : complementary output(s) available ***************/
Kojto 122:f9eeca106725 9937 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
Kojto 122:f9eeca106725 9938 ((((__INSTANCE__) == TIM1) && \
Kojto 122:f9eeca106725 9939 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9940 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 9941 ((__CHANNEL__) == TIM_CHANNEL_3))) \
Kojto 122:f9eeca106725 9942 || \
Kojto 122:f9eeca106725 9943 (((__INSTANCE__) == TIM8) && \
Kojto 122:f9eeca106725 9944 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 122:f9eeca106725 9945 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 122:f9eeca106725 9946 ((__CHANNEL__) == TIM_CHANNEL_3))))
Kojto 122:f9eeca106725 9947
Kojto 122:f9eeca106725 9948 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
Kojto 122:f9eeca106725 9949 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
Kojto 122:f9eeca106725 9950 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9951 ((__INSTANCE__) == TIM8) )
Kojto 122:f9eeca106725 9952
Kojto 122:f9eeca106725 9953 /****************** TIM Instances : supporting synchronization ****************/
Kojto 122:f9eeca106725 9954 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
Kojto 122:f9eeca106725 9955 (((__INSTANCE__) == TIM1) || \
Kojto 122:f9eeca106725 9956 ((__INSTANCE__) == TIM2) || \
Kojto 122:f9eeca106725 9957 ((__INSTANCE__) == TIM3) || \
Kojto 122:f9eeca106725 9958 ((__INSTANCE__) == TIM4) || \
Kojto 122:f9eeca106725 9959 ((__INSTANCE__) == TIM5) || \
Kojto 122:f9eeca106725 9960 ((__INSTANCE__) == TIM6) || \
Kojto 122:f9eeca106725 9961 ((__INSTANCE__) == TIM7) || \
Kojto 122:f9eeca106725 9962 ((__INSTANCE__) == TIM8))
Kojto 122:f9eeca106725 9963
Kojto 122:f9eeca106725 9964 /******************** USART Instances : Synchronous mode **********************/
Kojto 122:f9eeca106725 9965 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 122:f9eeca106725 9966 ((__INSTANCE__) == USART2) || \
Kojto 122:f9eeca106725 9967 ((__INSTANCE__) == USART3) || \
Kojto 122:f9eeca106725 9968 ((__INSTANCE__) == USART6))
Kojto 122:f9eeca106725 9969
Kojto 122:f9eeca106725 9970 /******************** UART Instances : Asynchronous mode **********************/
Kojto 122:f9eeca106725 9971 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 122:f9eeca106725 9972 ((__INSTANCE__) == USART2) || \
Kojto 122:f9eeca106725 9973 ((__INSTANCE__) == USART3) || \
Kojto 122:f9eeca106725 9974 ((__INSTANCE__) == UART4) || \
Kojto 122:f9eeca106725 9975 ((__INSTANCE__) == UART5) || \
Kojto 122:f9eeca106725 9976 ((__INSTANCE__) == USART6) || \
Kojto 122:f9eeca106725 9977 ((__INSTANCE__) == UART7) || \
Kojto 122:f9eeca106725 9978 ((__INSTANCE__) == UART8))
Kojto 122:f9eeca106725 9979
Kojto 122:f9eeca106725 9980 /****************** UART Instances : Driver Enable *****************/
Kojto 122:f9eeca106725 9981 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 122:f9eeca106725 9982 ((__INSTANCE__) == USART2) || \
Kojto 122:f9eeca106725 9983 ((__INSTANCE__) == USART3) || \
Kojto 122:f9eeca106725 9984 ((__INSTANCE__) == UART4) || \
Kojto 122:f9eeca106725 9985 ((__INSTANCE__) == UART5) || \
Kojto 122:f9eeca106725 9986 ((__INSTANCE__) == USART6) || \
Kojto 122:f9eeca106725 9987 ((__INSTANCE__) == UART7) || \
Kojto 122:f9eeca106725 9988 ((__INSTANCE__) == UART8))
Kojto 122:f9eeca106725 9989
Kojto 122:f9eeca106725 9990 /****************** UART Instances : Hardware Flow control ********************/
Kojto 122:f9eeca106725 9991 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 122:f9eeca106725 9992 ((__INSTANCE__) == USART2) || \
Kojto 122:f9eeca106725 9993 ((__INSTANCE__) == USART3) || \
Kojto 122:f9eeca106725 9994 ((__INSTANCE__) == UART4) || \
Kojto 122:f9eeca106725 9995 ((__INSTANCE__) == UART5) || \
Kojto 122:f9eeca106725 9996 ((__INSTANCE__) == USART6) || \
Kojto 122:f9eeca106725 9997 ((__INSTANCE__) == UART7) || \
Kojto 122:f9eeca106725 9998 ((__INSTANCE__) == UART8))
Kojto 122:f9eeca106725 9999
Kojto 122:f9eeca106725 10000 /********************* UART Instances : Smart card mode ***********************/
Kojto 122:f9eeca106725 10001 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 122:f9eeca106725 10002 ((__INSTANCE__) == USART2) || \
Kojto 122:f9eeca106725 10003 ((__INSTANCE__) == USART3) || \
Kojto 122:f9eeca106725 10004 ((__INSTANCE__) == USART6))
Kojto 122:f9eeca106725 10005
Kojto 122:f9eeca106725 10006 /*********************** UART Instances : IRDA mode ***************************/
Kojto 122:f9eeca106725 10007 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 122:f9eeca106725 10008 ((__INSTANCE__) == USART2) || \
Kojto 122:f9eeca106725 10009 ((__INSTANCE__) == USART3) || \
Kojto 122:f9eeca106725 10010 ((__INSTANCE__) == UART4) || \
Kojto 122:f9eeca106725 10011 ((__INSTANCE__) == UART5) || \
Kojto 122:f9eeca106725 10012 ((__INSTANCE__) == USART6) || \
Kojto 122:f9eeca106725 10013 ((__INSTANCE__) == UART7) || \
Kojto 122:f9eeca106725 10014 ((__INSTANCE__) == UART8))
Kojto 122:f9eeca106725 10015
Kojto 122:f9eeca106725 10016 /****************************** IWDG Instances ********************************/
Kojto 122:f9eeca106725 10017 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
Kojto 122:f9eeca106725 10018
Kojto 122:f9eeca106725 10019 /****************************** WWDG Instances ********************************/
Kojto 122:f9eeca106725 10020 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
Kojto 122:f9eeca106725 10021
Kojto 122:f9eeca106725 10022
Kojto 122:f9eeca106725 10023 /******************************************************************************/
Kojto 122:f9eeca106725 10024 /* For a painless codes migration between the STM32F7xx device product */
Kojto 122:f9eeca106725 10025 /* lines, the aliases defined below are put in place to overcome the */
Kojto 122:f9eeca106725 10026 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 122:f9eeca106725 10027 /* No need to update developed interrupt code when moving across */
Kojto 122:f9eeca106725 10028 /* product lines within the same STM32F7 Family */
Kojto 122:f9eeca106725 10029 /******************************************************************************/
Kojto 122:f9eeca106725 10030
Kojto 122:f9eeca106725 10031 /* Aliases for __IRQn */
Kojto 122:f9eeca106725 10032 #define HASH_RNG_IRQn RNG_IRQn
Kojto 122:f9eeca106725 10033
Kojto 122:f9eeca106725 10034 /* Aliases for __IRQHandler */
Kojto 122:f9eeca106725 10035 #define HASH_RNG_IRQHandler RNG_IRQHandler
Kojto 122:f9eeca106725 10036
Kojto 122:f9eeca106725 10037 /**
Kojto 122:f9eeca106725 10038 * @}
Kojto 122:f9eeca106725 10039 */
Kojto 122:f9eeca106725 10040
Kojto 122:f9eeca106725 10041 /**
Kojto 122:f9eeca106725 10042 * @}
Kojto 122:f9eeca106725 10043 */
Kojto 122:f9eeca106725 10044
Kojto 122:f9eeca106725 10045 /**
Kojto 122:f9eeca106725 10046 * @}
Kojto 122:f9eeca106725 10047 */
Kojto 122:f9eeca106725 10048
Kojto 122:f9eeca106725 10049 #ifdef __cplusplus
Kojto 122:f9eeca106725 10050 }
Kojto 122:f9eeca106725 10051 #endif /* __cplusplus */
Kojto 122:f9eeca106725 10052
Kojto 122:f9eeca106725 10053 #endif /* __STM32F767xx_H */
Kojto 122:f9eeca106725 10054
Kojto 122:f9eeca106725 10055
Kojto 122:f9eeca106725 10056 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/