mbed | Mbed

Users » kaoshen » Code » mbed

TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_qspi.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:: Kojto
Date:: Thu Jul 07 14:34:11 2016 +0100
Revision:: 122:f9eeca106725
Parent:: 110:165afa46840b

Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	101:7cff1c4259d7	1	/**
Kojto	101:7cff1c4259d7	2	******************************************************************************
Kojto	101:7cff1c4259d7	3	* @file stm32f4xx_hal_qspi.h
Kojto	101:7cff1c4259d7	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.0
Kojto	122:f9eeca106725	6	* @date 06-May-2016
Kojto	101:7cff1c4259d7	7	* @brief Header file of QSPI HAL module.
Kojto	101:7cff1c4259d7	8	******************************************************************************
Kojto	101:7cff1c4259d7	9	* @attention
Kojto	101:7cff1c4259d7	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	101:7cff1c4259d7	12	*
Kojto	101:7cff1c4259d7	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	101:7cff1c4259d7	14	* are permitted provided that the following conditions are met:
Kojto	101:7cff1c4259d7	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	101:7cff1c4259d7	16	* this list of conditions and the following disclaimer.
Kojto	101:7cff1c4259d7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	101:7cff1c4259d7	18	* this list of conditions and the following disclaimer in the documentation
Kojto	101:7cff1c4259d7	19	* and/or other materials provided with the distribution.
Kojto	101:7cff1c4259d7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	101:7cff1c4259d7	21	* may be used to endorse or promote products derived from this software
Kojto	101:7cff1c4259d7	22	* without specific prior written permission.
Kojto	101:7cff1c4259d7	23	*
Kojto	101:7cff1c4259d7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	101:7cff1c4259d7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	101:7cff1c4259d7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	101:7cff1c4259d7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	101:7cff1c4259d7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	101:7cff1c4259d7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	101:7cff1c4259d7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	101:7cff1c4259d7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	101:7cff1c4259d7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	101:7cff1c4259d7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	101:7cff1c4259d7	34	*
Kojto	101:7cff1c4259d7	35	******************************************************************************
Kojto	101:7cff1c4259d7	36	*/
Kojto	101:7cff1c4259d7	37
Kojto	101:7cff1c4259d7	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	101:7cff1c4259d7	39	#ifndef __STM32F4xx_HAL_QSPI_H
Kojto	101:7cff1c4259d7	40	#define __STM32F4xx_HAL_QSPI_H
Kojto	101:7cff1c4259d7	41
Kojto	101:7cff1c4259d7	42	#ifdef __cplusplus
Kojto	101:7cff1c4259d7	43	extern "C" {
Kojto	101:7cff1c4259d7	44	#endif
Kojto	101:7cff1c4259d7	45
Kojto	122:f9eeca106725	46	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Kojto	122:f9eeca106725	47	defined(STM32F412Rx)
Kojto	101:7cff1c4259d7	48	/* Includes ------------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	49	#include "stm32f4xx_hal_def.h"
Kojto	101:7cff1c4259d7	50
Kojto	101:7cff1c4259d7	51	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	101:7cff1c4259d7	52	* @{
Kojto	101:7cff1c4259d7	53	*/
Kojto	101:7cff1c4259d7	54
Kojto	101:7cff1c4259d7	55	/** @addtogroup QSPI
Kojto	101:7cff1c4259d7	56	* @{
Kojto	101:7cff1c4259d7	57	*/
Kojto	101:7cff1c4259d7	58
Kojto	101:7cff1c4259d7	59	/* Exported types ------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	60	/** @defgroup QSPI_Exported_Types QSPI Exported Types
Kojto	101:7cff1c4259d7	61	* @{
Kojto	101:7cff1c4259d7	62	*/
Kojto	101:7cff1c4259d7	63
Kojto	101:7cff1c4259d7	64	/**
Kojto	101:7cff1c4259d7	65	* @brief QSPI Init structure definition
Kojto	101:7cff1c4259d7	66	*/
Kojto	101:7cff1c4259d7	67
Kojto	101:7cff1c4259d7	68	typedef struct
Kojto	101:7cff1c4259d7	69	{
Kojto	101:7cff1c4259d7	70	uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
Kojto	101:7cff1c4259d7	71	This parameter can be a number between 0 and 255 */
Kojto	122:f9eeca106725	72
Kojto	101:7cff1c4259d7	73	uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
Kojto	101:7cff1c4259d7	74	This parameter can be a value between 1 and 32 */
Kojto	122:f9eeca106725	75
Kojto	101:7cff1c4259d7	76	uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
Kojto	101:7cff1c4259d7	77	take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
Kojto	101:7cff1c4259d7	78	This parameter can be a value of @ref QSPI_SampleShifting */
Kojto	122:f9eeca106725	79
Kojto	101:7cff1c4259d7	80	uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
Kojto	101:7cff1c4259d7	81	required to address the flash memory. The flash capacity can be up to 4GB
Kojto	101:7cff1c4259d7	82	(addressed using 32 bits) in indirect mode, but the addressable space in
Kojto	101:7cff1c4259d7	83	memory-mapped mode is limited to 256MB
Kojto	101:7cff1c4259d7	84	This parameter can be a number between 0 and 31 */
Kojto	122:f9eeca106725	85
Kojto	101:7cff1c4259d7	86	uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
Kojto	101:7cff1c4259d7	87	of clock cycles which the chip select must remain high between commands.
Kojto	101:7cff1c4259d7	88	This parameter can be a value of @ref QSPI_ChipSelectHighTime */
Kojto	122:f9eeca106725	89
Kojto	101:7cff1c4259d7	90	uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
Kojto	101:7cff1c4259d7	91	This parameter can be a value of @ref QSPI_ClockMode */
Kojto	122:f9eeca106725	92
Kojto	101:7cff1c4259d7	93	uint32_t FlashID; /* Specifies the Flash which will be used,
Kojto	101:7cff1c4259d7	94	This parameter can be a value of @ref QSPI_Flash_Select */
Kojto	122:f9eeca106725	95
Kojto	101:7cff1c4259d7	96	uint32_t DualFlash; /* Specifies the Dual Flash Mode State
Kojto	122:f9eeca106725	97	This parameter can be a value of @ref QSPI_DualFlash_Mode */
Kojto	101:7cff1c4259d7	98	}QSPI_InitTypeDef;
Kojto	101:7cff1c4259d7	99
Kojto	101:7cff1c4259d7	100	/**
Kojto	101:7cff1c4259d7	101	* @brief HAL QSPI State structures definition
Kojto	101:7cff1c4259d7	102	*/
Kojto	101:7cff1c4259d7	103	typedef enum
Kojto	101:7cff1c4259d7	104	{
Kojto	122:f9eeca106725	105	HAL_QSPI_STATE_RESET = 0x00U, /!< Peripheral not initialized /
Kojto	122:f9eeca106725	106	HAL_QSPI_STATE_READY = 0x01U, /!< Peripheral initialized and ready for use /
Kojto	122:f9eeca106725	107	HAL_QSPI_STATE_BUSY = 0x02U, /!< Peripheral in indirect mode and busy /
Kojto	122:f9eeca106725	108	HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /!< Peripheral in indirect mode with transmission ongoing /
Kojto	122:f9eeca106725	109	HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /!< Peripheral in indirect mode with reception ongoing /
Kojto	122:f9eeca106725	110	HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /!< Peripheral in auto polling mode ongoing /
Kojto	122:f9eeca106725	111	HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /!< Peripheral in memory mapped mode ongoing /
Kojto	122:f9eeca106725	112	HAL_QSPI_STATE_ABORT = 0x08U, /!< Peripheral with abort request ongoing /
Kojto	122:f9eeca106725	113	HAL_QSPI_STATE_ERROR = 0x04U /!< Peripheral in error /
Kojto	101:7cff1c4259d7	114	}HAL_QSPI_StateTypeDef;
Kojto	101:7cff1c4259d7	115
Kojto	101:7cff1c4259d7	116	/**
Kojto	101:7cff1c4259d7	117	* @brief QSPI Handle Structure definition
Kojto	101:7cff1c4259d7	118	*/
Kojto	101:7cff1c4259d7	119	typedef struct
Kojto	101:7cff1c4259d7	120	{
Kojto	101:7cff1c4259d7	121	QUADSPI_TypeDef Instance; / QSPI registers base address */
Kojto	101:7cff1c4259d7	122	QSPI_InitTypeDef Init; /* QSPI communication parameters */
Kojto	101:7cff1c4259d7	123	uint8_t pTxBuffPtr; / Pointer to QSPI Tx transfer Buffer */
Kojto	101:7cff1c4259d7	124	__IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
Kojto	101:7cff1c4259d7	125	__IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
Kojto	101:7cff1c4259d7	126	uint8_t pRxBuffPtr; / Pointer to QSPI Rx transfer Buffer */
Kojto	101:7cff1c4259d7	127	__IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
Kojto	101:7cff1c4259d7	128	__IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
Kojto	101:7cff1c4259d7	129	DMA_HandleTypeDef hdma; / QSPI Rx/Tx DMA Handle parameters */
Kojto	101:7cff1c4259d7	130	__IO HAL_LockTypeDef Lock; /* Locking object */
Kojto	101:7cff1c4259d7	131	__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
Kojto	101:7cff1c4259d7	132	__IO uint32_t ErrorCode; /* QSPI Error code */
Kojto	122:f9eeca106725	133	uint32_t Timeout; /* Timeout for the QSPI memory access */
Kojto	101:7cff1c4259d7	134	}QSPI_HandleTypeDef;
Kojto	101:7cff1c4259d7	135
Kojto	101:7cff1c4259d7	136	/**
Kojto	101:7cff1c4259d7	137	* @brief QSPI Command structure definition
Kojto	101:7cff1c4259d7	138	*/
Kojto	101:7cff1c4259d7	139	typedef struct
Kojto	101:7cff1c4259d7	140	{
Kojto	101:7cff1c4259d7	141	uint32_t Instruction; /* Specifies the Instruction to be sent
Kojto	101:7cff1c4259d7	142	This parameter can be a value (8-bit) between 0x00 and 0xFF */
Kojto	101:7cff1c4259d7	143	uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
Kojto	122:f9eeca106725	144	This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
Kojto	101:7cff1c4259d7	145	uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
Kojto	122:f9eeca106725	146	This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */
Kojto	101:7cff1c4259d7	147	uint32_t AddressSize; /* Specifies the Address Size
Kojto	101:7cff1c4259d7	148	This parameter can be a value of @ref QSPI_AddressSize */
Kojto	101:7cff1c4259d7	149	uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
Kojto	101:7cff1c4259d7	150	This parameter can be a value of @ref QSPI_AlternateBytesSize */
Kojto	101:7cff1c4259d7	151	uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
Kojto	101:7cff1c4259d7	152	This parameter can be a number between 0 and 31 */
Kojto	101:7cff1c4259d7	153	uint32_t InstructionMode; /* Specifies the Instruction Mode
Kojto	101:7cff1c4259d7	154	This parameter can be a value of @ref QSPI_InstructionMode */
Kojto	101:7cff1c4259d7	155	uint32_t AddressMode; /* Specifies the Address Mode
Kojto	101:7cff1c4259d7	156	This parameter can be a value of @ref QSPI_AddressMode */
Kojto	101:7cff1c4259d7	157	uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
Kojto	101:7cff1c4259d7	158	This parameter can be a value of @ref QSPI_AlternateBytesMode */
Kojto	101:7cff1c4259d7	159	uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
Kojto	101:7cff1c4259d7	160	This parameter can be a value of @ref QSPI_DataMode */
Kojto	101:7cff1c4259d7	161	uint32_t NbData; /* Specifies the number of data to transfer.
Kojto	122:f9eeca106725	162	This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length
Kojto	101:7cff1c4259d7	163	until end of memory)*/
Kojto	101:7cff1c4259d7	164	uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
Kojto	101:7cff1c4259d7	165	This parameter can be a value of @ref QSPI_DdrMode */
Kojto	101:7cff1c4259d7	166	uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
Kojto	101:7cff1c4259d7	167	system clock in DDR mode.
Kojto	101:7cff1c4259d7	168	This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
Kojto	101:7cff1c4259d7	169	uint32_t SIOOMode; /* Specifies the send instruction only once mode
Kojto	101:7cff1c4259d7	170	This parameter can be a value of @ref QSPI_SIOOMode */
Kojto	101:7cff1c4259d7	171	}QSPI_CommandTypeDef;
Kojto	101:7cff1c4259d7	172
Kojto	101:7cff1c4259d7	173	/**
Kojto	101:7cff1c4259d7	174	* @brief QSPI Auto Polling mode configuration structure definition
Kojto	101:7cff1c4259d7	175	*/
Kojto	101:7cff1c4259d7	176	typedef struct
Kojto	101:7cff1c4259d7	177	{
Kojto	101:7cff1c4259d7	178	uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
Kojto	122:f9eeca106725	179	This parameter can be any value between 0 and 0xFFFFFFFFU */
Kojto	101:7cff1c4259d7	180	uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
Kojto	122:f9eeca106725	181	This parameter can be any value between 0 and 0xFFFFFFFFU */
Kojto	101:7cff1c4259d7	182	uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
Kojto	122:f9eeca106725	183	This parameter can be any value between 0 and 0xFFFFU */
Kojto	101:7cff1c4259d7	184	uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
Kojto	101:7cff1c4259d7	185	This parameter can be any value between 1 and 4 */
Kojto	101:7cff1c4259d7	186	uint32_t MatchMode; /* Specifies the method used for determining a match.
Kojto	101:7cff1c4259d7	187	This parameter can be a value of @ref QSPI_MatchMode */
Kojto	101:7cff1c4259d7	188	uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
Kojto	101:7cff1c4259d7	189	This parameter can be a value of @ref QSPI_AutomaticStop */
Kojto	101:7cff1c4259d7	190	}QSPI_AutoPollingTypeDef;
Kojto	122:f9eeca106725	191
Kojto	101:7cff1c4259d7	192	/**
Kojto	101:7cff1c4259d7	193	* @brief QSPI Memory Mapped mode configuration structure definition
Kojto	101:7cff1c4259d7	194	*/
Kojto	101:7cff1c4259d7	195	typedef struct
Kojto	101:7cff1c4259d7	196	{
Kojto	101:7cff1c4259d7	197	uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
Kojto	122:f9eeca106725	198	This parameter can be any value between 0 and 0xFFFFU */
Kojto	101:7cff1c4259d7	199	uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
Kojto	101:7cff1c4259d7	200	This parameter can be a value of @ref QSPI_TimeOutActivation */
Kojto	101:7cff1c4259d7	201	}QSPI_MemoryMappedTypeDef;
Kojto	101:7cff1c4259d7	202	/**
Kojto	101:7cff1c4259d7	203	* @}
Kojto	101:7cff1c4259d7	204	*/
Kojto	101:7cff1c4259d7	205
Kojto	101:7cff1c4259d7	206	/* Exported constants --------------------------------------------------------*/
Kojto	101:7cff1c4259d7	207	/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
Kojto	101:7cff1c4259d7	208	* @{
Kojto	101:7cff1c4259d7	209	*/
Kojto	101:7cff1c4259d7	210	/** @defgroup QSPI_ErrorCode QSPI Error Code
Kojto	101:7cff1c4259d7	211	* @{
Kojto	101:7cff1c4259d7	212	*/
Kojto	122:f9eeca106725	213	#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
Kojto	122:f9eeca106725	214	#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /!< Timeout error /
Kojto	122:f9eeca106725	215	#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /!< Transfer error /
Kojto	122:f9eeca106725	216	#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /!< DMA transfer error /
Kojto	122:f9eeca106725	217	#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /!< Invalid parameters error /
Kojto	101:7cff1c4259d7	218	/**
Kojto	101:7cff1c4259d7	219	* @}
Kojto	101:7cff1c4259d7	220	*/
Kojto	101:7cff1c4259d7	221
Kojto	101:7cff1c4259d7	222	/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
Kojto	101:7cff1c4259d7	223	* @{
Kojto	101:7cff1c4259d7	224	*/
Kojto	122:f9eeca106725	225	#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /!<No clock cycle shift to sample data/
Kojto	101:7cff1c4259d7	226	#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /!<1/2 clock cycle shift to sample data/
Kojto	101:7cff1c4259d7	227	/**
Kojto	101:7cff1c4259d7	228	* @}
Kojto	101:7cff1c4259d7	229	*/
Kojto	101:7cff1c4259d7	230
Kojto	101:7cff1c4259d7	231	/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
Kojto	101:7cff1c4259d7	232	* @{
Kojto	101:7cff1c4259d7	233	*/
Kojto	122:f9eeca106725	234	#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /!<nCS stay high for at least 1 clock cycle between commands/
Kojto	101:7cff1c4259d7	235	#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /!<nCS stay high for at least 2 clock cycles between commands/
Kojto	101:7cff1c4259d7	236	#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 3 clock cycles between commands/
Kojto	101:7cff1c4259d7	237	#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 \| QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 4 clock cycles between commands/
Kojto	101:7cff1c4259d7	238	#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /!<nCS stay high for at least 5 clock cycles between commands/
Kojto	101:7cff1c4259d7	239	#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 \| QUADSPI_DCR_CSHT_0) /!<nCS stay high for at least 6 clock cycles between commands/
Kojto	101:7cff1c4259d7	240	#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 \| QUADSPI_DCR_CSHT_1) /!<nCS stay high for at least 7 clock cycles between commands/
Kojto	101:7cff1c4259d7	241	#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /!<nCS stay high for at least 8 clock cycles between commands/
Kojto	101:7cff1c4259d7	242	/**
Kojto	101:7cff1c4259d7	243	* @}
Kojto	101:7cff1c4259d7	244	*/
Kojto	101:7cff1c4259d7	245
Kojto	101:7cff1c4259d7	246	/** @defgroup QSPI_ClockMode QSPI Clock Mode
Kojto	101:7cff1c4259d7	247	* @{
Kojto	101:7cff1c4259d7	248	*/
Kojto	122:f9eeca106725	249	#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /!<Clk stays low while nCS is released/
Kojto	101:7cff1c4259d7	250	#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /!<Clk goes high while nCS is released/
Kojto	101:7cff1c4259d7	251	/**
Kojto	101:7cff1c4259d7	252	* @}
Kojto	101:7cff1c4259d7	253	*/
Kojto	101:7cff1c4259d7	254
Kojto	101:7cff1c4259d7	255	/** @defgroup QSPI_Flash_Select QSPI Flash Select
Kojto	101:7cff1c4259d7	256	* @{
Kojto	101:7cff1c4259d7	257	*/
Kojto	122:f9eeca106725	258	#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
Kojto	101:7cff1c4259d7	259	#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
Kojto	101:7cff1c4259d7	260	/**
Kojto	101:7cff1c4259d7	261	* @}
Kojto	101:7cff1c4259d7	262	*/
Kojto	101:7cff1c4259d7	263
Kojto	101:7cff1c4259d7	264	/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
Kojto	101:7cff1c4259d7	265	* @{
Kojto	101:7cff1c4259d7	266	*/
Kojto	101:7cff1c4259d7	267	#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
Kojto	122:f9eeca106725	268	#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U)
Kojto	101:7cff1c4259d7	269	/**
Kojto	101:7cff1c4259d7	270	* @}
Kojto	101:7cff1c4259d7	271	*/
Kojto	101:7cff1c4259d7	272
Kojto	101:7cff1c4259d7	273	/** @defgroup QSPI_AddressSize QSPI Address Size
Kojto	101:7cff1c4259d7	274	* @{
Kojto	101:7cff1c4259d7	275	*/
Kojto	122:f9eeca106725	276	#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /!<8-bit address/
Kojto	101:7cff1c4259d7	277	#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /!<16-bit address/
Kojto	101:7cff1c4259d7	278	#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /!<24-bit address/
Kojto	101:7cff1c4259d7	279	#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /!<32-bit address/
Kojto	101:7cff1c4259d7	280	/**
Kojto	101:7cff1c4259d7	281	* @}
Kojto	101:7cff1c4259d7	282	*/
Kojto	101:7cff1c4259d7	283
Kojto	101:7cff1c4259d7	284	/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
Kojto	101:7cff1c4259d7	285	* @{
Kojto	101:7cff1c4259d7	286	*/
Kojto	122:f9eeca106725	287	#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /!<8-bit alternate bytes/
Kojto	101:7cff1c4259d7	288	#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /!<16-bit alternate bytes/
Kojto	101:7cff1c4259d7	289	#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /!<24-bit alternate bytes/
Kojto	101:7cff1c4259d7	290	#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /!<32-bit alternate bytes/
Kojto	101:7cff1c4259d7	291	/**
Kojto	101:7cff1c4259d7	292	* @}
Kojto	101:7cff1c4259d7	293	*/
Kojto	101:7cff1c4259d7	294
Kojto	101:7cff1c4259d7	295	/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
Kojto	101:7cff1c4259d7	296	* @{
Kojto	101:7cff1c4259d7	297	*/
Kojto	122:f9eeca106725	298	#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /!<No instruction/
Kojto	101:7cff1c4259d7	299	#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /!<Instruction on a single line/
Kojto	101:7cff1c4259d7	300	#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /!<Instruction on two lines/
Kojto	101:7cff1c4259d7	301	#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /!<Instruction on four lines/
Kojto	101:7cff1c4259d7	302	/**
Kojto	101:7cff1c4259d7	303	* @}
Kojto	101:7cff1c4259d7	304	*/
Kojto	101:7cff1c4259d7	305
Kojto	101:7cff1c4259d7	306	/** @defgroup QSPI_AddressMode QSPI Address Mode
Kojto	101:7cff1c4259d7	307	* @{
Kojto	101:7cff1c4259d7	308	*/
Kojto	122:f9eeca106725	309	#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /!<No address/
Kojto	101:7cff1c4259d7	310	#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /!<Address on a single line/
Kojto	101:7cff1c4259d7	311	#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /!<Address on two lines/
Kojto	101:7cff1c4259d7	312	#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /!<Address on four lines/
Kojto	101:7cff1c4259d7	313	/**
Kojto	101:7cff1c4259d7	314	* @}
Kojto	101:7cff1c4259d7	315	*/
Kojto	101:7cff1c4259d7	316
Kojto	101:7cff1c4259d7	317	/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
Kojto	101:7cff1c4259d7	318	* @{
Kojto	101:7cff1c4259d7	319	*/
Kojto	122:f9eeca106725	320	#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /!<No alternate bytes/
Kojto	101:7cff1c4259d7	321	#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /!<Alternate bytes on a single line/
Kojto	101:7cff1c4259d7	322	#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /!<Alternate bytes on two lines/
Kojto	101:7cff1c4259d7	323	#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /!<Alternate bytes on four lines/
Kojto	101:7cff1c4259d7	324	/**
Kojto	101:7cff1c4259d7	325	* @}
Kojto	101:7cff1c4259d7	326	*/
Kojto	101:7cff1c4259d7	327
Kojto	101:7cff1c4259d7	328	/** @defgroup QSPI_DataMode QSPI Data Mode
Kojto	101:7cff1c4259d7	329	* @{
Kojto	101:7cff1c4259d7	330	*/
Kojto	122:f9eeca106725	331	#define QSPI_DATA_NONE ((uint32_t)0x00000000U) /!<No data/
Kojto	101:7cff1c4259d7	332	#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /!<Data on a single line/
Kojto	101:7cff1c4259d7	333	#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /!<Data on two lines/
Kojto	101:7cff1c4259d7	334	#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /!<Data on four lines/
Kojto	101:7cff1c4259d7	335	/**
Kojto	101:7cff1c4259d7	336	* @}
Kojto	101:7cff1c4259d7	337	*/
Kojto	101:7cff1c4259d7	338
Kojto	101:7cff1c4259d7	339	/** @defgroup QSPI_DdrMode QSPI Ddr Mode
Kojto	101:7cff1c4259d7	340	* @{
Kojto	101:7cff1c4259d7	341	*/
Kojto	122:f9eeca106725	342	#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) /!<Double data rate mode disabled/
Kojto	101:7cff1c4259d7	343	#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /!<Double data rate mode enabled/
Kojto	101:7cff1c4259d7	344	/**
Kojto	101:7cff1c4259d7	345	* @}
Kojto	101:7cff1c4259d7	346	*/
Kojto	101:7cff1c4259d7	347
Kojto	101:7cff1c4259d7	348	/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
Kojto	101:7cff1c4259d7	349	* @{
Kojto	101:7cff1c4259d7	350	*/
Kojto	122:f9eeca106725	351	#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) /!<Delay the data output using analog delay in DDR mode/
Kojto	101:7cff1c4259d7	352	#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /!<Delay the data output by 1/2 clock cycle in DDR mode/
Kojto	101:7cff1c4259d7	353	/**
Kojto	101:7cff1c4259d7	354	* @}
Kojto	101:7cff1c4259d7	355	*/
Kojto	101:7cff1c4259d7	356
Kojto	101:7cff1c4259d7	357	/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
Kojto	101:7cff1c4259d7	358	* @{
Kojto	101:7cff1c4259d7	359	*/
Kojto	122:f9eeca106725	360	#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /!<Send instruction on every transaction/
Kojto	101:7cff1c4259d7	361	#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /!<Send instruction only for the first command/
Kojto	101:7cff1c4259d7	362	/**
Kojto	101:7cff1c4259d7	363	* @}
Kojto	101:7cff1c4259d7	364	*/
Kojto	101:7cff1c4259d7	365
Kojto	101:7cff1c4259d7	366	/** @defgroup QSPI_MatchMode QSPI Match Mode
Kojto	101:7cff1c4259d7	367	* @{
Kojto	101:7cff1c4259d7	368	*/
Kojto	122:f9eeca106725	369	#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /!<AND match mode between unmasked bits/
Kojto	101:7cff1c4259d7	370	#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /!<OR match mode between unmasked bits/
Kojto	101:7cff1c4259d7	371	/**
Kojto	101:7cff1c4259d7	372	* @}
Kojto	101:7cff1c4259d7	373	*/
Kojto	101:7cff1c4259d7	374
Kojto	101:7cff1c4259d7	375	/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
Kojto	101:7cff1c4259d7	376	* @{
Kojto	101:7cff1c4259d7	377	*/
Kojto	122:f9eeca106725	378	#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /!<AutoPolling stops only with abort or QSPI disabling/
Kojto	101:7cff1c4259d7	379	#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /!<AutoPolling stops as soon as there is a match/
Kojto	101:7cff1c4259d7	380	/**
Kojto	101:7cff1c4259d7	381	* @}
Kojto	101:7cff1c4259d7	382	*/
Kojto	101:7cff1c4259d7	383
Kojto	101:7cff1c4259d7	384	/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
Kojto	101:7cff1c4259d7	385	* @{
Kojto	101:7cff1c4259d7	386	*/
Kojto	122:f9eeca106725	387	#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /!<Timeout counter disabled, nCS remains active/
Kojto	101:7cff1c4259d7	388	#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /!<Timeout counter enabled, nCS released when timeout expires/
Kojto	101:7cff1c4259d7	389	/**
Kojto	101:7cff1c4259d7	390	* @}
Kojto	101:7cff1c4259d7	391	*/
Kojto	101:7cff1c4259d7	392
Kojto	101:7cff1c4259d7	393	/** @defgroup QSPI_Flags QSPI Flags
Kojto	101:7cff1c4259d7	394	* @{
Kojto	101:7cff1c4259d7	395	*/
Kojto	101:7cff1c4259d7	396	#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /!<Busy flag: operation is ongoing/
Kojto	101:7cff1c4259d7	397	#define QSPI_FLAG_TO QUADSPI_SR_TOF /!<Timeout flag: timeout occurs in memory-mapped mode/
Kojto	101:7cff1c4259d7	398	#define QSPI_FLAG_SM QUADSPI_SR_SMF /!<Status match flag: received data matches in autopolling mode/
Kojto	101:7cff1c4259d7	399	#define QSPI_FLAG_FT QUADSPI_SR_FTF /!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete/
Kojto	101:7cff1c4259d7	400	#define QSPI_FLAG_TC QUADSPI_SR_TCF /!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted/
Kojto	101:7cff1c4259d7	401	#define QSPI_FLAG_TE QUADSPI_SR_TEF /!<Transfer error flag: invalid address is being accessed/
Kojto	101:7cff1c4259d7	402	/**
Kojto	101:7cff1c4259d7	403	* @}
Kojto	101:7cff1c4259d7	404	*/
Kojto	101:7cff1c4259d7	405
Kojto	101:7cff1c4259d7	406	/** @defgroup QSPI_Interrupts QSPI Interrupts
Kojto	101:7cff1c4259d7	407	* @{
Kojto	101:7cff1c4259d7	408	*/
Kojto	101:7cff1c4259d7	409	#define QSPI_IT_TO QUADSPI_CR_TOIE /!<Interrupt on the timeout flag/
Kojto	101:7cff1c4259d7	410	#define QSPI_IT_SM QUADSPI_CR_SMIE /!<Interrupt on the status match flag/
Kojto	101:7cff1c4259d7	411	#define QSPI_IT_FT QUADSPI_CR_FTIE /!<Interrupt on the fifo threshold flag/
Kojto	101:7cff1c4259d7	412	#define QSPI_IT_TC QUADSPI_CR_TCIE /!<Interrupt on the transfer complete flag/
Kojto	101:7cff1c4259d7	413	#define QSPI_IT_TE QUADSPI_CR_TEIE /!<Interrupt on the transfer error flag/
Kojto	101:7cff1c4259d7	414	/**
Kojto	101:7cff1c4259d7	415	* @}
Kojto	101:7cff1c4259d7	416	*/
Kojto	101:7cff1c4259d7	417
Kojto	101:7cff1c4259d7	418	/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
Kojto	101:7cff1c4259d7	419	* @{
Kojto	101:7cff1c4259d7	420	*/
Kojto	122:f9eeca106725	421	#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U)/* 5 s */
Kojto	101:7cff1c4259d7	422	/**
Kojto	101:7cff1c4259d7	423	* @}
Kojto	101:7cff1c4259d7	424	*/
Kojto	101:7cff1c4259d7	425
Kojto	101:7cff1c4259d7	426	/**
Kojto	101:7cff1c4259d7	427	* @}
Kojto	101:7cff1c4259d7	428	*/
Kojto	101:7cff1c4259d7	429
Kojto	101:7cff1c4259d7	430	/* Exported macros -----------------------------------------------------------*/
Kojto	101:7cff1c4259d7	431	/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
Kojto	101:7cff1c4259d7	432	* @{
Kojto	101:7cff1c4259d7	433	*/
Kojto	101:7cff1c4259d7	434
Kojto	101:7cff1c4259d7	435	/** @brief Reset QSPI handle state
Kojto	101:7cff1c4259d7	436	* @param __HANDLE__: QSPI handle.
Kojto	101:7cff1c4259d7	437	* @retval None
Kojto	101:7cff1c4259d7	438	*/
Kojto	101:7cff1c4259d7	439	#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
Kojto	101:7cff1c4259d7	440
Kojto	101:7cff1c4259d7	441	/** @brief Enable QSPI
Kojto	101:7cff1c4259d7	442	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	101:7cff1c4259d7	443	* @retval None
Kojto	101:7cff1c4259d7	444	*/
Kojto	101:7cff1c4259d7	445	#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Kojto	101:7cff1c4259d7	446
Kojto	101:7cff1c4259d7	447	/** @brief Disable QSPI
Kojto	101:7cff1c4259d7	448	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	101:7cff1c4259d7	449	* @retval None
Kojto	101:7cff1c4259d7	450	*/
Kojto	101:7cff1c4259d7	451	#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
Kojto	101:7cff1c4259d7	452
Kojto	101:7cff1c4259d7	453	/** @brief Enables the specified QSPI interrupt.
Kojto	101:7cff1c4259d7	454	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	101:7cff1c4259d7	455	* @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
Kojto	101:7cff1c4259d7	456	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	457	* @arg QSPI_IT_TO: QSPI Time out interrupt
Kojto	101:7cff1c4259d7	458	* @arg QSPI_IT_SM: QSPI Status match interrupt
Kojto	101:7cff1c4259d7	459	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
Kojto	101:7cff1c4259d7	460	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
Kojto	101:7cff1c4259d7	461	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
Kojto	101:7cff1c4259d7	462	* @retval None
Kojto	101:7cff1c4259d7	463	*/
Kojto	101:7cff1c4259d7	464	#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Kojto	101:7cff1c4259d7	465
Kojto	101:7cff1c4259d7	466
Kojto	101:7cff1c4259d7	467	/** @brief Disables the specified QSPI interrupt.
Kojto	101:7cff1c4259d7	468	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	101:7cff1c4259d7	469	* @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
Kojto	101:7cff1c4259d7	470	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	471	* @arg QSPI_IT_TO: QSPI Timeout interrupt
Kojto	101:7cff1c4259d7	472	* @arg QSPI_IT_SM: QSPI Status match interrupt
Kojto	101:7cff1c4259d7	473	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
Kojto	101:7cff1c4259d7	474	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
Kojto	101:7cff1c4259d7	475	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
Kojto	101:7cff1c4259d7	476	* @retval None
Kojto	101:7cff1c4259d7	477	*/
Kojto	101:7cff1c4259d7	478	#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
Kojto	101:7cff1c4259d7	479
Kojto	101:7cff1c4259d7	480	/** @brief Checks whether the specified QSPI interrupt source is enabled.
Kojto	101:7cff1c4259d7	481	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	101:7cff1c4259d7	482	* @param __INTERRUPT__: specifies the QSPI interrupt source to check.
Kojto	101:7cff1c4259d7	483	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	484	* @arg QSPI_IT_TO: QSPI Time out interrupt
Kojto	101:7cff1c4259d7	485	* @arg QSPI_IT_SM: QSPI Status match interrupt
Kojto	101:7cff1c4259d7	486	* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
Kojto	101:7cff1c4259d7	487	* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
Kojto	101:7cff1c4259d7	488	* @arg QSPI_IT_TE: QSPI Transfer error interrupt
Kojto	101:7cff1c4259d7	489	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	101:7cff1c4259d7	490	*/
Kojto	101:7cff1c4259d7	491	#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	101:7cff1c4259d7	492
Kojto	101:7cff1c4259d7	493	/**
Kojto	101:7cff1c4259d7	494	* @brief Get the selected QSPI's flag status.
Kojto	101:7cff1c4259d7	495	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	101:7cff1c4259d7	496	* @param __FLAG__: specifies the QSPI flag to check.
Kojto	101:7cff1c4259d7	497	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	498	* @arg QSPI_FLAG_BUSY: QSPI Busy flag
Kojto	101:7cff1c4259d7	499	* @arg QSPI_FLAG_TO: QSPI Time out flag
Kojto	101:7cff1c4259d7	500	* @arg QSPI_FLAG_SM: QSPI Status match flag
Kojto	101:7cff1c4259d7	501	* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
Kojto	101:7cff1c4259d7	502	* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
Kojto	101:7cff1c4259d7	503	* @arg QSPI_FLAG_TE: QSPI Transfer error flag
Kojto	101:7cff1c4259d7	504	* @retval None
Kojto	101:7cff1c4259d7	505	*/
Kojto	122:f9eeca106725	506	#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U)
Kojto	101:7cff1c4259d7	507
Kojto	101:7cff1c4259d7	508	/** @brief Clears the specified QSPI's flag status.
Kojto	101:7cff1c4259d7	509	* @param __HANDLE__: specifies the QSPI Handle.
Kojto	101:7cff1c4259d7	510	* @param __FLAG__: specifies the QSPI clear register flag that needs to be set
Kojto	101:7cff1c4259d7	511	* This parameter can be one of the following values:
Kojto	101:7cff1c4259d7	512	* @arg QSPI_FLAG_TO: QSPI Time out flag
Kojto	101:7cff1c4259d7	513	* @arg QSPI_FLAG_SM: QSPI Status match flag
Kojto	101:7cff1c4259d7	514	* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
Kojto	101:7cff1c4259d7	515	* @arg QSPI_FLAG_TE: QSPI Transfer error flag
Kojto	101:7cff1c4259d7	516	* @retval None
Kojto	101:7cff1c4259d7	517	*/
Kojto	101:7cff1c4259d7	518	#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
Kojto	101:7cff1c4259d7	519	/**
Kojto	101:7cff1c4259d7	520	* @}
Kojto	101:7cff1c4259d7	521	*/
Kojto	101:7cff1c4259d7	522
Kojto	101:7cff1c4259d7	523	/* Exported functions --------------------------------------------------------*/
Kojto	101:7cff1c4259d7	524	/** @addtogroup QSPI_Exported_Functions
Kojto	101:7cff1c4259d7	525	* @{
Kojto	101:7cff1c4259d7	526	*/
Kojto	101:7cff1c4259d7	527
Kojto	101:7cff1c4259d7	528	/** @addtogroup QSPI_Exported_Functions_Group1
Kojto	101:7cff1c4259d7	529	* @{
Kojto	101:7cff1c4259d7	530	*/
Kojto	101:7cff1c4259d7	531	/* Initialization/de-initialization functions ********************************/
Kojto	101:7cff1c4259d7	532	HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	533	HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	534	void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	535	void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	536	/**
Kojto	101:7cff1c4259d7	537	* @}
Kojto	101:7cff1c4259d7	538	*/
Kojto	101:7cff1c4259d7	539
Kojto	101:7cff1c4259d7	540	/** @addtogroup QSPI_Exported_Functions_Group2
Kojto	101:7cff1c4259d7	541	* @{
Kojto	101:7cff1c4259d7	542	*/
Kojto	101:7cff1c4259d7	543	/* IO operation functions *****************************************************/
Kojto	101:7cff1c4259d7	544	/* QSPI IRQ handler method */
Kojto	101:7cff1c4259d7	545	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	546
Kojto	101:7cff1c4259d7	547	/* QSPI indirect mode */
Kojto	101:7cff1c4259d7	548	HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout);
Kojto	101:7cff1c4259d7	549	HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout);
Kojto	101:7cff1c4259d7	550	HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout);
Kojto	101:7cff1c4259d7	551	HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd);
Kojto	101:7cff1c4259d7	552	HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef hqspi, uint8_t pData);
Kojto	101:7cff1c4259d7	553	HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef hqspi, uint8_t pData);
Kojto	101:7cff1c4259d7	554	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef hqspi, uint8_t pData);
Kojto	101:7cff1c4259d7	555	HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef hqspi, uint8_t pData);
Kojto	101:7cff1c4259d7	556
Kojto	101:7cff1c4259d7	557	/* QSPI status flag polling mode */
Kojto	101:7cff1c4259d7	558	HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
Kojto	101:7cff1c4259d7	559	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg);
Kojto	101:7cff1c4259d7	560
Kojto	101:7cff1c4259d7	561	/* QSPI memory-mapped mode */
Kojto	101:7cff1c4259d7	562	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg);
Kojto	101:7cff1c4259d7	563	/**
Kojto	101:7cff1c4259d7	564	* @}
Kojto	101:7cff1c4259d7	565	*/
Kojto	101:7cff1c4259d7	566
Kojto	101:7cff1c4259d7	567	/** @addtogroup QSPI_Exported_Functions_Group3
Kojto	101:7cff1c4259d7	568	* @{
Kojto	101:7cff1c4259d7	569	*/
Kojto	101:7cff1c4259d7	570	/* Callback functions in non-blocking modes ***********************************/
Kojto	101:7cff1c4259d7	571	void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	572	void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	573	void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	574
Kojto	101:7cff1c4259d7	575	/* QSPI indirect mode */
Kojto	101:7cff1c4259d7	576	void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	577	void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	578	void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	579	void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	580	void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	581
Kojto	101:7cff1c4259d7	582	/* QSPI status flag polling mode */
Kojto	101:7cff1c4259d7	583	void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	584
Kojto	101:7cff1c4259d7	585	/* QSPI memory-mapped mode */
Kojto	101:7cff1c4259d7	586	void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	587	/**
Kojto	101:7cff1c4259d7	588	* @}
Kojto	101:7cff1c4259d7	589	*/
Kojto	101:7cff1c4259d7	590
Kojto	101:7cff1c4259d7	591	/** @addtogroup QSPI_Exported_Functions_Group4
Kojto	101:7cff1c4259d7	592	* @{
Kojto	101:7cff1c4259d7	593	*/
Kojto	101:7cff1c4259d7	594	/* Peripheral Control and State functions ************************************/
Kojto	122:f9eeca106725	595	HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	596	uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	597	HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	598	HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
Kojto	122:f9eeca106725	599	void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
Kojto	122:f9eeca106725	600	HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
Kojto	122:f9eeca106725	601	uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
Kojto	101:7cff1c4259d7	602	/**
Kojto	101:7cff1c4259d7	603	* @}
Kojto	101:7cff1c4259d7	604	*/
Kojto	101:7cff1c4259d7	605
Kojto	101:7cff1c4259d7	606	/* Private macros ------------------------------------------------------------*/
Kojto	101:7cff1c4259d7	607	/** @defgroup QSPI_Private_Macros QSPI Private Macros
Kojto	101:7cff1c4259d7	608	* @{
Kojto	101:7cff1c4259d7	609	*/
Kojto	101:7cff1c4259d7	610	/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler
Kojto	101:7cff1c4259d7	611	* @{
Kojto	101:7cff1c4259d7	612	*/
Kojto	122:f9eeca106725	613	#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
Kojto	101:7cff1c4259d7	614	/**
Kojto	101:7cff1c4259d7	615	* @}
Kojto	101:7cff1c4259d7	616	*/
Kojto	101:7cff1c4259d7	617
Kojto	101:7cff1c4259d7	618	/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold
Kojto	101:7cff1c4259d7	619	* @{
Kojto	101:7cff1c4259d7	620	*/
Kojto	122:f9eeca106725	621	#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U))
Kojto	101:7cff1c4259d7	622	/**
Kojto	101:7cff1c4259d7	623	* @}
Kojto	101:7cff1c4259d7	624	*/
Kojto	101:7cff1c4259d7	625
Kojto	101:7cff1c4259d7	626	#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) \|\| \
Kojto	101:7cff1c4259d7	627	((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
Kojto	101:7cff1c4259d7	628
Kojto	101:7cff1c4259d7	629	/** @defgroup QSPI_FlashSize QSPI Flash Size
Kojto	101:7cff1c4259d7	630	* @{
Kojto	101:7cff1c4259d7	631	*/
Kojto	122:f9eeca106725	632	#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
Kojto	101:7cff1c4259d7	633	/**
Kojto	101:7cff1c4259d7	634	* @}
Kojto	101:7cff1c4259d7	635	*/
Kojto	101:7cff1c4259d7	636
Kojto	101:7cff1c4259d7	637	#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) \|\| \
Kojto	101:7cff1c4259d7	638	((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) \|\| \
Kojto	101:7cff1c4259d7	639	((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) \|\| \
Kojto	101:7cff1c4259d7	640	((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) \|\| \
Kojto	101:7cff1c4259d7	641	((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) \|\| \
Kojto	101:7cff1c4259d7	642	((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) \|\| \
Kojto	101:7cff1c4259d7	643	((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) \|\| \
Kojto	101:7cff1c4259d7	644	((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
Kojto	101:7cff1c4259d7	645
Kojto	101:7cff1c4259d7	646	#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) \|\| \
Kojto	101:7cff1c4259d7	647	((CLKMODE) == QSPI_CLOCK_MODE_3))
Kojto	101:7cff1c4259d7	648
Kojto	101:7cff1c4259d7	649	#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) \|\| \
Kojto	101:7cff1c4259d7	650	((FLA) == QSPI_FLASH_ID_2))
Kojto	101:7cff1c4259d7	651
Kojto	101:7cff1c4259d7	652	#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) \|\| \
Kojto	101:7cff1c4259d7	653	((MODE) == QSPI_DUALFLASH_DISABLE))
Kojto	101:7cff1c4259d7	654
Kojto	101:7cff1c4259d7	655
Kojto	101:7cff1c4259d7	656	/** @defgroup QSPI_Instruction QSPI Instruction
Kojto	101:7cff1c4259d7	657	* @{
Kojto	101:7cff1c4259d7	658	*/
Kojto	122:f9eeca106725	659	#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
Kojto	101:7cff1c4259d7	660	/**
Kojto	101:7cff1c4259d7	661	* @}
Kojto	101:7cff1c4259d7	662	*/
Kojto	101:7cff1c4259d7	663
Kojto	101:7cff1c4259d7	664	#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) \|\| \
Kojto	101:7cff1c4259d7	665	((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) \|\| \
Kojto	101:7cff1c4259d7	666	((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) \|\| \
Kojto	101:7cff1c4259d7	667	((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
Kojto	101:7cff1c4259d7	668
Kojto	101:7cff1c4259d7	669	#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) \|\| \
Kojto	101:7cff1c4259d7	670	((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) \|\| \
Kojto	101:7cff1c4259d7	671	((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) \|\| \
Kojto	122:f9eeca106725	672	((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
Kojto	101:7cff1c4259d7	673
Kojto	101:7cff1c4259d7	674
Kojto	101:7cff1c4259d7	675	/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles
Kojto	101:7cff1c4259d7	676	* @{
Kojto	101:7cff1c4259d7	677	*/
Kojto	122:f9eeca106725	678	#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
Kojto	101:7cff1c4259d7	679	/**
Kojto	101:7cff1c4259d7	680	* @}
Kojto	101:7cff1c4259d7	681	*/
Kojto	101:7cff1c4259d7	682
Kojto	101:7cff1c4259d7	683	#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) \|\| \
Kojto	101:7cff1c4259d7	684	((MODE) == QSPI_INSTRUCTION_1_LINE) \|\| \
Kojto	101:7cff1c4259d7	685	((MODE) == QSPI_INSTRUCTION_2_LINES) \|\| \
Kojto	101:7cff1c4259d7	686	((MODE) == QSPI_INSTRUCTION_4_LINES))
Kojto	101:7cff1c4259d7	687
Kojto	101:7cff1c4259d7	688	#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) \|\| \
Kojto	101:7cff1c4259d7	689	((MODE) == QSPI_ADDRESS_1_LINE) \|\| \
Kojto	101:7cff1c4259d7	690	((MODE) == QSPI_ADDRESS_2_LINES) \|\| \
Kojto	101:7cff1c4259d7	691	((MODE) == QSPI_ADDRESS_4_LINES))
Kojto	101:7cff1c4259d7	692
Kojto	101:7cff1c4259d7	693	#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) \|\| \
Kojto	101:7cff1c4259d7	694	((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) \|\| \
Kojto	101:7cff1c4259d7	695	((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) \|\| \
Kojto	101:7cff1c4259d7	696	((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
Kojto	101:7cff1c4259d7	697
Kojto	101:7cff1c4259d7	698	#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) \|\| \
Kojto	101:7cff1c4259d7	699	((MODE) == QSPI_DATA_1_LINE) \|\| \
Kojto	101:7cff1c4259d7	700	((MODE) == QSPI_DATA_2_LINES) \|\| \
Kojto	101:7cff1c4259d7	701	((MODE) == QSPI_DATA_4_LINES))
Kojto	101:7cff1c4259d7	702
Kojto	101:7cff1c4259d7	703	#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	704	((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
Kojto	101:7cff1c4259d7	705
Kojto	101:7cff1c4259d7	706	#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) \|\| \
Kojto	101:7cff1c4259d7	707	((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
Kojto	101:7cff1c4259d7	708
Kojto	101:7cff1c4259d7	709	#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) \|\| \
Kojto	101:7cff1c4259d7	710	((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
Kojto	101:7cff1c4259d7	711
Kojto	101:7cff1c4259d7	712	/** @defgroup QSPI_Interval QSPI Interval
Kojto	101:7cff1c4259d7	713	* @{
Kojto	101:7cff1c4259d7	714	*/
Kojto	101:7cff1c4259d7	715	#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
Kojto	101:7cff1c4259d7	716	/**
Kojto	101:7cff1c4259d7	717	* @}
Kojto	101:7cff1c4259d7	718	*/
Kojto	101:7cff1c4259d7	719
Kojto	101:7cff1c4259d7	720	/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size
Kojto	101:7cff1c4259d7	721	* @{
Kojto	101:7cff1c4259d7	722	*/
Kojto	122:f9eeca106725	723	#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
Kojto	101:7cff1c4259d7	724	/**
Kojto	101:7cff1c4259d7	725	* @}
Kojto	101:7cff1c4259d7	726	*/
Kojto	101:7cff1c4259d7	727	#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) \|\| \
Kojto	101:7cff1c4259d7	728	((MODE) == QSPI_MATCH_MODE_OR))
Kojto	101:7cff1c4259d7	729
Kojto	101:7cff1c4259d7	730	#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	731	((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
Kojto	101:7cff1c4259d7	732
Kojto	101:7cff1c4259d7	733	#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) \|\| \
Kojto	101:7cff1c4259d7	734	((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
Kojto	101:7cff1c4259d7	735
Kojto	101:7cff1c4259d7	736	/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period
Kojto	101:7cff1c4259d7	737	* @{
Kojto	101:7cff1c4259d7	738	*/
Kojto	122:f9eeca106725	739	#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
Kojto	101:7cff1c4259d7	740	/**
Kojto	101:7cff1c4259d7	741	* @}
Kojto	101:7cff1c4259d7	742	*/
Kojto	101:7cff1c4259d7	743
Kojto	101:7cff1c4259d7	744	#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) \|\| \
Kojto	101:7cff1c4259d7	745	((FLAG) == QSPI_FLAG_TO) \|\| \
Kojto	101:7cff1c4259d7	746	((FLAG) == QSPI_FLAG_SM) \|\| \
Kojto	101:7cff1c4259d7	747	((FLAG) == QSPI_FLAG_FT) \|\| \
Kojto	101:7cff1c4259d7	748	((FLAG) == QSPI_FLAG_TC) \|\| \
Kojto	101:7cff1c4259d7	749	((FLAG) == QSPI_FLAG_TE))
Kojto	101:7cff1c4259d7	750
Kojto	122:f9eeca106725	751	#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
Kojto	101:7cff1c4259d7	752	/**
Kojto	101:7cff1c4259d7	753	* @}
Kojto	101:7cff1c4259d7	754	*/
Kojto	101:7cff1c4259d7	755
Kojto	101:7cff1c4259d7	756	/* Private functions ---------------------------------------------------------*/
Kojto	101:7cff1c4259d7	757	/** @defgroup QSPI_Private_Functions QSPI Private Functions
Kojto	101:7cff1c4259d7	758	* @{
Kojto	101:7cff1c4259d7	759	*/
Kojto	101:7cff1c4259d7	760
Kojto	101:7cff1c4259d7	761	/**
Kojto	101:7cff1c4259d7	762	* @}
Kojto	101:7cff1c4259d7	763	*/
Kojto	101:7cff1c4259d7	764
Kojto	101:7cff1c4259d7	765	/**
Kojto	101:7cff1c4259d7	766	* @}
Kojto	101:7cff1c4259d7	767	*/
Kojto	101:7cff1c4259d7	768
Kojto	101:7cff1c4259d7	769	/**
Kojto	101:7cff1c4259d7	770	* @}
Kojto	101:7cff1c4259d7	771	*/
Kojto	122:f9eeca106725	772
Kojto	122:f9eeca106725	773	/**
Kojto	122:f9eeca106725	774	* @}
Kojto	122:f9eeca106725	775	*/
Kojto	122:f9eeca106725	776	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\| STM32F412Rx */
Kojto	101:7cff1c4259d7	777
Kojto	101:7cff1c4259d7	778	#ifdef __cplusplus
Kojto	101:7cff1c4259d7	779	}
Kojto	101:7cff1c4259d7	780	#endif
Kojto	101:7cff1c4259d7	781
Kojto	101:7cff1c4259d7	782	#endif /* __STM32F4xx_HAL_QSPI_H */
Kojto	101:7cff1c4259d7	783
Kojto	101:7cff1c4259d7	784	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Repository details

Type:	Library
Created:	17 Jan 2017
Imports:	0
Forks:	0
Commits:	136
Dependents:	0
Dependencies:	0
Followers:	1

Important changes to repositories hosted on mbed.com

TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_qspi.h@122:f9eeca106725, 2016-07-07 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

TARGET_MTS_DRAGONFLY_F411RE/stm32f4xx_hal_qspi.h@122:f9eeca106725, 2016-07-07 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning