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TARGET_KL05Z/core_cm4.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
110:165afa46840b
Child:
128:9bcdf88f62b0
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 78:ed8466a608b4 1 /**************************************************************************//**
emilmont 78:ed8466a608b4 2 * @file core_cm4.h
emilmont 78:ed8466a608b4 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
emilmont 78:ed8466a608b4 6 *
emilmont 78:ed8466a608b4 7 * @note
emilmont 78:ed8466a608b4 8 *
emilmont 78:ed8466a608b4 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont 78:ed8466a608b4 11
emilmont 78:ed8466a608b4 12 All rights reserved.
emilmont 78:ed8466a608b4 13 Redistribution and use in source and binary forms, with or without
emilmont 78:ed8466a608b4 14 modification, are permitted provided that the following conditions are met:
emilmont 78:ed8466a608b4 15 - Redistributions of source code must retain the above copyright
emilmont 78:ed8466a608b4 16 notice, this list of conditions and the following disclaimer.
emilmont 78:ed8466a608b4 17 - Redistributions in binary form must reproduce the above copyright
emilmont 78:ed8466a608b4 18 notice, this list of conditions and the following disclaimer in the
emilmont 78:ed8466a608b4 19 documentation and/or other materials provided with the distribution.
emilmont 78:ed8466a608b4 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 78:ed8466a608b4 21 to endorse or promote products derived from this software without
emilmont 78:ed8466a608b4 22 specific prior written permission.
emilmont 78:ed8466a608b4 23 *
emilmont 78:ed8466a608b4 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 78:ed8466a608b4 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 78:ed8466a608b4 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 78:ed8466a608b4 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 78:ed8466a608b4 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 78:ed8466a608b4 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 78:ed8466a608b4 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 78:ed8466a608b4 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 78:ed8466a608b4 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 78:ed8466a608b4 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 78:ed8466a608b4 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 78:ed8466a608b4 35 ---------------------------------------------------------------------------*/
emilmont 78:ed8466a608b4 36
emilmont 78:ed8466a608b4 37
emilmont 78:ed8466a608b4 38 #if defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 78:ed8466a608b4 40 #endif
emilmont 78:ed8466a608b4 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM4_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM4_H_GENERIC
Kojto 110:165afa46840b 44
emilmont 78:ed8466a608b4 45 #ifdef __cplusplus
emilmont 78:ed8466a608b4 46 extern "C" {
emilmont 78:ed8466a608b4 47 #endif
emilmont 78:ed8466a608b4 48
emilmont 78:ed8466a608b4 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 78:ed8466a608b4 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 78:ed8466a608b4 51
emilmont 78:ed8466a608b4 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 78:ed8466a608b4 53 Function definitions in header files are used to allow 'inlining'.
emilmont 78:ed8466a608b4 54
emilmont 78:ed8466a608b4 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 78:ed8466a608b4 56 Unions are used for effective representation of core registers.
emilmont 78:ed8466a608b4 57
emilmont 78:ed8466a608b4 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 78:ed8466a608b4 59 Function-like macros are used to allow more efficient code.
emilmont 78:ed8466a608b4 60 */
emilmont 78:ed8466a608b4 61
emilmont 78:ed8466a608b4 62
emilmont 78:ed8466a608b4 63 /*******************************************************************************
emilmont 78:ed8466a608b4 64 * CMSIS definitions
emilmont 78:ed8466a608b4 65 ******************************************************************************/
emilmont 78:ed8466a608b4 66 /** \ingroup Cortex_M4
emilmont 78:ed8466a608b4 67 @{
emilmont 78:ed8466a608b4 68 */
emilmont 78:ed8466a608b4 69
emilmont 78:ed8466a608b4 70 /* CMSIS CM4 definitions */
Kojto 110:165afa46840b 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
emilmont 78:ed8466a608b4 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
emilmont 78:ed8466a608b4 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 78:ed8466a608b4 75
emilmont 78:ed8466a608b4 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
emilmont 78:ed8466a608b4 77
emilmont 78:ed8466a608b4 78
emilmont 78:ed8466a608b4 79 #if defined ( __CC_ARM )
emilmont 78:ed8466a608b4 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 78:ed8466a608b4 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 78:ed8466a608b4 82 #define __STATIC_INLINE static __inline
emilmont 78:ed8466a608b4 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
emilmont 78:ed8466a608b4 89 #elif defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 78:ed8466a608b4 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 78:ed8466a608b4 92 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 93
emilmont 78:ed8466a608b4 94 #elif defined ( __TMS470__ )
emilmont 78:ed8466a608b4 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emilmont 78:ed8466a608b4 96 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 97
emilmont 78:ed8466a608b4 98 #elif defined ( __TASKING__ )
emilmont 78:ed8466a608b4 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 78:ed8466a608b4 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 78:ed8466a608b4 101 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
emilmont 78:ed8466a608b4 109 #endif
emilmont 78:ed8466a608b4 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
emilmont 78:ed8466a608b4 113 */
emilmont 78:ed8466a608b4 114 #if defined ( __CC_ARM )
emilmont 78:ed8466a608b4 115 #if defined __TARGET_FPU_VFP
emilmont 78:ed8466a608b4 116 #if (__FPU_PRESENT == 1)
emilmont 78:ed8466a608b4 117 #define __FPU_USED 1
emilmont 78:ed8466a608b4 118 #else
emilmont 78:ed8466a608b4 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 120 #define __FPU_USED 0
emilmont 78:ed8466a608b4 121 #endif
emilmont 78:ed8466a608b4 122 #else
emilmont 78:ed8466a608b4 123 #define __FPU_USED 0
emilmont 78:ed8466a608b4 124 #endif
emilmont 78:ed8466a608b4 125
Kojto 110:165afa46840b 126 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 128 #if (__FPU_PRESENT == 1)
Kojto 110:165afa46840b 129 #define __FPU_USED 1
Kojto 110:165afa46840b 130 #else
Kojto 110:165afa46840b 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 132 #define __FPU_USED 0
Kojto 110:165afa46840b 133 #endif
Kojto 110:165afa46840b 134 #else
Kojto 110:165afa46840b 135 #define __FPU_USED 0
Kojto 110:165afa46840b 136 #endif
Kojto 110:165afa46840b 137
emilmont 78:ed8466a608b4 138 #elif defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 139 #if defined __ARMVFP__
emilmont 78:ed8466a608b4 140 #if (__FPU_PRESENT == 1)
emilmont 78:ed8466a608b4 141 #define __FPU_USED 1
emilmont 78:ed8466a608b4 142 #else
emilmont 78:ed8466a608b4 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 144 #define __FPU_USED 0
emilmont 78:ed8466a608b4 145 #endif
emilmont 78:ed8466a608b4 146 #else
emilmont 78:ed8466a608b4 147 #define __FPU_USED 0
emilmont 78:ed8466a608b4 148 #endif
emilmont 78:ed8466a608b4 149
emilmont 78:ed8466a608b4 150 #elif defined ( __TMS470__ )
emilmont 78:ed8466a608b4 151 #if defined __TI_VFP_SUPPORT__
emilmont 78:ed8466a608b4 152 #if (__FPU_PRESENT == 1)
emilmont 78:ed8466a608b4 153 #define __FPU_USED 1
emilmont 78:ed8466a608b4 154 #else
emilmont 78:ed8466a608b4 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 156 #define __FPU_USED 0
emilmont 78:ed8466a608b4 157 #endif
emilmont 78:ed8466a608b4 158 #else
emilmont 78:ed8466a608b4 159 #define __FPU_USED 0
emilmont 78:ed8466a608b4 160 #endif
emilmont 78:ed8466a608b4 161
Kojto 110:165afa46840b 162 #elif defined ( __TASKING__ )
Kojto 110:165afa46840b 163 #if defined __FPU_VFP__
emilmont 78:ed8466a608b4 164 #if (__FPU_PRESENT == 1)
emilmont 78:ed8466a608b4 165 #define __FPU_USED 1
emilmont 78:ed8466a608b4 166 #else
Kojto 110:165afa46840b 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 168 #define __FPU_USED 0
emilmont 78:ed8466a608b4 169 #endif
emilmont 78:ed8466a608b4 170 #else
emilmont 78:ed8466a608b4 171 #define __FPU_USED 0
emilmont 78:ed8466a608b4 172 #endif
emilmont 78:ed8466a608b4 173
Kojto 110:165afa46840b 174 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 175 #if ( __CSMC__ & 0x400) // FPU present for parser
emilmont 78:ed8466a608b4 176 #if (__FPU_PRESENT == 1)
emilmont 78:ed8466a608b4 177 #define __FPU_USED 1
emilmont 78:ed8466a608b4 178 #else
emilmont 78:ed8466a608b4 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 180 #define __FPU_USED 0
emilmont 78:ed8466a608b4 181 #endif
emilmont 78:ed8466a608b4 182 #else
emilmont 78:ed8466a608b4 183 #define __FPU_USED 0
emilmont 78:ed8466a608b4 184 #endif
emilmont 78:ed8466a608b4 185 #endif
emilmont 78:ed8466a608b4 186
emilmont 78:ed8466a608b4 187 #include <stdint.h> /* standard types definitions */
emilmont 78:ed8466a608b4 188 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 78:ed8466a608b4 189 #include <core_cmFunc.h> /* Core Function Access */
Kojto 110:165afa46840b 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
Kojto 110:165afa46840b 191
Kojto 110:165afa46840b 192 #ifdef __cplusplus
Kojto 110:165afa46840b 193 }
Kojto 110:165afa46840b 194 #endif
emilmont 78:ed8466a608b4 195
emilmont 78:ed8466a608b4 196 #endif /* __CORE_CM4_H_GENERIC */
emilmont 78:ed8466a608b4 197
emilmont 78:ed8466a608b4 198 #ifndef __CMSIS_GENERIC
emilmont 78:ed8466a608b4 199
emilmont 78:ed8466a608b4 200 #ifndef __CORE_CM4_H_DEPENDANT
emilmont 78:ed8466a608b4 201 #define __CORE_CM4_H_DEPENDANT
emilmont 78:ed8466a608b4 202
Kojto 110:165afa46840b 203 #ifdef __cplusplus
Kojto 110:165afa46840b 204 extern "C" {
Kojto 110:165afa46840b 205 #endif
Kojto 110:165afa46840b 206
emilmont 78:ed8466a608b4 207 /* check device defines and use defaults */
emilmont 78:ed8466a608b4 208 #if defined __CHECK_DEVICE_DEFINES
emilmont 78:ed8466a608b4 209 #ifndef __CM4_REV
emilmont 78:ed8466a608b4 210 #define __CM4_REV 0x0000
emilmont 78:ed8466a608b4 211 #warning "__CM4_REV not defined in device header file; using default!"
emilmont 78:ed8466a608b4 212 #endif
emilmont 78:ed8466a608b4 213
emilmont 78:ed8466a608b4 214 #ifndef __FPU_PRESENT
emilmont 78:ed8466a608b4 215 #define __FPU_PRESENT 0
emilmont 78:ed8466a608b4 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
emilmont 78:ed8466a608b4 217 #endif
emilmont 78:ed8466a608b4 218
emilmont 78:ed8466a608b4 219 #ifndef __MPU_PRESENT
emilmont 78:ed8466a608b4 220 #define __MPU_PRESENT 0
emilmont 78:ed8466a608b4 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 78:ed8466a608b4 222 #endif
emilmont 78:ed8466a608b4 223
emilmont 78:ed8466a608b4 224 #ifndef __NVIC_PRIO_BITS
emilmont 78:ed8466a608b4 225 #define __NVIC_PRIO_BITS 4
emilmont 78:ed8466a608b4 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 78:ed8466a608b4 227 #endif
emilmont 78:ed8466a608b4 228
emilmont 78:ed8466a608b4 229 #ifndef __Vendor_SysTickConfig
emilmont 78:ed8466a608b4 230 #define __Vendor_SysTickConfig 0
emilmont 78:ed8466a608b4 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 78:ed8466a608b4 232 #endif
emilmont 78:ed8466a608b4 233 #endif
emilmont 78:ed8466a608b4 234
emilmont 78:ed8466a608b4 235 /* IO definitions (access restrictions to peripheral registers) */
emilmont 78:ed8466a608b4 236 /**
emilmont 78:ed8466a608b4 237 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 78:ed8466a608b4 238
emilmont 78:ed8466a608b4 239 <strong>IO Type Qualifiers</strong> are used
emilmont 78:ed8466a608b4 240 \li to specify the access to peripheral variables.
emilmont 78:ed8466a608b4 241 \li for automatic generation of peripheral register debug information.
emilmont 78:ed8466a608b4 242 */
emilmont 78:ed8466a608b4 243 #ifdef __cplusplus
emilmont 78:ed8466a608b4 244 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 78:ed8466a608b4 245 #else
emilmont 78:ed8466a608b4 246 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 78:ed8466a608b4 247 #endif
emilmont 78:ed8466a608b4 248 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 78:ed8466a608b4 249 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 78:ed8466a608b4 250
emilmont 78:ed8466a608b4 251 /*@} end of group Cortex_M4 */
emilmont 78:ed8466a608b4 252
emilmont 78:ed8466a608b4 253
emilmont 78:ed8466a608b4 254
emilmont 78:ed8466a608b4 255 /*******************************************************************************
emilmont 78:ed8466a608b4 256 * Register Abstraction
emilmont 78:ed8466a608b4 257 Core Register contain:
emilmont 78:ed8466a608b4 258 - Core Register
emilmont 78:ed8466a608b4 259 - Core NVIC Register
emilmont 78:ed8466a608b4 260 - Core SCB Register
emilmont 78:ed8466a608b4 261 - Core SysTick Register
emilmont 78:ed8466a608b4 262 - Core Debug Register
emilmont 78:ed8466a608b4 263 - Core MPU Register
emilmont 78:ed8466a608b4 264 - Core FPU Register
emilmont 78:ed8466a608b4 265 ******************************************************************************/
emilmont 78:ed8466a608b4 266 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 78:ed8466a608b4 267 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 78:ed8466a608b4 268 */
emilmont 78:ed8466a608b4 269
emilmont 78:ed8466a608b4 270 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 271 \defgroup CMSIS_CORE Status and Control Registers
emilmont 78:ed8466a608b4 272 \brief Core Register type definitions.
emilmont 78:ed8466a608b4 273 @{
emilmont 78:ed8466a608b4 274 */
emilmont 78:ed8466a608b4 275
emilmont 78:ed8466a608b4 276 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 78:ed8466a608b4 277 */
emilmont 78:ed8466a608b4 278 typedef union
emilmont 78:ed8466a608b4 279 {
emilmont 78:ed8466a608b4 280 struct
emilmont 78:ed8466a608b4 281 {
emilmont 78:ed8466a608b4 282 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 78:ed8466a608b4 283 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 78:ed8466a608b4 284 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 78:ed8466a608b4 285 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 78:ed8466a608b4 286 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 78:ed8466a608b4 287 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 78:ed8466a608b4 288 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 78:ed8466a608b4 289 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 78:ed8466a608b4 290 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 291 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 292 } APSR_Type;
emilmont 78:ed8466a608b4 293
Kojto 110:165afa46840b 294 /* APSR Register Definitions */
Kojto 110:165afa46840b 295 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 296 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 297
Kojto 110:165afa46840b 298 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 299 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 300
Kojto 110:165afa46840b 301 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 302 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 303
Kojto 110:165afa46840b 304 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 305 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 306
Kojto 110:165afa46840b 307 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
Kojto 110:165afa46840b 308 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
Kojto 110:165afa46840b 309
Kojto 110:165afa46840b 310 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
Kojto 110:165afa46840b 311 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
Kojto 110:165afa46840b 312
emilmont 78:ed8466a608b4 313
emilmont 78:ed8466a608b4 314 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 78:ed8466a608b4 315 */
emilmont 78:ed8466a608b4 316 typedef union
emilmont 78:ed8466a608b4 317 {
emilmont 78:ed8466a608b4 318 struct
emilmont 78:ed8466a608b4 319 {
emilmont 78:ed8466a608b4 320 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 78:ed8466a608b4 321 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 78:ed8466a608b4 322 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 323 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 324 } IPSR_Type;
emilmont 78:ed8466a608b4 325
Kojto 110:165afa46840b 326 /* IPSR Register Definitions */
Kojto 110:165afa46840b 327 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 328 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 329
emilmont 78:ed8466a608b4 330
emilmont 78:ed8466a608b4 331 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 78:ed8466a608b4 332 */
emilmont 78:ed8466a608b4 333 typedef union
emilmont 78:ed8466a608b4 334 {
emilmont 78:ed8466a608b4 335 struct
emilmont 78:ed8466a608b4 336 {
emilmont 78:ed8466a608b4 337 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 78:ed8466a608b4 338 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 78:ed8466a608b4 339 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 78:ed8466a608b4 340 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 78:ed8466a608b4 341 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 78:ed8466a608b4 342 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 78:ed8466a608b4 343 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 78:ed8466a608b4 344 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 78:ed8466a608b4 345 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 78:ed8466a608b4 346 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 78:ed8466a608b4 347 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 78:ed8466a608b4 348 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 349 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 350 } xPSR_Type;
emilmont 78:ed8466a608b4 351
Kojto 110:165afa46840b 352 /* xPSR Register Definitions */
Kojto 110:165afa46840b 353 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 354 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 355
Kojto 110:165afa46840b 356 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 357 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 358
Kojto 110:165afa46840b 359 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 360 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 361
Kojto 110:165afa46840b 362 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 363 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 364
Kojto 110:165afa46840b 365 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
Kojto 110:165afa46840b 366 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
Kojto 110:165afa46840b 367
Kojto 110:165afa46840b 368 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
Kojto 110:165afa46840b 369 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
Kojto 110:165afa46840b 370
Kojto 110:165afa46840b 371 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 372 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 373
Kojto 110:165afa46840b 374 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
Kojto 110:165afa46840b 375 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
Kojto 110:165afa46840b 376
Kojto 110:165afa46840b 377 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 378 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 379
emilmont 78:ed8466a608b4 380
emilmont 78:ed8466a608b4 381 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 78:ed8466a608b4 382 */
emilmont 78:ed8466a608b4 383 typedef union
emilmont 78:ed8466a608b4 384 {
emilmont 78:ed8466a608b4 385 struct
emilmont 78:ed8466a608b4 386 {
emilmont 78:ed8466a608b4 387 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 78:ed8466a608b4 388 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 78:ed8466a608b4 389 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 78:ed8466a608b4 390 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 78:ed8466a608b4 391 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 392 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 393 } CONTROL_Type;
emilmont 78:ed8466a608b4 394
Kojto 110:165afa46840b 395 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 396 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
Kojto 110:165afa46840b 397 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
Kojto 110:165afa46840b 398
Kojto 110:165afa46840b 399 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 400 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 401
Kojto 110:165afa46840b 402 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
Kojto 110:165afa46840b 403 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
Kojto 110:165afa46840b 404
emilmont 78:ed8466a608b4 405 /*@} end of group CMSIS_CORE */
emilmont 78:ed8466a608b4 406
emilmont 78:ed8466a608b4 407
emilmont 78:ed8466a608b4 408 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 409 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 78:ed8466a608b4 410 \brief Type definitions for the NVIC Registers
emilmont 78:ed8466a608b4 411 @{
emilmont 78:ed8466a608b4 412 */
emilmont 78:ed8466a608b4 413
emilmont 78:ed8466a608b4 414 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 78:ed8466a608b4 415 */
emilmont 78:ed8466a608b4 416 typedef struct
emilmont 78:ed8466a608b4 417 {
emilmont 78:ed8466a608b4 418 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 78:ed8466a608b4 419 uint32_t RESERVED0[24];
emilmont 78:ed8466a608b4 420 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 78:ed8466a608b4 421 uint32_t RSERVED1[24];
emilmont 78:ed8466a608b4 422 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 78:ed8466a608b4 423 uint32_t RESERVED2[24];
emilmont 78:ed8466a608b4 424 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 78:ed8466a608b4 425 uint32_t RESERVED3[24];
emilmont 78:ed8466a608b4 426 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
emilmont 78:ed8466a608b4 427 uint32_t RESERVED4[56];
emilmont 78:ed8466a608b4 428 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
emilmont 78:ed8466a608b4 429 uint32_t RESERVED5[644];
emilmont 78:ed8466a608b4 430 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
emilmont 78:ed8466a608b4 431 } NVIC_Type;
emilmont 78:ed8466a608b4 432
emilmont 78:ed8466a608b4 433 /* Software Triggered Interrupt Register Definitions */
emilmont 78:ed8466a608b4 434 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
Kojto 110:165afa46840b 435 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
emilmont 78:ed8466a608b4 436
emilmont 78:ed8466a608b4 437 /*@} end of group CMSIS_NVIC */
emilmont 78:ed8466a608b4 438
emilmont 78:ed8466a608b4 439
emilmont 78:ed8466a608b4 440 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 441 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 78:ed8466a608b4 442 \brief Type definitions for the System Control Block Registers
emilmont 78:ed8466a608b4 443 @{
emilmont 78:ed8466a608b4 444 */
emilmont 78:ed8466a608b4 445
emilmont 78:ed8466a608b4 446 /** \brief Structure type to access the System Control Block (SCB).
emilmont 78:ed8466a608b4 447 */
emilmont 78:ed8466a608b4 448 typedef struct
emilmont 78:ed8466a608b4 449 {
emilmont 78:ed8466a608b4 450 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 78:ed8466a608b4 451 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 78:ed8466a608b4 452 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 78:ed8466a608b4 453 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 78:ed8466a608b4 454 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 78:ed8466a608b4 455 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 78:ed8466a608b4 456 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
emilmont 78:ed8466a608b4 457 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 78:ed8466a608b4 458 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
emilmont 78:ed8466a608b4 459 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
emilmont 78:ed8466a608b4 460 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
emilmont 78:ed8466a608b4 461 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
emilmont 78:ed8466a608b4 462 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
emilmont 78:ed8466a608b4 463 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
emilmont 78:ed8466a608b4 464 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
emilmont 78:ed8466a608b4 465 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
emilmont 78:ed8466a608b4 466 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
emilmont 78:ed8466a608b4 467 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
emilmont 78:ed8466a608b4 468 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
emilmont 78:ed8466a608b4 469 uint32_t RESERVED0[5];
emilmont 78:ed8466a608b4 470 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
emilmont 78:ed8466a608b4 471 } SCB_Type;
emilmont 78:ed8466a608b4 472
emilmont 78:ed8466a608b4 473 /* SCB CPUID Register Definitions */
emilmont 78:ed8466a608b4 474 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 78:ed8466a608b4 475 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 78:ed8466a608b4 476
emilmont 78:ed8466a608b4 477 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 78:ed8466a608b4 478 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 78:ed8466a608b4 479
emilmont 78:ed8466a608b4 480 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 78:ed8466a608b4 481 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 78:ed8466a608b4 482
emilmont 78:ed8466a608b4 483 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 78:ed8466a608b4 484 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 78:ed8466a608b4 485
emilmont 78:ed8466a608b4 486 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 487 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
emilmont 78:ed8466a608b4 488
emilmont 78:ed8466a608b4 489 /* SCB Interrupt Control State Register Definitions */
emilmont 78:ed8466a608b4 490 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 78:ed8466a608b4 491 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 78:ed8466a608b4 492
emilmont 78:ed8466a608b4 493 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 78:ed8466a608b4 494 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 78:ed8466a608b4 495
emilmont 78:ed8466a608b4 496 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 78:ed8466a608b4 497 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 78:ed8466a608b4 498
emilmont 78:ed8466a608b4 499 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 78:ed8466a608b4 500 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 78:ed8466a608b4 501
emilmont 78:ed8466a608b4 502 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 78:ed8466a608b4 503 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 78:ed8466a608b4 504
emilmont 78:ed8466a608b4 505 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 78:ed8466a608b4 506 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 78:ed8466a608b4 507
emilmont 78:ed8466a608b4 508 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 78:ed8466a608b4 509 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 78:ed8466a608b4 510
emilmont 78:ed8466a608b4 511 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 78:ed8466a608b4 512 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 78:ed8466a608b4 513
emilmont 78:ed8466a608b4 514 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
emilmont 78:ed8466a608b4 515 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
emilmont 78:ed8466a608b4 516
emilmont 78:ed8466a608b4 517 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 518 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 78:ed8466a608b4 519
emilmont 78:ed8466a608b4 520 /* SCB Vector Table Offset Register Definitions */
emilmont 78:ed8466a608b4 521 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
emilmont 78:ed8466a608b4 522 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 78:ed8466a608b4 523
emilmont 78:ed8466a608b4 524 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 78:ed8466a608b4 525 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 78:ed8466a608b4 526 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 78:ed8466a608b4 527
emilmont 78:ed8466a608b4 528 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 78:ed8466a608b4 529 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 78:ed8466a608b4 530
emilmont 78:ed8466a608b4 531 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 78:ed8466a608b4 532 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 78:ed8466a608b4 533
emilmont 78:ed8466a608b4 534 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
emilmont 78:ed8466a608b4 535 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
emilmont 78:ed8466a608b4 536
emilmont 78:ed8466a608b4 537 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 78:ed8466a608b4 538 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 78:ed8466a608b4 539
emilmont 78:ed8466a608b4 540 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 78:ed8466a608b4 541 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 78:ed8466a608b4 542
emilmont 78:ed8466a608b4 543 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
Kojto 110:165afa46840b 544 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
emilmont 78:ed8466a608b4 545
emilmont 78:ed8466a608b4 546 /* SCB System Control Register Definitions */
emilmont 78:ed8466a608b4 547 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 78:ed8466a608b4 548 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 78:ed8466a608b4 549
emilmont 78:ed8466a608b4 550 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 78:ed8466a608b4 551 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 78:ed8466a608b4 552
emilmont 78:ed8466a608b4 553 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 78:ed8466a608b4 554 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 78:ed8466a608b4 555
emilmont 78:ed8466a608b4 556 /* SCB Configuration Control Register Definitions */
emilmont 78:ed8466a608b4 557 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 78:ed8466a608b4 558 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 78:ed8466a608b4 559
emilmont 78:ed8466a608b4 560 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
emilmont 78:ed8466a608b4 561 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
emilmont 78:ed8466a608b4 562
emilmont 78:ed8466a608b4 563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
emilmont 78:ed8466a608b4 564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
emilmont 78:ed8466a608b4 565
emilmont 78:ed8466a608b4 566 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 78:ed8466a608b4 567 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 78:ed8466a608b4 568
emilmont 78:ed8466a608b4 569 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
emilmont 78:ed8466a608b4 570 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
emilmont 78:ed8466a608b4 571
emilmont 78:ed8466a608b4 572 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
Kojto 110:165afa46840b 573 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
emilmont 78:ed8466a608b4 574
emilmont 78:ed8466a608b4 575 /* SCB System Handler Control and State Register Definitions */
emilmont 78:ed8466a608b4 576 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
emilmont 78:ed8466a608b4 577 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
emilmont 78:ed8466a608b4 578
emilmont 78:ed8466a608b4 579 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
emilmont 78:ed8466a608b4 580 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
emilmont 78:ed8466a608b4 581
emilmont 78:ed8466a608b4 582 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
emilmont 78:ed8466a608b4 583 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
emilmont 78:ed8466a608b4 584
emilmont 78:ed8466a608b4 585 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 78:ed8466a608b4 586 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 78:ed8466a608b4 587
emilmont 78:ed8466a608b4 588 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
emilmont 78:ed8466a608b4 589 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
emilmont 78:ed8466a608b4 590
emilmont 78:ed8466a608b4 591 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
emilmont 78:ed8466a608b4 592 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
emilmont 78:ed8466a608b4 593
emilmont 78:ed8466a608b4 594 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
emilmont 78:ed8466a608b4 595 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
emilmont 78:ed8466a608b4 596
emilmont 78:ed8466a608b4 597 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
emilmont 78:ed8466a608b4 598 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
emilmont 78:ed8466a608b4 599
emilmont 78:ed8466a608b4 600 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
emilmont 78:ed8466a608b4 601 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
emilmont 78:ed8466a608b4 602
emilmont 78:ed8466a608b4 603 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
emilmont 78:ed8466a608b4 604 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
emilmont 78:ed8466a608b4 605
emilmont 78:ed8466a608b4 606 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
emilmont 78:ed8466a608b4 607 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
emilmont 78:ed8466a608b4 608
emilmont 78:ed8466a608b4 609 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
emilmont 78:ed8466a608b4 610 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
emilmont 78:ed8466a608b4 611
emilmont 78:ed8466a608b4 612 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
emilmont 78:ed8466a608b4 613 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
emilmont 78:ed8466a608b4 614
emilmont 78:ed8466a608b4 615 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
Kojto 110:165afa46840b 616 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
emilmont 78:ed8466a608b4 617
emilmont 78:ed8466a608b4 618 /* SCB Configurable Fault Status Registers Definitions */
emilmont 78:ed8466a608b4 619 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
emilmont 78:ed8466a608b4 620 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
emilmont 78:ed8466a608b4 621
emilmont 78:ed8466a608b4 622 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
emilmont 78:ed8466a608b4 623 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
emilmont 78:ed8466a608b4 624
emilmont 78:ed8466a608b4 625 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
Kojto 110:165afa46840b 626 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
emilmont 78:ed8466a608b4 627
emilmont 78:ed8466a608b4 628 /* SCB Hard Fault Status Registers Definitions */
emilmont 78:ed8466a608b4 629 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
emilmont 78:ed8466a608b4 630 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
emilmont 78:ed8466a608b4 631
emilmont 78:ed8466a608b4 632 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
emilmont 78:ed8466a608b4 633 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
emilmont 78:ed8466a608b4 634
emilmont 78:ed8466a608b4 635 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
emilmont 78:ed8466a608b4 636 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
emilmont 78:ed8466a608b4 637
emilmont 78:ed8466a608b4 638 /* SCB Debug Fault Status Register Definitions */
emilmont 78:ed8466a608b4 639 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
emilmont 78:ed8466a608b4 640 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
emilmont 78:ed8466a608b4 641
emilmont 78:ed8466a608b4 642 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
emilmont 78:ed8466a608b4 643 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
emilmont 78:ed8466a608b4 644
emilmont 78:ed8466a608b4 645 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
emilmont 78:ed8466a608b4 646 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
emilmont 78:ed8466a608b4 647
emilmont 78:ed8466a608b4 648 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
emilmont 78:ed8466a608b4 649 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
emilmont 78:ed8466a608b4 650
emilmont 78:ed8466a608b4 651 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
Kojto 110:165afa46840b 652 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
emilmont 78:ed8466a608b4 653
emilmont 78:ed8466a608b4 654 /*@} end of group CMSIS_SCB */
emilmont 78:ed8466a608b4 655
emilmont 78:ed8466a608b4 656
emilmont 78:ed8466a608b4 657 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 658 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont 78:ed8466a608b4 659 \brief Type definitions for the System Control and ID Register not in the SCB
emilmont 78:ed8466a608b4 660 @{
emilmont 78:ed8466a608b4 661 */
emilmont 78:ed8466a608b4 662
emilmont 78:ed8466a608b4 663 /** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont 78:ed8466a608b4 664 */
emilmont 78:ed8466a608b4 665 typedef struct
emilmont 78:ed8466a608b4 666 {
emilmont 78:ed8466a608b4 667 uint32_t RESERVED0[1];
emilmont 78:ed8466a608b4 668 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
emilmont 78:ed8466a608b4 669 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
emilmont 78:ed8466a608b4 670 } SCnSCB_Type;
emilmont 78:ed8466a608b4 671
emilmont 78:ed8466a608b4 672 /* Interrupt Controller Type Register Definitions */
emilmont 78:ed8466a608b4 673 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
Kojto 110:165afa46840b 674 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
emilmont 78:ed8466a608b4 675
emilmont 78:ed8466a608b4 676 /* Auxiliary Control Register Definitions */
emilmont 78:ed8466a608b4 677 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
emilmont 78:ed8466a608b4 678 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
emilmont 78:ed8466a608b4 679
emilmont 78:ed8466a608b4 680 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
emilmont 78:ed8466a608b4 681 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
emilmont 78:ed8466a608b4 682
emilmont 78:ed8466a608b4 683 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
emilmont 78:ed8466a608b4 684 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
emilmont 78:ed8466a608b4 685
emilmont 78:ed8466a608b4 686 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
emilmont 78:ed8466a608b4 687 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
emilmont 78:ed8466a608b4 688
emilmont 78:ed8466a608b4 689 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
Kojto 110:165afa46840b 690 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
emilmont 78:ed8466a608b4 691
emilmont 78:ed8466a608b4 692 /*@} end of group CMSIS_SCnotSCB */
emilmont 78:ed8466a608b4 693
emilmont 78:ed8466a608b4 694
emilmont 78:ed8466a608b4 695 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 696 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 78:ed8466a608b4 697 \brief Type definitions for the System Timer Registers.
emilmont 78:ed8466a608b4 698 @{
emilmont 78:ed8466a608b4 699 */
emilmont 78:ed8466a608b4 700
emilmont 78:ed8466a608b4 701 /** \brief Structure type to access the System Timer (SysTick).
emilmont 78:ed8466a608b4 702 */
emilmont 78:ed8466a608b4 703 typedef struct
emilmont 78:ed8466a608b4 704 {
emilmont 78:ed8466a608b4 705 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 78:ed8466a608b4 706 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 78:ed8466a608b4 707 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 78:ed8466a608b4 708 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 78:ed8466a608b4 709 } SysTick_Type;
emilmont 78:ed8466a608b4 710
emilmont 78:ed8466a608b4 711 /* SysTick Control / Status Register Definitions */
emilmont 78:ed8466a608b4 712 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 78:ed8466a608b4 713 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 78:ed8466a608b4 714
emilmont 78:ed8466a608b4 715 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 78:ed8466a608b4 716 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 78:ed8466a608b4 717
emilmont 78:ed8466a608b4 718 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 78:ed8466a608b4 719 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 78:ed8466a608b4 720
emilmont 78:ed8466a608b4 721 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 722 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
emilmont 78:ed8466a608b4 723
emilmont 78:ed8466a608b4 724 /* SysTick Reload Register Definitions */
emilmont 78:ed8466a608b4 725 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 726 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
emilmont 78:ed8466a608b4 727
emilmont 78:ed8466a608b4 728 /* SysTick Current Register Definitions */
emilmont 78:ed8466a608b4 729 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 730 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
emilmont 78:ed8466a608b4 731
emilmont 78:ed8466a608b4 732 /* SysTick Calibration Register Definitions */
emilmont 78:ed8466a608b4 733 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 78:ed8466a608b4 734 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 78:ed8466a608b4 735
emilmont 78:ed8466a608b4 736 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 78:ed8466a608b4 737 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 78:ed8466a608b4 738
emilmont 78:ed8466a608b4 739 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 740 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
emilmont 78:ed8466a608b4 741
emilmont 78:ed8466a608b4 742 /*@} end of group CMSIS_SysTick */
emilmont 78:ed8466a608b4 743
emilmont 78:ed8466a608b4 744
emilmont 78:ed8466a608b4 745 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 746 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont 78:ed8466a608b4 747 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont 78:ed8466a608b4 748 @{
emilmont 78:ed8466a608b4 749 */
emilmont 78:ed8466a608b4 750
emilmont 78:ed8466a608b4 751 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont 78:ed8466a608b4 752 */
emilmont 78:ed8466a608b4 753 typedef struct
emilmont 78:ed8466a608b4 754 {
emilmont 78:ed8466a608b4 755 __O union
emilmont 78:ed8466a608b4 756 {
emilmont 78:ed8466a608b4 757 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
emilmont 78:ed8466a608b4 758 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
emilmont 78:ed8466a608b4 759 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
emilmont 78:ed8466a608b4 760 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
emilmont 78:ed8466a608b4 761 uint32_t RESERVED0[864];
emilmont 78:ed8466a608b4 762 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
emilmont 78:ed8466a608b4 763 uint32_t RESERVED1[15];
emilmont 78:ed8466a608b4 764 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
emilmont 78:ed8466a608b4 765 uint32_t RESERVED2[15];
emilmont 78:ed8466a608b4 766 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
emilmont 78:ed8466a608b4 767 uint32_t RESERVED3[29];
emilmont 78:ed8466a608b4 768 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
emilmont 78:ed8466a608b4 769 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
emilmont 78:ed8466a608b4 770 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
emilmont 78:ed8466a608b4 771 uint32_t RESERVED4[43];
emilmont 78:ed8466a608b4 772 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
emilmont 78:ed8466a608b4 773 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
emilmont 78:ed8466a608b4 774 uint32_t RESERVED5[6];
emilmont 78:ed8466a608b4 775 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
emilmont 78:ed8466a608b4 776 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
emilmont 78:ed8466a608b4 777 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
emilmont 78:ed8466a608b4 778 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
emilmont 78:ed8466a608b4 779 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
emilmont 78:ed8466a608b4 780 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
emilmont 78:ed8466a608b4 781 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
emilmont 78:ed8466a608b4 782 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
emilmont 78:ed8466a608b4 783 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
emilmont 78:ed8466a608b4 784 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
emilmont 78:ed8466a608b4 785 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
emilmont 78:ed8466a608b4 786 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
emilmont 78:ed8466a608b4 787 } ITM_Type;
emilmont 78:ed8466a608b4 788
emilmont 78:ed8466a608b4 789 /* ITM Trace Privilege Register Definitions */
emilmont 78:ed8466a608b4 790 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
Kojto 110:165afa46840b 791 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
emilmont 78:ed8466a608b4 792
emilmont 78:ed8466a608b4 793 /* ITM Trace Control Register Definitions */
emilmont 78:ed8466a608b4 794 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
emilmont 78:ed8466a608b4 795 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
emilmont 78:ed8466a608b4 796
emilmont 78:ed8466a608b4 797 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
emilmont 78:ed8466a608b4 798 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
emilmont 78:ed8466a608b4 799
emilmont 78:ed8466a608b4 800 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
emilmont 78:ed8466a608b4 801 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
emilmont 78:ed8466a608b4 802
emilmont 78:ed8466a608b4 803 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
emilmont 78:ed8466a608b4 804 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
emilmont 78:ed8466a608b4 805
emilmont 78:ed8466a608b4 806 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
emilmont 78:ed8466a608b4 807 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
emilmont 78:ed8466a608b4 808
emilmont 78:ed8466a608b4 809 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
emilmont 78:ed8466a608b4 810 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
emilmont 78:ed8466a608b4 811
emilmont 78:ed8466a608b4 812 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
emilmont 78:ed8466a608b4 813 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
emilmont 78:ed8466a608b4 814
emilmont 78:ed8466a608b4 815 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
emilmont 78:ed8466a608b4 816 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
emilmont 78:ed8466a608b4 817
emilmont 78:ed8466a608b4 818 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
Kojto 110:165afa46840b 819 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
emilmont 78:ed8466a608b4 820
emilmont 78:ed8466a608b4 821 /* ITM Integration Write Register Definitions */
emilmont 78:ed8466a608b4 822 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
Kojto 110:165afa46840b 823 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
emilmont 78:ed8466a608b4 824
emilmont 78:ed8466a608b4 825 /* ITM Integration Read Register Definitions */
emilmont 78:ed8466a608b4 826 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
Kojto 110:165afa46840b 827 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
emilmont 78:ed8466a608b4 828
emilmont 78:ed8466a608b4 829 /* ITM Integration Mode Control Register Definitions */
emilmont 78:ed8466a608b4 830 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
Kojto 110:165afa46840b 831 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
emilmont 78:ed8466a608b4 832
emilmont 78:ed8466a608b4 833 /* ITM Lock Status Register Definitions */
emilmont 78:ed8466a608b4 834 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
emilmont 78:ed8466a608b4 835 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
emilmont 78:ed8466a608b4 836
emilmont 78:ed8466a608b4 837 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
emilmont 78:ed8466a608b4 838 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
emilmont 78:ed8466a608b4 839
emilmont 78:ed8466a608b4 840 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
Kojto 110:165afa46840b 841 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
emilmont 78:ed8466a608b4 842
emilmont 78:ed8466a608b4 843 /*@}*/ /* end of group CMSIS_ITM */
emilmont 78:ed8466a608b4 844
emilmont 78:ed8466a608b4 845
emilmont 78:ed8466a608b4 846 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 847 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
emilmont 78:ed8466a608b4 848 \brief Type definitions for the Data Watchpoint and Trace (DWT)
emilmont 78:ed8466a608b4 849 @{
emilmont 78:ed8466a608b4 850 */
emilmont 78:ed8466a608b4 851
emilmont 78:ed8466a608b4 852 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
emilmont 78:ed8466a608b4 853 */
emilmont 78:ed8466a608b4 854 typedef struct
emilmont 78:ed8466a608b4 855 {
emilmont 78:ed8466a608b4 856 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
emilmont 78:ed8466a608b4 857 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
emilmont 78:ed8466a608b4 858 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
emilmont 78:ed8466a608b4 859 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
emilmont 78:ed8466a608b4 860 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
emilmont 78:ed8466a608b4 861 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
emilmont 78:ed8466a608b4 862 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
emilmont 78:ed8466a608b4 863 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
emilmont 78:ed8466a608b4 864 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
emilmont 78:ed8466a608b4 865 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
emilmont 78:ed8466a608b4 866 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
emilmont 78:ed8466a608b4 867 uint32_t RESERVED0[1];
emilmont 78:ed8466a608b4 868 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
emilmont 78:ed8466a608b4 869 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
emilmont 78:ed8466a608b4 870 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
emilmont 78:ed8466a608b4 871 uint32_t RESERVED1[1];
emilmont 78:ed8466a608b4 872 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
emilmont 78:ed8466a608b4 873 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
emilmont 78:ed8466a608b4 874 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
emilmont 78:ed8466a608b4 875 uint32_t RESERVED2[1];
emilmont 78:ed8466a608b4 876 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
emilmont 78:ed8466a608b4 877 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
emilmont 78:ed8466a608b4 878 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
emilmont 78:ed8466a608b4 879 } DWT_Type;
emilmont 78:ed8466a608b4 880
emilmont 78:ed8466a608b4 881 /* DWT Control Register Definitions */
emilmont 78:ed8466a608b4 882 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
emilmont 78:ed8466a608b4 883 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
emilmont 78:ed8466a608b4 884
emilmont 78:ed8466a608b4 885 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
emilmont 78:ed8466a608b4 886 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
emilmont 78:ed8466a608b4 887
emilmont 78:ed8466a608b4 888 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
emilmont 78:ed8466a608b4 889 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
emilmont 78:ed8466a608b4 890
emilmont 78:ed8466a608b4 891 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
emilmont 78:ed8466a608b4 892 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
emilmont 78:ed8466a608b4 893
emilmont 78:ed8466a608b4 894 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
emilmont 78:ed8466a608b4 895 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
emilmont 78:ed8466a608b4 896
emilmont 78:ed8466a608b4 897 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
emilmont 78:ed8466a608b4 898 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
emilmont 78:ed8466a608b4 899
emilmont 78:ed8466a608b4 900 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
emilmont 78:ed8466a608b4 901 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
emilmont 78:ed8466a608b4 902
emilmont 78:ed8466a608b4 903 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
emilmont 78:ed8466a608b4 904 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
emilmont 78:ed8466a608b4 905
emilmont 78:ed8466a608b4 906 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
emilmont 78:ed8466a608b4 907 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
emilmont 78:ed8466a608b4 908
emilmont 78:ed8466a608b4 909 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
emilmont 78:ed8466a608b4 910 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
emilmont 78:ed8466a608b4 911
emilmont 78:ed8466a608b4 912 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
emilmont 78:ed8466a608b4 913 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
emilmont 78:ed8466a608b4 914
emilmont 78:ed8466a608b4 915 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
emilmont 78:ed8466a608b4 916 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
emilmont 78:ed8466a608b4 917
emilmont 78:ed8466a608b4 918 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
emilmont 78:ed8466a608b4 919 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
emilmont 78:ed8466a608b4 920
emilmont 78:ed8466a608b4 921 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
emilmont 78:ed8466a608b4 922 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
emilmont 78:ed8466a608b4 923
emilmont 78:ed8466a608b4 924 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
emilmont 78:ed8466a608b4 925 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
emilmont 78:ed8466a608b4 926
emilmont 78:ed8466a608b4 927 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
emilmont 78:ed8466a608b4 928 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
emilmont 78:ed8466a608b4 929
emilmont 78:ed8466a608b4 930 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
emilmont 78:ed8466a608b4 931 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
emilmont 78:ed8466a608b4 932
emilmont 78:ed8466a608b4 933 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
Kojto 110:165afa46840b 934 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
emilmont 78:ed8466a608b4 935
emilmont 78:ed8466a608b4 936 /* DWT CPI Count Register Definitions */
emilmont 78:ed8466a608b4 937 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
Kojto 110:165afa46840b 938 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
emilmont 78:ed8466a608b4 939
emilmont 78:ed8466a608b4 940 /* DWT Exception Overhead Count Register Definitions */
emilmont 78:ed8466a608b4 941 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
Kojto 110:165afa46840b 942 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
emilmont 78:ed8466a608b4 943
emilmont 78:ed8466a608b4 944 /* DWT Sleep Count Register Definitions */
emilmont 78:ed8466a608b4 945 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
Kojto 110:165afa46840b 946 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
emilmont 78:ed8466a608b4 947
emilmont 78:ed8466a608b4 948 /* DWT LSU Count Register Definitions */
emilmont 78:ed8466a608b4 949 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
Kojto 110:165afa46840b 950 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
emilmont 78:ed8466a608b4 951
emilmont 78:ed8466a608b4 952 /* DWT Folded-instruction Count Register Definitions */
emilmont 78:ed8466a608b4 953 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
Kojto 110:165afa46840b 954 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
emilmont 78:ed8466a608b4 955
emilmont 78:ed8466a608b4 956 /* DWT Comparator Mask Register Definitions */
emilmont 78:ed8466a608b4 957 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
Kojto 110:165afa46840b 958 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
emilmont 78:ed8466a608b4 959
emilmont 78:ed8466a608b4 960 /* DWT Comparator Function Register Definitions */
emilmont 78:ed8466a608b4 961 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
emilmont 78:ed8466a608b4 962 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
emilmont 78:ed8466a608b4 963
emilmont 78:ed8466a608b4 964 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
emilmont 78:ed8466a608b4 965 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
emilmont 78:ed8466a608b4 966
emilmont 78:ed8466a608b4 967 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
emilmont 78:ed8466a608b4 968 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
emilmont 78:ed8466a608b4 969
emilmont 78:ed8466a608b4 970 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
emilmont 78:ed8466a608b4 971 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
emilmont 78:ed8466a608b4 972
emilmont 78:ed8466a608b4 973 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
emilmont 78:ed8466a608b4 974 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
emilmont 78:ed8466a608b4 975
emilmont 78:ed8466a608b4 976 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
emilmont 78:ed8466a608b4 977 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
emilmont 78:ed8466a608b4 978
emilmont 78:ed8466a608b4 979 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
emilmont 78:ed8466a608b4 980 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
emilmont 78:ed8466a608b4 981
emilmont 78:ed8466a608b4 982 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
emilmont 78:ed8466a608b4 983 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
emilmont 78:ed8466a608b4 984
emilmont 78:ed8466a608b4 985 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
Kojto 110:165afa46840b 986 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
emilmont 78:ed8466a608b4 987
emilmont 78:ed8466a608b4 988 /*@}*/ /* end of group CMSIS_DWT */
emilmont 78:ed8466a608b4 989
emilmont 78:ed8466a608b4 990
emilmont 78:ed8466a608b4 991 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 992 \defgroup CMSIS_TPI Trace Port Interface (TPI)
emilmont 78:ed8466a608b4 993 \brief Type definitions for the Trace Port Interface (TPI)
emilmont 78:ed8466a608b4 994 @{
emilmont 78:ed8466a608b4 995 */
emilmont 78:ed8466a608b4 996
emilmont 78:ed8466a608b4 997 /** \brief Structure type to access the Trace Port Interface Register (TPI).
emilmont 78:ed8466a608b4 998 */
emilmont 78:ed8466a608b4 999 typedef struct
emilmont 78:ed8466a608b4 1000 {
emilmont 78:ed8466a608b4 1001 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
emilmont 78:ed8466a608b4 1002 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
emilmont 78:ed8466a608b4 1003 uint32_t RESERVED0[2];
emilmont 78:ed8466a608b4 1004 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
emilmont 78:ed8466a608b4 1005 uint32_t RESERVED1[55];
emilmont 78:ed8466a608b4 1006 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
emilmont 78:ed8466a608b4 1007 uint32_t RESERVED2[131];
emilmont 78:ed8466a608b4 1008 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
emilmont 78:ed8466a608b4 1009 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
emilmont 78:ed8466a608b4 1010 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
emilmont 78:ed8466a608b4 1011 uint32_t RESERVED3[759];
emilmont 78:ed8466a608b4 1012 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
emilmont 78:ed8466a608b4 1013 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
emilmont 78:ed8466a608b4 1014 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
emilmont 78:ed8466a608b4 1015 uint32_t RESERVED4[1];
emilmont 78:ed8466a608b4 1016 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
emilmont 78:ed8466a608b4 1017 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
emilmont 78:ed8466a608b4 1018 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
emilmont 78:ed8466a608b4 1019 uint32_t RESERVED5[39];
emilmont 78:ed8466a608b4 1020 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
emilmont 78:ed8466a608b4 1021 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
emilmont 78:ed8466a608b4 1022 uint32_t RESERVED7[8];
emilmont 78:ed8466a608b4 1023 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
emilmont 78:ed8466a608b4 1024 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
emilmont 78:ed8466a608b4 1025 } TPI_Type;
emilmont 78:ed8466a608b4 1026
emilmont 78:ed8466a608b4 1027 /* TPI Asynchronous Clock Prescaler Register Definitions */
emilmont 78:ed8466a608b4 1028 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
Kojto 110:165afa46840b 1029 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
emilmont 78:ed8466a608b4 1030
emilmont 78:ed8466a608b4 1031 /* TPI Selected Pin Protocol Register Definitions */
emilmont 78:ed8466a608b4 1032 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
Kojto 110:165afa46840b 1033 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
emilmont 78:ed8466a608b4 1034
emilmont 78:ed8466a608b4 1035 /* TPI Formatter and Flush Status Register Definitions */
emilmont 78:ed8466a608b4 1036 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
emilmont 78:ed8466a608b4 1037 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
emilmont 78:ed8466a608b4 1038
emilmont 78:ed8466a608b4 1039 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
emilmont 78:ed8466a608b4 1040 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
emilmont 78:ed8466a608b4 1041
emilmont 78:ed8466a608b4 1042 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
emilmont 78:ed8466a608b4 1043 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
emilmont 78:ed8466a608b4 1044
emilmont 78:ed8466a608b4 1045 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
Kojto 110:165afa46840b 1046 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
emilmont 78:ed8466a608b4 1047
emilmont 78:ed8466a608b4 1048 /* TPI Formatter and Flush Control Register Definitions */
emilmont 78:ed8466a608b4 1049 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
emilmont 78:ed8466a608b4 1050 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
emilmont 78:ed8466a608b4 1051
emilmont 78:ed8466a608b4 1052 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
emilmont 78:ed8466a608b4 1053 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
emilmont 78:ed8466a608b4 1054
emilmont 78:ed8466a608b4 1055 /* TPI TRIGGER Register Definitions */
emilmont 78:ed8466a608b4 1056 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
Kojto 110:165afa46840b 1057 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
emilmont 78:ed8466a608b4 1058
emilmont 78:ed8466a608b4 1059 /* TPI Integration ETM Data Register Definitions (FIFO0) */
emilmont 78:ed8466a608b4 1060 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
emilmont 78:ed8466a608b4 1061 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
emilmont 78:ed8466a608b4 1062
emilmont 78:ed8466a608b4 1063 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
emilmont 78:ed8466a608b4 1064 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
emilmont 78:ed8466a608b4 1065
emilmont 78:ed8466a608b4 1066 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
emilmont 78:ed8466a608b4 1067 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
emilmont 78:ed8466a608b4 1068
emilmont 78:ed8466a608b4 1069 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
emilmont 78:ed8466a608b4 1070 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
emilmont 78:ed8466a608b4 1071
emilmont 78:ed8466a608b4 1072 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
emilmont 78:ed8466a608b4 1073 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
emilmont 78:ed8466a608b4 1074
emilmont 78:ed8466a608b4 1075 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
emilmont 78:ed8466a608b4 1076 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
emilmont 78:ed8466a608b4 1077
emilmont 78:ed8466a608b4 1078 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
Kojto 110:165afa46840b 1079 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
emilmont 78:ed8466a608b4 1080
emilmont 78:ed8466a608b4 1081 /* TPI ITATBCTR2 Register Definitions */
emilmont 78:ed8466a608b4 1082 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
Kojto 110:165afa46840b 1083 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
emilmont 78:ed8466a608b4 1084
emilmont 78:ed8466a608b4 1085 /* TPI Integration ITM Data Register Definitions (FIFO1) */
emilmont 78:ed8466a608b4 1086 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
emilmont 78:ed8466a608b4 1087 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
emilmont 78:ed8466a608b4 1088
emilmont 78:ed8466a608b4 1089 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
emilmont 78:ed8466a608b4 1090 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
emilmont 78:ed8466a608b4 1091
emilmont 78:ed8466a608b4 1092 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
emilmont 78:ed8466a608b4 1093 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
emilmont 78:ed8466a608b4 1094
emilmont 78:ed8466a608b4 1095 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
emilmont 78:ed8466a608b4 1096 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
emilmont 78:ed8466a608b4 1097
emilmont 78:ed8466a608b4 1098 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
emilmont 78:ed8466a608b4 1099 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
emilmont 78:ed8466a608b4 1100
emilmont 78:ed8466a608b4 1101 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
emilmont 78:ed8466a608b4 1102 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
emilmont 78:ed8466a608b4 1103
emilmont 78:ed8466a608b4 1104 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
Kojto 110:165afa46840b 1105 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
emilmont 78:ed8466a608b4 1106
emilmont 78:ed8466a608b4 1107 /* TPI ITATBCTR0 Register Definitions */
emilmont 78:ed8466a608b4 1108 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
Kojto 110:165afa46840b 1109 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
emilmont 78:ed8466a608b4 1110
emilmont 78:ed8466a608b4 1111 /* TPI Integration Mode Control Register Definitions */
emilmont 78:ed8466a608b4 1112 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
Kojto 110:165afa46840b 1113 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
emilmont 78:ed8466a608b4 1114
emilmont 78:ed8466a608b4 1115 /* TPI DEVID Register Definitions */
emilmont 78:ed8466a608b4 1116 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
emilmont 78:ed8466a608b4 1117 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
emilmont 78:ed8466a608b4 1118
emilmont 78:ed8466a608b4 1119 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
emilmont 78:ed8466a608b4 1120 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
emilmont 78:ed8466a608b4 1121
emilmont 78:ed8466a608b4 1122 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
emilmont 78:ed8466a608b4 1123 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
emilmont 78:ed8466a608b4 1124
emilmont 78:ed8466a608b4 1125 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
emilmont 78:ed8466a608b4 1126 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
emilmont 78:ed8466a608b4 1127
emilmont 78:ed8466a608b4 1128 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
emilmont 78:ed8466a608b4 1129 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
emilmont 78:ed8466a608b4 1130
emilmont 78:ed8466a608b4 1131 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
Kojto 110:165afa46840b 1132 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
emilmont 78:ed8466a608b4 1133
emilmont 78:ed8466a608b4 1134 /* TPI DEVTYPE Register Definitions */
emilmont 78:ed8466a608b4 1135 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
emilmont 78:ed8466a608b4 1136 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
emilmont 78:ed8466a608b4 1137
Kojto 110:165afa46840b 1138 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
Kojto 110:165afa46840b 1139 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
Kojto 110:165afa46840b 1140
emilmont 78:ed8466a608b4 1141 /*@}*/ /* end of group CMSIS_TPI */
emilmont 78:ed8466a608b4 1142
emilmont 78:ed8466a608b4 1143
emilmont 78:ed8466a608b4 1144 #if (__MPU_PRESENT == 1)
emilmont 78:ed8466a608b4 1145 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 1146 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 78:ed8466a608b4 1147 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 78:ed8466a608b4 1148 @{
emilmont 78:ed8466a608b4 1149 */
emilmont 78:ed8466a608b4 1150
emilmont 78:ed8466a608b4 1151 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 78:ed8466a608b4 1152 */
emilmont 78:ed8466a608b4 1153 typedef struct
emilmont 78:ed8466a608b4 1154 {
emilmont 78:ed8466a608b4 1155 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 78:ed8466a608b4 1156 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 78:ed8466a608b4 1157 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 78:ed8466a608b4 1158 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 78:ed8466a608b4 1159 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1160 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
emilmont 78:ed8466a608b4 1161 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1162 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
emilmont 78:ed8466a608b4 1163 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1164 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
emilmont 78:ed8466a608b4 1165 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1166 } MPU_Type;
emilmont 78:ed8466a608b4 1167
emilmont 78:ed8466a608b4 1168 /* MPU Type Register */
emilmont 78:ed8466a608b4 1169 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 78:ed8466a608b4 1170 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 78:ed8466a608b4 1171
emilmont 78:ed8466a608b4 1172 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 78:ed8466a608b4 1173 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 78:ed8466a608b4 1174
emilmont 78:ed8466a608b4 1175 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 110:165afa46840b 1176 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
emilmont 78:ed8466a608b4 1177
emilmont 78:ed8466a608b4 1178 /* MPU Control Register */
emilmont 78:ed8466a608b4 1179 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 78:ed8466a608b4 1180 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 78:ed8466a608b4 1181
emilmont 78:ed8466a608b4 1182 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 78:ed8466a608b4 1183 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 78:ed8466a608b4 1184
emilmont 78:ed8466a608b4 1185 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 110:165afa46840b 1186 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
emilmont 78:ed8466a608b4 1187
emilmont 78:ed8466a608b4 1188 /* MPU Region Number Register */
emilmont 78:ed8466a608b4 1189 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 110:165afa46840b 1190 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
emilmont 78:ed8466a608b4 1191
emilmont 78:ed8466a608b4 1192 /* MPU Region Base Address Register */
emilmont 78:ed8466a608b4 1193 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
emilmont 78:ed8466a608b4 1194 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 78:ed8466a608b4 1195
emilmont 78:ed8466a608b4 1196 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 78:ed8466a608b4 1197 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 78:ed8466a608b4 1198
emilmont 78:ed8466a608b4 1199 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 110:165afa46840b 1200 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
emilmont 78:ed8466a608b4 1201
emilmont 78:ed8466a608b4 1202 /* MPU Region Attribute and Size Register */
emilmont 78:ed8466a608b4 1203 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 78:ed8466a608b4 1204 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 78:ed8466a608b4 1205
emilmont 78:ed8466a608b4 1206 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 78:ed8466a608b4 1207 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 78:ed8466a608b4 1208
emilmont 78:ed8466a608b4 1209 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 78:ed8466a608b4 1210 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 78:ed8466a608b4 1211
emilmont 78:ed8466a608b4 1212 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 78:ed8466a608b4 1213 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 78:ed8466a608b4 1214
emilmont 78:ed8466a608b4 1215 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 78:ed8466a608b4 1216 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 78:ed8466a608b4 1217
emilmont 78:ed8466a608b4 1218 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 78:ed8466a608b4 1219 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 78:ed8466a608b4 1220
emilmont 78:ed8466a608b4 1221 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 78:ed8466a608b4 1222 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 78:ed8466a608b4 1223
emilmont 78:ed8466a608b4 1224 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 78:ed8466a608b4 1225 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 78:ed8466a608b4 1226
emilmont 78:ed8466a608b4 1227 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 78:ed8466a608b4 1228 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 78:ed8466a608b4 1229
emilmont 78:ed8466a608b4 1230 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 110:165afa46840b 1231 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 78:ed8466a608b4 1232
emilmont 78:ed8466a608b4 1233 /*@} end of group CMSIS_MPU */
emilmont 78:ed8466a608b4 1234 #endif
emilmont 78:ed8466a608b4 1235
emilmont 78:ed8466a608b4 1236
emilmont 78:ed8466a608b4 1237 #if (__FPU_PRESENT == 1)
emilmont 78:ed8466a608b4 1238 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 1239 \defgroup CMSIS_FPU Floating Point Unit (FPU)
emilmont 78:ed8466a608b4 1240 \brief Type definitions for the Floating Point Unit (FPU)
emilmont 78:ed8466a608b4 1241 @{
emilmont 78:ed8466a608b4 1242 */
emilmont 78:ed8466a608b4 1243
emilmont 78:ed8466a608b4 1244 /** \brief Structure type to access the Floating Point Unit (FPU).
emilmont 78:ed8466a608b4 1245 */
emilmont 78:ed8466a608b4 1246 typedef struct
emilmont 78:ed8466a608b4 1247 {
emilmont 78:ed8466a608b4 1248 uint32_t RESERVED0[1];
emilmont 78:ed8466a608b4 1249 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
emilmont 78:ed8466a608b4 1250 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
emilmont 78:ed8466a608b4 1251 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
emilmont 78:ed8466a608b4 1252 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
emilmont 78:ed8466a608b4 1253 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
emilmont 78:ed8466a608b4 1254 } FPU_Type;
emilmont 78:ed8466a608b4 1255
emilmont 78:ed8466a608b4 1256 /* Floating-Point Context Control Register */
emilmont 78:ed8466a608b4 1257 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
emilmont 78:ed8466a608b4 1258 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
emilmont 78:ed8466a608b4 1259
emilmont 78:ed8466a608b4 1260 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
emilmont 78:ed8466a608b4 1261 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
emilmont 78:ed8466a608b4 1262
emilmont 78:ed8466a608b4 1263 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
emilmont 78:ed8466a608b4 1264 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
emilmont 78:ed8466a608b4 1265
emilmont 78:ed8466a608b4 1266 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
emilmont 78:ed8466a608b4 1267 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
emilmont 78:ed8466a608b4 1268
emilmont 78:ed8466a608b4 1269 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
emilmont 78:ed8466a608b4 1270 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
emilmont 78:ed8466a608b4 1271
emilmont 78:ed8466a608b4 1272 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
emilmont 78:ed8466a608b4 1273 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
emilmont 78:ed8466a608b4 1274
emilmont 78:ed8466a608b4 1275 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
emilmont 78:ed8466a608b4 1276 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
emilmont 78:ed8466a608b4 1277
emilmont 78:ed8466a608b4 1278 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
emilmont 78:ed8466a608b4 1279 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
emilmont 78:ed8466a608b4 1280
emilmont 78:ed8466a608b4 1281 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
Kojto 110:165afa46840b 1282 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
emilmont 78:ed8466a608b4 1283
emilmont 78:ed8466a608b4 1284 /* Floating-Point Context Address Register */
emilmont 78:ed8466a608b4 1285 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
emilmont 78:ed8466a608b4 1286 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
emilmont 78:ed8466a608b4 1287
emilmont 78:ed8466a608b4 1288 /* Floating-Point Default Status Control Register */
emilmont 78:ed8466a608b4 1289 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
emilmont 78:ed8466a608b4 1290 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
emilmont 78:ed8466a608b4 1291
emilmont 78:ed8466a608b4 1292 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
emilmont 78:ed8466a608b4 1293 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
emilmont 78:ed8466a608b4 1294
emilmont 78:ed8466a608b4 1295 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
emilmont 78:ed8466a608b4 1296 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
emilmont 78:ed8466a608b4 1297
emilmont 78:ed8466a608b4 1298 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
emilmont 78:ed8466a608b4 1299 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
emilmont 78:ed8466a608b4 1300
emilmont 78:ed8466a608b4 1301 /* Media and FP Feature Register 0 */
emilmont 78:ed8466a608b4 1302 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
emilmont 78:ed8466a608b4 1303 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
emilmont 78:ed8466a608b4 1304
emilmont 78:ed8466a608b4 1305 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
emilmont 78:ed8466a608b4 1306 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
emilmont 78:ed8466a608b4 1307
emilmont 78:ed8466a608b4 1308 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
emilmont 78:ed8466a608b4 1309 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
emilmont 78:ed8466a608b4 1310
emilmont 78:ed8466a608b4 1311 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
emilmont 78:ed8466a608b4 1312 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
emilmont 78:ed8466a608b4 1313
emilmont 78:ed8466a608b4 1314 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
emilmont 78:ed8466a608b4 1315 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
emilmont 78:ed8466a608b4 1316
emilmont 78:ed8466a608b4 1317 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
emilmont 78:ed8466a608b4 1318 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
emilmont 78:ed8466a608b4 1319
emilmont 78:ed8466a608b4 1320 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
emilmont 78:ed8466a608b4 1321 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
emilmont 78:ed8466a608b4 1322
emilmont 78:ed8466a608b4 1323 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
Kojto 110:165afa46840b 1324 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
emilmont 78:ed8466a608b4 1325
emilmont 78:ed8466a608b4 1326 /* Media and FP Feature Register 1 */
emilmont 78:ed8466a608b4 1327 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
emilmont 78:ed8466a608b4 1328 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
emilmont 78:ed8466a608b4 1329
emilmont 78:ed8466a608b4 1330 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
emilmont 78:ed8466a608b4 1331 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
emilmont 78:ed8466a608b4 1332
emilmont 78:ed8466a608b4 1333 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
emilmont 78:ed8466a608b4 1334 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
emilmont 78:ed8466a608b4 1335
emilmont 78:ed8466a608b4 1336 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
Kojto 110:165afa46840b 1337 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
emilmont 78:ed8466a608b4 1338
emilmont 78:ed8466a608b4 1339 /*@} end of group CMSIS_FPU */
emilmont 78:ed8466a608b4 1340 #endif
emilmont 78:ed8466a608b4 1341
emilmont 78:ed8466a608b4 1342
emilmont 78:ed8466a608b4 1343 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 1344 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 78:ed8466a608b4 1345 \brief Type definitions for the Core Debug Registers
emilmont 78:ed8466a608b4 1346 @{
emilmont 78:ed8466a608b4 1347 */
emilmont 78:ed8466a608b4 1348
emilmont 78:ed8466a608b4 1349 /** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont 78:ed8466a608b4 1350 */
emilmont 78:ed8466a608b4 1351 typedef struct
emilmont 78:ed8466a608b4 1352 {
emilmont 78:ed8466a608b4 1353 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
emilmont 78:ed8466a608b4 1354 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
emilmont 78:ed8466a608b4 1355 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
emilmont 78:ed8466a608b4 1356 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
emilmont 78:ed8466a608b4 1357 } CoreDebug_Type;
emilmont 78:ed8466a608b4 1358
emilmont 78:ed8466a608b4 1359 /* Debug Halting Control and Status Register */
emilmont 78:ed8466a608b4 1360 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
emilmont 78:ed8466a608b4 1361 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
emilmont 78:ed8466a608b4 1362
emilmont 78:ed8466a608b4 1363 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
emilmont 78:ed8466a608b4 1364 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
emilmont 78:ed8466a608b4 1365
emilmont 78:ed8466a608b4 1366 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
emilmont 78:ed8466a608b4 1367 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
emilmont 78:ed8466a608b4 1368
emilmont 78:ed8466a608b4 1369 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
emilmont 78:ed8466a608b4 1370 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
emilmont 78:ed8466a608b4 1371
emilmont 78:ed8466a608b4 1372 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
emilmont 78:ed8466a608b4 1373 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
emilmont 78:ed8466a608b4 1374
emilmont 78:ed8466a608b4 1375 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
emilmont 78:ed8466a608b4 1376 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
emilmont 78:ed8466a608b4 1377
emilmont 78:ed8466a608b4 1378 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
emilmont 78:ed8466a608b4 1379 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
emilmont 78:ed8466a608b4 1380
emilmont 78:ed8466a608b4 1381 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
emilmont 78:ed8466a608b4 1382 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
emilmont 78:ed8466a608b4 1383
emilmont 78:ed8466a608b4 1384 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
emilmont 78:ed8466a608b4 1385 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
emilmont 78:ed8466a608b4 1386
emilmont 78:ed8466a608b4 1387 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
emilmont 78:ed8466a608b4 1388 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
emilmont 78:ed8466a608b4 1389
emilmont 78:ed8466a608b4 1390 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
emilmont 78:ed8466a608b4 1391 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
emilmont 78:ed8466a608b4 1392
emilmont 78:ed8466a608b4 1393 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
Kojto 110:165afa46840b 1394 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
emilmont 78:ed8466a608b4 1395
emilmont 78:ed8466a608b4 1396 /* Debug Core Register Selector Register */
emilmont 78:ed8466a608b4 1397 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
emilmont 78:ed8466a608b4 1398 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
emilmont 78:ed8466a608b4 1399
emilmont 78:ed8466a608b4 1400 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
Kojto 110:165afa46840b 1401 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
emilmont 78:ed8466a608b4 1402
emilmont 78:ed8466a608b4 1403 /* Debug Exception and Monitor Control Register */
emilmont 78:ed8466a608b4 1404 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
emilmont 78:ed8466a608b4 1405 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
emilmont 78:ed8466a608b4 1406
emilmont 78:ed8466a608b4 1407 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
emilmont 78:ed8466a608b4 1408 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
emilmont 78:ed8466a608b4 1409
emilmont 78:ed8466a608b4 1410 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
emilmont 78:ed8466a608b4 1411 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
emilmont 78:ed8466a608b4 1412
emilmont 78:ed8466a608b4 1413 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
emilmont 78:ed8466a608b4 1414 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
emilmont 78:ed8466a608b4 1415
emilmont 78:ed8466a608b4 1416 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
emilmont 78:ed8466a608b4 1417 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
emilmont 78:ed8466a608b4 1418
emilmont 78:ed8466a608b4 1419 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
emilmont 78:ed8466a608b4 1420 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
emilmont 78:ed8466a608b4 1421
emilmont 78:ed8466a608b4 1422 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
emilmont 78:ed8466a608b4 1423 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
emilmont 78:ed8466a608b4 1424
emilmont 78:ed8466a608b4 1425 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
emilmont 78:ed8466a608b4 1426 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
emilmont 78:ed8466a608b4 1427
emilmont 78:ed8466a608b4 1428 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
emilmont 78:ed8466a608b4 1429 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
emilmont 78:ed8466a608b4 1430
emilmont 78:ed8466a608b4 1431 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
emilmont 78:ed8466a608b4 1432 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
emilmont 78:ed8466a608b4 1433
emilmont 78:ed8466a608b4 1434 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
emilmont 78:ed8466a608b4 1435 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
emilmont 78:ed8466a608b4 1436
emilmont 78:ed8466a608b4 1437 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
emilmont 78:ed8466a608b4 1438 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
emilmont 78:ed8466a608b4 1439
emilmont 78:ed8466a608b4 1440 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
Kojto 110:165afa46840b 1441 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
emilmont 78:ed8466a608b4 1442
emilmont 78:ed8466a608b4 1443 /*@} end of group CMSIS_CoreDebug */
emilmont 78:ed8466a608b4 1444
emilmont 78:ed8466a608b4 1445
emilmont 78:ed8466a608b4 1446 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 1447 \defgroup CMSIS_core_base Core Definitions
emilmont 78:ed8466a608b4 1448 \brief Definitions for base addresses, unions, and structures.
emilmont 78:ed8466a608b4 1449 @{
emilmont 78:ed8466a608b4 1450 */
emilmont 78:ed8466a608b4 1451
emilmont 78:ed8466a608b4 1452 /* Memory mapping of Cortex-M4 Hardware */
emilmont 78:ed8466a608b4 1453 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 78:ed8466a608b4 1454 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
emilmont 78:ed8466a608b4 1455 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
emilmont 78:ed8466a608b4 1456 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
emilmont 78:ed8466a608b4 1457 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
emilmont 78:ed8466a608b4 1458 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 78:ed8466a608b4 1459 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 78:ed8466a608b4 1460 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 78:ed8466a608b4 1461
emilmont 78:ed8466a608b4 1462 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
emilmont 78:ed8466a608b4 1463 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 78:ed8466a608b4 1464 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 78:ed8466a608b4 1465 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 78:ed8466a608b4 1466 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
emilmont 78:ed8466a608b4 1467 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
emilmont 78:ed8466a608b4 1468 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
emilmont 78:ed8466a608b4 1469 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
emilmont 78:ed8466a608b4 1470
emilmont 78:ed8466a608b4 1471 #if (__MPU_PRESENT == 1)
emilmont 78:ed8466a608b4 1472 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 78:ed8466a608b4 1473 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 78:ed8466a608b4 1474 #endif
emilmont 78:ed8466a608b4 1475
emilmont 78:ed8466a608b4 1476 #if (__FPU_PRESENT == 1)
emilmont 78:ed8466a608b4 1477 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
emilmont 78:ed8466a608b4 1478 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
emilmont 78:ed8466a608b4 1479 #endif
emilmont 78:ed8466a608b4 1480
emilmont 78:ed8466a608b4 1481 /*@} */
emilmont 78:ed8466a608b4 1482
emilmont 78:ed8466a608b4 1483
emilmont 78:ed8466a608b4 1484
emilmont 78:ed8466a608b4 1485 /*******************************************************************************
emilmont 78:ed8466a608b4 1486 * Hardware Abstraction Layer
emilmont 78:ed8466a608b4 1487 Core Function Interface contains:
emilmont 78:ed8466a608b4 1488 - Core NVIC Functions
emilmont 78:ed8466a608b4 1489 - Core SysTick Functions
emilmont 78:ed8466a608b4 1490 - Core Debug Functions
emilmont 78:ed8466a608b4 1491 - Core Register Access Functions
emilmont 78:ed8466a608b4 1492 ******************************************************************************/
emilmont 78:ed8466a608b4 1493 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 78:ed8466a608b4 1494 */
emilmont 78:ed8466a608b4 1495
emilmont 78:ed8466a608b4 1496
emilmont 78:ed8466a608b4 1497
emilmont 78:ed8466a608b4 1498 /* ########################## NVIC functions #################################### */
emilmont 78:ed8466a608b4 1499 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 1500 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 78:ed8466a608b4 1501 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 78:ed8466a608b4 1502 @{
emilmont 78:ed8466a608b4 1503 */
emilmont 78:ed8466a608b4 1504
Kojto 122:f9eeca106725 1505 #ifdef CMSIS_NVIC_VIRTUAL
Kojto 122:f9eeca106725 1506 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto 122:f9eeca106725 1507 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
Kojto 122:f9eeca106725 1508 #endif
Kojto 122:f9eeca106725 1509 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
Kojto 122:f9eeca106725 1510 #else
Kojto 122:f9eeca106725 1511 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
Kojto 122:f9eeca106725 1512 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
Kojto 122:f9eeca106725 1513 #define NVIC_EnableIRQ __NVIC_EnableIRQ
Kojto 122:f9eeca106725 1514 #define NVIC_DisableIRQ __NVIC_DisableIRQ
Kojto 122:f9eeca106725 1515 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
Kojto 122:f9eeca106725 1516 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
Kojto 122:f9eeca106725 1517 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
Kojto 122:f9eeca106725 1518 #define NVIC_GetActive __NVIC_GetActive
Kojto 122:f9eeca106725 1519 #define NVIC_SetPriority __NVIC_SetPriority
Kojto 122:f9eeca106725 1520 #define NVIC_GetPriority __NVIC_GetPriority
Kojto 122:f9eeca106725 1521 #endif /* CMSIS_NVIC_VIRTUAL */
Kojto 122:f9eeca106725 1522
Kojto 122:f9eeca106725 1523 #ifdef CMSIS_VECTAB_VIRTUAL
Kojto 122:f9eeca106725 1524 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto 122:f9eeca106725 1525 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
Kojto 122:f9eeca106725 1526 #endif
Kojto 122:f9eeca106725 1527 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
Kojto 122:f9eeca106725 1528 #else
Kojto 122:f9eeca106725 1529 #define NVIC_SetVector __NVIC_SetVector
Kojto 122:f9eeca106725 1530 #define NVIC_GetVector __NVIC_GetVector
Kojto 122:f9eeca106725 1531 #endif /* CMSIS_VECTAB_VIRTUAL */
Kojto 122:f9eeca106725 1532
Kojto 122:f9eeca106725 1533
emilmont 78:ed8466a608b4 1534 /** \brief Set Priority Grouping
emilmont 78:ed8466a608b4 1535
emilmont 78:ed8466a608b4 1536 The function sets the priority grouping field using the required unlock sequence.
emilmont 78:ed8466a608b4 1537 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont 78:ed8466a608b4 1538 Only values from 0..7 are used.
emilmont 78:ed8466a608b4 1539 In case of a conflict between priority grouping and available
emilmont 78:ed8466a608b4 1540 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont 78:ed8466a608b4 1541
emilmont 78:ed8466a608b4 1542 \param [in] PriorityGroup Priority grouping field.
emilmont 78:ed8466a608b4 1543 */
Kojto 122:f9eeca106725 1544 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont 78:ed8466a608b4 1545 {
emilmont 78:ed8466a608b4 1546 uint32_t reg_value;
Kojto 110:165afa46840b 1547 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont 78:ed8466a608b4 1548
emilmont 78:ed8466a608b4 1549 reg_value = SCB->AIRCR; /* read old register configuration */
Kojto 110:165afa46840b 1550 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
Kojto 110:165afa46840b 1551 reg_value = (reg_value |
Kojto 110:165afa46840b 1552 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 110:165afa46840b 1553 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
emilmont 78:ed8466a608b4 1554 SCB->AIRCR = reg_value;
emilmont 78:ed8466a608b4 1555 }
emilmont 78:ed8466a608b4 1556
emilmont 78:ed8466a608b4 1557
emilmont 78:ed8466a608b4 1558 /** \brief Get Priority Grouping
emilmont 78:ed8466a608b4 1559
emilmont 78:ed8466a608b4 1560 The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont 78:ed8466a608b4 1561
emilmont 78:ed8466a608b4 1562 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont 78:ed8466a608b4 1563 */
Kojto 122:f9eeca106725 1564 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
emilmont 78:ed8466a608b4 1565 {
Kojto 110:165afa46840b 1566 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
emilmont 78:ed8466a608b4 1567 }
emilmont 78:ed8466a608b4 1568
emilmont 78:ed8466a608b4 1569
emilmont 78:ed8466a608b4 1570 /** \brief Enable External Interrupt
emilmont 78:ed8466a608b4 1571
emilmont 78:ed8466a608b4 1572 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 78:ed8466a608b4 1573
emilmont 78:ed8466a608b4 1574 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 1575 */
Kojto 122:f9eeca106725 1576 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1577 {
Kojto 110:165afa46840b 1578 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 1579 }
emilmont 78:ed8466a608b4 1580
emilmont 78:ed8466a608b4 1581
emilmont 78:ed8466a608b4 1582 /** \brief Disable External Interrupt
emilmont 78:ed8466a608b4 1583
emilmont 78:ed8466a608b4 1584 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 78:ed8466a608b4 1585
emilmont 78:ed8466a608b4 1586 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 1587 */
Kojto 122:f9eeca106725 1588 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1589 {
Kojto 110:165afa46840b 1590 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 1591 }
emilmont 78:ed8466a608b4 1592
emilmont 78:ed8466a608b4 1593
emilmont 78:ed8466a608b4 1594 /** \brief Get Pending Interrupt
emilmont 78:ed8466a608b4 1595
emilmont 78:ed8466a608b4 1596 The function reads the pending register in the NVIC and returns the pending bit
emilmont 78:ed8466a608b4 1597 for the specified interrupt.
emilmont 78:ed8466a608b4 1598
emilmont 78:ed8466a608b4 1599 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 1600
emilmont 78:ed8466a608b4 1601 \return 0 Interrupt status is not pending.
emilmont 78:ed8466a608b4 1602 \return 1 Interrupt status is pending.
emilmont 78:ed8466a608b4 1603 */
Kojto 122:f9eeca106725 1604 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1605 {
Kojto 110:165afa46840b 1606 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont 78:ed8466a608b4 1607 }
emilmont 78:ed8466a608b4 1608
emilmont 78:ed8466a608b4 1609
emilmont 78:ed8466a608b4 1610 /** \brief Set Pending Interrupt
emilmont 78:ed8466a608b4 1611
emilmont 78:ed8466a608b4 1612 The function sets the pending bit of an external interrupt.
emilmont 78:ed8466a608b4 1613
emilmont 78:ed8466a608b4 1614 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 1615 */
Kojto 122:f9eeca106725 1616 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1617 {
Kojto 110:165afa46840b 1618 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 1619 }
emilmont 78:ed8466a608b4 1620
emilmont 78:ed8466a608b4 1621
emilmont 78:ed8466a608b4 1622 /** \brief Clear Pending Interrupt
emilmont 78:ed8466a608b4 1623
emilmont 78:ed8466a608b4 1624 The function clears the pending bit of an external interrupt.
emilmont 78:ed8466a608b4 1625
emilmont 78:ed8466a608b4 1626 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 1627 */
Kojto 122:f9eeca106725 1628 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1629 {
Kojto 110:165afa46840b 1630 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 78:ed8466a608b4 1631 }
emilmont 78:ed8466a608b4 1632
emilmont 78:ed8466a608b4 1633
emilmont 78:ed8466a608b4 1634 /** \brief Get Active Interrupt
emilmont 78:ed8466a608b4 1635
emilmont 78:ed8466a608b4 1636 The function reads the active register in NVIC and returns the active bit.
emilmont 78:ed8466a608b4 1637
emilmont 78:ed8466a608b4 1638 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 1639
emilmont 78:ed8466a608b4 1640 \return 0 Interrupt status is not active.
emilmont 78:ed8466a608b4 1641 \return 1 Interrupt status is active.
emilmont 78:ed8466a608b4 1642 */
Kojto 122:f9eeca106725 1643 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1644 {
Kojto 110:165afa46840b 1645 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont 78:ed8466a608b4 1646 }
emilmont 78:ed8466a608b4 1647
emilmont 78:ed8466a608b4 1648
emilmont 78:ed8466a608b4 1649 /** \brief Set Interrupt Priority
emilmont 78:ed8466a608b4 1650
emilmont 78:ed8466a608b4 1651 The function sets the priority of an interrupt.
emilmont 78:ed8466a608b4 1652
emilmont 78:ed8466a608b4 1653 \note The priority cannot be set for every core interrupt.
emilmont 78:ed8466a608b4 1654
emilmont 78:ed8466a608b4 1655 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 1656 \param [in] priority Priority to set.
emilmont 78:ed8466a608b4 1657 */
Kojto 122:f9eeca106725 1658 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 78:ed8466a608b4 1659 {
Kojto 110:165afa46840b 1660 if((int32_t)IRQn < 0) {
Kojto 110:165afa46840b 1661 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 110:165afa46840b 1662 }
emilmont 78:ed8466a608b4 1663 else {
Kojto 110:165afa46840b 1664 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
Kojto 110:165afa46840b 1665 }
emilmont 78:ed8466a608b4 1666 }
emilmont 78:ed8466a608b4 1667
emilmont 78:ed8466a608b4 1668
emilmont 78:ed8466a608b4 1669 /** \brief Get Interrupt Priority
emilmont 78:ed8466a608b4 1670
emilmont 78:ed8466a608b4 1671 The function reads the priority of an interrupt. The interrupt
emilmont 78:ed8466a608b4 1672 number can be positive to specify an external (device specific)
emilmont 78:ed8466a608b4 1673 interrupt, or negative to specify an internal (core) interrupt.
emilmont 78:ed8466a608b4 1674
emilmont 78:ed8466a608b4 1675
emilmont 78:ed8466a608b4 1676 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 1677 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 78:ed8466a608b4 1678 priority bits of the microcontroller.
emilmont 78:ed8466a608b4 1679 */
Kojto 122:f9eeca106725 1680 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 1681 {
emilmont 78:ed8466a608b4 1682
Kojto 110:165afa46840b 1683 if((int32_t)IRQn < 0) {
Kojto 110:165afa46840b 1684 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 1685 }
emilmont 78:ed8466a608b4 1686 else {
Kojto 110:165afa46840b 1687 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 1688 }
emilmont 78:ed8466a608b4 1689 }
emilmont 78:ed8466a608b4 1690
emilmont 78:ed8466a608b4 1691
emilmont 78:ed8466a608b4 1692 /** \brief Encode Priority
emilmont 78:ed8466a608b4 1693
emilmont 78:ed8466a608b4 1694 The function encodes the priority for an interrupt with the given priority group,
emilmont 78:ed8466a608b4 1695 preemptive priority value, and subpriority value.
emilmont 78:ed8466a608b4 1696 In case of a conflict between priority grouping and available
Kojto 110:165afa46840b 1697 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont 78:ed8466a608b4 1698
emilmont 78:ed8466a608b4 1699 \param [in] PriorityGroup Used priority group.
emilmont 78:ed8466a608b4 1700 \param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont 78:ed8466a608b4 1701 \param [in] SubPriority Subpriority value (starting from 0).
emilmont 78:ed8466a608b4 1702 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont 78:ed8466a608b4 1703 */
emilmont 78:ed8466a608b4 1704 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont 78:ed8466a608b4 1705 {
Kojto 110:165afa46840b 1706 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont 78:ed8466a608b4 1707 uint32_t PreemptPriorityBits;
emilmont 78:ed8466a608b4 1708 uint32_t SubPriorityBits;
emilmont 78:ed8466a608b4 1709
Kojto 110:165afa46840b 1710 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 110:165afa46840b 1711 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
emilmont 78:ed8466a608b4 1712
emilmont 78:ed8466a608b4 1713 return (
Kojto 110:165afa46840b 1714 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
Kojto 110:165afa46840b 1715 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
emilmont 78:ed8466a608b4 1716 );
emilmont 78:ed8466a608b4 1717 }
emilmont 78:ed8466a608b4 1718
emilmont 78:ed8466a608b4 1719
emilmont 78:ed8466a608b4 1720 /** \brief Decode Priority
emilmont 78:ed8466a608b4 1721
emilmont 78:ed8466a608b4 1722 The function decodes an interrupt priority value with a given priority group to
emilmont 78:ed8466a608b4 1723 preemptive priority value and subpriority value.
emilmont 78:ed8466a608b4 1724 In case of a conflict between priority grouping and available
Kojto 110:165afa46840b 1725 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
emilmont 78:ed8466a608b4 1726
emilmont 78:ed8466a608b4 1727 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont 78:ed8466a608b4 1728 \param [in] PriorityGroup Used priority group.
emilmont 78:ed8466a608b4 1729 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont 78:ed8466a608b4 1730 \param [out] pSubPriority Subpriority value (starting from 0).
emilmont 78:ed8466a608b4 1731 */
emilmont 78:ed8466a608b4 1732 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont 78:ed8466a608b4 1733 {
Kojto 110:165afa46840b 1734 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
emilmont 78:ed8466a608b4 1735 uint32_t PreemptPriorityBits;
emilmont 78:ed8466a608b4 1736 uint32_t SubPriorityBits;
emilmont 78:ed8466a608b4 1737
Kojto 110:165afa46840b 1738 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
Kojto 110:165afa46840b 1739 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
emilmont 78:ed8466a608b4 1740
Kojto 110:165afa46840b 1741 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
Kojto 110:165afa46840b 1742 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
emilmont 78:ed8466a608b4 1743 }
emilmont 78:ed8466a608b4 1744
emilmont 78:ed8466a608b4 1745
emilmont 78:ed8466a608b4 1746 /** \brief System Reset
emilmont 78:ed8466a608b4 1747
emilmont 78:ed8466a608b4 1748 The function initiates a system reset request to reset the MCU.
emilmont 78:ed8466a608b4 1749 */
emilmont 78:ed8466a608b4 1750 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 78:ed8466a608b4 1751 {
Kojto 110:165afa46840b 1752 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 110:165afa46840b 1753 buffered write are completed before reset */
Kojto 110:165afa46840b 1754 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 110:165afa46840b 1755 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
Kojto 110:165afa46840b 1756 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
Kojto 110:165afa46840b 1757 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 1758 while(1) { __NOP(); } /* wait until reset */
emilmont 78:ed8466a608b4 1759 }
emilmont 78:ed8466a608b4 1760
emilmont 78:ed8466a608b4 1761 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 78:ed8466a608b4 1762
emilmont 78:ed8466a608b4 1763
emilmont 78:ed8466a608b4 1764
emilmont 78:ed8466a608b4 1765 /* ################################## SysTick function ############################################ */
emilmont 78:ed8466a608b4 1766 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 1767 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 78:ed8466a608b4 1768 \brief Functions that configure the System.
emilmont 78:ed8466a608b4 1769 @{
emilmont 78:ed8466a608b4 1770 */
emilmont 78:ed8466a608b4 1771
emilmont 78:ed8466a608b4 1772 #if (__Vendor_SysTickConfig == 0)
emilmont 78:ed8466a608b4 1773
emilmont 78:ed8466a608b4 1774 /** \brief System Tick Configuration
emilmont 78:ed8466a608b4 1775
emilmont 78:ed8466a608b4 1776 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 78:ed8466a608b4 1777 Counter is in free running mode to generate periodic interrupts.
emilmont 78:ed8466a608b4 1778
emilmont 78:ed8466a608b4 1779 \param [in] ticks Number of ticks between two interrupts.
emilmont 78:ed8466a608b4 1780
emilmont 78:ed8466a608b4 1781 \return 0 Function succeeded.
emilmont 78:ed8466a608b4 1782 \return 1 Function failed.
emilmont 78:ed8466a608b4 1783
emilmont 78:ed8466a608b4 1784 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 78:ed8466a608b4 1785 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 78:ed8466a608b4 1786 must contain a vendor-specific implementation of this function.
emilmont 78:ed8466a608b4 1787
emilmont 78:ed8466a608b4 1788 */
emilmont 78:ed8466a608b4 1789 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 78:ed8466a608b4 1790 {
Kojto 110:165afa46840b 1791 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
emilmont 78:ed8466a608b4 1792
Kojto 110:165afa46840b 1793 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 1794 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 1795 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
emilmont 78:ed8466a608b4 1796 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 78:ed8466a608b4 1797 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 1798 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 1799 return (0UL); /* Function successful */
emilmont 78:ed8466a608b4 1800 }
emilmont 78:ed8466a608b4 1801
emilmont 78:ed8466a608b4 1802 #endif
emilmont 78:ed8466a608b4 1803
emilmont 78:ed8466a608b4 1804 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 78:ed8466a608b4 1805
emilmont 78:ed8466a608b4 1806
emilmont 78:ed8466a608b4 1807
emilmont 78:ed8466a608b4 1808 /* ##################################### Debug In/Output function ########################################### */
emilmont 78:ed8466a608b4 1809 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 1810 \defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont 78:ed8466a608b4 1811 \brief Functions that access the ITM debug interface.
emilmont 78:ed8466a608b4 1812 @{
emilmont 78:ed8466a608b4 1813 */
emilmont 78:ed8466a608b4 1814
emilmont 78:ed8466a608b4 1815 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
emilmont 78:ed8466a608b4 1816 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
emilmont 78:ed8466a608b4 1817
emilmont 78:ed8466a608b4 1818
emilmont 78:ed8466a608b4 1819 /** \brief ITM Send Character
emilmont 78:ed8466a608b4 1820
emilmont 78:ed8466a608b4 1821 The function transmits a character via the ITM channel 0, and
emilmont 78:ed8466a608b4 1822 \li Just returns when no debugger is connected that has booked the output.
emilmont 78:ed8466a608b4 1823 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont 78:ed8466a608b4 1824
emilmont 78:ed8466a608b4 1825 \param [in] ch Character to transmit.
emilmont 78:ed8466a608b4 1826
emilmont 78:ed8466a608b4 1827 \returns Character to transmit.
emilmont 78:ed8466a608b4 1828 */
emilmont 78:ed8466a608b4 1829 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont 78:ed8466a608b4 1830 {
Kojto 110:165afa46840b 1831 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
Kojto 110:165afa46840b 1832 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
emilmont 78:ed8466a608b4 1833 {
Kojto 110:165afa46840b 1834 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
Kojto 110:165afa46840b 1835 ITM->PORT[0].u8 = (uint8_t)ch;
emilmont 78:ed8466a608b4 1836 }
emilmont 78:ed8466a608b4 1837 return (ch);
emilmont 78:ed8466a608b4 1838 }
emilmont 78:ed8466a608b4 1839
emilmont 78:ed8466a608b4 1840
emilmont 78:ed8466a608b4 1841 /** \brief ITM Receive Character
emilmont 78:ed8466a608b4 1842
emilmont 78:ed8466a608b4 1843 The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont 78:ed8466a608b4 1844
emilmont 78:ed8466a608b4 1845 \return Received character.
emilmont 78:ed8466a608b4 1846 \return -1 No character pending.
emilmont 78:ed8466a608b4 1847 */
emilmont 78:ed8466a608b4 1848 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
emilmont 78:ed8466a608b4 1849 int32_t ch = -1; /* no character available */
emilmont 78:ed8466a608b4 1850
emilmont 78:ed8466a608b4 1851 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont 78:ed8466a608b4 1852 ch = ITM_RxBuffer;
emilmont 78:ed8466a608b4 1853 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont 78:ed8466a608b4 1854 }
emilmont 78:ed8466a608b4 1855
emilmont 78:ed8466a608b4 1856 return (ch);
emilmont 78:ed8466a608b4 1857 }
emilmont 78:ed8466a608b4 1858
emilmont 78:ed8466a608b4 1859
emilmont 78:ed8466a608b4 1860 /** \brief ITM Check Character
emilmont 78:ed8466a608b4 1861
emilmont 78:ed8466a608b4 1862 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont 78:ed8466a608b4 1863
emilmont 78:ed8466a608b4 1864 \return 0 No character available.
emilmont 78:ed8466a608b4 1865 \return 1 Character available.
emilmont 78:ed8466a608b4 1866 */
emilmont 78:ed8466a608b4 1867 __STATIC_INLINE int32_t ITM_CheckChar (void) {
emilmont 78:ed8466a608b4 1868
emilmont 78:ed8466a608b4 1869 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont 78:ed8466a608b4 1870 return (0); /* no character available */
emilmont 78:ed8466a608b4 1871 } else {
emilmont 78:ed8466a608b4 1872 return (1); /* character available */
emilmont 78:ed8466a608b4 1873 }
emilmont 78:ed8466a608b4 1874 }
emilmont 78:ed8466a608b4 1875
emilmont 78:ed8466a608b4 1876 /*@} end of CMSIS_core_DebugFunctions */
emilmont 78:ed8466a608b4 1877
emilmont 78:ed8466a608b4 1878
Kojto 110:165afa46840b 1879
emilmont 78:ed8466a608b4 1880
emilmont 78:ed8466a608b4 1881 #ifdef __cplusplus
emilmont 78:ed8466a608b4 1882 }
emilmont 78:ed8466a608b4 1883 #endif
Kojto 110:165afa46840b 1884
Kojto 110:165afa46840b 1885 #endif /* __CORE_CM4_H_DEPENDANT */
Kojto 110:165afa46840b 1886
Kojto 110:165afa46840b 1887 #endif /* __CMSIS_GENERIC */