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TARGET_EFM32WG_STK3800/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg_dmactrl.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32wg_dmactrl.h
<> 128:9bcdf88f62b0 3 * @brief EFM32WG_DMACTRL register and bit field definitions
<> 128:9bcdf88f62b0 4 * @version 5.0.0
<> 128:9bcdf88f62b0 5 ******************************************************************************
<> 128:9bcdf88f62b0 6 * @section License
<> 128:9bcdf88f62b0 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 8 ******************************************************************************
<> 128:9bcdf88f62b0 9 *
<> 128:9bcdf88f62b0 10 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 11 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 12 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 15 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 17 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 18 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 19 *
<> 128:9bcdf88f62b0 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 23 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 24 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 25 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 26 *
<> 128:9bcdf88f62b0 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 28 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 29 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 30 *
<> 128:9bcdf88f62b0 31 *****************************************************************************/
<> 128:9bcdf88f62b0 32 /**************************************************************************//**
<> 128:9bcdf88f62b0 33 * @addtogroup Parts
<> 128:9bcdf88f62b0 34 * @{
<> 128:9bcdf88f62b0 35 ******************************************************************************/
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 /**************************************************************************//**
<> 128:9bcdf88f62b0 38 * @defgroup EFM32WG_DMACTRL_BitFields
<> 128:9bcdf88f62b0 39 * @{
<> 128:9bcdf88f62b0 40 *****************************************************************************/
<> 128:9bcdf88f62b0 41 #define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
<> 128:9bcdf88f62b0 42 #define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
<> 128:9bcdf88f62b0 43 #define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
<> 128:9bcdf88f62b0 44 #define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
<> 128:9bcdf88f62b0 45 #define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
<> 128:9bcdf88f62b0 46 #define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
<> 128:9bcdf88f62b0 47 #define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
<> 128:9bcdf88f62b0 48 #define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
<> 128:9bcdf88f62b0 49 #define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
<> 128:9bcdf88f62b0 50 #define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
<> 128:9bcdf88f62b0 51 #define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
<> 128:9bcdf88f62b0 52 #define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
<> 128:9bcdf88f62b0 53 #define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
<> 128:9bcdf88f62b0 54 #define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
<> 128:9bcdf88f62b0 55 #define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
<> 128:9bcdf88f62b0 56 #define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
<> 128:9bcdf88f62b0 57 #define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
<> 128:9bcdf88f62b0 58 #define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
<> 128:9bcdf88f62b0 59 #define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
<> 128:9bcdf88f62b0 60 #define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
<> 128:9bcdf88f62b0 61 #define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
<> 128:9bcdf88f62b0 62 #define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
<> 128:9bcdf88f62b0 63 #define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
<> 128:9bcdf88f62b0 64 #define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
<> 128:9bcdf88f62b0 65 #define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
<> 128:9bcdf88f62b0 66 #define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
<> 128:9bcdf88f62b0 67 #define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
<> 128:9bcdf88f62b0 68 #define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
<> 128:9bcdf88f62b0 69 #define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
<> 128:9bcdf88f62b0 70 #define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
<> 128:9bcdf88f62b0 71 #define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
<> 128:9bcdf88f62b0 72 #define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
<> 128:9bcdf88f62b0 73 #define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
<> 128:9bcdf88f62b0 74 #define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
<> 128:9bcdf88f62b0 75 #define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
<> 128:9bcdf88f62b0 76 #define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
<> 128:9bcdf88f62b0 77 #define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
<> 128:9bcdf88f62b0 78 #define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
<> 128:9bcdf88f62b0 79 #define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
<> 128:9bcdf88f62b0 80 #define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
<> 128:9bcdf88f62b0 81 #define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
<> 128:9bcdf88f62b0 82 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
<> 128:9bcdf88f62b0 83 #define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
<> 128:9bcdf88f62b0 84 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
<> 128:9bcdf88f62b0 85 #define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
<> 128:9bcdf88f62b0 86 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
<> 128:9bcdf88f62b0 87 #define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
<> 128:9bcdf88f62b0 88 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for destination */
<> 128:9bcdf88f62b0 89 #define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
<> 128:9bcdf88f62b0 90 #define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
<> 128:9bcdf88f62b0 91 #define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
<> 128:9bcdf88f62b0 92 #define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
<> 128:9bcdf88f62b0 93 #define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
<> 128:9bcdf88f62b0 94 #define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
<> 128:9bcdf88f62b0 95 #define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
<> 128:9bcdf88f62b0 96 #define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
<> 128:9bcdf88f62b0 97 #define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
<> 128:9bcdf88f62b0 98 #define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
<> 128:9bcdf88f62b0 99 #define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
<> 128:9bcdf88f62b0 100 #define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
<> 128:9bcdf88f62b0 101 #define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
<> 128:9bcdf88f62b0 102 #define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
<> 128:9bcdf88f62b0 103 #define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
<> 128:9bcdf88f62b0 104 #define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
<> 128:9bcdf88f62b0 105 #define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
<> 128:9bcdf88f62b0 106 #define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
<> 128:9bcdf88f62b0 107 #define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
<> 128:9bcdf88f62b0 108 #define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
<> 128:9bcdf88f62b0 109 #define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
<> 128:9bcdf88f62b0 110 #define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
<> 128:9bcdf88f62b0 111 #define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
<> 128:9bcdf88f62b0 112 #define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
<> 128:9bcdf88f62b0 113 #define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
<> 128:9bcdf88f62b0 114 #define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
<> 128:9bcdf88f62b0 115 #define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
<> 128:9bcdf88f62b0 116 #define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
<> 128:9bcdf88f62b0 117 #define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
<> 128:9bcdf88f62b0 118 #define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
<> 128:9bcdf88f62b0 119 #define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
<> 128:9bcdf88f62b0 120 #define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
<> 128:9bcdf88f62b0 121 #define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
<> 128:9bcdf88f62b0 122 #define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
<> 128:9bcdf88f62b0 123 #define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
<> 128:9bcdf88f62b0 124 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
<> 128:9bcdf88f62b0 125 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
<> 128:9bcdf88f62b0 126 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
<> 128:9bcdf88f62b0 127 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
<> 128:9bcdf88f62b0 128 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
<> 128:9bcdf88f62b0 129 #define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
<> 128:9bcdf88f62b0 130 #define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
<> 128:9bcdf88f62b0 131 #define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
<> 128:9bcdf88f62b0 132 #define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
<> 128:9bcdf88f62b0 133 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
<> 128:9bcdf88f62b0 134 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
<> 128:9bcdf88f62b0 135 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
<> 128:9bcdf88f62b0 136 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
<> 128:9bcdf88f62b0 137
<> 128:9bcdf88f62b0 138 /** @} End of group EFM32WG_DMA */
<> 128:9bcdf88f62b0 139 /** @} End of group Parts */
<> 128:9bcdf88f62b0 140