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TARGET_NUCLEO_F030R8/stm32f0xx_pwr.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:
emilmont
Date:
Fri Feb 14 14:36:43 2014 +0000
Revision:
77:869cf507173a
Child:
81:7d30d6019079
Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f0xx_pwr.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 16-January-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the PWR firmware
emilmont 77:869cf507173a 8 * library.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
emilmont 77:869cf507173a 12 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
emilmont 77:869cf507173a 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
emilmont 77:869cf507173a 15 * You may not use this file except in compliance with the License.
emilmont 77:869cf507173a 16 * You may obtain a copy of the License at:
emilmont 77:869cf507173a 17 *
emilmont 77:869cf507173a 18 * http://www.st.com/software_license_agreement_liberty_v2
emilmont 77:869cf507173a 19 *
emilmont 77:869cf507173a 20 * Unless required by applicable law or agreed to in writing, software
emilmont 77:869cf507173a 21 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 77:869cf507173a 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 77:869cf507173a 23 * See the License for the specific language governing permissions and
emilmont 77:869cf507173a 24 * limitations under the License.
emilmont 77:869cf507173a 25 *
emilmont 77:869cf507173a 26 ******************************************************************************
emilmont 77:869cf507173a 27 */
emilmont 77:869cf507173a 28
emilmont 77:869cf507173a 29 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 30 #ifndef __STM32F0XX_PWR_H
emilmont 77:869cf507173a 31 #define __STM32F0XX_PWR_H
emilmont 77:869cf507173a 32
emilmont 77:869cf507173a 33 #ifdef __cplusplus
emilmont 77:869cf507173a 34 extern "C" {
emilmont 77:869cf507173a 35 #endif
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 38 #include "stm32f0xx.h"
emilmont 77:869cf507173a 39
emilmont 77:869cf507173a 40 /** @addtogroup STM32F0xx_StdPeriph_Driver
emilmont 77:869cf507173a 41 * @{
emilmont 77:869cf507173a 42 */
emilmont 77:869cf507173a 43
emilmont 77:869cf507173a 44 /** @addtogroup PWR
emilmont 77:869cf507173a 45 * @{
emilmont 77:869cf507173a 46 */
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 51
emilmont 77:869cf507173a 52 /** @defgroup PWR_Exported_Constants
emilmont 77:869cf507173a 53 * @{
emilmont 77:869cf507173a 54 */
emilmont 77:869cf507173a 55
emilmont 77:869cf507173a 56 /** @defgroup PWR_PVD_detection_level
emilmont 77:869cf507173a 57 * @brief This parameters are only applicable for STM32F051 and STM32F072 devices
emilmont 77:869cf507173a 58 * @{
emilmont 77:869cf507173a 59 */
emilmont 77:869cf507173a 60
emilmont 77:869cf507173a 61 #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
emilmont 77:869cf507173a 62 #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
emilmont 77:869cf507173a 63 #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
emilmont 77:869cf507173a 64 #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
emilmont 77:869cf507173a 65 #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
emilmont 77:869cf507173a 66 #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
emilmont 77:869cf507173a 67 #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
emilmont 77:869cf507173a 68 #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
emilmont 77:869cf507173a 69
emilmont 77:869cf507173a 70 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
emilmont 77:869cf507173a 71 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
emilmont 77:869cf507173a 72 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
emilmont 77:869cf507173a 73 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
emilmont 77:869cf507173a 74 /**
emilmont 77:869cf507173a 75 * @}
emilmont 77:869cf507173a 76 */
emilmont 77:869cf507173a 77
emilmont 77:869cf507173a 78 /** @defgroup PWR_WakeUp_Pins
emilmont 77:869cf507173a 79 * @{
emilmont 77:869cf507173a 80 */
emilmont 77:869cf507173a 81
emilmont 77:869cf507173a 82 #define PWR_WakeUpPin_1 PWR_CSR_EWUP1
emilmont 77:869cf507173a 83 #define PWR_WakeUpPin_2 PWR_CSR_EWUP2
emilmont 77:869cf507173a 84 #define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 85 #define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 86 #define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 87 #define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 88 #define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 89 #define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 90 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \
emilmont 77:869cf507173a 91 ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \
emilmont 77:869cf507173a 92 ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \
emilmont 77:869cf507173a 93 ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8))
emilmont 77:869cf507173a 94 /**
emilmont 77:869cf507173a 95 * @}
emilmont 77:869cf507173a 96 */
emilmont 77:869cf507173a 97
emilmont 77:869cf507173a 98
emilmont 77:869cf507173a 99 /** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
emilmont 77:869cf507173a 100 * @{
emilmont 77:869cf507173a 101 */
emilmont 77:869cf507173a 102
emilmont 77:869cf507173a 103 #define PWR_Regulator_ON ((uint32_t)0x00000000)
emilmont 77:869cf507173a 104 #define PWR_Regulator_LowPower PWR_CR_LPSDSR
emilmont 77:869cf507173a 105 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
emilmont 77:869cf507173a 106 ((REGULATOR) == PWR_Regulator_LowPower))
emilmont 77:869cf507173a 107 /**
emilmont 77:869cf507173a 108 * @}
emilmont 77:869cf507173a 109 */
emilmont 77:869cf507173a 110
emilmont 77:869cf507173a 111 /** @defgroup PWR_SLEEP_mode_entry
emilmont 77:869cf507173a 112 * @{
emilmont 77:869cf507173a 113 */
emilmont 77:869cf507173a 114
emilmont 77:869cf507173a 115 #define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
emilmont 77:869cf507173a 116 #define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
emilmont 77:869cf507173a 117 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
emilmont 77:869cf507173a 118
emilmont 77:869cf507173a 119 /**
emilmont 77:869cf507173a 120 * @}
emilmont 77:869cf507173a 121 */
emilmont 77:869cf507173a 122
emilmont 77:869cf507173a 123 /** @defgroup PWR_STOP_mode_entry
emilmont 77:869cf507173a 124 * @{
emilmont 77:869cf507173a 125 */
emilmont 77:869cf507173a 126
emilmont 77:869cf507173a 127 #define PWR_STOPEntry_WFI ((uint8_t)0x01)
emilmont 77:869cf507173a 128 #define PWR_STOPEntry_WFE ((uint8_t)0x02)
emilmont 77:869cf507173a 129 #define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03)
emilmont 77:869cf507173a 130 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\
emilmont 77:869cf507173a 131 ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT))
emilmont 77:869cf507173a 132
emilmont 77:869cf507173a 133 /**
emilmont 77:869cf507173a 134 * @}
emilmont 77:869cf507173a 135 */
emilmont 77:869cf507173a 136
emilmont 77:869cf507173a 137 /** @defgroup PWR_Flag
emilmont 77:869cf507173a 138 * @{
emilmont 77:869cf507173a 139 */
emilmont 77:869cf507173a 140
emilmont 77:869cf507173a 141 #define PWR_FLAG_WU PWR_CSR_WUF
emilmont 77:869cf507173a 142 #define PWR_FLAG_SB PWR_CSR_SBF
emilmont 77:869cf507173a 143 #define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */
emilmont 77:869cf507173a 144 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
emilmont 77:869cf507173a 145
emilmont 77:869cf507173a 146 #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
emilmont 77:869cf507173a 147 ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
emilmont 77:869cf507173a 148
emilmont 77:869cf507173a 149 #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
emilmont 77:869cf507173a 150 /**
emilmont 77:869cf507173a 151 * @}
emilmont 77:869cf507173a 152 */
emilmont 77:869cf507173a 153
emilmont 77:869cf507173a 154 /**
emilmont 77:869cf507173a 155 * @}
emilmont 77:869cf507173a 156 */
emilmont 77:869cf507173a 157
emilmont 77:869cf507173a 158 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 159 /* Exported functions ------------------------------------------------------- */
emilmont 77:869cf507173a 160
emilmont 77:869cf507173a 161 /* Function used to set the PWR configuration to the default reset state ******/
emilmont 77:869cf507173a 162 void PWR_DeInit(void);
emilmont 77:869cf507173a 163
emilmont 77:869cf507173a 164 /* Backup Domain Access function **********************************************/
emilmont 77:869cf507173a 165 void PWR_BackupAccessCmd(FunctionalState NewState);
emilmont 77:869cf507173a 166
emilmont 77:869cf507173a 167 /* PVD configuration functions ************************************************/
emilmont 77:869cf507173a 168 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */
emilmont 77:869cf507173a 169 void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */
emilmont 77:869cf507173a 170
emilmont 77:869cf507173a 171 /* WakeUp pins configuration functions ****************************************/
emilmont 77:869cf507173a 172 void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
emilmont 77:869cf507173a 173
emilmont 77:869cf507173a 174 /* Low Power modes configuration functions ************************************/
emilmont 77:869cf507173a 175 void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
emilmont 77:869cf507173a 176 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
emilmont 77:869cf507173a 177 void PWR_EnterSTANDBYMode(void);
emilmont 77:869cf507173a 178
emilmont 77:869cf507173a 179 /* Flags management functions *************************************************/
emilmont 77:869cf507173a 180 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
emilmont 77:869cf507173a 181 void PWR_ClearFlag(uint32_t PWR_FLAG);
emilmont 77:869cf507173a 182
emilmont 77:869cf507173a 183 #ifdef __cplusplus
emilmont 77:869cf507173a 184 }
emilmont 77:869cf507173a 185 #endif
emilmont 77:869cf507173a 186
emilmont 77:869cf507173a 187 #endif /* __STM32F0XX_PWR_H */
emilmont 77:869cf507173a 188
emilmont 77:869cf507173a 189 /**
emilmont 77:869cf507173a 190 * @}
emilmont 77:869cf507173a 191 */
emilmont 77:869cf507173a 192
emilmont 77:869cf507173a 193 /**
emilmont 77:869cf507173a 194 * @}
emilmont 77:869cf507173a 195 */
emilmont 77:869cf507173a 196
emilmont 77:869cf507173a 197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/