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TARGET_ARCH_MAX/stm32f4xx_hal_rcc_ex.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Child:
92:4fc01daae5a5
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_rcc_ex.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 89:552587b429a1 5 * @version V1.1.0RC2
bogdanm 89:552587b429a1 6 * @date 14-May-2014
bogdanm 89:552587b429a1 7 * @brief Header file of RCC HAL Extension module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_RCC_EX_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_RCC_EX_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup RCCEx
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 58 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 59 /**
bogdanm 89:552587b429a1 60 * @brief PLLI2S Clock structure definition
bogdanm 89:552587b429a1 61 */
bogdanm 89:552587b429a1 62 typedef struct
bogdanm 89:552587b429a1 63 {
bogdanm 89:552587b429a1 64 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 89:552587b429a1 65 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 89:552587b429a1 66 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 89:552587b429a1 67
bogdanm 89:552587b429a1 68 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm 89:552587b429a1 69 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 89:552587b429a1 70 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 89:552587b429a1 71
bogdanm 89:552587b429a1 72 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm 89:552587b429a1 73 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 89:552587b429a1 74 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm 89:552587b429a1 75 }RCC_PLLI2SInitTypeDef;
bogdanm 89:552587b429a1 76
bogdanm 89:552587b429a1 77 /**
bogdanm 89:552587b429a1 78 * @brief PLLSAI Clock structure definition
bogdanm 89:552587b429a1 79 */
bogdanm 89:552587b429a1 80 typedef struct
bogdanm 89:552587b429a1 81 {
bogdanm 89:552587b429a1 82 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 89:552587b429a1 83 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 89:552587b429a1 84 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm 89:552587b429a1 85
bogdanm 89:552587b429a1 86 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm 89:552587b429a1 87 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 89:552587b429a1 88 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
bogdanm 89:552587b429a1 89
bogdanm 89:552587b429a1 90 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm 89:552587b429a1 91 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 89:552587b429a1 92 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
bogdanm 89:552587b429a1 93
bogdanm 89:552587b429a1 94 }RCC_PLLSAIInitTypeDef;
bogdanm 89:552587b429a1 95 /**
bogdanm 89:552587b429a1 96 * @brief RCC extended clocks structure definition
bogdanm 89:552587b429a1 97 */
bogdanm 89:552587b429a1 98 typedef struct
bogdanm 89:552587b429a1 99 {
bogdanm 89:552587b429a1 100 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 89:552587b429a1 101 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 89:552587b429a1 102
bogdanm 89:552587b429a1 103 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm 89:552587b429a1 104 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 89:552587b429a1 105
bogdanm 89:552587b429a1 106 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
bogdanm 89:552587b429a1 107 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
bogdanm 89:552587b429a1 108
bogdanm 89:552587b429a1 109 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm 89:552587b429a1 110 This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm 89:552587b429a1 111 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
bogdanm 89:552587b429a1 112
bogdanm 89:552587b429a1 113 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
bogdanm 89:552587b429a1 114 This parameter must be a number between Min_Data = 1 and Max_Data = 32
bogdanm 89:552587b429a1 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
bogdanm 89:552587b429a1 116
bogdanm 89:552587b429a1 117 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
bogdanm 89:552587b429a1 118 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
bogdanm 89:552587b429a1 119
bogdanm 89:552587b429a1 120 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm 89:552587b429a1 121 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 89:552587b429a1 122
bogdanm 89:552587b429a1 123 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
bogdanm 89:552587b429a1 124 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
bogdanm 89:552587b429a1 125
bogdanm 89:552587b429a1 126 }RCC_PeriphCLKInitTypeDef;
bogdanm 89:552587b429a1 127 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 128
bogdanm 89:552587b429a1 129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
bogdanm 89:552587b429a1 130 /**
bogdanm 89:552587b429a1 131 * @brief PLLI2S Clock structure definition
bogdanm 89:552587b429a1 132 */
bogdanm 89:552587b429a1 133 typedef struct
bogdanm 89:552587b429a1 134 {
bogdanm 89:552587b429a1 135 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 89:552587b429a1 136 This parameter must be a number between Min_Data = 192 and Max_Data = 432
bogdanm 89:552587b429a1 137 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 89:552587b429a1 138
bogdanm 89:552587b429a1 139 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm 89:552587b429a1 140 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 89:552587b429a1 141 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 89:552587b429a1 142
bogdanm 89:552587b429a1 143 }RCC_PLLI2SInitTypeDef;
bogdanm 89:552587b429a1 144
bogdanm 89:552587b429a1 145
bogdanm 89:552587b429a1 146 /**
bogdanm 89:552587b429a1 147 * @brief RCC extended clocks structure definition
bogdanm 89:552587b429a1 148 */
bogdanm 89:552587b429a1 149 typedef struct
bogdanm 89:552587b429a1 150 {
bogdanm 89:552587b429a1 151 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 89:552587b429a1 152 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 89:552587b429a1 153
bogdanm 89:552587b429a1 154 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
bogdanm 89:552587b429a1 155 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
bogdanm 89:552587b429a1 156
bogdanm 89:552587b429a1 157 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
bogdanm 89:552587b429a1 158 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 89:552587b429a1 159
bogdanm 89:552587b429a1 160 }RCC_PeriphCLKInitTypeDef;
bogdanm 89:552587b429a1 161 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
bogdanm 89:552587b429a1 162 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 163 /** @defgroup RCCEx_Exported_Constants
bogdanm 89:552587b429a1 164 * @{
bogdanm 89:552587b429a1 165 */
bogdanm 89:552587b429a1 166
bogdanm 89:552587b429a1 167 /** @defgroup RCCEx_Periph_Clock_Selection
bogdanm 89:552587b429a1 168 * @{
bogdanm 89:552587b429a1 169 */
bogdanm 89:552587b429a1 170 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 171 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 172 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 173 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 174 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 175 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 176 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 177 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
bogdanm 89:552587b429a1 178 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 179
bogdanm 89:552587b429a1 180 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE)
bogdanm 89:552587b429a1 181 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 182 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 183 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
bogdanm 89:552587b429a1 184 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE */
bogdanm 89:552587b429a1 185
bogdanm 89:552587b429a1 186 /**
bogdanm 89:552587b429a1 187 * @}
bogdanm 89:552587b429a1 188 */
bogdanm 89:552587b429a1 189
bogdanm 89:552587b429a1 190 /** @defgroup RCCEx_BitAddress_AliasRegion
bogdanm 89:552587b429a1 191 * @brief RCC registers bit address in the alias region
bogdanm 89:552587b429a1 192 * @{
bogdanm 89:552587b429a1 193 */
bogdanm 89:552587b429a1 194 /* --- CR Register ---*/
bogdanm 89:552587b429a1 195 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 196 /* Alias word address of PLLSAION bit */
bogdanm 89:552587b429a1 197 #define PLLSAION_BitNumber 0x1C
bogdanm 89:552587b429a1 198 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
bogdanm 89:552587b429a1 199
bogdanm 89:552587b429a1 200 /* --- DCKCFGR Register ---*/
bogdanm 89:552587b429a1 201 /* Alias word address of TIMPRE bit */
bogdanm 89:552587b429a1 202 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
bogdanm 89:552587b429a1 203 #define TIMPRE_BitNumber 0x18
bogdanm 89:552587b429a1 204 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
bogdanm 89:552587b429a1 205 /**
bogdanm 89:552587b429a1 206 * @}
bogdanm 89:552587b429a1 207 */
bogdanm 89:552587b429a1 208
bogdanm 89:552587b429a1 209 /** @defgroup RCCEx_PLLI2S_Clock_Source
bogdanm 89:552587b429a1 210 * @{
bogdanm 89:552587b429a1 211 */
bogdanm 89:552587b429a1 212 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm 89:552587b429a1 213 /**
bogdanm 89:552587b429a1 214 * @}
bogdanm 89:552587b429a1 215 */
bogdanm 89:552587b429a1 216
bogdanm 89:552587b429a1 217 /** @defgroup RCCEx_PLLSAI_Clock_Source
bogdanm 89:552587b429a1 218 * @{
bogdanm 89:552587b429a1 219 */
bogdanm 89:552587b429a1 220 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm 89:552587b429a1 221 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
bogdanm 89:552587b429a1 222 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm 89:552587b429a1 223 /**
bogdanm 89:552587b429a1 224 * @}
bogdanm 89:552587b429a1 225 */
bogdanm 89:552587b429a1 226
bogdanm 89:552587b429a1 227 /** @defgroup RCCEx_PLLSAI_DIVQ
bogdanm 89:552587b429a1 228 * @{
bogdanm 89:552587b429a1 229 */
bogdanm 89:552587b429a1 230 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm 89:552587b429a1 231 /**
bogdanm 89:552587b429a1 232 * @}
bogdanm 89:552587b429a1 233 */
bogdanm 89:552587b429a1 234
bogdanm 89:552587b429a1 235 /** @defgroup RCCEx_PLLI2S_DIVQ
bogdanm 89:552587b429a1 236 * @{
bogdanm 89:552587b429a1 237 */
bogdanm 89:552587b429a1 238 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
bogdanm 89:552587b429a1 239
bogdanm 89:552587b429a1 240 /**
bogdanm 89:552587b429a1 241 * @}
bogdanm 89:552587b429a1 242 */
bogdanm 89:552587b429a1 243
bogdanm 89:552587b429a1 244 /** @defgroup RCCEx_PLLSAI_DIVR
bogdanm 89:552587b429a1 245 * @{
bogdanm 89:552587b429a1 246 */
bogdanm 89:552587b429a1 247 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 248 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
bogdanm 89:552587b429a1 249 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
bogdanm 89:552587b429a1 250 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
bogdanm 89:552587b429a1 251 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
bogdanm 89:552587b429a1 252 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
bogdanm 89:552587b429a1 253 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
bogdanm 89:552587b429a1 254 ((VALUE) == RCC_PLLSAIDIVR_16))
bogdanm 89:552587b429a1 255
bogdanm 89:552587b429a1 256 /**
bogdanm 89:552587b429a1 257 * @}
bogdanm 89:552587b429a1 258 */
bogdanm 89:552587b429a1 259
bogdanm 89:552587b429a1 260 /** @defgroup RCCEx_SAI_BlockA_Clock_Source
bogdanm 89:552587b429a1 261 * @{
bogdanm 89:552587b429a1 262 */
bogdanm 89:552587b429a1 263 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 264 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
bogdanm 89:552587b429a1 265 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
bogdanm 89:552587b429a1 266 /**
bogdanm 89:552587b429a1 267 * @}
bogdanm 89:552587b429a1 268 */
bogdanm 89:552587b429a1 269
bogdanm 89:552587b429a1 270 /** @defgroup RCCEx_SAI_BlockB_Clock_Source
bogdanm 89:552587b429a1 271 * @{
bogdanm 89:552587b429a1 272 */
bogdanm 89:552587b429a1 273 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 274 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
bogdanm 89:552587b429a1 275 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
bogdanm 89:552587b429a1 276 /**
bogdanm 89:552587b429a1 277 * @}
bogdanm 89:552587b429a1 278 */
bogdanm 89:552587b429a1 279
bogdanm 89:552587b429a1 280 /** @defgroup RCCEx_TIM_PRescaler_Selection
bogdanm 89:552587b429a1 281 * @{
bogdanm 89:552587b429a1 282 */
bogdanm 89:552587b429a1 283 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
bogdanm 89:552587b429a1 284 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
bogdanm 89:552587b429a1 285 /**
bogdanm 89:552587b429a1 286 * @}
bogdanm 89:552587b429a1 287 */
bogdanm 89:552587b429a1 288 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 289 /**
bogdanm 89:552587b429a1 290 * @}
bogdanm 89:552587b429a1 291 */
bogdanm 89:552587b429a1 292
bogdanm 89:552587b429a1 293 /**
bogdanm 89:552587b429a1 294 * @}
bogdanm 89:552587b429a1 295 */
bogdanm 89:552587b429a1 296
bogdanm 89:552587b429a1 297 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 298
bogdanm 89:552587b429a1 299 /** @brief Enables or disables the AHB1 peripheral clock.
bogdanm 89:552587b429a1 300 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 301 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 302 * using it.
bogdanm 89:552587b429a1 303 */
bogdanm 89:552587b429a1 304
bogdanm 89:552587b429a1 305 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 306 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
bogdanm 89:552587b429a1 307 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
bogdanm 89:552587b429a1 308 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
bogdanm 89:552587b429a1 309 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
bogdanm 89:552587b429a1 310 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
bogdanm 89:552587b429a1 311 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
bogdanm 89:552587b429a1 312 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
bogdanm 89:552587b429a1 313 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
bogdanm 89:552587b429a1 314 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
bogdanm 89:552587b429a1 315
bogdanm 89:552587b429a1 316 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
bogdanm 89:552587b429a1 317 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm 89:552587b429a1 318 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
bogdanm 89:552587b429a1 319 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
bogdanm 89:552587b429a1 320 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
bogdanm 89:552587b429a1 321 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
bogdanm 89:552587b429a1 322 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
bogdanm 89:552587b429a1 323 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
bogdanm 89:552587b429a1 324 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
bogdanm 89:552587b429a1 325 #endif /* !(STM32F401xC && STM32F401xE) */
bogdanm 89:552587b429a1 326
bogdanm 89:552587b429a1 327 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 328 #define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
bogdanm 89:552587b429a1 329 #define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
bogdanm 89:552587b429a1 330 #define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
bogdanm 89:552587b429a1 331
bogdanm 89:552587b429a1 332 #define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
bogdanm 89:552587b429a1 333 #define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
bogdanm 89:552587b429a1 334 #define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
bogdanm 89:552587b429a1 335 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
bogdanm 89:552587b429a1 336
bogdanm 89:552587b429a1 337 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 338 /**
bogdanm 89:552587b429a1 339 * @brief Enable ETHERNET clock.
bogdanm 89:552587b429a1 340 */
bogdanm 89:552587b429a1 341 #define __ETH_CLK_ENABLE() do { \
bogdanm 89:552587b429a1 342 __ETHMAC_CLK_ENABLE(); \
bogdanm 89:552587b429a1 343 __ETHMACTX_CLK_ENABLE(); \
bogdanm 89:552587b429a1 344 __ETHMACRX_CLK_ENABLE(); \
bogdanm 89:552587b429a1 345 } while(0)
bogdanm 89:552587b429a1 346
bogdanm 89:552587b429a1 347 /**
bogdanm 89:552587b429a1 348 * @brief Disable ETHERNET clock.
bogdanm 89:552587b429a1 349 */
bogdanm 89:552587b429a1 350 #define __ETH_CLK_DISABLE() do { \
bogdanm 89:552587b429a1 351 __ETHMACTX_CLK_DISABLE(); \
bogdanm 89:552587b429a1 352 __ETHMACRX_CLK_DISABLE(); \
bogdanm 89:552587b429a1 353 __ETHMAC_CLK_DISABLE(); \
bogdanm 89:552587b429a1 354 } while(0)
bogdanm 89:552587b429a1 355 #endif /* !(STM32F401xC && STM32F401xE) */
bogdanm 89:552587b429a1 356
bogdanm 89:552587b429a1 357 /** @brief Enable or disable the AHB2 peripheral clock.
bogdanm 89:552587b429a1 358 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 359 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 360 * using it.
bogdanm 89:552587b429a1 361 */
bogdanm 89:552587b429a1 362 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 363 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
bogdanm 89:552587b429a1 364 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
bogdanm 89:552587b429a1 365 #endif /* !(STM32F401xC && STM32F401xE) */
bogdanm 89:552587b429a1 366
bogdanm 89:552587b429a1 367 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 368 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
bogdanm 89:552587b429a1 369 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
bogdanm 89:552587b429a1 370
bogdanm 89:552587b429a1 371 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
bogdanm 89:552587b429a1 372 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
bogdanm 89:552587b429a1 373
bogdanm 89:552587b429a1 374 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
bogdanm 89:552587b429a1 375
bogdanm 89:552587b429a1 376 /** @brief Enables or disables the AHB3 peripheral clock.
bogdanm 89:552587b429a1 377 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 378 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 379 * using it.
bogdanm 89:552587b429a1 380 */
bogdanm 89:552587b429a1 381 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 89:552587b429a1 382 #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
bogdanm 89:552587b429a1 383 #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
bogdanm 89:552587b429a1 384 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 385
bogdanm 89:552587b429a1 386 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 387 #define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
bogdanm 89:552587b429a1 388 #define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
bogdanm 89:552587b429a1 389 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
bogdanm 89:552587b429a1 390
bogdanm 89:552587b429a1 391
bogdanm 89:552587b429a1 392 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 89:552587b429a1 393 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 394 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 395 * using it.
bogdanm 89:552587b429a1 396 */
bogdanm 89:552587b429a1 397 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 398 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
bogdanm 89:552587b429a1 399 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
bogdanm 89:552587b429a1 400 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
bogdanm 89:552587b429a1 401 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
bogdanm 89:552587b429a1 402 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
bogdanm 89:552587b429a1 403 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
bogdanm 89:552587b429a1 404 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
bogdanm 89:552587b429a1 405 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
bogdanm 89:552587b429a1 406 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
bogdanm 89:552587b429a1 407 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
bogdanm 89:552587b429a1 408 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
bogdanm 89:552587b429a1 409 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
bogdanm 89:552587b429a1 410
bogdanm 89:552587b429a1 411 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm 89:552587b429a1 412 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm 89:552587b429a1 413 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm 89:552587b429a1 414 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm 89:552587b429a1 415 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm 89:552587b429a1 416 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm 89:552587b429a1 417 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm 89:552587b429a1 418 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm 89:552587b429a1 419 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm 89:552587b429a1 420 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
bogdanm 89:552587b429a1 421 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
bogdanm 89:552587b429a1 422 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm 89:552587b429a1 423 #endif /* !(STM32F401xC && STM32F401xE) */
bogdanm 89:552587b429a1 424
bogdanm 89:552587b429a1 425 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 426 #define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
bogdanm 89:552587b429a1 427 #define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
bogdanm 89:552587b429a1 428
bogdanm 89:552587b429a1 429 #define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
bogdanm 89:552587b429a1 430 #define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
bogdanm 89:552587b429a1 431 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
bogdanm 89:552587b429a1 432
bogdanm 89:552587b429a1 433 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 89:552587b429a1 434 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 435 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 436 * using it.
bogdanm 89:552587b429a1 437 */
bogdanm 89:552587b429a1 438 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 439 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
bogdanm 89:552587b429a1 440 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
bogdanm 89:552587b429a1 441 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
bogdanm 89:552587b429a1 442
bogdanm 89:552587b429a1 443 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm 89:552587b429a1 444 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
bogdanm 89:552587b429a1 445 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
bogdanm 89:552587b429a1 446 #endif /* !(STM32F401xC && STM32F401xE) */
bogdanm 89:552587b429a1 447
bogdanm 89:552587b429a1 448 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 449 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
bogdanm 89:552587b429a1 450 #define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
bogdanm 89:552587b429a1 451 #define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
bogdanm 89:552587b429a1 452 #define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
bogdanm 89:552587b429a1 453
bogdanm 89:552587b429a1 454 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
bogdanm 89:552587b429a1 455 #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
bogdanm 89:552587b429a1 456 #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
bogdanm 89:552587b429a1 457 #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
bogdanm 89:552587b429a1 458 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 459
bogdanm 89:552587b429a1 460 /** @brief Force or release AHB1 peripheral reset.
bogdanm 89:552587b429a1 461 */
bogdanm 89:552587b429a1 462 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 463 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
bogdanm 89:552587b429a1 464 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
bogdanm 89:552587b429a1 465 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
bogdanm 89:552587b429a1 466 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
bogdanm 89:552587b429a1 467 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
bogdanm 89:552587b429a1 468
bogdanm 89:552587b429a1 469 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm 89:552587b429a1 470 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm 89:552587b429a1 471 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm 89:552587b429a1 472 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
bogdanm 89:552587b429a1 473 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
bogdanm 89:552587b429a1 474 #endif /* !STM32F401xC && STM32F401xE */
bogdanm 89:552587b429a1 475
bogdanm 89:552587b429a1 476 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 477 #define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
bogdanm 89:552587b429a1 478 #define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
bogdanm 89:552587b429a1 479 #define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
bogdanm 89:552587b429a1 480
bogdanm 89:552587b429a1 481 #define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
bogdanm 89:552587b429a1 482 #define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
bogdanm 89:552587b429a1 483 #define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
bogdanm 89:552587b429a1 484 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 485
bogdanm 89:552587b429a1 486 /** @brief Force or release AHB2 peripheral reset.
bogdanm 89:552587b429a1 487 */
bogdanm 89:552587b429a1 488 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 489 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
bogdanm 89:552587b429a1 490 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
bogdanm 89:552587b429a1 491 #endif /* !STM32F401xC && STM32F401xE */
bogdanm 89:552587b429a1 492
bogdanm 89:552587b429a1 493 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 494 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
bogdanm 89:552587b429a1 495 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
bogdanm 89:552587b429a1 496
bogdanm 89:552587b429a1 497 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
bogdanm 89:552587b429a1 498 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
bogdanm 89:552587b429a1 499
bogdanm 89:552587b429a1 500 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
bogdanm 89:552587b429a1 501
bogdanm 89:552587b429a1 502 /** @brief Force or release AHB3 peripheral reset
bogdanm 89:552587b429a1 503 */
bogdanm 89:552587b429a1 504 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 89:552587b429a1 505 #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
bogdanm 89:552587b429a1 506 #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
bogdanm 89:552587b429a1 507 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 508
bogdanm 89:552587b429a1 509 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 510 #define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
bogdanm 89:552587b429a1 511 #define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
bogdanm 89:552587b429a1 512 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 513
bogdanm 89:552587b429a1 514 /** @brief Force or release APB1 peripheral reset.
bogdanm 89:552587b429a1 515 */
bogdanm 89:552587b429a1 516 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 517 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
bogdanm 89:552587b429a1 518 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
bogdanm 89:552587b429a1 519 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
bogdanm 89:552587b429a1 520 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
bogdanm 89:552587b429a1 521 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
bogdanm 89:552587b429a1 522 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
bogdanm 89:552587b429a1 523 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
bogdanm 89:552587b429a1 524 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
bogdanm 89:552587b429a1 525 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
bogdanm 89:552587b429a1 526 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
bogdanm 89:552587b429a1 527 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
bogdanm 89:552587b429a1 528
bogdanm 89:552587b429a1 529 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm 89:552587b429a1 530 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm 89:552587b429a1 531 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm 89:552587b429a1 532 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm 89:552587b429a1 533 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm 89:552587b429a1 534 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm 89:552587b429a1 535 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm 89:552587b429a1 536 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm 89:552587b429a1 537 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
bogdanm 89:552587b429a1 538 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
bogdanm 89:552587b429a1 539 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm 89:552587b429a1 540 #endif /* !STM32F401xC && STM32F401xE */
bogdanm 89:552587b429a1 541
bogdanm 89:552587b429a1 542 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 543 #define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
bogdanm 89:552587b429a1 544 #define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
bogdanm 89:552587b429a1 545
bogdanm 89:552587b429a1 546 #define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
bogdanm 89:552587b429a1 547 #define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
bogdanm 89:552587b429a1 548 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 549
bogdanm 89:552587b429a1 550 /** @brief Force or release APB2 peripheral reset.
bogdanm 89:552587b429a1 551 */
bogdanm 89:552587b429a1 552 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 553 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
bogdanm 89:552587b429a1 554 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm 89:552587b429a1 555 #endif /* !STM32F401xC && STM32F401xE */
bogdanm 89:552587b429a1 556
bogdanm 89:552587b429a1 557 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 558 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
bogdanm 89:552587b429a1 559 #define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
bogdanm 89:552587b429a1 560 #define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
bogdanm 89:552587b429a1 561 #define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
bogdanm 89:552587b429a1 562
bogdanm 89:552587b429a1 563 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
bogdanm 89:552587b429a1 564 #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
bogdanm 89:552587b429a1 565 #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
bogdanm 89:552587b429a1 566 #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
bogdanm 89:552587b429a1 567 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 568
bogdanm 89:552587b429a1 569
bogdanm 89:552587b429a1 570 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 571 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 572 * power consumption.
bogdanm 89:552587b429a1 573 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 574 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 575 */
bogdanm 89:552587b429a1 576 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 577 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
bogdanm 89:552587b429a1 578 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
bogdanm 89:552587b429a1 579 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
bogdanm 89:552587b429a1 580 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
bogdanm 89:552587b429a1 581 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
bogdanm 89:552587b429a1 582 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm 89:552587b429a1 583 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm 89:552587b429a1 584 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm 89:552587b429a1 585 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
bogdanm 89:552587b429a1 586 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm 89:552587b429a1 587
bogdanm 89:552587b429a1 588 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
bogdanm 89:552587b429a1 589 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
bogdanm 89:552587b429a1 590 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
bogdanm 89:552587b429a1 591 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
bogdanm 89:552587b429a1 592 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
bogdanm 89:552587b429a1 593 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
bogdanm 89:552587b429a1 594 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
bogdanm 89:552587b429a1 595 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
bogdanm 89:552587b429a1 596 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
bogdanm 89:552587b429a1 597 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
bogdanm 89:552587b429a1 598 #endif /* !STM32F401xC && STM32F401xE */
bogdanm 89:552587b429a1 599
bogdanm 89:552587b429a1 600 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 601 #define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
bogdanm 89:552587b429a1 602 #define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
bogdanm 89:552587b429a1 603 #define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
bogdanm 89:552587b429a1 604 #define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
bogdanm 89:552587b429a1 605
bogdanm 89:552587b429a1 606 #define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
bogdanm 89:552587b429a1 607 #define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
bogdanm 89:552587b429a1 608 #define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
bogdanm 89:552587b429a1 609 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 610
bogdanm 89:552587b429a1 611 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 612 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 613 * power consumption.
bogdanm 89:552587b429a1 614 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 615 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 616 */
bogdanm 89:552587b429a1 617 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 618 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
bogdanm 89:552587b429a1 619 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
bogdanm 89:552587b429a1 620 #endif /* !STM32F401xC && STM32F401xE */
bogdanm 89:552587b429a1 621
bogdanm 89:552587b429a1 622 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 623 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
bogdanm 89:552587b429a1 624 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
bogdanm 89:552587b429a1 625
bogdanm 89:552587b429a1 626 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
bogdanm 89:552587b429a1 627 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
bogdanm 89:552587b429a1 628
bogdanm 89:552587b429a1 629 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx */
bogdanm 89:552587b429a1 630
bogdanm 89:552587b429a1 631 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 632 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 633 * power consumption.
bogdanm 89:552587b429a1 634 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 635 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 636 */
bogdanm 89:552587b429a1 637 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 89:552587b429a1 638 #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
bogdanm 89:552587b429a1 639 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
bogdanm 89:552587b429a1 640 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 89:552587b429a1 641
bogdanm 89:552587b429a1 642 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 643 #define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
bogdanm 89:552587b429a1 644 #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
bogdanm 89:552587b429a1 645 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 646
bogdanm 89:552587b429a1 647 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 648 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 649 * power consumption.
bogdanm 89:552587b429a1 650 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 651 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 652 */
bogdanm 89:552587b429a1 653 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 654 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
bogdanm 89:552587b429a1 655 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
bogdanm 89:552587b429a1 656 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
bogdanm 89:552587b429a1 657 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
bogdanm 89:552587b429a1 658 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
bogdanm 89:552587b429a1 659 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
bogdanm 89:552587b429a1 660 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
bogdanm 89:552587b429a1 661 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
bogdanm 89:552587b429a1 662 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
bogdanm 89:552587b429a1 663 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
bogdanm 89:552587b429a1 664 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
bogdanm 89:552587b429a1 665
bogdanm 89:552587b429a1 666 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
bogdanm 89:552587b429a1 667 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
bogdanm 89:552587b429a1 668 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
bogdanm 89:552587b429a1 669 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
bogdanm 89:552587b429a1 670 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
bogdanm 89:552587b429a1 671 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
bogdanm 89:552587b429a1 672 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
bogdanm 89:552587b429a1 673 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
bogdanm 89:552587b429a1 674 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
bogdanm 89:552587b429a1 675 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
bogdanm 89:552587b429a1 676 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
bogdanm 89:552587b429a1 677 #endif /* !STM32F401xC && STM32F401xE */
bogdanm 89:552587b429a1 678
bogdanm 89:552587b429a1 679 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 680 #define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
bogdanm 89:552587b429a1 681 #define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
bogdanm 89:552587b429a1 682
bogdanm 89:552587b429a1 683 #define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
bogdanm 89:552587b429a1 684 #define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
bogdanm 89:552587b429a1 685 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 686
bogdanm 89:552587b429a1 687 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 688 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 689 * power consumption.
bogdanm 89:552587b429a1 690 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 691 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 692 */
bogdanm 89:552587b429a1 693 #if !defined(STM32F401xC) && !defined(STM32F401xE)
bogdanm 89:552587b429a1 694 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
bogdanm 89:552587b429a1 695 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
bogdanm 89:552587b429a1 696 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
bogdanm 89:552587b429a1 697
bogdanm 89:552587b429a1 698 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
bogdanm 89:552587b429a1 699 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
bogdanm 89:552587b429a1 700 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
bogdanm 89:552587b429a1 701 #endif /* !STM32F401xC && STM32F401xE */
bogdanm 89:552587b429a1 702
bogdanm 89:552587b429a1 703 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 704 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
bogdanm 89:552587b429a1 705 #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
bogdanm 89:552587b429a1 706 #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
bogdanm 89:552587b429a1 707 #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
bogdanm 89:552587b429a1 708
bogdanm 89:552587b429a1 709 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
bogdanm 89:552587b429a1 710 #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
bogdanm 89:552587b429a1 711 #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
bogdanm 89:552587b429a1 712 #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
bogdanm 89:552587b429a1 713 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 714
bogdanm 89:552587b429a1 715 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 89:552587b429a1 716
bogdanm 89:552587b429a1 717 /** @brief Macro to configure the Timers clocks prescalers
bogdanm 89:552587b429a1 718 * @note This feature is only available with STM32F429x/439x Devices.
bogdanm 89:552587b429a1 719 * @param __PRESC__ : specifies the Timers clocks prescalers selection
bogdanm 89:552587b429a1 720 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 721 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
bogdanm 89:552587b429a1 722 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
bogdanm 89:552587b429a1 723 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
bogdanm 89:552587b429a1 724 * division by 4 or more.
bogdanm 89:552587b429a1 725 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
bogdanm 89:552587b429a1 726 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
bogdanm 89:552587b429a1 727 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
bogdanm 89:552587b429a1 728 * to division by 8 or more.
bogdanm 89:552587b429a1 729 */
bogdanm 89:552587b429a1 730 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
bogdanm 89:552587b429a1 731
bogdanm 89:552587b429a1 732 /** @brief Macros to Enable or Disable the PLLISAI.
bogdanm 89:552587b429a1 733 * @note The PLLSAI is only available with STM32F429x/439x Devices.
bogdanm 89:552587b429a1 734 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 89:552587b429a1 735 */
bogdanm 89:552587b429a1 736 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
bogdanm 89:552587b429a1 737 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
bogdanm 89:552587b429a1 738
bogdanm 89:552587b429a1 739 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
bogdanm 89:552587b429a1 740 * @note The PLLSAI is only available with STM32F429x/439x Devices.
bogdanm 89:552587b429a1 741 * @note This function must be used only when the PLLSAI is disabled.
bogdanm 89:552587b429a1 742 * @note PLLSAI clock source is common with the main PLL (configured in
bogdanm 89:552587b429a1 743 * RCC_PLLConfig function )
bogdanm 89:552587b429a1 744 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
bogdanm 89:552587b429a1 745 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 89:552587b429a1 746 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
bogdanm 89:552587b429a1 747 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm 89:552587b429a1 748 * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
bogdanm 89:552587b429a1 749 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 89:552587b429a1 750 * @param __PLLSAIR__: specifies the division factor for LTDC clock
bogdanm 89:552587b429a1 751 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 89:552587b429a1 752 */
bogdanm 89:552587b429a1 753 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
bogdanm 89:552587b429a1 754
bogdanm 89:552587b429a1 755 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
bogdanm 89:552587b429a1 756 * @note This macro must be used only when the PLLI2S is disabled.
bogdanm 89:552587b429a1 757 * @note PLLI2S clock source is common with the main PLL (configured in
bogdanm 89:552587b429a1 758 * HAL_RCC_ClockConfig() API)
bogdanm 89:552587b429a1 759 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 89:552587b429a1 760 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 89:552587b429a1 761 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm 89:552587b429a1 762 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm 89:552587b429a1 763 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
bogdanm 89:552587b429a1 764 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 89:552587b429a1 765 * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
bogdanm 89:552587b429a1 766 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
bogdanm 89:552587b429a1 767 * @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm 89:552587b429a1 768 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 89:552587b429a1 769 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm 89:552587b429a1 770 * on the I2S clock frequency.
bogdanm 89:552587b429a1 771 */
bogdanm 89:552587b429a1 772 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
bogdanm 89:552587b429a1 773
bogdanm 89:552587b429a1 774 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
bogdanm 89:552587b429a1 775 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm 89:552587b429a1 776 * @note This function must be called before enabling the PLLI2S.
bogdanm 89:552587b429a1 777 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
bogdanm 89:552587b429a1 778 * This parameter must be a number between 1 and 32.
bogdanm 89:552587b429a1 779 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
bogdanm 89:552587b429a1 780 */
bogdanm 89:552587b429a1 781 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
bogdanm 89:552587b429a1 782
bogdanm 89:552587b429a1 783 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
bogdanm 89:552587b429a1 784 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm 89:552587b429a1 785 * @note This function must be called before enabling the PLLSAI.
bogdanm 89:552587b429a1 786 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
bogdanm 89:552587b429a1 787 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
bogdanm 89:552587b429a1 788 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
bogdanm 89:552587b429a1 789 */
bogdanm 89:552587b429a1 790 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
bogdanm 89:552587b429a1 791
bogdanm 89:552587b429a1 792 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
bogdanm 89:552587b429a1 793 *
bogdanm 89:552587b429a1 794 * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
bogdanm 89:552587b429a1 795 * @note This function must be called before enabling the PLLSAI.
bogdanm 89:552587b429a1 796 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
bogdanm 89:552587b429a1 797 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
bogdanm 89:552587b429a1 798 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
bogdanm 89:552587b429a1 799 */
bogdanm 89:552587b429a1 800 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
bogdanm 89:552587b429a1 801
bogdanm 89:552587b429a1 802 /** @brief Macro to configure SAI1BlockA clock source selection.
bogdanm 89:552587b429a1 803 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm 89:552587b429a1 804 * @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm 89:552587b429a1 805 * the SAI clock.
bogdanm 89:552587b429a1 806 * @param __SOURCE__: specifies the SAI Block A clock source.
bogdanm 89:552587b429a1 807 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 808 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm 89:552587b429a1 809 * as SAI1 Block A clock.
bogdanm 89:552587b429a1 810 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm 89:552587b429a1 811 * as SAI1 Block A clock.
bogdanm 89:552587b429a1 812 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
bogdanm 89:552587b429a1 813 * used as SAI1 Block A clock.
bogdanm 89:552587b429a1 814 */
bogdanm 89:552587b429a1 815 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
bogdanm 89:552587b429a1 816
bogdanm 89:552587b429a1 817 /** @brief Macro to configure SAI1BlockB clock source selection.
bogdanm 89:552587b429a1 818 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
bogdanm 89:552587b429a1 819 * @note This function must be called before enabling PLLSAI, PLLI2S and
bogdanm 89:552587b429a1 820 * the SAI clock.
bogdanm 89:552587b429a1 821 * @param __SOURCE__: specifies the SAI Block B clock source.
bogdanm 89:552587b429a1 822 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 823 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
bogdanm 89:552587b429a1 824 * as SAI1 Block B clock.
bogdanm 89:552587b429a1 825 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
bogdanm 89:552587b429a1 826 * as SAI1 Block B clock.
bogdanm 89:552587b429a1 827 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
bogdanm 89:552587b429a1 828 * used as SAI1 Block B clock.
bogdanm 89:552587b429a1 829 */
bogdanm 89:552587b429a1 830 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
bogdanm 89:552587b429a1 831
bogdanm 89:552587b429a1 832 /** @brief Enable PLLSAI_RDY interrupt.
bogdanm 89:552587b429a1 833 */
bogdanm 89:552587b429a1 834 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
bogdanm 89:552587b429a1 835
bogdanm 89:552587b429a1 836 /** @brief Disable PLLSAI_RDY interrupt.
bogdanm 89:552587b429a1 837 */
bogdanm 89:552587b429a1 838 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
bogdanm 89:552587b429a1 839
bogdanm 89:552587b429a1 840 /** @brief Clear the PLLSAI RDY interrupt pending bits.
bogdanm 89:552587b429a1 841 */
bogdanm 89:552587b429a1 842 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
bogdanm 89:552587b429a1 843
bogdanm 89:552587b429a1 844 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
bogdanm 89:552587b429a1 845 * @retval The new state (TRUE or FALSE).
bogdanm 89:552587b429a1 846 */
bogdanm 89:552587b429a1 847 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
bogdanm 89:552587b429a1 848
bogdanm 89:552587b429a1 849 /** @brief Check PLLSAI RDY flag is set or not.
bogdanm 89:552587b429a1 850 * @retval The new state (TRUE or FALSE).
bogdanm 89:552587b429a1 851 */
bogdanm 89:552587b429a1 852 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
bogdanm 89:552587b429a1 853
bogdanm 89:552587b429a1 854 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 855
bogdanm 89:552587b429a1 856 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 857 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm 89:552587b429a1 858 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm 89:552587b429a1 859
bogdanm 89:552587b429a1 860 /**
bogdanm 89:552587b429a1 861 * @}
bogdanm 89:552587b429a1 862 */
bogdanm 89:552587b429a1 863
bogdanm 89:552587b429a1 864 /**
bogdanm 89:552587b429a1 865 * @}
bogdanm 89:552587b429a1 866 */
bogdanm 89:552587b429a1 867
bogdanm 89:552587b429a1 868 #ifdef __cplusplus
bogdanm 89:552587b429a1 869 }
bogdanm 89:552587b429a1 870 #endif
bogdanm 89:552587b429a1 871
bogdanm 89:552587b429a1 872 #endif /* __STM32F4xx_HAL_RCC_EX_H */
bogdanm 89:552587b429a1 873
bogdanm 89:552587b429a1 874 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/