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TARGET_KL05Z/core_caFunc.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Child:
95:7e07b6fb45cf
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file core_caFunc.h
bogdanm 92:4fc01daae5a5 3 * @brief CMSIS Cortex-A Core Function Access Header File
bogdanm 92:4fc01daae5a5 4 * @version V3.10
bogdanm 92:4fc01daae5a5 5 * @date 9 May 2013
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
bogdanm 92:4fc01daae5a5 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #ifndef __CORE_CAFUNC_H__
bogdanm 92:4fc01daae5a5 39 #define __CORE_CAFUNC_H__
bogdanm 92:4fc01daae5a5 40
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 /* ########################### Core Function Access ########################### */
bogdanm 92:4fc01daae5a5 43 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 92:4fc01daae5a5 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
bogdanm 92:4fc01daae5a5 45 @{
bogdanm 92:4fc01daae5a5 46 */
bogdanm 92:4fc01daae5a5 47
bogdanm 92:4fc01daae5a5 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 92:4fc01daae5a5 49 /* ARM armcc specific functions */
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 #if (__ARMCC_VERSION < 400677)
bogdanm 92:4fc01daae5a5 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
bogdanm 92:4fc01daae5a5 53 #endif
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 #define MODE_USR 0x10
bogdanm 92:4fc01daae5a5 56 #define MODE_FIQ 0x11
bogdanm 92:4fc01daae5a5 57 #define MODE_IRQ 0x12
bogdanm 92:4fc01daae5a5 58 #define MODE_SVC 0x13
bogdanm 92:4fc01daae5a5 59 #define MODE_MON 0x16
bogdanm 92:4fc01daae5a5 60 #define MODE_ABT 0x17
bogdanm 92:4fc01daae5a5 61 #define MODE_HYP 0x1A
bogdanm 92:4fc01daae5a5 62 #define MODE_UND 0x1B
bogdanm 92:4fc01daae5a5 63 #define MODE_SYS 0x1F
bogdanm 92:4fc01daae5a5 64
bogdanm 92:4fc01daae5a5 65 /** \brief Get APSR Register
bogdanm 92:4fc01daae5a5 66
bogdanm 92:4fc01daae5a5 67 This function returns the content of the APSR Register.
bogdanm 92:4fc01daae5a5 68
bogdanm 92:4fc01daae5a5 69 \return APSR Register value
bogdanm 92:4fc01daae5a5 70 */
bogdanm 92:4fc01daae5a5 71 __STATIC_INLINE uint32_t __get_APSR(void)
bogdanm 92:4fc01daae5a5 72 {
bogdanm 92:4fc01daae5a5 73 register uint32_t __regAPSR __ASM("apsr");
bogdanm 92:4fc01daae5a5 74 return(__regAPSR);
bogdanm 92:4fc01daae5a5 75 }
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 /** \brief Get CPSR Register
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 This function returns the content of the CPSR Register.
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 \return CPSR Register value
bogdanm 92:4fc01daae5a5 83 */
bogdanm 92:4fc01daae5a5 84 __STATIC_INLINE uint32_t __get_CPSR(void)
bogdanm 92:4fc01daae5a5 85 {
bogdanm 92:4fc01daae5a5 86 register uint32_t __regCPSR __ASM("cpsr");
bogdanm 92:4fc01daae5a5 87 return(__regCPSR);
bogdanm 92:4fc01daae5a5 88 }
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 /** \brief Set Stack Pointer
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92 This function assigns the given value to the current stack pointer.
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 \param [in] topOfStack Stack Pointer value to set
bogdanm 92:4fc01daae5a5 95 */
bogdanm 92:4fc01daae5a5 96 register uint32_t __regSP __ASM("sp");
bogdanm 92:4fc01daae5a5 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
bogdanm 92:4fc01daae5a5 98 {
bogdanm 92:4fc01daae5a5 99 __regSP = topOfStack;
bogdanm 92:4fc01daae5a5 100 }
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 /** \brief Get link register
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 This function returns the value of the link register
bogdanm 92:4fc01daae5a5 106
bogdanm 92:4fc01daae5a5 107 \return Value of link register
bogdanm 92:4fc01daae5a5 108 */
bogdanm 92:4fc01daae5a5 109 register uint32_t __reglr __ASM("lr");
bogdanm 92:4fc01daae5a5 110 __STATIC_INLINE uint32_t __get_LR(void)
bogdanm 92:4fc01daae5a5 111 {
bogdanm 92:4fc01daae5a5 112 return(__reglr);
bogdanm 92:4fc01daae5a5 113 }
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115 /** \brief Set link register
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 This function sets the value of the link register
bogdanm 92:4fc01daae5a5 118
bogdanm 92:4fc01daae5a5 119 \param [in] lr LR value to set
bogdanm 92:4fc01daae5a5 120 */
bogdanm 92:4fc01daae5a5 121 __STATIC_INLINE void __set_LR(uint32_t lr)
bogdanm 92:4fc01daae5a5 122 {
bogdanm 92:4fc01daae5a5 123 __reglr = lr;
bogdanm 92:4fc01daae5a5 124 }
bogdanm 92:4fc01daae5a5 125
bogdanm 92:4fc01daae5a5 126 /** \brief Set Process Stack Pointer
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
bogdanm 92:4fc01daae5a5 131 */
bogdanm 92:4fc01daae5a5 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
bogdanm 92:4fc01daae5a5 133 {
bogdanm 92:4fc01daae5a5 134 ARM
bogdanm 92:4fc01daae5a5 135 PRESERVE8
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
bogdanm 92:4fc01daae5a5 138 MRS R1, CPSR
bogdanm 92:4fc01daae5a5 139 CPS #MODE_SYS ;no effect in USR mode
bogdanm 92:4fc01daae5a5 140 MOV SP, R0
bogdanm 92:4fc01daae5a5 141 MSR CPSR_c, R1 ;no effect in USR mode
bogdanm 92:4fc01daae5a5 142 ISB
bogdanm 92:4fc01daae5a5 143 BX LR
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 }
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 /** \brief Set User Mode
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 This function changes the processor state to User Mode
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
bogdanm 92:4fc01daae5a5 152 */
bogdanm 92:4fc01daae5a5 153 __STATIC_ASM void __set_CPS_USR(void)
bogdanm 92:4fc01daae5a5 154 {
bogdanm 92:4fc01daae5a5 155 ARM
bogdanm 92:4fc01daae5a5 156
bogdanm 92:4fc01daae5a5 157 CPS #MODE_USR
bogdanm 92:4fc01daae5a5 158 BX LR
bogdanm 92:4fc01daae5a5 159 }
bogdanm 92:4fc01daae5a5 160
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 /** \brief Enable FIQ
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
bogdanm 92:4fc01daae5a5 165 Can only be executed in Privileged modes.
bogdanm 92:4fc01daae5a5 166 */
bogdanm 92:4fc01daae5a5 167 #define __enable_fault_irq __enable_fiq
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169
bogdanm 92:4fc01daae5a5 170 /** \brief Disable FIQ
bogdanm 92:4fc01daae5a5 171
bogdanm 92:4fc01daae5a5 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
bogdanm 92:4fc01daae5a5 173 Can only be executed in Privileged modes.
bogdanm 92:4fc01daae5a5 174 */
bogdanm 92:4fc01daae5a5 175 #define __disable_fault_irq __disable_fiq
bogdanm 92:4fc01daae5a5 176
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 /** \brief Get FPSCR
bogdanm 92:4fc01daae5a5 179
bogdanm 92:4fc01daae5a5 180 This function returns the current value of the Floating Point Status/Control register.
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 \return Floating Point Status/Control register value
bogdanm 92:4fc01daae5a5 183 */
bogdanm 92:4fc01daae5a5 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
bogdanm 92:4fc01daae5a5 185 {
bogdanm 92:4fc01daae5a5 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 92:4fc01daae5a5 187 register uint32_t __regfpscr __ASM("fpscr");
bogdanm 92:4fc01daae5a5 188 return(__regfpscr);
bogdanm 92:4fc01daae5a5 189 #else
bogdanm 92:4fc01daae5a5 190 return(0);
bogdanm 92:4fc01daae5a5 191 #endif
bogdanm 92:4fc01daae5a5 192 }
bogdanm 92:4fc01daae5a5 193
bogdanm 92:4fc01daae5a5 194
bogdanm 92:4fc01daae5a5 195 /** \brief Set FPSCR
bogdanm 92:4fc01daae5a5 196
bogdanm 92:4fc01daae5a5 197 This function assigns the given value to the Floating Point Status/Control register.
bogdanm 92:4fc01daae5a5 198
bogdanm 92:4fc01daae5a5 199 \param [in] fpscr Floating Point Status/Control value to set
bogdanm 92:4fc01daae5a5 200 */
bogdanm 92:4fc01daae5a5 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
bogdanm 92:4fc01daae5a5 202 {
bogdanm 92:4fc01daae5a5 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 92:4fc01daae5a5 204 register uint32_t __regfpscr __ASM("fpscr");
bogdanm 92:4fc01daae5a5 205 __regfpscr = (fpscr);
bogdanm 92:4fc01daae5a5 206 #endif
bogdanm 92:4fc01daae5a5 207 }
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 /** \brief Get FPEXC
bogdanm 92:4fc01daae5a5 210
bogdanm 92:4fc01daae5a5 211 This function returns the current value of the Floating Point Exception Control register.
bogdanm 92:4fc01daae5a5 212
bogdanm 92:4fc01daae5a5 213 \return Floating Point Exception Control register value
bogdanm 92:4fc01daae5a5 214 */
bogdanm 92:4fc01daae5a5 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
bogdanm 92:4fc01daae5a5 216 {
bogdanm 92:4fc01daae5a5 217 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 218 register uint32_t __regfpexc __ASM("fpexc");
bogdanm 92:4fc01daae5a5 219 return(__regfpexc);
bogdanm 92:4fc01daae5a5 220 #else
bogdanm 92:4fc01daae5a5 221 return(0);
bogdanm 92:4fc01daae5a5 222 #endif
bogdanm 92:4fc01daae5a5 223 }
bogdanm 92:4fc01daae5a5 224
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226 /** \brief Set FPEXC
bogdanm 92:4fc01daae5a5 227
bogdanm 92:4fc01daae5a5 228 This function assigns the given value to the Floating Point Exception Control register.
bogdanm 92:4fc01daae5a5 229
bogdanm 92:4fc01daae5a5 230 \param [in] fpscr Floating Point Exception Control value to set
bogdanm 92:4fc01daae5a5 231 */
bogdanm 92:4fc01daae5a5 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
bogdanm 92:4fc01daae5a5 233 {
bogdanm 92:4fc01daae5a5 234 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 235 register uint32_t __regfpexc __ASM("fpexc");
bogdanm 92:4fc01daae5a5 236 __regfpexc = (fpexc);
bogdanm 92:4fc01daae5a5 237 #endif
bogdanm 92:4fc01daae5a5 238 }
bogdanm 92:4fc01daae5a5 239
bogdanm 92:4fc01daae5a5 240 /** \brief Get CPACR
bogdanm 92:4fc01daae5a5 241
bogdanm 92:4fc01daae5a5 242 This function returns the current value of the Coprocessor Access Control register.
bogdanm 92:4fc01daae5a5 243
bogdanm 92:4fc01daae5a5 244 \return Coprocessor Access Control register value
bogdanm 92:4fc01daae5a5 245 */
bogdanm 92:4fc01daae5a5 246 __STATIC_INLINE uint32_t __get_CPACR(void)
bogdanm 92:4fc01daae5a5 247 {
bogdanm 92:4fc01daae5a5 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
bogdanm 92:4fc01daae5a5 249 return __regCPACR;
bogdanm 92:4fc01daae5a5 250 }
bogdanm 92:4fc01daae5a5 251
bogdanm 92:4fc01daae5a5 252 /** \brief Set CPACR
bogdanm 92:4fc01daae5a5 253
bogdanm 92:4fc01daae5a5 254 This function assigns the given value to the Coprocessor Access Control register.
bogdanm 92:4fc01daae5a5 255
bogdanm 92:4fc01daae5a5 256 \param [in] cpacr Coporcessor Acccess Control value to set
bogdanm 92:4fc01daae5a5 257 */
bogdanm 92:4fc01daae5a5 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
bogdanm 92:4fc01daae5a5 259 {
bogdanm 92:4fc01daae5a5 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
bogdanm 92:4fc01daae5a5 261 __regCPACR = cpacr;
bogdanm 92:4fc01daae5a5 262 __ISB();
bogdanm 92:4fc01daae5a5 263 }
bogdanm 92:4fc01daae5a5 264
bogdanm 92:4fc01daae5a5 265 /** \brief Get CBAR
bogdanm 92:4fc01daae5a5 266
bogdanm 92:4fc01daae5a5 267 This function returns the value of the Configuration Base Address register.
bogdanm 92:4fc01daae5a5 268
bogdanm 92:4fc01daae5a5 269 \return Configuration Base Address register value
bogdanm 92:4fc01daae5a5 270 */
bogdanm 92:4fc01daae5a5 271 __STATIC_INLINE uint32_t __get_CBAR() {
bogdanm 92:4fc01daae5a5 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
bogdanm 92:4fc01daae5a5 273 return(__regCBAR);
bogdanm 92:4fc01daae5a5 274 }
bogdanm 92:4fc01daae5a5 275
bogdanm 92:4fc01daae5a5 276 /** \brief Get TTBR0
bogdanm 92:4fc01daae5a5 277
bogdanm 92:4fc01daae5a5 278 This function returns the value of the Configuration Base Address register.
bogdanm 92:4fc01daae5a5 279
bogdanm 92:4fc01daae5a5 280 \return Translation Table Base Register 0 value
bogdanm 92:4fc01daae5a5 281 */
bogdanm 92:4fc01daae5a5 282 __STATIC_INLINE uint32_t __get_TTBR0() {
bogdanm 92:4fc01daae5a5 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
bogdanm 92:4fc01daae5a5 284 return(__regTTBR0);
bogdanm 92:4fc01daae5a5 285 }
bogdanm 92:4fc01daae5a5 286
bogdanm 92:4fc01daae5a5 287 /** \brief Set TTBR0
bogdanm 92:4fc01daae5a5 288
bogdanm 92:4fc01daae5a5 289 This function assigns the given value to the Coprocessor Access Control register.
bogdanm 92:4fc01daae5a5 290
bogdanm 92:4fc01daae5a5 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
bogdanm 92:4fc01daae5a5 292 */
bogdanm 92:4fc01daae5a5 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
bogdanm 92:4fc01daae5a5 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
bogdanm 92:4fc01daae5a5 295 __regTTBR0 = ttbr0;
bogdanm 92:4fc01daae5a5 296 __ISB();
bogdanm 92:4fc01daae5a5 297 }
bogdanm 92:4fc01daae5a5 298
bogdanm 92:4fc01daae5a5 299 /** \brief Get DACR
bogdanm 92:4fc01daae5a5 300
bogdanm 92:4fc01daae5a5 301 This function returns the value of the Domain Access Control Register.
bogdanm 92:4fc01daae5a5 302
bogdanm 92:4fc01daae5a5 303 \return Domain Access Control Register value
bogdanm 92:4fc01daae5a5 304 */
bogdanm 92:4fc01daae5a5 305 __STATIC_INLINE uint32_t __get_DACR() {
bogdanm 92:4fc01daae5a5 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
bogdanm 92:4fc01daae5a5 307 return(__regDACR);
bogdanm 92:4fc01daae5a5 308 }
bogdanm 92:4fc01daae5a5 309
bogdanm 92:4fc01daae5a5 310 /** \brief Set DACR
bogdanm 92:4fc01daae5a5 311
bogdanm 92:4fc01daae5a5 312 This function assigns the given value to the Coprocessor Access Control register.
bogdanm 92:4fc01daae5a5 313
bogdanm 92:4fc01daae5a5 314 \param [in] dacr Domain Access Control Register value to set
bogdanm 92:4fc01daae5a5 315 */
bogdanm 92:4fc01daae5a5 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
bogdanm 92:4fc01daae5a5 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
bogdanm 92:4fc01daae5a5 318 __regDACR = dacr;
bogdanm 92:4fc01daae5a5 319 __ISB();
bogdanm 92:4fc01daae5a5 320 }
bogdanm 92:4fc01daae5a5 321
bogdanm 92:4fc01daae5a5 322 /******************************** Cache and BTAC enable ****************************************************/
bogdanm 92:4fc01daae5a5 323
bogdanm 92:4fc01daae5a5 324 /** \brief Set SCTLR
bogdanm 92:4fc01daae5a5 325
bogdanm 92:4fc01daae5a5 326 This function assigns the given value to the System Control Register.
bogdanm 92:4fc01daae5a5 327
bogdanm 92:4fc01daae5a5 328 \param [in] sctlr System Control Register, value to set
bogdanm 92:4fc01daae5a5 329 */
bogdanm 92:4fc01daae5a5 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
bogdanm 92:4fc01daae5a5 331 {
bogdanm 92:4fc01daae5a5 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
bogdanm 92:4fc01daae5a5 333 __regSCTLR = sctlr;
bogdanm 92:4fc01daae5a5 334 }
bogdanm 92:4fc01daae5a5 335
bogdanm 92:4fc01daae5a5 336 /** \brief Get SCTLR
bogdanm 92:4fc01daae5a5 337
bogdanm 92:4fc01daae5a5 338 This function returns the value of the System Control Register.
bogdanm 92:4fc01daae5a5 339
bogdanm 92:4fc01daae5a5 340 \return System Control Register value
bogdanm 92:4fc01daae5a5 341 */
bogdanm 92:4fc01daae5a5 342 __STATIC_INLINE uint32_t __get_SCTLR() {
bogdanm 92:4fc01daae5a5 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
bogdanm 92:4fc01daae5a5 344 return(__regSCTLR);
bogdanm 92:4fc01daae5a5 345 }
bogdanm 92:4fc01daae5a5 346
bogdanm 92:4fc01daae5a5 347 /** \brief Enable Caches
bogdanm 92:4fc01daae5a5 348
bogdanm 92:4fc01daae5a5 349 Enable Caches
bogdanm 92:4fc01daae5a5 350 */
bogdanm 92:4fc01daae5a5 351 __STATIC_INLINE void __enable_caches(void) {
bogdanm 92:4fc01daae5a5 352 // Set I bit 12 to enable I Cache
bogdanm 92:4fc01daae5a5 353 // Set C bit 2 to enable D Cache
bogdanm 92:4fc01daae5a5 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
bogdanm 92:4fc01daae5a5 355 }
bogdanm 92:4fc01daae5a5 356
bogdanm 92:4fc01daae5a5 357 /** \brief Disable Caches
bogdanm 92:4fc01daae5a5 358
bogdanm 92:4fc01daae5a5 359 Disable Caches
bogdanm 92:4fc01daae5a5 360 */
bogdanm 92:4fc01daae5a5 361 __STATIC_INLINE void __disable_caches(void) {
bogdanm 92:4fc01daae5a5 362 // Clear I bit 12 to disable I Cache
bogdanm 92:4fc01daae5a5 363 // Clear C bit 2 to disable D Cache
bogdanm 92:4fc01daae5a5 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
bogdanm 92:4fc01daae5a5 365 __ISB();
bogdanm 92:4fc01daae5a5 366 }
bogdanm 92:4fc01daae5a5 367
bogdanm 92:4fc01daae5a5 368 /** \brief Enable BTAC
bogdanm 92:4fc01daae5a5 369
bogdanm 92:4fc01daae5a5 370 Enable BTAC
bogdanm 92:4fc01daae5a5 371 */
bogdanm 92:4fc01daae5a5 372 __STATIC_INLINE void __enable_btac(void) {
bogdanm 92:4fc01daae5a5 373 // Set Z bit 11 to enable branch prediction
bogdanm 92:4fc01daae5a5 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
bogdanm 92:4fc01daae5a5 375 __ISB();
bogdanm 92:4fc01daae5a5 376 }
bogdanm 92:4fc01daae5a5 377
bogdanm 92:4fc01daae5a5 378 /** \brief Disable BTAC
bogdanm 92:4fc01daae5a5 379
bogdanm 92:4fc01daae5a5 380 Disable BTAC
bogdanm 92:4fc01daae5a5 381 */
bogdanm 92:4fc01daae5a5 382 __STATIC_INLINE void __disable_btac(void) {
bogdanm 92:4fc01daae5a5 383 // Clear Z bit 11 to disable branch prediction
bogdanm 92:4fc01daae5a5 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
bogdanm 92:4fc01daae5a5 385 }
bogdanm 92:4fc01daae5a5 386
bogdanm 92:4fc01daae5a5 387
bogdanm 92:4fc01daae5a5 388 /** \brief Enable MMU
bogdanm 92:4fc01daae5a5 389
bogdanm 92:4fc01daae5a5 390 Enable MMU
bogdanm 92:4fc01daae5a5 391 */
bogdanm 92:4fc01daae5a5 392 __STATIC_INLINE void __enable_mmu(void) {
bogdanm 92:4fc01daae5a5 393 // Set M bit 0 to enable the MMU
bogdanm 92:4fc01daae5a5 394 // Set AFE bit to enable simplified access permissions model
bogdanm 92:4fc01daae5a5 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
bogdanm 92:4fc01daae5a5 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
bogdanm 92:4fc01daae5a5 397 __ISB();
bogdanm 92:4fc01daae5a5 398 }
bogdanm 92:4fc01daae5a5 399
bogdanm 92:4fc01daae5a5 400 /** \brief Enable MMU
bogdanm 92:4fc01daae5a5 401
bogdanm 92:4fc01daae5a5 402 Enable MMU
bogdanm 92:4fc01daae5a5 403 */
bogdanm 92:4fc01daae5a5 404 __STATIC_INLINE void __disable_mmu(void) {
bogdanm 92:4fc01daae5a5 405 // Clear M bit 0 to disable the MMU
bogdanm 92:4fc01daae5a5 406 __set_SCTLR( __get_SCTLR() & ~1);
bogdanm 92:4fc01daae5a5 407 __ISB();
bogdanm 92:4fc01daae5a5 408 }
bogdanm 92:4fc01daae5a5 409
bogdanm 92:4fc01daae5a5 410 /******************************** TLB maintenance operations ************************************************/
bogdanm 92:4fc01daae5a5 411 /** \brief Invalidate the whole tlb
bogdanm 92:4fc01daae5a5 412
bogdanm 92:4fc01daae5a5 413 TLBIALL. Invalidate the whole tlb
bogdanm 92:4fc01daae5a5 414 */
bogdanm 92:4fc01daae5a5 415
bogdanm 92:4fc01daae5a5 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
bogdanm 92:4fc01daae5a5 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
bogdanm 92:4fc01daae5a5 418 __TLBIALL = 0;
bogdanm 92:4fc01daae5a5 419 __DSB();
bogdanm 92:4fc01daae5a5 420 __ISB();
bogdanm 92:4fc01daae5a5 421 }
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 /******************************** BTB maintenance operations ************************************************/
bogdanm 92:4fc01daae5a5 424 /** \brief Invalidate entire branch predictor array
bogdanm 92:4fc01daae5a5 425
bogdanm 92:4fc01daae5a5 426 BPIALL. Branch Predictor Invalidate All.
bogdanm 92:4fc01daae5a5 427 */
bogdanm 92:4fc01daae5a5 428
bogdanm 92:4fc01daae5a5 429 __STATIC_INLINE void __v7_inv_btac(void) {
bogdanm 92:4fc01daae5a5 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
bogdanm 92:4fc01daae5a5 431 __BPIALL = 0;
bogdanm 92:4fc01daae5a5 432 __DSB(); //ensure completion of the invalidation
bogdanm 92:4fc01daae5a5 433 __ISB(); //ensure instruction fetch path sees new state
bogdanm 92:4fc01daae5a5 434 }
bogdanm 92:4fc01daae5a5 435
bogdanm 92:4fc01daae5a5 436
bogdanm 92:4fc01daae5a5 437 /******************************** L1 cache operations ******************************************************/
bogdanm 92:4fc01daae5a5 438
bogdanm 92:4fc01daae5a5 439 /** \brief Invalidate the whole I$
bogdanm 92:4fc01daae5a5 440
bogdanm 92:4fc01daae5a5 441 ICIALLU. Instruction Cache Invalidate All to PoU
bogdanm 92:4fc01daae5a5 442 */
bogdanm 92:4fc01daae5a5 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
bogdanm 92:4fc01daae5a5 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
bogdanm 92:4fc01daae5a5 445 __ICIALLU = 0;
bogdanm 92:4fc01daae5a5 446 __DSB(); //ensure completion of the invalidation
bogdanm 92:4fc01daae5a5 447 __ISB(); //ensure instruction fetch path sees new I cache state
bogdanm 92:4fc01daae5a5 448 }
bogdanm 92:4fc01daae5a5 449
bogdanm 92:4fc01daae5a5 450 /** \brief Clean D$ by MVA
bogdanm 92:4fc01daae5a5 451
bogdanm 92:4fc01daae5a5 452 DCCMVAC. Data cache clean by MVA to PoC
bogdanm 92:4fc01daae5a5 453 */
bogdanm 92:4fc01daae5a5 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
bogdanm 92:4fc01daae5a5 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
bogdanm 92:4fc01daae5a5 456 __DCCMVAC = (uint32_t)va;
bogdanm 92:4fc01daae5a5 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
bogdanm 92:4fc01daae5a5 458 }
bogdanm 92:4fc01daae5a5 459
bogdanm 92:4fc01daae5a5 460 /** \brief Invalidate D$ by MVA
bogdanm 92:4fc01daae5a5 461
bogdanm 92:4fc01daae5a5 462 DCIMVAC. Data cache invalidate by MVA to PoC
bogdanm 92:4fc01daae5a5 463 */
bogdanm 92:4fc01daae5a5 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
bogdanm 92:4fc01daae5a5 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
bogdanm 92:4fc01daae5a5 466 __DCIMVAC = (uint32_t)va;
bogdanm 92:4fc01daae5a5 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
bogdanm 92:4fc01daae5a5 468 }
bogdanm 92:4fc01daae5a5 469
bogdanm 92:4fc01daae5a5 470 /** \brief Clean and Invalidate D$ by MVA
bogdanm 92:4fc01daae5a5 471
bogdanm 92:4fc01daae5a5 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
bogdanm 92:4fc01daae5a5 473 */
bogdanm 92:4fc01daae5a5 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
bogdanm 92:4fc01daae5a5 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
bogdanm 92:4fc01daae5a5 476 __DCCIMVAC = (uint32_t)va;
bogdanm 92:4fc01daae5a5 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
bogdanm 92:4fc01daae5a5 478 }
bogdanm 92:4fc01daae5a5 479
bogdanm 92:4fc01daae5a5 480 /** \brief
bogdanm 92:4fc01daae5a5 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
bogdanm 92:4fc01daae5a5 482 */
bogdanm 92:4fc01daae5a5 483 #pragma push
bogdanm 92:4fc01daae5a5 484 #pragma arm
bogdanm 92:4fc01daae5a5 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
bogdanm 92:4fc01daae5a5 486 ARM
bogdanm 92:4fc01daae5a5 487
bogdanm 92:4fc01daae5a5 488 PUSH {R4-R11}
bogdanm 92:4fc01daae5a5 489
bogdanm 92:4fc01daae5a5 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
bogdanm 92:4fc01daae5a5 491 ANDS R3, R6, #0x07000000 // Extract coherency level
bogdanm 92:4fc01daae5a5 492 MOV R3, R3, LSR #23 // Total cache levels << 1
bogdanm 92:4fc01daae5a5 493 BEQ Finished // If 0, no need to clean
bogdanm 92:4fc01daae5a5 494
bogdanm 92:4fc01daae5a5 495 MOV R10, #0 // R10 holds current cache level << 1
bogdanm 92:4fc01daae5a5 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
bogdanm 92:4fc01daae5a5 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
bogdanm 92:4fc01daae5a5 498 AND R1, R1, #7 // Isolate those lower 3 bits
bogdanm 92:4fc01daae5a5 499 CMP R1, #2
bogdanm 92:4fc01daae5a5 500 BLT Skip // No cache or only instruction cache at this level
bogdanm 92:4fc01daae5a5 501
bogdanm 92:4fc01daae5a5 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
bogdanm 92:4fc01daae5a5 503 ISB // ISB to sync the change to the CacheSizeID reg
bogdanm 92:4fc01daae5a5 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
bogdanm 92:4fc01daae5a5 505 AND R2, R1, #7 // Extract the line length field
bogdanm 92:4fc01daae5a5 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
bogdanm 92:4fc01daae5a5 507 LDR R4, =0x3FF
bogdanm 92:4fc01daae5a5 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
bogdanm 92:4fc01daae5a5 509 CLZ R5, R4 // R5 is the bit position of the way size increment
bogdanm 92:4fc01daae5a5 510 LDR R7, =0x7FFF
bogdanm 92:4fc01daae5a5 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
bogdanm 92:4fc01daae5a5 512
bogdanm 92:4fc01daae5a5 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
bogdanm 92:4fc01daae5a5 514
bogdanm 92:4fc01daae5a5 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
bogdanm 92:4fc01daae5a5 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
bogdanm 92:4fc01daae5a5 517 CMP R0, #0
bogdanm 92:4fc01daae5a5 518 BNE Dccsw
bogdanm 92:4fc01daae5a5 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
bogdanm 92:4fc01daae5a5 520 B cont
bogdanm 92:4fc01daae5a5 521 Dccsw CMP R0, #1
bogdanm 92:4fc01daae5a5 522 BNE Dccisw
bogdanm 92:4fc01daae5a5 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
bogdanm 92:4fc01daae5a5 524 B cont
bogdanm 92:4fc01daae5a5 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
bogdanm 92:4fc01daae5a5 526 cont SUBS R9, R9, #1 // Decrement the Way number
bogdanm 92:4fc01daae5a5 527 BGE Loop3
bogdanm 92:4fc01daae5a5 528 SUBS R7, R7, #1 // Decrement the Set number
bogdanm 92:4fc01daae5a5 529 BGE Loop2
bogdanm 92:4fc01daae5a5 530 Skip ADD R10, R10, #2 // increment the cache number
bogdanm 92:4fc01daae5a5 531 CMP R3, R10
bogdanm 92:4fc01daae5a5 532 BGT Loop1
bogdanm 92:4fc01daae5a5 533
bogdanm 92:4fc01daae5a5 534 Finished
bogdanm 92:4fc01daae5a5 535 DSB
bogdanm 92:4fc01daae5a5 536 POP {R4-R11}
bogdanm 92:4fc01daae5a5 537 BX lr
bogdanm 92:4fc01daae5a5 538
bogdanm 92:4fc01daae5a5 539 }
bogdanm 92:4fc01daae5a5 540 #pragma pop
bogdanm 92:4fc01daae5a5 541
bogdanm 92:4fc01daae5a5 542 /** \brief __v7_all_cache - helper function
bogdanm 92:4fc01daae5a5 543
bogdanm 92:4fc01daae5a5 544 */
bogdanm 92:4fc01daae5a5 545
bogdanm 92:4fc01daae5a5 546 /** \brief Invalidate the whole D$
bogdanm 92:4fc01daae5a5 547
bogdanm 92:4fc01daae5a5 548 DCISW. Invalidate by Set/Way
bogdanm 92:4fc01daae5a5 549 */
bogdanm 92:4fc01daae5a5 550
bogdanm 92:4fc01daae5a5 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
bogdanm 92:4fc01daae5a5 552 __v7_all_cache(0);
bogdanm 92:4fc01daae5a5 553 }
bogdanm 92:4fc01daae5a5 554
bogdanm 92:4fc01daae5a5 555 /** \brief Clean the whole D$
bogdanm 92:4fc01daae5a5 556
bogdanm 92:4fc01daae5a5 557 DCCSW. Clean by Set/Way
bogdanm 92:4fc01daae5a5 558 */
bogdanm 92:4fc01daae5a5 559
bogdanm 92:4fc01daae5a5 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
bogdanm 92:4fc01daae5a5 561 __v7_all_cache(1);
bogdanm 92:4fc01daae5a5 562 }
bogdanm 92:4fc01daae5a5 563
bogdanm 92:4fc01daae5a5 564 /** \brief Clean and invalidate the whole D$
bogdanm 92:4fc01daae5a5 565
bogdanm 92:4fc01daae5a5 566 DCCISW. Clean and Invalidate by Set/Way
bogdanm 92:4fc01daae5a5 567 */
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
bogdanm 92:4fc01daae5a5 570 __v7_all_cache(2);
bogdanm 92:4fc01daae5a5 571 }
bogdanm 92:4fc01daae5a5 572
bogdanm 92:4fc01daae5a5 573 #include "core_ca_mmu.h"
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
bogdanm 92:4fc01daae5a5 576
bogdanm 92:4fc01daae5a5 577 #error IAR Compiler support not implemented for Cortex-A
bogdanm 92:4fc01daae5a5 578
bogdanm 92:4fc01daae5a5 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
bogdanm 92:4fc01daae5a5 580
bogdanm 92:4fc01daae5a5 581 //#error GNU Compiler support not implemented for Cortex-A
bogdanm 92:4fc01daae5a5 582
bogdanm 92:4fc01daae5a5 583 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
bogdanm 92:4fc01daae5a5 584
bogdanm 92:4fc01daae5a5 585 #error TASKING Compiler support not implemented for Cortex-A
bogdanm 92:4fc01daae5a5 586
bogdanm 92:4fc01daae5a5 587 #endif
bogdanm 92:4fc01daae5a5 588
bogdanm 92:4fc01daae5a5 589 /*@} end of CMSIS_Core_RegAccFunctions */
bogdanm 92:4fc01daae5a5 590
bogdanm 92:4fc01daae5a5 591
bogdanm 92:4fc01daae5a5 592 #endif /* __CORE_CAFUNC_H__ */