takashi kadono / Mbed OS Nucleo_446

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Dependencies:   ssd1331

mbed-os/cmsis/TARGET_CORTEX_A/cmsis_cp15.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /**************************************************************************//**
kadonotakashi 0:8fdf9a60065b 2 * @file cmsis_cp15.h
kadonotakashi 0:8fdf9a60065b 3 * @brief CMSIS compiler specific macros, functions, instructions
kadonotakashi 0:8fdf9a60065b 4 * @version V1.0.1
kadonotakashi 0:8fdf9a60065b 5 * @date 07. Sep 2017
kadonotakashi 0:8fdf9a60065b 6 ******************************************************************************/
kadonotakashi 0:8fdf9a60065b 7 /*
kadonotakashi 0:8fdf9a60065b 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * SPDX-License-Identifier: Apache-2.0
kadonotakashi 0:8fdf9a60065b 11 *
kadonotakashi 0:8fdf9a60065b 12 * Licensed under the Apache License, Version 2.0 (the License); you may
kadonotakashi 0:8fdf9a60065b 13 * not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 14 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 15 *
kadonotakashi 0:8fdf9a60065b 16 * www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 17 *
kadonotakashi 0:8fdf9a60065b 18 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
kadonotakashi 0:8fdf9a60065b 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 21 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 22 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 23 */
kadonotakashi 0:8fdf9a60065b 24
kadonotakashi 0:8fdf9a60065b 25 #if defined ( __ICCARM__ )
kadonotakashi 0:8fdf9a60065b 26 #pragma system_include /* treat file as system include file for MISRA check */
kadonotakashi 0:8fdf9a60065b 27 #elif defined (__clang__)
kadonotakashi 0:8fdf9a60065b 28 #pragma clang system_header /* treat file as system include file */
kadonotakashi 0:8fdf9a60065b 29 #endif
kadonotakashi 0:8fdf9a60065b 30
kadonotakashi 0:8fdf9a60065b 31 #ifndef __CMSIS_CP15_H
kadonotakashi 0:8fdf9a60065b 32 #define __CMSIS_CP15_H
kadonotakashi 0:8fdf9a60065b 33
kadonotakashi 0:8fdf9a60065b 34 /** \brief Get ACTLR
kadonotakashi 0:8fdf9a60065b 35 \return Auxiliary Control register value
kadonotakashi 0:8fdf9a60065b 36 */
kadonotakashi 0:8fdf9a60065b 37 __STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
kadonotakashi 0:8fdf9a60065b 38 {
kadonotakashi 0:8fdf9a60065b 39 uint32_t result;
kadonotakashi 0:8fdf9a60065b 40 __get_CP(15, 0, result, 1, 0, 1);
kadonotakashi 0:8fdf9a60065b 41 return(result);
kadonotakashi 0:8fdf9a60065b 42 }
kadonotakashi 0:8fdf9a60065b 43
kadonotakashi 0:8fdf9a60065b 44 /** \brief Set ACTLR
kadonotakashi 0:8fdf9a60065b 45 \param [in] actlr Auxiliary Control value to set
kadonotakashi 0:8fdf9a60065b 46 */
kadonotakashi 0:8fdf9a60065b 47 __STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
kadonotakashi 0:8fdf9a60065b 48 {
kadonotakashi 0:8fdf9a60065b 49 __set_CP(15, 0, actlr, 1, 0, 1);
kadonotakashi 0:8fdf9a60065b 50 }
kadonotakashi 0:8fdf9a60065b 51
kadonotakashi 0:8fdf9a60065b 52 /** \brief Get CPACR
kadonotakashi 0:8fdf9a60065b 53 \return Coprocessor Access Control register value
kadonotakashi 0:8fdf9a60065b 54 */
kadonotakashi 0:8fdf9a60065b 55 __STATIC_FORCEINLINE uint32_t __get_CPACR(void)
kadonotakashi 0:8fdf9a60065b 56 {
kadonotakashi 0:8fdf9a60065b 57 uint32_t result;
kadonotakashi 0:8fdf9a60065b 58 __get_CP(15, 0, result, 1, 0, 2);
kadonotakashi 0:8fdf9a60065b 59 return result;
kadonotakashi 0:8fdf9a60065b 60 }
kadonotakashi 0:8fdf9a60065b 61
kadonotakashi 0:8fdf9a60065b 62 /** \brief Set CPACR
kadonotakashi 0:8fdf9a60065b 63 \param [in] cpacr Coprocessor Access Control value to set
kadonotakashi 0:8fdf9a60065b 64 */
kadonotakashi 0:8fdf9a60065b 65 __STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
kadonotakashi 0:8fdf9a60065b 66 {
kadonotakashi 0:8fdf9a60065b 67 __set_CP(15, 0, cpacr, 1, 0, 2);
kadonotakashi 0:8fdf9a60065b 68 }
kadonotakashi 0:8fdf9a60065b 69
kadonotakashi 0:8fdf9a60065b 70 /** \brief Get DFSR
kadonotakashi 0:8fdf9a60065b 71 \return Data Fault Status Register value
kadonotakashi 0:8fdf9a60065b 72 */
kadonotakashi 0:8fdf9a60065b 73 __STATIC_FORCEINLINE uint32_t __get_DFSR(void)
kadonotakashi 0:8fdf9a60065b 74 {
kadonotakashi 0:8fdf9a60065b 75 uint32_t result;
kadonotakashi 0:8fdf9a60065b 76 __get_CP(15, 0, result, 5, 0, 0);
kadonotakashi 0:8fdf9a60065b 77 return result;
kadonotakashi 0:8fdf9a60065b 78 }
kadonotakashi 0:8fdf9a60065b 79
kadonotakashi 0:8fdf9a60065b 80 /** \brief Set DFSR
kadonotakashi 0:8fdf9a60065b 81 \param [in] dfsr Data Fault Status value to set
kadonotakashi 0:8fdf9a60065b 82 */
kadonotakashi 0:8fdf9a60065b 83 __STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
kadonotakashi 0:8fdf9a60065b 84 {
kadonotakashi 0:8fdf9a60065b 85 __set_CP(15, 0, dfsr, 5, 0, 0);
kadonotakashi 0:8fdf9a60065b 86 }
kadonotakashi 0:8fdf9a60065b 87
kadonotakashi 0:8fdf9a60065b 88 /** \brief Get IFSR
kadonotakashi 0:8fdf9a60065b 89 \return Instruction Fault Status Register value
kadonotakashi 0:8fdf9a60065b 90 */
kadonotakashi 0:8fdf9a60065b 91 __STATIC_FORCEINLINE uint32_t __get_IFSR(void)
kadonotakashi 0:8fdf9a60065b 92 {
kadonotakashi 0:8fdf9a60065b 93 uint32_t result;
kadonotakashi 0:8fdf9a60065b 94 __get_CP(15, 0, result, 5, 0, 1);
kadonotakashi 0:8fdf9a60065b 95 return result;
kadonotakashi 0:8fdf9a60065b 96 }
kadonotakashi 0:8fdf9a60065b 97
kadonotakashi 0:8fdf9a60065b 98 /** \brief Set IFSR
kadonotakashi 0:8fdf9a60065b 99 \param [in] ifsr Instruction Fault Status value to set
kadonotakashi 0:8fdf9a60065b 100 */
kadonotakashi 0:8fdf9a60065b 101 __STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
kadonotakashi 0:8fdf9a60065b 102 {
kadonotakashi 0:8fdf9a60065b 103 __set_CP(15, 0, ifsr, 5, 0, 1);
kadonotakashi 0:8fdf9a60065b 104 }
kadonotakashi 0:8fdf9a60065b 105
kadonotakashi 0:8fdf9a60065b 106 /** \brief Get ISR
kadonotakashi 0:8fdf9a60065b 107 \return Interrupt Status Register value
kadonotakashi 0:8fdf9a60065b 108 */
kadonotakashi 0:8fdf9a60065b 109 __STATIC_FORCEINLINE uint32_t __get_ISR(void)
kadonotakashi 0:8fdf9a60065b 110 {
kadonotakashi 0:8fdf9a60065b 111 uint32_t result;
kadonotakashi 0:8fdf9a60065b 112 __get_CP(15, 0, result, 12, 1, 0);
kadonotakashi 0:8fdf9a60065b 113 return result;
kadonotakashi 0:8fdf9a60065b 114 }
kadonotakashi 0:8fdf9a60065b 115
kadonotakashi 0:8fdf9a60065b 116 /** \brief Get CBAR
kadonotakashi 0:8fdf9a60065b 117 \return Configuration Base Address register value
kadonotakashi 0:8fdf9a60065b 118 */
kadonotakashi 0:8fdf9a60065b 119 __STATIC_FORCEINLINE uint32_t __get_CBAR(void)
kadonotakashi 0:8fdf9a60065b 120 {
kadonotakashi 0:8fdf9a60065b 121 uint32_t result;
kadonotakashi 0:8fdf9a60065b 122 __get_CP(15, 4, result, 15, 0, 0);
kadonotakashi 0:8fdf9a60065b 123 return result;
kadonotakashi 0:8fdf9a60065b 124 }
kadonotakashi 0:8fdf9a60065b 125
kadonotakashi 0:8fdf9a60065b 126 /** \brief Get TTBR0
kadonotakashi 0:8fdf9a60065b 127
kadonotakashi 0:8fdf9a60065b 128 This function returns the value of the Translation Table Base Register 0.
kadonotakashi 0:8fdf9a60065b 129
kadonotakashi 0:8fdf9a60065b 130 \return Translation Table Base Register 0 value
kadonotakashi 0:8fdf9a60065b 131 */
kadonotakashi 0:8fdf9a60065b 132 __STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
kadonotakashi 0:8fdf9a60065b 133 {
kadonotakashi 0:8fdf9a60065b 134 uint32_t result;
kadonotakashi 0:8fdf9a60065b 135 __get_CP(15, 0, result, 2, 0, 0);
kadonotakashi 0:8fdf9a60065b 136 return result;
kadonotakashi 0:8fdf9a60065b 137 }
kadonotakashi 0:8fdf9a60065b 138
kadonotakashi 0:8fdf9a60065b 139 /** \brief Set TTBR0
kadonotakashi 0:8fdf9a60065b 140
kadonotakashi 0:8fdf9a60065b 141 This function assigns the given value to the Translation Table Base Register 0.
kadonotakashi 0:8fdf9a60065b 142
kadonotakashi 0:8fdf9a60065b 143 \param [in] ttbr0 Translation Table Base Register 0 value to set
kadonotakashi 0:8fdf9a60065b 144 */
kadonotakashi 0:8fdf9a60065b 145 __STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
kadonotakashi 0:8fdf9a60065b 146 {
kadonotakashi 0:8fdf9a60065b 147 __set_CP(15, 0, ttbr0, 2, 0, 0);
kadonotakashi 0:8fdf9a60065b 148 }
kadonotakashi 0:8fdf9a60065b 149
kadonotakashi 0:8fdf9a60065b 150 /** \brief Get DACR
kadonotakashi 0:8fdf9a60065b 151
kadonotakashi 0:8fdf9a60065b 152 This function returns the value of the Domain Access Control Register.
kadonotakashi 0:8fdf9a60065b 153
kadonotakashi 0:8fdf9a60065b 154 \return Domain Access Control Register value
kadonotakashi 0:8fdf9a60065b 155 */
kadonotakashi 0:8fdf9a60065b 156 __STATIC_FORCEINLINE uint32_t __get_DACR(void)
kadonotakashi 0:8fdf9a60065b 157 {
kadonotakashi 0:8fdf9a60065b 158 uint32_t result;
kadonotakashi 0:8fdf9a60065b 159 __get_CP(15, 0, result, 3, 0, 0);
kadonotakashi 0:8fdf9a60065b 160 return result;
kadonotakashi 0:8fdf9a60065b 161 }
kadonotakashi 0:8fdf9a60065b 162
kadonotakashi 0:8fdf9a60065b 163 /** \brief Set DACR
kadonotakashi 0:8fdf9a60065b 164
kadonotakashi 0:8fdf9a60065b 165 This function assigns the given value to the Domain Access Control Register.
kadonotakashi 0:8fdf9a60065b 166
kadonotakashi 0:8fdf9a60065b 167 \param [in] dacr Domain Access Control Register value to set
kadonotakashi 0:8fdf9a60065b 168 */
kadonotakashi 0:8fdf9a60065b 169 __STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
kadonotakashi 0:8fdf9a60065b 170 {
kadonotakashi 0:8fdf9a60065b 171 __set_CP(15, 0, dacr, 3, 0, 0);
kadonotakashi 0:8fdf9a60065b 172 }
kadonotakashi 0:8fdf9a60065b 173
kadonotakashi 0:8fdf9a60065b 174 /** \brief Set SCTLR
kadonotakashi 0:8fdf9a60065b 175
kadonotakashi 0:8fdf9a60065b 176 This function assigns the given value to the System Control Register.
kadonotakashi 0:8fdf9a60065b 177
kadonotakashi 0:8fdf9a60065b 178 \param [in] sctlr System Control Register value to set
kadonotakashi 0:8fdf9a60065b 179 */
kadonotakashi 0:8fdf9a60065b 180 __STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
kadonotakashi 0:8fdf9a60065b 181 {
kadonotakashi 0:8fdf9a60065b 182 __set_CP(15, 0, sctlr, 1, 0, 0);
kadonotakashi 0:8fdf9a60065b 183 }
kadonotakashi 0:8fdf9a60065b 184
kadonotakashi 0:8fdf9a60065b 185 /** \brief Get SCTLR
kadonotakashi 0:8fdf9a60065b 186 \return System Control Register value
kadonotakashi 0:8fdf9a60065b 187 */
kadonotakashi 0:8fdf9a60065b 188 __STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
kadonotakashi 0:8fdf9a60065b 189 {
kadonotakashi 0:8fdf9a60065b 190 uint32_t result;
kadonotakashi 0:8fdf9a60065b 191 __get_CP(15, 0, result, 1, 0, 0);
kadonotakashi 0:8fdf9a60065b 192 return result;
kadonotakashi 0:8fdf9a60065b 193 }
kadonotakashi 0:8fdf9a60065b 194
kadonotakashi 0:8fdf9a60065b 195 /** \brief Set ACTRL
kadonotakashi 0:8fdf9a60065b 196 \param [in] actrl Auxiliary Control Register value to set
kadonotakashi 0:8fdf9a60065b 197 */
kadonotakashi 0:8fdf9a60065b 198 __STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
kadonotakashi 0:8fdf9a60065b 199 {
kadonotakashi 0:8fdf9a60065b 200 __set_CP(15, 0, actrl, 1, 0, 1);
kadonotakashi 0:8fdf9a60065b 201 }
kadonotakashi 0:8fdf9a60065b 202
kadonotakashi 0:8fdf9a60065b 203 /** \brief Get ACTRL
kadonotakashi 0:8fdf9a60065b 204 \return Auxiliary Control Register value
kadonotakashi 0:8fdf9a60065b 205 */
kadonotakashi 0:8fdf9a60065b 206 __STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
kadonotakashi 0:8fdf9a60065b 207 {
kadonotakashi 0:8fdf9a60065b 208 uint32_t result;
kadonotakashi 0:8fdf9a60065b 209 __get_CP(15, 0, result, 1, 0, 1);
kadonotakashi 0:8fdf9a60065b 210 return result;
kadonotakashi 0:8fdf9a60065b 211 }
kadonotakashi 0:8fdf9a60065b 212
kadonotakashi 0:8fdf9a60065b 213 /** \brief Get MPIDR
kadonotakashi 0:8fdf9a60065b 214
kadonotakashi 0:8fdf9a60065b 215 This function returns the value of the Multiprocessor Affinity Register.
kadonotakashi 0:8fdf9a60065b 216
kadonotakashi 0:8fdf9a60065b 217 \return Multiprocessor Affinity Register value
kadonotakashi 0:8fdf9a60065b 218 */
kadonotakashi 0:8fdf9a60065b 219 __STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
kadonotakashi 0:8fdf9a60065b 220 {
kadonotakashi 0:8fdf9a60065b 221 uint32_t result;
kadonotakashi 0:8fdf9a60065b 222 __get_CP(15, 0, result, 0, 0, 5);
kadonotakashi 0:8fdf9a60065b 223 return result;
kadonotakashi 0:8fdf9a60065b 224 }
kadonotakashi 0:8fdf9a60065b 225
kadonotakashi 0:8fdf9a60065b 226 /** \brief Get VBAR
kadonotakashi 0:8fdf9a60065b 227
kadonotakashi 0:8fdf9a60065b 228 This function returns the value of the Vector Base Address Register.
kadonotakashi 0:8fdf9a60065b 229
kadonotakashi 0:8fdf9a60065b 230 \return Vector Base Address Register
kadonotakashi 0:8fdf9a60065b 231 */
kadonotakashi 0:8fdf9a60065b 232 __STATIC_FORCEINLINE uint32_t __get_VBAR(void)
kadonotakashi 0:8fdf9a60065b 233 {
kadonotakashi 0:8fdf9a60065b 234 uint32_t result;
kadonotakashi 0:8fdf9a60065b 235 __get_CP(15, 0, result, 12, 0, 0);
kadonotakashi 0:8fdf9a60065b 236 return result;
kadonotakashi 0:8fdf9a60065b 237 }
kadonotakashi 0:8fdf9a60065b 238
kadonotakashi 0:8fdf9a60065b 239 /** \brief Set VBAR
kadonotakashi 0:8fdf9a60065b 240
kadonotakashi 0:8fdf9a60065b 241 This function assigns the given value to the Vector Base Address Register.
kadonotakashi 0:8fdf9a60065b 242
kadonotakashi 0:8fdf9a60065b 243 \param [in] vbar Vector Base Address Register value to set
kadonotakashi 0:8fdf9a60065b 244 */
kadonotakashi 0:8fdf9a60065b 245 __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
kadonotakashi 0:8fdf9a60065b 246 {
kadonotakashi 0:8fdf9a60065b 247 __set_CP(15, 0, vbar, 12, 0, 0);
kadonotakashi 0:8fdf9a60065b 248 }
kadonotakashi 0:8fdf9a60065b 249
kadonotakashi 0:8fdf9a60065b 250 /** \brief Get MVBAR
kadonotakashi 0:8fdf9a60065b 251
kadonotakashi 0:8fdf9a60065b 252 This function returns the value of the Monitor Vector Base Address Register.
kadonotakashi 0:8fdf9a60065b 253
kadonotakashi 0:8fdf9a60065b 254 \return Monitor Vector Base Address Register
kadonotakashi 0:8fdf9a60065b 255 */
kadonotakashi 0:8fdf9a60065b 256 __STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
kadonotakashi 0:8fdf9a60065b 257 {
kadonotakashi 0:8fdf9a60065b 258 uint32_t result;
kadonotakashi 0:8fdf9a60065b 259 __get_CP(15, 0, result, 12, 0, 1);
kadonotakashi 0:8fdf9a60065b 260 return result;
kadonotakashi 0:8fdf9a60065b 261 }
kadonotakashi 0:8fdf9a60065b 262
kadonotakashi 0:8fdf9a60065b 263 /** \brief Set MVBAR
kadonotakashi 0:8fdf9a60065b 264
kadonotakashi 0:8fdf9a60065b 265 This function assigns the given value to the Monitor Vector Base Address Register.
kadonotakashi 0:8fdf9a60065b 266
kadonotakashi 0:8fdf9a60065b 267 \param [in] mvbar Monitor Vector Base Address Register value to set
kadonotakashi 0:8fdf9a60065b 268 */
kadonotakashi 0:8fdf9a60065b 269 __STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
kadonotakashi 0:8fdf9a60065b 270 {
kadonotakashi 0:8fdf9a60065b 271 __set_CP(15, 0, mvbar, 12, 0, 1);
kadonotakashi 0:8fdf9a60065b 272 }
kadonotakashi 0:8fdf9a60065b 273
kadonotakashi 0:8fdf9a60065b 274 #if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
kadonotakashi 0:8fdf9a60065b 275 defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
kadonotakashi 0:8fdf9a60065b 276 defined(DOXYGEN)
kadonotakashi 0:8fdf9a60065b 277
kadonotakashi 0:8fdf9a60065b 278 /** \brief Set CNTFRQ
kadonotakashi 0:8fdf9a60065b 279
kadonotakashi 0:8fdf9a60065b 280 This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
kadonotakashi 0:8fdf9a60065b 281
kadonotakashi 0:8fdf9a60065b 282 \param [in] value CNTFRQ Register value to set
kadonotakashi 0:8fdf9a60065b 283 */
kadonotakashi 0:8fdf9a60065b 284 __STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
kadonotakashi 0:8fdf9a60065b 285 {
kadonotakashi 0:8fdf9a60065b 286 __set_CP(15, 0, value, 14, 0, 0);
kadonotakashi 0:8fdf9a60065b 287 }
kadonotakashi 0:8fdf9a60065b 288
kadonotakashi 0:8fdf9a60065b 289 /** \brief Get CNTFRQ
kadonotakashi 0:8fdf9a60065b 290
kadonotakashi 0:8fdf9a60065b 291 This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
kadonotakashi 0:8fdf9a60065b 292
kadonotakashi 0:8fdf9a60065b 293 \return CNTFRQ Register value
kadonotakashi 0:8fdf9a60065b 294 */
kadonotakashi 0:8fdf9a60065b 295 __STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
kadonotakashi 0:8fdf9a60065b 296 {
kadonotakashi 0:8fdf9a60065b 297 uint32_t result;
kadonotakashi 0:8fdf9a60065b 298 __get_CP(15, 0, result, 14, 0 , 0);
kadonotakashi 0:8fdf9a60065b 299 return result;
kadonotakashi 0:8fdf9a60065b 300 }
kadonotakashi 0:8fdf9a60065b 301
kadonotakashi 0:8fdf9a60065b 302 /** \brief Set CNTP_TVAL
kadonotakashi 0:8fdf9a60065b 303
kadonotakashi 0:8fdf9a60065b 304 This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
kadonotakashi 0:8fdf9a60065b 305
kadonotakashi 0:8fdf9a60065b 306 \param [in] value CNTP_TVAL Register value to set
kadonotakashi 0:8fdf9a60065b 307 */
kadonotakashi 0:8fdf9a60065b 308 __STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
kadonotakashi 0:8fdf9a60065b 309 {
kadonotakashi 0:8fdf9a60065b 310 __set_CP(15, 0, value, 14, 2, 0);
kadonotakashi 0:8fdf9a60065b 311 }
kadonotakashi 0:8fdf9a60065b 312
kadonotakashi 0:8fdf9a60065b 313 /** \brief Get CNTP_TVAL
kadonotakashi 0:8fdf9a60065b 314
kadonotakashi 0:8fdf9a60065b 315 This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
kadonotakashi 0:8fdf9a60065b 316
kadonotakashi 0:8fdf9a60065b 317 \return CNTP_TVAL Register value
kadonotakashi 0:8fdf9a60065b 318 */
kadonotakashi 0:8fdf9a60065b 319 __STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
kadonotakashi 0:8fdf9a60065b 320 {
kadonotakashi 0:8fdf9a60065b 321 uint32_t result;
kadonotakashi 0:8fdf9a60065b 322 __get_CP(15, 0, result, 14, 2, 0);
kadonotakashi 0:8fdf9a60065b 323 return result;
kadonotakashi 0:8fdf9a60065b 324 }
kadonotakashi 0:8fdf9a60065b 325
kadonotakashi 0:8fdf9a60065b 326 /** \brief Get CNTPCT
kadonotakashi 0:8fdf9a60065b 327
kadonotakashi 0:8fdf9a60065b 328 This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
kadonotakashi 0:8fdf9a60065b 329
kadonotakashi 0:8fdf9a60065b 330 \return CNTPCT Register value
kadonotakashi 0:8fdf9a60065b 331 */
kadonotakashi 0:8fdf9a60065b 332 __STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
kadonotakashi 0:8fdf9a60065b 333 {
kadonotakashi 0:8fdf9a60065b 334 uint64_t result;
kadonotakashi 0:8fdf9a60065b 335 __get_CP64(15, 0, result, 14);
kadonotakashi 0:8fdf9a60065b 336 return result;
kadonotakashi 0:8fdf9a60065b 337 }
kadonotakashi 0:8fdf9a60065b 338
kadonotakashi 0:8fdf9a60065b 339 /** \brief Set CNTP_CVAL
kadonotakashi 0:8fdf9a60065b 340
kadonotakashi 0:8fdf9a60065b 341 This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
kadonotakashi 0:8fdf9a60065b 342
kadonotakashi 0:8fdf9a60065b 343 \param [in] value CNTP_CVAL Register value to set
kadonotakashi 0:8fdf9a60065b 344 */
kadonotakashi 0:8fdf9a60065b 345 __STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
kadonotakashi 0:8fdf9a60065b 346 {
kadonotakashi 0:8fdf9a60065b 347 __set_CP64(15, 2, value, 14);
kadonotakashi 0:8fdf9a60065b 348 }
kadonotakashi 0:8fdf9a60065b 349
kadonotakashi 0:8fdf9a60065b 350 /** \brief Get CNTP_CVAL
kadonotakashi 0:8fdf9a60065b 351
kadonotakashi 0:8fdf9a60065b 352 This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
kadonotakashi 0:8fdf9a60065b 353
kadonotakashi 0:8fdf9a60065b 354 \return CNTP_CVAL Register value
kadonotakashi 0:8fdf9a60065b 355 */
kadonotakashi 0:8fdf9a60065b 356 __STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
kadonotakashi 0:8fdf9a60065b 357 {
kadonotakashi 0:8fdf9a60065b 358 uint64_t result;
kadonotakashi 0:8fdf9a60065b 359 __get_CP64(15, 2, result, 14);
kadonotakashi 0:8fdf9a60065b 360 return result;
kadonotakashi 0:8fdf9a60065b 361 }
kadonotakashi 0:8fdf9a60065b 362
kadonotakashi 0:8fdf9a60065b 363 /** \brief Set CNTP_CTL
kadonotakashi 0:8fdf9a60065b 364
kadonotakashi 0:8fdf9a60065b 365 This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
kadonotakashi 0:8fdf9a60065b 366
kadonotakashi 0:8fdf9a60065b 367 \param [in] value CNTP_CTL Register value to set
kadonotakashi 0:8fdf9a60065b 368 */
kadonotakashi 0:8fdf9a60065b 369 __STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
kadonotakashi 0:8fdf9a60065b 370 {
kadonotakashi 0:8fdf9a60065b 371 __set_CP(15, 0, value, 14, 2, 1);
kadonotakashi 0:8fdf9a60065b 372 }
kadonotakashi 0:8fdf9a60065b 373
kadonotakashi 0:8fdf9a60065b 374 /** \brief Get CNTP_CTL register
kadonotakashi 0:8fdf9a60065b 375 \return CNTP_CTL Register value
kadonotakashi 0:8fdf9a60065b 376 */
kadonotakashi 0:8fdf9a60065b 377 __STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
kadonotakashi 0:8fdf9a60065b 378 {
kadonotakashi 0:8fdf9a60065b 379 uint32_t result;
kadonotakashi 0:8fdf9a60065b 380 __get_CP(15, 0, result, 14, 2, 1);
kadonotakashi 0:8fdf9a60065b 381 return result;
kadonotakashi 0:8fdf9a60065b 382 }
kadonotakashi 0:8fdf9a60065b 383
kadonotakashi 0:8fdf9a60065b 384 #endif
kadonotakashi 0:8fdf9a60065b 385
kadonotakashi 0:8fdf9a60065b 386 /** \brief Set TLBIALL
kadonotakashi 0:8fdf9a60065b 387
kadonotakashi 0:8fdf9a60065b 388 TLB Invalidate All
kadonotakashi 0:8fdf9a60065b 389 */
kadonotakashi 0:8fdf9a60065b 390 __STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
kadonotakashi 0:8fdf9a60065b 391 {
kadonotakashi 0:8fdf9a60065b 392 __set_CP(15, 0, value, 8, 7, 0);
kadonotakashi 0:8fdf9a60065b 393 }
kadonotakashi 0:8fdf9a60065b 394
kadonotakashi 0:8fdf9a60065b 395 /** \brief Set BPIALL.
kadonotakashi 0:8fdf9a60065b 396
kadonotakashi 0:8fdf9a60065b 397 Branch Predictor Invalidate All
kadonotakashi 0:8fdf9a60065b 398 */
kadonotakashi 0:8fdf9a60065b 399 __STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
kadonotakashi 0:8fdf9a60065b 400 {
kadonotakashi 0:8fdf9a60065b 401 __set_CP(15, 0, value, 7, 5, 6);
kadonotakashi 0:8fdf9a60065b 402 }
kadonotakashi 0:8fdf9a60065b 403
kadonotakashi 0:8fdf9a60065b 404 /** \brief Set ICIALLU
kadonotakashi 0:8fdf9a60065b 405
kadonotakashi 0:8fdf9a60065b 406 Instruction Cache Invalidate All
kadonotakashi 0:8fdf9a60065b 407 */
kadonotakashi 0:8fdf9a60065b 408 __STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
kadonotakashi 0:8fdf9a60065b 409 {
kadonotakashi 0:8fdf9a60065b 410 __set_CP(15, 0, value, 7, 5, 0);
kadonotakashi 0:8fdf9a60065b 411 }
kadonotakashi 0:8fdf9a60065b 412
kadonotakashi 0:8fdf9a60065b 413 /** \brief Set DCCMVAC
kadonotakashi 0:8fdf9a60065b 414
kadonotakashi 0:8fdf9a60065b 415 Data cache clean
kadonotakashi 0:8fdf9a60065b 416 */
kadonotakashi 0:8fdf9a60065b 417 __STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
kadonotakashi 0:8fdf9a60065b 418 {
kadonotakashi 0:8fdf9a60065b 419 __set_CP(15, 0, value, 7, 10, 1);
kadonotakashi 0:8fdf9a60065b 420 }
kadonotakashi 0:8fdf9a60065b 421
kadonotakashi 0:8fdf9a60065b 422 /** \brief Set DCIMVAC
kadonotakashi 0:8fdf9a60065b 423
kadonotakashi 0:8fdf9a60065b 424 Data cache invalidate
kadonotakashi 0:8fdf9a60065b 425 */
kadonotakashi 0:8fdf9a60065b 426 __STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
kadonotakashi 0:8fdf9a60065b 427 {
kadonotakashi 0:8fdf9a60065b 428 __set_CP(15, 0, value, 7, 6, 1);
kadonotakashi 0:8fdf9a60065b 429 }
kadonotakashi 0:8fdf9a60065b 430
kadonotakashi 0:8fdf9a60065b 431 /** \brief Set DCCIMVAC
kadonotakashi 0:8fdf9a60065b 432
kadonotakashi 0:8fdf9a60065b 433 Data cache clean and invalidate
kadonotakashi 0:8fdf9a60065b 434 */
kadonotakashi 0:8fdf9a60065b 435 __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
kadonotakashi 0:8fdf9a60065b 436 {
kadonotakashi 0:8fdf9a60065b 437 __set_CP(15, 0, value, 7, 14, 1);
kadonotakashi 0:8fdf9a60065b 438 }
kadonotakashi 0:8fdf9a60065b 439
kadonotakashi 0:8fdf9a60065b 440 /** \brief Set CSSELR
kadonotakashi 0:8fdf9a60065b 441 */
kadonotakashi 0:8fdf9a60065b 442 __STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
kadonotakashi 0:8fdf9a60065b 443 {
kadonotakashi 0:8fdf9a60065b 444 // __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
kadonotakashi 0:8fdf9a60065b 445 __set_CP(15, 2, value, 0, 0, 0);
kadonotakashi 0:8fdf9a60065b 446 }
kadonotakashi 0:8fdf9a60065b 447
kadonotakashi 0:8fdf9a60065b 448 /** \brief Get CSSELR
kadonotakashi 0:8fdf9a60065b 449 \return CSSELR Register value
kadonotakashi 0:8fdf9a60065b 450 */
kadonotakashi 0:8fdf9a60065b 451 __STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
kadonotakashi 0:8fdf9a60065b 452 {
kadonotakashi 0:8fdf9a60065b 453 uint32_t result;
kadonotakashi 0:8fdf9a60065b 454 // __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
kadonotakashi 0:8fdf9a60065b 455 __get_CP(15, 2, result, 0, 0, 0);
kadonotakashi 0:8fdf9a60065b 456 return result;
kadonotakashi 0:8fdf9a60065b 457 }
kadonotakashi 0:8fdf9a60065b 458
kadonotakashi 0:8fdf9a60065b 459 /** \brief Set CCSIDR
kadonotakashi 0:8fdf9a60065b 460 \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
kadonotakashi 0:8fdf9a60065b 461 */
kadonotakashi 0:8fdf9a60065b 462 CMSIS_DEPRECATED
kadonotakashi 0:8fdf9a60065b 463 __STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
kadonotakashi 0:8fdf9a60065b 464 {
kadonotakashi 0:8fdf9a60065b 465 __set_CSSELR(value);
kadonotakashi 0:8fdf9a60065b 466 }
kadonotakashi 0:8fdf9a60065b 467
kadonotakashi 0:8fdf9a60065b 468 /** \brief Get CCSIDR
kadonotakashi 0:8fdf9a60065b 469 \return CCSIDR Register value
kadonotakashi 0:8fdf9a60065b 470 */
kadonotakashi 0:8fdf9a60065b 471 __STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
kadonotakashi 0:8fdf9a60065b 472 {
kadonotakashi 0:8fdf9a60065b 473 uint32_t result;
kadonotakashi 0:8fdf9a60065b 474 // __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
kadonotakashi 0:8fdf9a60065b 475 __get_CP(15, 1, result, 0, 0, 0);
kadonotakashi 0:8fdf9a60065b 476 return result;
kadonotakashi 0:8fdf9a60065b 477 }
kadonotakashi 0:8fdf9a60065b 478
kadonotakashi 0:8fdf9a60065b 479 /** \brief Get CLIDR
kadonotakashi 0:8fdf9a60065b 480 \return CLIDR Register value
kadonotakashi 0:8fdf9a60065b 481 */
kadonotakashi 0:8fdf9a60065b 482 __STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
kadonotakashi 0:8fdf9a60065b 483 {
kadonotakashi 0:8fdf9a60065b 484 uint32_t result;
kadonotakashi 0:8fdf9a60065b 485 // __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
kadonotakashi 0:8fdf9a60065b 486 __get_CP(15, 1, result, 0, 0, 1);
kadonotakashi 0:8fdf9a60065b 487 return result;
kadonotakashi 0:8fdf9a60065b 488 }
kadonotakashi 0:8fdf9a60065b 489
kadonotakashi 0:8fdf9a60065b 490 /** \brief Set DCISW
kadonotakashi 0:8fdf9a60065b 491 */
kadonotakashi 0:8fdf9a60065b 492 __STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
kadonotakashi 0:8fdf9a60065b 493 {
kadonotakashi 0:8fdf9a60065b 494 // __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
kadonotakashi 0:8fdf9a60065b 495 __set_CP(15, 0, value, 7, 6, 2);
kadonotakashi 0:8fdf9a60065b 496 }
kadonotakashi 0:8fdf9a60065b 497
kadonotakashi 0:8fdf9a60065b 498 /** \brief Set DCCSW
kadonotakashi 0:8fdf9a60065b 499 */
kadonotakashi 0:8fdf9a60065b 500 __STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
kadonotakashi 0:8fdf9a60065b 501 {
kadonotakashi 0:8fdf9a60065b 502 // __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
kadonotakashi 0:8fdf9a60065b 503 __set_CP(15, 0, value, 7, 10, 2);
kadonotakashi 0:8fdf9a60065b 504 }
kadonotakashi 0:8fdf9a60065b 505
kadonotakashi 0:8fdf9a60065b 506 /** \brief Set DCCISW
kadonotakashi 0:8fdf9a60065b 507 */
kadonotakashi 0:8fdf9a60065b 508 __STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
kadonotakashi 0:8fdf9a60065b 509 {
kadonotakashi 0:8fdf9a60065b 510 // __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
kadonotakashi 0:8fdf9a60065b 511 __set_CP(15, 0, value, 7, 14, 2);
kadonotakashi 0:8fdf9a60065b 512 }
kadonotakashi 0:8fdf9a60065b 513
kadonotakashi 0:8fdf9a60065b 514 #endif