qspi_test_utils.h

00001 /* mbed Microcontroller Library
00002  * Copyright (c) 2018-2018 ARM Limited
00003  *
00004  * Licensed under the Apache License, Version 2.0 (the "License");
00005  * you may not use this file except in compliance with the License.
00006  * You may obtain a copy of the License at
00007  *
00008  *     http://www.apache.org/licenses/LICENSE-2.0
00009  *
00010  * Unless required by applicable law or agreed to in writing, software
00011  * distributed under the License is distributed on an "AS IS" BASIS,
00012  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00013  * See the License for the specific language governing permissions and
00014  * limitations under the License.
00015  */
00016 #ifndef MBED_QSPI_TEST_UTILS_H
00017 #define MBED_QSPI_TEST_UTILS_H
00018 
00019 #include "flash_configs/flash_configs.h"
00020 #include "unity/unity.h"
00021 
00022 #define QSPI_NONE (-1)
00023 
00024 enum QspiStatus {
00025     sOK,
00026     sError,
00027     sTimeout,
00028     sUnknown
00029 };
00030 
00031 class QspiCommand {
00032 public:
00033     void configure(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width,
00034                    qspi_bus_width_t alt_width, qspi_address_size_t addr_size, qspi_alt_size_t alt_size,
00035                    int dummy_cycles = 0);
00036 
00037     void set_dummy_cycles(int dummy_cycles);
00038 
00039     void build(int instruction, int address = QSPI_NONE, int alt = QSPI_NONE);
00040 
00041     qspi_command_t *get();
00042 
00043 private:
00044     qspi_command_t _cmd;
00045 };
00046 
00047 struct Qspi {
00048     qspi_t handle;
00049     QspiCommand cmd;
00050 };
00051 
00052 // MODE_Command_Address_Data_Alt
00053 #define MODE_1_1_1      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE
00054 #define MODE_1_1_2      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL
00055 #define MODE_1_2_2      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL
00056 #define MODE_2_2_2      QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL,   QSPI_CFG_BUS_DUAL
00057 #define MODE_1_1_4      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_QUAD
00058 #define MODE_1_4_4      QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_QUAD
00059 #define MODE_4_4_4      QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_QUAD,   QSPI_CFG_BUS_QUAD
00060 
00061 #define WRITE_1_1_1     MODE_1_1_1, QSPI_CMD_WRITE_1IO
00062 #ifdef QSPI_CMD_WRITE_2IO
00063 #define WRITE_1_2_2     MODE_1_2_2, QSPI_CMD_WRITE_2IO
00064 #endif
00065 #ifdef QSPI_CMD_WRITE_4IO
00066 #define WRITE_1_4_4     MODE_1_4_4, QSPI_CMD_WRITE_4IO
00067 #endif
00068 #ifdef QSPI_CMD_WRITE_DPI
00069 #define WRITE_2_2_2     MODE_2_2_2, QSPI_CMD_WRITE_DPI
00070 #endif
00071 #ifdef QSPI_CMD_WRITE_QPI
00072 #define WRITE_4_4_4     MODE_4_4_4, QSPI_CMD_WRITE_QPI
00073 #endif
00074 
00075 
00076 #define READ_1_1_1      MODE_1_1_1, QSPI_CMD_READ_1IO,  QSPI_READ_1IO_DUMMY_CYCLE
00077 #define READ_1_1_2      MODE_1_1_2, QSPI_CMD_READ_1I2O, QSPI_READ_1I2O_DUMMY_CYCLE
00078 #define READ_1_2_2      MODE_1_2_2, QSPI_CMD_READ_2IO,  QSPI_READ_2IO_DUMMY_CYCLE
00079 #define READ_1_1_4      MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
00080 #define READ_1_4_4      MODE_1_4_4, QSPI_CMD_READ_4IO,  QSPI_READ_4IO_DUMMY_CYCLE
00081 #ifdef QSPI_CMD_READ_DPI
00082 #define READ_2_2_2      MODE_2_2_2, QSPI_CMD_READ_DPI,  QSPI_READ_2IO_DUMMY_CYCLE
00083 #endif
00084 #ifdef QSPI_CMD_READ_QPI
00085 #define READ_4_4_4      MODE_4_4_4, QSPI_CMD_READ_QPI,  QSPI_READ_4IO_DUMMY_CYCLE
00086 #endif
00087 
00088 #define ADDR_SIZE_8  QSPI_CFG_ADDR_SIZE_8
00089 #define ADDR_SIZE_16 QSPI_CFG_ADDR_SIZE_16
00090 #define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24
00091 #define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32
00092 
00093 #define ALT_SIZE_8  QSPI_CFG_ALT_SIZE_8
00094 #define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16
00095 #define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24
00096 #define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32
00097 
00098 #define STATUS_REG      QSPI_CMD_RDSR
00099 #define CONFIG_REG0      QSPI_CMD_RDCR0
00100 #ifdef QSPI_CMD_RDCR1
00101 #define CONFIG_REG1      QSPI_CMD_RDCR1
00102 #endif
00103 #ifdef QSPI_CMD_RDCR2
00104 #define CONFIG_REG2      QSPI_CMD_RDCR2
00105 #endif
00106 #define SECURITY_REG    QSPI_CMD_RDSCUR
00107 
00108 #ifndef QSPI_CONFIG_REG_1_SIZE
00109 #define QSPI_CONFIG_REG_1_SIZE 0
00110 #endif
00111 
00112 #ifndef QSPI_CONFIG_REG_2_SIZE
00113 #define QSPI_CONFIG_REG_2_SIZE 0
00114 #endif
00115 
00116 
00117 #define SECTOR_ERASE  QSPI_CMD_ERASE_SECTOR
00118 #define BLOCK_ERASE   QSPI_CMD_ERASE_BLOCK_64
00119 
00120 
00121 #define SECTOR_ERASE_MAX_TIME   QSPI_ERASE_SECTOR_MAX_TIME
00122 #define BLOCK32_ERASE_MAX_TIME  QSPI_ERASE_BLOCK_32_MAX_TIME
00123 #define BLOCK64_ERASE_MAX_TIME  QSPI_ERASE_BLOCK_64_MAX_TIME
00124 #define PAGE_PROG_MAX_TIME      QSPI_PAGE_PROG_MAX_TIME
00125 #define WRSR_MAX_TIME           QSPI_WRSR_MAX_TIME
00126 #define WAIT_MAX_TIME           QSPI_WAIT_MAX_TIME
00127 
00128 
00129 
00130 qspi_status_t read_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
00131 qspi_status_t write_register(uint32_t cmd, uint8_t *buf, uint32_t size, Qspi &q);
00132 
00133 QspiStatus flash_wait_for(uint32_t time_us, Qspi &qspi);
00134 
00135 void flash_init(Qspi &qspi);
00136 
00137 qspi_status_t write_enable(Qspi &qspi);
00138 qspi_status_t write_disable(Qspi &qspi);
00139 
00140 void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi, const char *str = NULL);
00141 
00142 qspi_status_t mode_enable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
00143 qspi_status_t mode_disable(Qspi &qspi, qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
00144 
00145 qspi_status_t fast_mode_enable(Qspi &qspi);
00146 qspi_status_t fast_mode_disable(Qspi &qspi);
00147 
00148 qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi);
00149 
00150 bool is_extended_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
00151 bool is_dual_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
00152 bool is_quad_mode(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width);
00153 
00154 #define  WAIT_FOR(timeout, q)   TEST_ASSERT_EQUAL_MESSAGE(sOK, flash_wait_for(timeout, q), "flash_wait_for failed!!!")
00155 
00156 
00157 #endif // MBED_QSPI_TEST_UTILS_H