takashi kadono
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Nucleo_446
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N25Q128A_config.h
00001 /* mbed Microcontroller Library 00002 * Copyright (c) 2018-2018 ARM Limited 00003 * 00004 * Licensed under the Apache License, Version 2.0 (the "License"); 00005 * you may not use this file except in compliance with the License. 00006 * You may obtain a copy of the License at 00007 * 00008 * http://www.apache.org/licenses/LICENSE-2.0 00009 * 00010 * Unless required by applicable law or agreed to in writing, software 00011 * distributed under the License is distributed on an "AS IS" BASIS, 00012 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00013 * See the License for the specific language governing permissions and 00014 * limitations under the License. 00015 */ 00016 #ifndef MBED_QSPI_FLASH_N25Q128A_H 00017 #define MBED_QSPI_FLASH_N25Q128A_H 00018 00019 00020 #define QSPI_FLASH_CHIP_STRING "Micron N25Q128A" 00021 00022 // Command for reading status register 00023 #define QSPI_CMD_RDSR 0x05 00024 // Command for reading configuration register 0 (NONVOLATILE CONFIGURATION REGISTER) 00025 #define QSPI_CMD_RDCR0 0xB5 00026 // Command for reading configuration register 1 (VOLATILE CONFIGURATION REGISTER) 00027 #define QSPI_CMD_RDCR1 0x85 00028 // Command for reading configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER) 00029 #define QSPI_CMD_RDCR2 0x65 00030 // Command for writing status 00031 #define QSPI_CMD_WRSR 0x01 00032 // Command for writing configuration register 0 (NONVOLATILE CONFIGURATION REGISTER) 00033 #define QSPI_CMD_WRCR0 0xB1 00034 // Command for writing configuration register 1 (VOLATILE CONFIGURATION REGISTER) 00035 #define QSPI_CMD_WRCR1 0x81 00036 // Command for writing configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER) 00037 #define QSPI_CMD_WRCR2 0x61 00038 // Command for reading security register 00039 #define QSPI_CMD_RDSCUR 0x2B 00040 00041 // Command for setting Reset Enable 00042 #define QSPI_CMD_RSTEN 0x66 00043 // Command for setting Reset 00044 #define QSPI_CMD_RST 0x99 00045 00046 // Command for setting write enable 00047 #define QSPI_CMD_WREN 0x06 00048 // Command for setting write disable 00049 #define QSPI_CMD_WRDI 0x04 00050 00051 // WRSR operations max time [us] (datasheet max time + 15%) 00052 #define QSPI_WRSR_MAX_TIME 9200 // 8ms 00053 // general wait max time [us] 00054 #define QSPI_WAIT_MAX_TIME 100000 // 100ms 00055 00056 00057 // Commands for writing (page programming) 00058 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode 00059 #define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode 00060 #define QSPI_CMD_WRITE_4IO 0x12 // 1-4-4 mode 00061 #define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode 00062 #define QSPI_CMD_WRITE_QPI 0x12 // 4-4-4 mode 00063 00064 // write operations max time [us] (datasheet max time + 15%) 00065 #define QSPI_PAGE_PROG_MAX_TIME 5750 // 5ms 00066 00067 #define QSPI_PAGE_SIZE 256 // 256B 00068 #define QSPI_SECTOR_SIZE 4096 // 4kB 00069 #define QSPI_SECTOR_COUNT 4096 00070 00071 // Commands for reading 00072 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode 00073 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode 00074 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode 00075 #define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode 00076 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode 00077 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode 00078 #define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode 00079 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode 00080 00081 00082 #define QSPI_READ_1IO_DUMMY_CYCLE 0 00083 #define QSPI_READ_FAST_DUMMY_CYCLE 8 00084 // 8 dummy (10 dummy when quad SPI protocol is enabled) 00085 #define QSPI_READ_2IO_DUMMY_CYCLE 8 00086 #define QSPI_READ_1I2O_DUMMY_CYCLE 8 00087 #define QSPI_READ_4IO_DUMMY_CYCLE 10 00088 #define QSPI_READ_1I4O_DUMMY_CYCLE 8 00089 00090 // Commands for erasing 00091 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB 00092 #define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB 00093 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB 00094 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7 00095 00096 // erase operations max time [us] (datasheet max time + 15%) 00097 #define QSPI_ERASE_SECTOR_MAX_TIME 920000 // 0.8s 00098 #define QSPI_ERASE_BLOCK_32_MAX_TIME 3000000 // 3s 00099 #define QSPI_ERASE_BLOCK_64_MAX_TIME 3500000 // 3.5s 00100 00101 // max frequency for basic rw operation 00102 #define QSPI_COMMON_MAX_FREQUENCY 50000000 00103 00104 #define QSPI_STATUS_REG_SIZE 1 00105 #define QSPI_CONFIG_REG_0_SIZE 2 00106 #define QSPI_CONFIG_REG_1_SIZE 1 00107 #define QSPI_CONFIG_REG_2_SIZE 1 00108 #define QSPI_MAX_REG_SIZE 2 00109 00110 // status register 00111 #define STATUS_BIT_WIP (1 << 0) // write in progress bit 00112 #define STATUS_BIT_WEL (1 << 1) // write enable latch 00113 #define STATUS_BIT_BP0 (1 << 2) // block 00114 #define STATUS_BIT_BP1 (1 << 3) // 00115 #define STATUS_BIT_BP2 (1 << 4) // 00116 #define STATUS_BIT_BP_TB (1 << 5) // Block protect top/bottom 00117 #define STATUS_BIT_BP3 (1 << 6) // 00118 #define STATUS_BIT_SRWD (1 << 7) // status register write protect 00119 00120 // configuration register 0 (Nonvolatile Configuration Register) 00121 // bit 1, 5, reserved 00122 #define CONFIG0_BIT_LOCK (1 << 0) // Lock nonvolatile configuration register 00123 #define CONFIG0_BIT_DE (1 << 2) // Dual Enable 0 = Enabled / 1 = Disabled 00124 #define CONFIG0_BIT_QE (1 << 3) // Quad Enable 0 = Enabled / 1 = Disabled 00125 #define CONFIG0_BIT_RH (1 << 4) // Reset/hold 00126 #define CONFIG0_BIT_ODS0 (1 << 6) // Output driver strength 00127 #define CONFIG0_BIT_ODS1 (1 << 7) // Output driver strength 00128 #define CONFIG0_BIT_ODS2 (1 << 8) // Output driver strength 00129 #define CONFIG0_BIT_XIP_MODE0 (1 << 9) // XIP mode at power-on reset 00130 #define CONFIG0_BIT_XIP_MODE1 (1 << 10) // XIP mode at power-on reset 00131 #define CONFIG0_BIT_XIP_MODE2 (1 << 11) // XIP mode at power-on reset 00132 #define CONFIG0_BIT_DCYCLE0 (1 << 12) // Dummy Cycle 00133 #define CONFIG0_BIT_DCYCLE1 (1 << 13) // Dummy Cycle 00134 #define CONFIG0_BIT_DCYCLE2 (1 << 14) // Dummy Cycle 00135 #define CONFIG0_BIT_DCYCLE3 (1 << 15) // Dummy Cycle 00136 #define CONFIG0_BITS_DEFAULT 0xFFFF // reg default state 00137 00138 00139 // configuration register 1 (Volatile Configuration Register) 00140 // bit 2, reserved 00141 #define CONFIG1_BIT_WRAP0 (1 << 0) // Output data wrap 00142 #define CONFIG1_BIT_WRAP1 (1 << 1) // Output data wrap 00143 #define CONFIG1_BIT_XIP (1 << 3) // 0 = Enable / 1 = Disable (default) 00144 #define CONFIG1_BIT_DCYCLE0 (1 << 4) // Number of dummy clock cycles 00145 #define CONFIG1_BIT_DCYCLE1 (1 << 5) // Number of dummy clock cycles 00146 #define CONFIG1_BIT_DCYCLE2 (1 << 6) // Number of dummy clock cycles 00147 #define CONFIG1_BIT_DCYCLE3 (1 << 7) // Number of dummy clock cycles 00148 #define CONFIG1_BITS_DEFAULT 0xB // reg default state 00149 00150 00151 // configuration register 2 (Enhanced Volatile Configuration Register) 00152 // bit 5, reserved 00153 #define CONFIG2_BIT_ODS0 (1 << 0) // Output driver strength 111 = 30 Ohms (Default) 00154 #define CONFIG2_BIT_ODS1 (1 << 1) // Output driver strength 00155 #define CONFIG2_BIT_ODS2 (1 << 2) // Output driver strength 00156 #define CONFIG2_BIT_VPP (1 << 3) // VPP accelerator 1 = Disabled (Default) 00157 #define CONFIG2_BIT_RH (1 << 4) // Reset/hold 00158 #define CONFIG2_BIT_DE (1 << 6) // Dual I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol) 00159 #define CONFIG2_BIT_QE (1 << 7) // Quad I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol) 00160 #define CONFIG2_BITS_DEFAULT 0xDF // reg default state 00161 00162 00163 #define DUAL_ENABLE() \ 00164 \ 00165 uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \ 00166 \ 00167 memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \ 00168 if (read_register(QSPI_CMD_RDCR2, reg_data, \ 00169 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00170 return QSPI_STATUS_ERROR; \ 00171 } \ 00172 if (write_enable(qspi) != QSPI_STATUS_OK) { \ 00173 return QSPI_STATUS_ERROR; \ 00174 } \ 00175 \ 00176 reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \ 00177 if (write_register(QSPI_CMD_WRCR2, reg_data, \ 00178 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00179 return QSPI_STATUS_ERROR; \ 00180 } \ 00181 qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \ 00182 WAIT_FOR(WRSR_MAX_TIME, qspi); \ 00183 memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \ 00184 if (read_register(QSPI_CMD_RDCR2, reg_data, \ 00185 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00186 return QSPI_STATUS_ERROR; \ 00187 } \ 00188 \ 00189 return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \ 00190 QSPI_STATUS_OK : QSPI_STATUS_ERROR) 00191 00192 00193 #define DUAL_DISABLE() \ 00194 \ 00195 uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \ 00196 \ 00197 memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \ 00198 if (read_register(QSPI_CMD_RDCR2, reg_data, \ 00199 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00200 return QSPI_STATUS_ERROR; \ 00201 } \ 00202 if (write_enable(qspi) != QSPI_STATUS_OK) { \ 00203 return QSPI_STATUS_ERROR; \ 00204 } \ 00205 \ 00206 reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \ 00207 if (write_register(QSPI_CMD_WRCR2, reg_data, \ 00208 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00209 return QSPI_STATUS_ERROR; \ 00210 } \ 00211 WAIT_FOR(WRSR_MAX_TIME, qspi); \ 00212 qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \ 00213 memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \ 00214 if (read_register(QSPI_CMD_RDCR2, reg_data, \ 00215 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00216 return QSPI_STATUS_ERROR; \ 00217 } \ 00218 \ 00219 return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \ 00220 QSPI_STATUS_OK : QSPI_STATUS_ERROR) 00221 00222 00223 #define QUAD_ENABLE() \ 00224 \ 00225 uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \ 00226 \ 00227 memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \ 00228 if (read_register(QSPI_CMD_RDCR2, reg_data, \ 00229 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00230 return QSPI_STATUS_ERROR; \ 00231 } \ 00232 if (write_enable(qspi) != QSPI_STATUS_OK) { \ 00233 return QSPI_STATUS_ERROR; \ 00234 } \ 00235 \ 00236 reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \ 00237 if (write_register(QSPI_CMD_WRCR2, reg_data, \ 00238 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00239 return QSPI_STATUS_ERROR; \ 00240 } \ 00241 qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \ 00242 WAIT_FOR(WRSR_MAX_TIME, qspi); \ 00243 memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \ 00244 if (read_register(QSPI_CMD_RDCR2, reg_data, \ 00245 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00246 return QSPI_STATUS_ERROR; \ 00247 } \ 00248 \ 00249 return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \ 00250 QSPI_STATUS_OK : QSPI_STATUS_ERROR) 00251 00252 00253 #define QUAD_DISABLE() \ 00254 \ 00255 uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \ 00256 \ 00257 memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \ 00258 if (read_register(QSPI_CMD_RDCR2, reg_data, \ 00259 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00260 return QSPI_STATUS_ERROR; \ 00261 } \ 00262 if (write_enable(qspi) != QSPI_STATUS_OK) { \ 00263 return QSPI_STATUS_ERROR; \ 00264 } \ 00265 \ 00266 reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \ 00267 if (write_register(QSPI_CMD_WRCR2, reg_data, \ 00268 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00269 return QSPI_STATUS_ERROR; \ 00270 } \ 00271 WAIT_FOR(WRSR_MAX_TIME, qspi); \ 00272 qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \ 00273 memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \ 00274 if (read_register(QSPI_CMD_RDCR2, reg_data, \ 00275 QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \ 00276 return QSPI_STATUS_ERROR; \ 00277 } \ 00278 \ 00279 return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \ 00280 QSPI_STATUS_OK : QSPI_STATUS_ERROR) 00281 00282 #endif // MBED_QSPI_FLASH_N25Q128A_H
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