takashi kadono
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Nucleo_446
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MX25RXX35F_config.h
00001 /* mbed Microcontroller Library 00002 * Copyright (c) 2018-2018 ARM Limited 00003 * 00004 * Licensed under the Apache License, Version 2.0 (the "License"); 00005 * you may not use this file except in compliance with the License. 00006 * You may obtain a copy of the License at 00007 * 00008 * http://www.apache.org/licenses/LICENSE-2.0 00009 * 00010 * Unless required by applicable law or agreed to in writing, software 00011 * distributed under the License is distributed on an "AS IS" BASIS, 00012 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00013 * See the License for the specific language governing permissions and 00014 * limitations under the License. 00015 */ 00016 #ifndef MBED_QSPI_FLASH_MX25RXX35F_H 00017 #define MBED_QSPI_FLASH_MX25RXX35F_H 00018 00019 00020 #define QSPI_FLASH_CHIP_STRING "macronix MX25RXX35F" 00021 00022 // Command for reading status register 00023 #define QSPI_CMD_RDSR 0x05 00024 // Command for reading configuration register 00025 #define QSPI_CMD_RDCR0 0x15 00026 // Command for writing status/configuration register 00027 #define QSPI_CMD_WRSR 0x01 00028 // Command for reading security register 00029 #define QSPI_CMD_RDSCUR 0x2B 00030 00031 // Command for setting Reset Enable 00032 #define QSPI_CMD_RSTEN 0x66 00033 // Command for setting Reset 00034 #define QSPI_CMD_RST 0x99 00035 00036 // Command for setting write enable 00037 #define QSPI_CMD_WREN 0x06 00038 // Command for setting write disable 00039 #define QSPI_CMD_WRDI 0x04 00040 00041 // WRSR operations max time [us] (datasheet max time + 15%) 00042 #define QSPI_WRSR_MAX_TIME 34500 // 30ms 00043 // general wait max time [us] 00044 #define QSPI_WAIT_MAX_TIME 100000 // 100ms 00045 00046 00047 // Commands for writing (page programming) 00048 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode 00049 #define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode 00050 00051 // write operations max time [us] (datasheet max time + 15%) 00052 #define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms 00053 00054 #define QSPI_PAGE_SIZE 256 // 256B 00055 #define QSPI_SECTOR_SIZE 4096 // 4kB 00056 #define QSPI_SECTOR_COUNT 32 // adjusted to MX25R1035F smallest one from MX25RXX35F family 00057 00058 // Commands for reading 00059 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode 00060 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode 00061 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode 00062 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode 00063 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode 00064 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode 00065 00066 #define QSPI_READ_1IO_DUMMY_CYCLE 0 00067 #define QSPI_READ_FAST_DUMMY_CYCLE 8 00068 #define QSPI_READ_2IO_DUMMY_CYCLE 4 00069 #define QSPI_READ_1I2O_DUMMY_CYCLE 8 00070 #define QSPI_READ_4IO_DUMMY_CYCLE 6 00071 #define QSPI_READ_1I4O_DUMMY_CYCLE 8 00072 00073 // Commands for erasing 00074 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB 00075 #define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB 00076 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB 00077 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7 00078 00079 // erase operations max time [us] (datasheet max time + 15%) 00080 #define QSPI_ERASE_SECTOR_MAX_TIME 276000 // 240 ms 00081 #define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s 00082 #define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s 00083 00084 // max frequency for basic rw operation (for fast mode) 00085 #define QSPI_COMMON_MAX_FREQUENCY 32000000 00086 00087 #define QSPI_STATUS_REG_SIZE 1 00088 #define QSPI_CONFIG_REG_0_SIZE 2 00089 #define QSPI_SECURITY_REG_SIZE 1 00090 #define QSPI_MAX_REG_SIZE 2 00091 00092 // status register 00093 #define STATUS_BIT_WIP (1 << 0) // write in progress bit 00094 #define STATUS_BIT_WEL (1 << 1) // write enable latch 00095 #define STATUS_BIT_BP0 (1 << 2) // 00096 #define STATUS_BIT_BP1 (1 << 3) // 00097 #define STATUS_BIT_BP2 (1 << 4) // 00098 #define STATUS_BIT_BP3 (1 << 5) // 00099 #define STATUS_BIT_QE (1 << 6) // Quad Enable 00100 #define STATUS_BIT_SRWD (1 << 7) // status register write protect 00101 00102 // configuration register 0 00103 // bit 0, 1, 2, 4, 5, 7 reserved 00104 #define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect 00105 #define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle 00106 00107 // configuration register 1 00108 // bit 0, 2, 3, 4, 5, 6, 7 reserved 00109 #define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode 00110 00111 00112 00113 #define EXTENDED_SPI_ENABLE() \ 00114 \ 00115 const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \ 00116 uint8_t reg_data[reg_size] = { 0 }; \ 00117 \ 00118 if (read_register(STATUS_REG, reg_data, \ 00119 QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ 00120 return QSPI_STATUS_ERROR; \ 00121 } \ 00122 if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \ 00123 QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \ 00124 return QSPI_STATUS_ERROR; \ 00125 } \ 00126 \ 00127 if (write_enable(qspi) != QSPI_STATUS_OK) { \ 00128 return QSPI_STATUS_ERROR; \ 00129 } \ 00130 \ 00131 reg_data[0] = STATUS_BIT_QE; \ 00132 if (write_register(QSPI_CMD_WRSR, reg_data, \ 00133 reg_size, qspi) != QSPI_STATUS_OK) { \ 00134 return QSPI_STATUS_ERROR; \ 00135 } \ 00136 WAIT_FOR(WRSR_MAX_TIME, qspi); \ 00137 \ 00138 memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \ 00139 if (read_register(STATUS_REG, reg_data, \ 00140 QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ 00141 return QSPI_STATUS_ERROR; \ 00142 } \ 00143 \ 00144 return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \ 00145 QSPI_STATUS_OK : QSPI_STATUS_ERROR) 00146 00147 00148 00149 #define EXTENDED_SPI_DISABLE() \ 00150 \ 00151 const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \ 00152 uint8_t reg_data[reg_size] = { 0 }; \ 00153 \ 00154 if (read_register(STATUS_REG, reg_data, \ 00155 QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ 00156 return QSPI_STATUS_ERROR; \ 00157 } \ 00158 if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \ 00159 QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \ 00160 return QSPI_STATUS_ERROR; \ 00161 } \ 00162 \ 00163 if (write_enable(qspi) != QSPI_STATUS_OK) { \ 00164 return QSPI_STATUS_ERROR; \ 00165 } \ 00166 \ 00167 reg_data[0] &= ~(STATUS_BIT_QE); \ 00168 \ 00169 if (write_register(QSPI_CMD_WRSR, reg_data, \ 00170 reg_size, qspi) != QSPI_STATUS_OK) { \ 00171 return QSPI_STATUS_ERROR; \ 00172 } \ 00173 WAIT_FOR(WRSR_MAX_TIME, qspi); \ 00174 \ 00175 reg_data[0] = 0; \ 00176 if (read_register(STATUS_REG, reg_data, \ 00177 QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ 00178 return QSPI_STATUS_ERROR; \ 00179 } \ 00180 \ 00181 return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \ 00182 QSPI_STATUS_OK : QSPI_STATUS_ERROR) 00183 00184 00185 00186 #define FAST_MODE_ENABLE() \ 00187 \ 00188 const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \ 00189 uint8_t reg_data[reg_size]; \ 00190 \ 00191 if (read_register(STATUS_REG, reg_data, \ 00192 QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ 00193 return QSPI_STATUS_ERROR; \ 00194 } \ 00195 if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \ 00196 QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \ 00197 return QSPI_STATUS_ERROR; \ 00198 } \ 00199 \ 00200 if (write_enable(qspi) != QSPI_STATUS_OK) { \ 00201 return QSPI_STATUS_ERROR; \ 00202 } \ 00203 \ 00204 reg_data[2] |= CONFIG1_BIT_LH; \ 00205 if (write_register(QSPI_CMD_WRSR, reg_data, \ 00206 reg_size, qspi) != QSPI_STATUS_OK) { \ 00207 return QSPI_STATUS_ERROR; \ 00208 } \ 00209 WAIT_FOR(WRSR_MAX_TIME, qspi); \ 00210 \ 00211 if (read_register(CONFIG_REG0, reg_data, \ 00212 QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \ 00213 return QSPI_STATUS_ERROR; \ 00214 } \ 00215 \ 00216 return ((reg_data[1] & CONFIG1_BIT_LH) != 0 ? \ 00217 QSPI_STATUS_OK : QSPI_STATUS_ERROR) 00218 00219 00220 #define FAST_MODE_DISABLE() \ 00221 \ 00222 const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \ 00223 uint8_t reg_data[reg_size]; \ 00224 \ 00225 if (read_register(STATUS_REG, reg_data, \ 00226 QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \ 00227 return QSPI_STATUS_ERROR; \ 00228 } \ 00229 if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \ 00230 QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \ 00231 return QSPI_STATUS_ERROR; \ 00232 } \ 00233 \ 00234 if (write_enable(qspi) != QSPI_STATUS_OK) { \ 00235 return QSPI_STATUS_ERROR; \ 00236 } \ 00237 \ 00238 reg_data[2] &= ~(CONFIG1_BIT_LH); \ 00239 if (write_register(QSPI_CMD_WRSR, reg_data, \ 00240 reg_size, qspi) != QSPI_STATUS_OK) { \ 00241 return QSPI_STATUS_ERROR; \ 00242 } \ 00243 WAIT_FOR(WRSR_MAX_TIME, qspi); \ 00244 \ 00245 if (read_register(CONFIG_REG0, reg_data, \ 00246 QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \ 00247 return QSPI_STATUS_ERROR; \ 00248 } \ 00249 \ 00250 return ((reg_data[1] & CONFIG1_BIT_LH) == 0 ? \ 00251 QSPI_STATUS_OK : QSPI_STATUS_ERROR) 00252 00253 00254 #endif // MBED_QSPI_FLASH_MX25RXX35F_H
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