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Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466
mbed-os/cmsis/TARGET_CORTEX_M/core_sc000.h@3:f3764f852aa8, 2018-10-11 (annotated)
- Committer:
- kadonotakashi
- Date:
- Thu Oct 11 02:27:46 2018 +0000
- Revision:
- 3:f3764f852aa8
- Parent:
- 0:8fdf9a60065b
Nucreo 446 + SSD1331 test version;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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kadonotakashi | 0:8fdf9a60065b | 1 | /**************************************************************************//** |
kadonotakashi | 0:8fdf9a60065b | 2 | * @file core_sc000.h |
kadonotakashi | 0:8fdf9a60065b | 3 | * @brief CMSIS SC000 Core Peripheral Access Layer Header File |
kadonotakashi | 0:8fdf9a60065b | 4 | * @version V5.0.5 |
kadonotakashi | 0:8fdf9a60065b | 5 | * @date 28. May 2018 |
kadonotakashi | 0:8fdf9a60065b | 6 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 7 | /* |
kadonotakashi | 0:8fdf9a60065b | 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
kadonotakashi | 0:8fdf9a60065b | 9 | * |
kadonotakashi | 0:8fdf9a60065b | 10 | * SPDX-License-Identifier: Apache-2.0 |
kadonotakashi | 0:8fdf9a60065b | 11 | * |
kadonotakashi | 0:8fdf9a60065b | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
kadonotakashi | 0:8fdf9a60065b | 13 | * not use this file except in compliance with the License. |
kadonotakashi | 0:8fdf9a60065b | 14 | * You may obtain a copy of the License at |
kadonotakashi | 0:8fdf9a60065b | 15 | * |
kadonotakashi | 0:8fdf9a60065b | 16 | * www.apache.org/licenses/LICENSE-2.0 |
kadonotakashi | 0:8fdf9a60065b | 17 | * |
kadonotakashi | 0:8fdf9a60065b | 18 | * Unless required by applicable law or agreed to in writing, software |
kadonotakashi | 0:8fdf9a60065b | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
kadonotakashi | 0:8fdf9a60065b | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
kadonotakashi | 0:8fdf9a60065b | 21 | * See the License for the specific language governing permissions and |
kadonotakashi | 0:8fdf9a60065b | 22 | * limitations under the License. |
kadonotakashi | 0:8fdf9a60065b | 23 | */ |
kadonotakashi | 0:8fdf9a60065b | 24 | |
kadonotakashi | 0:8fdf9a60065b | 25 | #if defined ( __ICCARM__ ) |
kadonotakashi | 0:8fdf9a60065b | 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
kadonotakashi | 0:8fdf9a60065b | 27 | #elif defined (__clang__) |
kadonotakashi | 0:8fdf9a60065b | 28 | #pragma clang system_header /* treat file as system include file */ |
kadonotakashi | 0:8fdf9a60065b | 29 | #endif |
kadonotakashi | 0:8fdf9a60065b | 30 | |
kadonotakashi | 0:8fdf9a60065b | 31 | #ifndef __CORE_SC000_H_GENERIC |
kadonotakashi | 0:8fdf9a60065b | 32 | #define __CORE_SC000_H_GENERIC |
kadonotakashi | 0:8fdf9a60065b | 33 | |
kadonotakashi | 0:8fdf9a60065b | 34 | #include <stdint.h> |
kadonotakashi | 0:8fdf9a60065b | 35 | |
kadonotakashi | 0:8fdf9a60065b | 36 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 37 | extern "C" { |
kadonotakashi | 0:8fdf9a60065b | 38 | #endif |
kadonotakashi | 0:8fdf9a60065b | 39 | |
kadonotakashi | 0:8fdf9a60065b | 40 | /** |
kadonotakashi | 0:8fdf9a60065b | 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
kadonotakashi | 0:8fdf9a60065b | 42 | CMSIS violates the following MISRA-C:2004 rules: |
kadonotakashi | 0:8fdf9a60065b | 43 | |
kadonotakashi | 0:8fdf9a60065b | 44 | \li Required Rule 8.5, object/function definition in header file.<br> |
kadonotakashi | 0:8fdf9a60065b | 45 | Function definitions in header files are used to allow 'inlining'. |
kadonotakashi | 0:8fdf9a60065b | 46 | |
kadonotakashi | 0:8fdf9a60065b | 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
kadonotakashi | 0:8fdf9a60065b | 48 | Unions are used for effective representation of core registers. |
kadonotakashi | 0:8fdf9a60065b | 49 | |
kadonotakashi | 0:8fdf9a60065b | 50 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
kadonotakashi | 0:8fdf9a60065b | 51 | Function-like macros are used to allow more efficient code. |
kadonotakashi | 0:8fdf9a60065b | 52 | */ |
kadonotakashi | 0:8fdf9a60065b | 53 | |
kadonotakashi | 0:8fdf9a60065b | 54 | |
kadonotakashi | 0:8fdf9a60065b | 55 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 56 | * CMSIS definitions |
kadonotakashi | 0:8fdf9a60065b | 57 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 58 | /** |
kadonotakashi | 0:8fdf9a60065b | 59 | \ingroup SC000 |
kadonotakashi | 0:8fdf9a60065b | 60 | @{ |
kadonotakashi | 0:8fdf9a60065b | 61 | */ |
kadonotakashi | 0:8fdf9a60065b | 62 | |
kadonotakashi | 0:8fdf9a60065b | 63 | #include "cmsis_version.h" |
kadonotakashi | 0:8fdf9a60065b | 64 | |
kadonotakashi | 0:8fdf9a60065b | 65 | /* CMSIS SC000 definitions */ |
kadonotakashi | 0:8fdf9a60065b | 66 | #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ |
kadonotakashi | 0:8fdf9a60065b | 67 | #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ |
kadonotakashi | 0:8fdf9a60065b | 68 | #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ |
kadonotakashi | 0:8fdf9a60065b | 69 | __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ |
kadonotakashi | 0:8fdf9a60065b | 70 | |
kadonotakashi | 0:8fdf9a60065b | 71 | #define __CORTEX_SC (000U) /*!< Cortex secure core */ |
kadonotakashi | 0:8fdf9a60065b | 72 | |
kadonotakashi | 0:8fdf9a60065b | 73 | /** __FPU_USED indicates whether an FPU is used or not. |
kadonotakashi | 0:8fdf9a60065b | 74 | This core does not support an FPU at all |
kadonotakashi | 0:8fdf9a60065b | 75 | */ |
kadonotakashi | 0:8fdf9a60065b | 76 | #define __FPU_USED 0U |
kadonotakashi | 0:8fdf9a60065b | 77 | |
kadonotakashi | 0:8fdf9a60065b | 78 | #if defined ( __CC_ARM ) |
kadonotakashi | 0:8fdf9a60065b | 79 | #if defined __TARGET_FPU_VFP |
kadonotakashi | 0:8fdf9a60065b | 80 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 81 | #endif |
kadonotakashi | 0:8fdf9a60065b | 82 | |
kadonotakashi | 0:8fdf9a60065b | 83 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
kadonotakashi | 0:8fdf9a60065b | 84 | #if defined __ARM_PCS_VFP |
kadonotakashi | 0:8fdf9a60065b | 85 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 86 | #endif |
kadonotakashi | 0:8fdf9a60065b | 87 | |
kadonotakashi | 0:8fdf9a60065b | 88 | #elif defined ( __GNUC__ ) |
kadonotakashi | 0:8fdf9a60065b | 89 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
kadonotakashi | 0:8fdf9a60065b | 90 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 91 | #endif |
kadonotakashi | 0:8fdf9a60065b | 92 | |
kadonotakashi | 0:8fdf9a60065b | 93 | #elif defined ( __ICCARM__ ) |
kadonotakashi | 0:8fdf9a60065b | 94 | #if defined __ARMVFP__ |
kadonotakashi | 0:8fdf9a60065b | 95 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 96 | #endif |
kadonotakashi | 0:8fdf9a60065b | 97 | |
kadonotakashi | 0:8fdf9a60065b | 98 | #elif defined ( __TI_ARM__ ) |
kadonotakashi | 0:8fdf9a60065b | 99 | #if defined __TI_VFP_SUPPORT__ |
kadonotakashi | 0:8fdf9a60065b | 100 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 101 | #endif |
kadonotakashi | 0:8fdf9a60065b | 102 | |
kadonotakashi | 0:8fdf9a60065b | 103 | #elif defined ( __TASKING__ ) |
kadonotakashi | 0:8fdf9a60065b | 104 | #if defined __FPU_VFP__ |
kadonotakashi | 0:8fdf9a60065b | 105 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 106 | #endif |
kadonotakashi | 0:8fdf9a60065b | 107 | |
kadonotakashi | 0:8fdf9a60065b | 108 | #elif defined ( __CSMC__ ) |
kadonotakashi | 0:8fdf9a60065b | 109 | #if ( __CSMC__ & 0x400U) |
kadonotakashi | 0:8fdf9a60065b | 110 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kadonotakashi | 0:8fdf9a60065b | 111 | #endif |
kadonotakashi | 0:8fdf9a60065b | 112 | |
kadonotakashi | 0:8fdf9a60065b | 113 | #endif |
kadonotakashi | 0:8fdf9a60065b | 114 | |
kadonotakashi | 0:8fdf9a60065b | 115 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
kadonotakashi | 0:8fdf9a60065b | 116 | |
kadonotakashi | 0:8fdf9a60065b | 117 | |
kadonotakashi | 0:8fdf9a60065b | 118 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 119 | } |
kadonotakashi | 0:8fdf9a60065b | 120 | #endif |
kadonotakashi | 0:8fdf9a60065b | 121 | |
kadonotakashi | 0:8fdf9a60065b | 122 | #endif /* __CORE_SC000_H_GENERIC */ |
kadonotakashi | 0:8fdf9a60065b | 123 | |
kadonotakashi | 0:8fdf9a60065b | 124 | #ifndef __CMSIS_GENERIC |
kadonotakashi | 0:8fdf9a60065b | 125 | |
kadonotakashi | 0:8fdf9a60065b | 126 | #ifndef __CORE_SC000_H_DEPENDANT |
kadonotakashi | 0:8fdf9a60065b | 127 | #define __CORE_SC000_H_DEPENDANT |
kadonotakashi | 0:8fdf9a60065b | 128 | |
kadonotakashi | 0:8fdf9a60065b | 129 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 130 | extern "C" { |
kadonotakashi | 0:8fdf9a60065b | 131 | #endif |
kadonotakashi | 0:8fdf9a60065b | 132 | |
kadonotakashi | 0:8fdf9a60065b | 133 | /* check device defines and use defaults */ |
kadonotakashi | 0:8fdf9a60065b | 134 | #if defined __CHECK_DEVICE_DEFINES |
kadonotakashi | 0:8fdf9a60065b | 135 | #ifndef __SC000_REV |
kadonotakashi | 0:8fdf9a60065b | 136 | #define __SC000_REV 0x0000U |
kadonotakashi | 0:8fdf9a60065b | 137 | #warning "__SC000_REV not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 138 | #endif |
kadonotakashi | 0:8fdf9a60065b | 139 | |
kadonotakashi | 0:8fdf9a60065b | 140 | #ifndef __MPU_PRESENT |
kadonotakashi | 0:8fdf9a60065b | 141 | #define __MPU_PRESENT 0U |
kadonotakashi | 0:8fdf9a60065b | 142 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 143 | #endif |
kadonotakashi | 0:8fdf9a60065b | 144 | |
kadonotakashi | 0:8fdf9a60065b | 145 | #ifndef __NVIC_PRIO_BITS |
kadonotakashi | 0:8fdf9a60065b | 146 | #define __NVIC_PRIO_BITS 2U |
kadonotakashi | 0:8fdf9a60065b | 147 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 148 | #endif |
kadonotakashi | 0:8fdf9a60065b | 149 | |
kadonotakashi | 0:8fdf9a60065b | 150 | #ifndef __Vendor_SysTickConfig |
kadonotakashi | 0:8fdf9a60065b | 151 | #define __Vendor_SysTickConfig 0U |
kadonotakashi | 0:8fdf9a60065b | 152 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
kadonotakashi | 0:8fdf9a60065b | 153 | #endif |
kadonotakashi | 0:8fdf9a60065b | 154 | #endif |
kadonotakashi | 0:8fdf9a60065b | 155 | |
kadonotakashi | 0:8fdf9a60065b | 156 | /* IO definitions (access restrictions to peripheral registers) */ |
kadonotakashi | 0:8fdf9a60065b | 157 | /** |
kadonotakashi | 0:8fdf9a60065b | 158 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
kadonotakashi | 0:8fdf9a60065b | 159 | |
kadonotakashi | 0:8fdf9a60065b | 160 | <strong>IO Type Qualifiers</strong> are used |
kadonotakashi | 0:8fdf9a60065b | 161 | \li to specify the access to peripheral variables. |
kadonotakashi | 0:8fdf9a60065b | 162 | \li for automatic generation of peripheral register debug information. |
kadonotakashi | 0:8fdf9a60065b | 163 | */ |
kadonotakashi | 0:8fdf9a60065b | 164 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 165 | #define __I volatile /*!< Defines 'read only' permissions */ |
kadonotakashi | 0:8fdf9a60065b | 166 | #else |
kadonotakashi | 0:8fdf9a60065b | 167 | #define __I volatile const /*!< Defines 'read only' permissions */ |
kadonotakashi | 0:8fdf9a60065b | 168 | #endif |
kadonotakashi | 0:8fdf9a60065b | 169 | #define __O volatile /*!< Defines 'write only' permissions */ |
kadonotakashi | 0:8fdf9a60065b | 170 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
kadonotakashi | 0:8fdf9a60065b | 171 | |
kadonotakashi | 0:8fdf9a60065b | 172 | /* following defines should be used for structure members */ |
kadonotakashi | 0:8fdf9a60065b | 173 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
kadonotakashi | 0:8fdf9a60065b | 174 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
kadonotakashi | 0:8fdf9a60065b | 175 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
kadonotakashi | 0:8fdf9a60065b | 176 | |
kadonotakashi | 0:8fdf9a60065b | 177 | /*@} end of group SC000 */ |
kadonotakashi | 0:8fdf9a60065b | 178 | |
kadonotakashi | 0:8fdf9a60065b | 179 | |
kadonotakashi | 0:8fdf9a60065b | 180 | |
kadonotakashi | 0:8fdf9a60065b | 181 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 182 | * Register Abstraction |
kadonotakashi | 0:8fdf9a60065b | 183 | Core Register contain: |
kadonotakashi | 0:8fdf9a60065b | 184 | - Core Register |
kadonotakashi | 0:8fdf9a60065b | 185 | - Core NVIC Register |
kadonotakashi | 0:8fdf9a60065b | 186 | - Core SCB Register |
kadonotakashi | 0:8fdf9a60065b | 187 | - Core SysTick Register |
kadonotakashi | 0:8fdf9a60065b | 188 | - Core MPU Register |
kadonotakashi | 0:8fdf9a60065b | 189 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 190 | /** |
kadonotakashi | 0:8fdf9a60065b | 191 | \defgroup CMSIS_core_register Defines and Type Definitions |
kadonotakashi | 0:8fdf9a60065b | 192 | \brief Type definitions and defines for Cortex-M processor based devices. |
kadonotakashi | 0:8fdf9a60065b | 193 | */ |
kadonotakashi | 0:8fdf9a60065b | 194 | |
kadonotakashi | 0:8fdf9a60065b | 195 | /** |
kadonotakashi | 0:8fdf9a60065b | 196 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 197 | \defgroup CMSIS_CORE Status and Control Registers |
kadonotakashi | 0:8fdf9a60065b | 198 | \brief Core Register type definitions. |
kadonotakashi | 0:8fdf9a60065b | 199 | @{ |
kadonotakashi | 0:8fdf9a60065b | 200 | */ |
kadonotakashi | 0:8fdf9a60065b | 201 | |
kadonotakashi | 0:8fdf9a60065b | 202 | /** |
kadonotakashi | 0:8fdf9a60065b | 203 | \brief Union type to access the Application Program Status Register (APSR). |
kadonotakashi | 0:8fdf9a60065b | 204 | */ |
kadonotakashi | 0:8fdf9a60065b | 205 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 206 | { |
kadonotakashi | 0:8fdf9a60065b | 207 | struct |
kadonotakashi | 0:8fdf9a60065b | 208 | { |
kadonotakashi | 0:8fdf9a60065b | 209 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
kadonotakashi | 0:8fdf9a60065b | 210 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 211 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 212 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 213 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 214 | } b; /*!< Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 215 | uint32_t w; /*!< Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 216 | } APSR_Type; |
kadonotakashi | 0:8fdf9a60065b | 217 | |
kadonotakashi | 0:8fdf9a60065b | 218 | /* APSR Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 219 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
kadonotakashi | 0:8fdf9a60065b | 220 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
kadonotakashi | 0:8fdf9a60065b | 221 | |
kadonotakashi | 0:8fdf9a60065b | 222 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
kadonotakashi | 0:8fdf9a60065b | 223 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
kadonotakashi | 0:8fdf9a60065b | 224 | |
kadonotakashi | 0:8fdf9a60065b | 225 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
kadonotakashi | 0:8fdf9a60065b | 226 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
kadonotakashi | 0:8fdf9a60065b | 227 | |
kadonotakashi | 0:8fdf9a60065b | 228 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
kadonotakashi | 0:8fdf9a60065b | 229 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
kadonotakashi | 0:8fdf9a60065b | 230 | |
kadonotakashi | 0:8fdf9a60065b | 231 | |
kadonotakashi | 0:8fdf9a60065b | 232 | /** |
kadonotakashi | 0:8fdf9a60065b | 233 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
kadonotakashi | 0:8fdf9a60065b | 234 | */ |
kadonotakashi | 0:8fdf9a60065b | 235 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 236 | { |
kadonotakashi | 0:8fdf9a60065b | 237 | struct |
kadonotakashi | 0:8fdf9a60065b | 238 | { |
kadonotakashi | 0:8fdf9a60065b | 239 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
kadonotakashi | 0:8fdf9a60065b | 240 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
kadonotakashi | 0:8fdf9a60065b | 241 | } b; /*!< Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 242 | uint32_t w; /*!< Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 243 | } IPSR_Type; |
kadonotakashi | 0:8fdf9a60065b | 244 | |
kadonotakashi | 0:8fdf9a60065b | 245 | /* IPSR Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 246 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
kadonotakashi | 0:8fdf9a60065b | 247 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 248 | |
kadonotakashi | 0:8fdf9a60065b | 249 | |
kadonotakashi | 0:8fdf9a60065b | 250 | /** |
kadonotakashi | 0:8fdf9a60065b | 251 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
kadonotakashi | 0:8fdf9a60065b | 252 | */ |
kadonotakashi | 0:8fdf9a60065b | 253 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 254 | { |
kadonotakashi | 0:8fdf9a60065b | 255 | struct |
kadonotakashi | 0:8fdf9a60065b | 256 | { |
kadonotakashi | 0:8fdf9a60065b | 257 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
kadonotakashi | 0:8fdf9a60065b | 258 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
kadonotakashi | 0:8fdf9a60065b | 259 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
kadonotakashi | 0:8fdf9a60065b | 260 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
kadonotakashi | 0:8fdf9a60065b | 261 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 262 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 263 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 264 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
kadonotakashi | 0:8fdf9a60065b | 265 | } b; /*!< Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 266 | uint32_t w; /*!< Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 267 | } xPSR_Type; |
kadonotakashi | 0:8fdf9a60065b | 268 | |
kadonotakashi | 0:8fdf9a60065b | 269 | /* xPSR Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 270 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
kadonotakashi | 0:8fdf9a60065b | 271 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
kadonotakashi | 0:8fdf9a60065b | 272 | |
kadonotakashi | 0:8fdf9a60065b | 273 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
kadonotakashi | 0:8fdf9a60065b | 274 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
kadonotakashi | 0:8fdf9a60065b | 275 | |
kadonotakashi | 0:8fdf9a60065b | 276 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
kadonotakashi | 0:8fdf9a60065b | 277 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
kadonotakashi | 0:8fdf9a60065b | 278 | |
kadonotakashi | 0:8fdf9a60065b | 279 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
kadonotakashi | 0:8fdf9a60065b | 280 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
kadonotakashi | 0:8fdf9a60065b | 281 | |
kadonotakashi | 0:8fdf9a60065b | 282 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
kadonotakashi | 0:8fdf9a60065b | 283 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
kadonotakashi | 0:8fdf9a60065b | 284 | |
kadonotakashi | 0:8fdf9a60065b | 285 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
kadonotakashi | 0:8fdf9a60065b | 286 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 287 | |
kadonotakashi | 0:8fdf9a60065b | 288 | |
kadonotakashi | 0:8fdf9a60065b | 289 | /** |
kadonotakashi | 0:8fdf9a60065b | 290 | \brief Union type to access the Control Registers (CONTROL). |
kadonotakashi | 0:8fdf9a60065b | 291 | */ |
kadonotakashi | 0:8fdf9a60065b | 292 | typedef union |
kadonotakashi | 0:8fdf9a60065b | 293 | { |
kadonotakashi | 0:8fdf9a60065b | 294 | struct |
kadonotakashi | 0:8fdf9a60065b | 295 | { |
kadonotakashi | 0:8fdf9a60065b | 296 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
kadonotakashi | 0:8fdf9a60065b | 297 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
kadonotakashi | 0:8fdf9a60065b | 298 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
kadonotakashi | 0:8fdf9a60065b | 299 | } b; /*!< Structure used for bit access */ |
kadonotakashi | 0:8fdf9a60065b | 300 | uint32_t w; /*!< Type used for word access */ |
kadonotakashi | 0:8fdf9a60065b | 301 | } CONTROL_Type; |
kadonotakashi | 0:8fdf9a60065b | 302 | |
kadonotakashi | 0:8fdf9a60065b | 303 | /* CONTROL Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 304 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
kadonotakashi | 0:8fdf9a60065b | 305 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
kadonotakashi | 0:8fdf9a60065b | 306 | |
kadonotakashi | 0:8fdf9a60065b | 307 | /*@} end of group CMSIS_CORE */ |
kadonotakashi | 0:8fdf9a60065b | 308 | |
kadonotakashi | 0:8fdf9a60065b | 309 | |
kadonotakashi | 0:8fdf9a60065b | 310 | /** |
kadonotakashi | 0:8fdf9a60065b | 311 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 312 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
kadonotakashi | 0:8fdf9a60065b | 313 | \brief Type definitions for the NVIC Registers |
kadonotakashi | 0:8fdf9a60065b | 314 | @{ |
kadonotakashi | 0:8fdf9a60065b | 315 | */ |
kadonotakashi | 0:8fdf9a60065b | 316 | |
kadonotakashi | 0:8fdf9a60065b | 317 | /** |
kadonotakashi | 0:8fdf9a60065b | 318 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
kadonotakashi | 0:8fdf9a60065b | 319 | */ |
kadonotakashi | 0:8fdf9a60065b | 320 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 321 | { |
kadonotakashi | 0:8fdf9a60065b | 322 | __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 323 | uint32_t RESERVED0[31U]; |
kadonotakashi | 0:8fdf9a60065b | 324 | __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
kadonotakashi | 0:8fdf9a60065b | 325 | uint32_t RSERVED1[31U]; |
kadonotakashi | 0:8fdf9a60065b | 326 | __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
kadonotakashi | 0:8fdf9a60065b | 327 | uint32_t RESERVED2[31U]; |
kadonotakashi | 0:8fdf9a60065b | 328 | __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
kadonotakashi | 0:8fdf9a60065b | 329 | uint32_t RESERVED3[31U]; |
kadonotakashi | 0:8fdf9a60065b | 330 | uint32_t RESERVED4[64U]; |
kadonotakashi | 0:8fdf9a60065b | 331 | __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
kadonotakashi | 0:8fdf9a60065b | 332 | } NVIC_Type; |
kadonotakashi | 0:8fdf9a60065b | 333 | |
kadonotakashi | 0:8fdf9a60065b | 334 | /*@} end of group CMSIS_NVIC */ |
kadonotakashi | 0:8fdf9a60065b | 335 | |
kadonotakashi | 0:8fdf9a60065b | 336 | |
kadonotakashi | 0:8fdf9a60065b | 337 | /** |
kadonotakashi | 0:8fdf9a60065b | 338 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 339 | \defgroup CMSIS_SCB System Control Block (SCB) |
kadonotakashi | 0:8fdf9a60065b | 340 | \brief Type definitions for the System Control Block Registers |
kadonotakashi | 0:8fdf9a60065b | 341 | @{ |
kadonotakashi | 0:8fdf9a60065b | 342 | */ |
kadonotakashi | 0:8fdf9a60065b | 343 | |
kadonotakashi | 0:8fdf9a60065b | 344 | /** |
kadonotakashi | 0:8fdf9a60065b | 345 | \brief Structure type to access the System Control Block (SCB). |
kadonotakashi | 0:8fdf9a60065b | 346 | */ |
kadonotakashi | 0:8fdf9a60065b | 347 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 348 | { |
kadonotakashi | 0:8fdf9a60065b | 349 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
kadonotakashi | 0:8fdf9a60065b | 350 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
kadonotakashi | 0:8fdf9a60065b | 351 | __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
kadonotakashi | 0:8fdf9a60065b | 352 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 353 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 354 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 355 | uint32_t RESERVED0[1U]; |
kadonotakashi | 0:8fdf9a60065b | 356 | __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
kadonotakashi | 0:8fdf9a60065b | 357 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
kadonotakashi | 0:8fdf9a60065b | 358 | uint32_t RESERVED1[154U]; |
kadonotakashi | 0:8fdf9a60065b | 359 | __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 360 | } SCB_Type; |
kadonotakashi | 0:8fdf9a60065b | 361 | |
kadonotakashi | 0:8fdf9a60065b | 362 | /* SCB CPUID Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 363 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
kadonotakashi | 0:8fdf9a60065b | 364 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
kadonotakashi | 0:8fdf9a60065b | 365 | |
kadonotakashi | 0:8fdf9a60065b | 366 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
kadonotakashi | 0:8fdf9a60065b | 367 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 368 | |
kadonotakashi | 0:8fdf9a60065b | 369 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
kadonotakashi | 0:8fdf9a60065b | 370 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 371 | |
kadonotakashi | 0:8fdf9a60065b | 372 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
kadonotakashi | 0:8fdf9a60065b | 373 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
kadonotakashi | 0:8fdf9a60065b | 374 | |
kadonotakashi | 0:8fdf9a60065b | 375 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
kadonotakashi | 0:8fdf9a60065b | 376 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
kadonotakashi | 0:8fdf9a60065b | 377 | |
kadonotakashi | 0:8fdf9a60065b | 378 | /* SCB Interrupt Control State Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 379 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
kadonotakashi | 0:8fdf9a60065b | 380 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
kadonotakashi | 0:8fdf9a60065b | 381 | |
kadonotakashi | 0:8fdf9a60065b | 382 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
kadonotakashi | 0:8fdf9a60065b | 383 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
kadonotakashi | 0:8fdf9a60065b | 384 | |
kadonotakashi | 0:8fdf9a60065b | 385 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
kadonotakashi | 0:8fdf9a60065b | 386 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 387 | |
kadonotakashi | 0:8fdf9a60065b | 388 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
kadonotakashi | 0:8fdf9a60065b | 389 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
kadonotakashi | 0:8fdf9a60065b | 390 | |
kadonotakashi | 0:8fdf9a60065b | 391 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
kadonotakashi | 0:8fdf9a60065b | 392 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 393 | |
kadonotakashi | 0:8fdf9a60065b | 394 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
kadonotakashi | 0:8fdf9a60065b | 395 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 396 | |
kadonotakashi | 0:8fdf9a60065b | 397 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
kadonotakashi | 0:8fdf9a60065b | 398 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
kadonotakashi | 0:8fdf9a60065b | 399 | |
kadonotakashi | 0:8fdf9a60065b | 400 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
kadonotakashi | 0:8fdf9a60065b | 401 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
kadonotakashi | 0:8fdf9a60065b | 402 | |
kadonotakashi | 0:8fdf9a60065b | 403 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
kadonotakashi | 0:8fdf9a60065b | 404 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 405 | |
kadonotakashi | 0:8fdf9a60065b | 406 | /* SCB Interrupt Control State Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 407 | #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
kadonotakashi | 0:8fdf9a60065b | 408 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 409 | |
kadonotakashi | 0:8fdf9a60065b | 410 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 411 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
kadonotakashi | 0:8fdf9a60065b | 412 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
kadonotakashi | 0:8fdf9a60065b | 413 | |
kadonotakashi | 0:8fdf9a60065b | 414 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
kadonotakashi | 0:8fdf9a60065b | 415 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 416 | |
kadonotakashi | 0:8fdf9a60065b | 417 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
kadonotakashi | 0:8fdf9a60065b | 418 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 419 | |
kadonotakashi | 0:8fdf9a60065b | 420 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
kadonotakashi | 0:8fdf9a60065b | 421 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
kadonotakashi | 0:8fdf9a60065b | 422 | |
kadonotakashi | 0:8fdf9a60065b | 423 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
kadonotakashi | 0:8fdf9a60065b | 424 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 425 | |
kadonotakashi | 0:8fdf9a60065b | 426 | /* SCB System Control Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 427 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
kadonotakashi | 0:8fdf9a60065b | 428 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
kadonotakashi | 0:8fdf9a60065b | 429 | |
kadonotakashi | 0:8fdf9a60065b | 430 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
kadonotakashi | 0:8fdf9a60065b | 431 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 432 | |
kadonotakashi | 0:8fdf9a60065b | 433 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
kadonotakashi | 0:8fdf9a60065b | 434 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 435 | |
kadonotakashi | 0:8fdf9a60065b | 436 | /* SCB Configuration Control Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 437 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
kadonotakashi | 0:8fdf9a60065b | 438 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 439 | |
kadonotakashi | 0:8fdf9a60065b | 440 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
kadonotakashi | 0:8fdf9a60065b | 441 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 442 | |
kadonotakashi | 0:8fdf9a60065b | 443 | /* SCB System Handler Control and State Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 444 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
kadonotakashi | 0:8fdf9a60065b | 445 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
kadonotakashi | 0:8fdf9a60065b | 446 | |
kadonotakashi | 0:8fdf9a60065b | 447 | /*@} end of group CMSIS_SCB */ |
kadonotakashi | 0:8fdf9a60065b | 448 | |
kadonotakashi | 0:8fdf9a60065b | 449 | |
kadonotakashi | 0:8fdf9a60065b | 450 | /** |
kadonotakashi | 0:8fdf9a60065b | 451 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 452 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
kadonotakashi | 0:8fdf9a60065b | 453 | \brief Type definitions for the System Control and ID Register not in the SCB |
kadonotakashi | 0:8fdf9a60065b | 454 | @{ |
kadonotakashi | 0:8fdf9a60065b | 455 | */ |
kadonotakashi | 0:8fdf9a60065b | 456 | |
kadonotakashi | 0:8fdf9a60065b | 457 | /** |
kadonotakashi | 0:8fdf9a60065b | 458 | \brief Structure type to access the System Control and ID Register not in the SCB. |
kadonotakashi | 0:8fdf9a60065b | 459 | */ |
kadonotakashi | 0:8fdf9a60065b | 460 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 461 | { |
kadonotakashi | 0:8fdf9a60065b | 462 | uint32_t RESERVED0[2U]; |
kadonotakashi | 0:8fdf9a60065b | 463 | __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 464 | } SCnSCB_Type; |
kadonotakashi | 0:8fdf9a60065b | 465 | |
kadonotakashi | 0:8fdf9a60065b | 466 | /* Auxiliary Control Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 467 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ |
kadonotakashi | 0:8fdf9a60065b | 468 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 469 | |
kadonotakashi | 0:8fdf9a60065b | 470 | /*@} end of group CMSIS_SCnotSCB */ |
kadonotakashi | 0:8fdf9a60065b | 471 | |
kadonotakashi | 0:8fdf9a60065b | 472 | |
kadonotakashi | 0:8fdf9a60065b | 473 | /** |
kadonotakashi | 0:8fdf9a60065b | 474 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 475 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
kadonotakashi | 0:8fdf9a60065b | 476 | \brief Type definitions for the System Timer Registers. |
kadonotakashi | 0:8fdf9a60065b | 477 | @{ |
kadonotakashi | 0:8fdf9a60065b | 478 | */ |
kadonotakashi | 0:8fdf9a60065b | 479 | |
kadonotakashi | 0:8fdf9a60065b | 480 | /** |
kadonotakashi | 0:8fdf9a60065b | 481 | \brief Structure type to access the System Timer (SysTick). |
kadonotakashi | 0:8fdf9a60065b | 482 | */ |
kadonotakashi | 0:8fdf9a60065b | 483 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 484 | { |
kadonotakashi | 0:8fdf9a60065b | 485 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
kadonotakashi | 0:8fdf9a60065b | 486 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
kadonotakashi | 0:8fdf9a60065b | 487 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
kadonotakashi | 0:8fdf9a60065b | 488 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
kadonotakashi | 0:8fdf9a60065b | 489 | } SysTick_Type; |
kadonotakashi | 0:8fdf9a60065b | 490 | |
kadonotakashi | 0:8fdf9a60065b | 491 | /* SysTick Control / Status Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 492 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
kadonotakashi | 0:8fdf9a60065b | 493 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
kadonotakashi | 0:8fdf9a60065b | 494 | |
kadonotakashi | 0:8fdf9a60065b | 495 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
kadonotakashi | 0:8fdf9a60065b | 496 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 497 | |
kadonotakashi | 0:8fdf9a60065b | 498 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
kadonotakashi | 0:8fdf9a60065b | 499 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 500 | |
kadonotakashi | 0:8fdf9a60065b | 501 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
kadonotakashi | 0:8fdf9a60065b | 502 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 503 | |
kadonotakashi | 0:8fdf9a60065b | 504 | /* SysTick Reload Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 505 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
kadonotakashi | 0:8fdf9a60065b | 506 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
kadonotakashi | 0:8fdf9a60065b | 507 | |
kadonotakashi | 0:8fdf9a60065b | 508 | /* SysTick Current Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 509 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
kadonotakashi | 0:8fdf9a60065b | 510 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
kadonotakashi | 0:8fdf9a60065b | 511 | |
kadonotakashi | 0:8fdf9a60065b | 512 | /* SysTick Calibration Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 513 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
kadonotakashi | 0:8fdf9a60065b | 514 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
kadonotakashi | 0:8fdf9a60065b | 515 | |
kadonotakashi | 0:8fdf9a60065b | 516 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
kadonotakashi | 0:8fdf9a60065b | 517 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
kadonotakashi | 0:8fdf9a60065b | 518 | |
kadonotakashi | 0:8fdf9a60065b | 519 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
kadonotakashi | 0:8fdf9a60065b | 520 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
kadonotakashi | 0:8fdf9a60065b | 521 | |
kadonotakashi | 0:8fdf9a60065b | 522 | /*@} end of group CMSIS_SysTick */ |
kadonotakashi | 0:8fdf9a60065b | 523 | |
kadonotakashi | 0:8fdf9a60065b | 524 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
kadonotakashi | 0:8fdf9a60065b | 525 | /** |
kadonotakashi | 0:8fdf9a60065b | 526 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 527 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
kadonotakashi | 0:8fdf9a60065b | 528 | \brief Type definitions for the Memory Protection Unit (MPU) |
kadonotakashi | 0:8fdf9a60065b | 529 | @{ |
kadonotakashi | 0:8fdf9a60065b | 530 | */ |
kadonotakashi | 0:8fdf9a60065b | 531 | |
kadonotakashi | 0:8fdf9a60065b | 532 | /** |
kadonotakashi | 0:8fdf9a60065b | 533 | \brief Structure type to access the Memory Protection Unit (MPU). |
kadonotakashi | 0:8fdf9a60065b | 534 | */ |
kadonotakashi | 0:8fdf9a60065b | 535 | typedef struct |
kadonotakashi | 0:8fdf9a60065b | 536 | { |
kadonotakashi | 0:8fdf9a60065b | 537 | __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
kadonotakashi | 0:8fdf9a60065b | 538 | __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
kadonotakashi | 0:8fdf9a60065b | 539 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
kadonotakashi | 0:8fdf9a60065b | 540 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
kadonotakashi | 0:8fdf9a60065b | 541 | __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
kadonotakashi | 0:8fdf9a60065b | 542 | } MPU_Type; |
kadonotakashi | 0:8fdf9a60065b | 543 | |
kadonotakashi | 0:8fdf9a60065b | 544 | /* MPU Type Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 545 | #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
kadonotakashi | 0:8fdf9a60065b | 546 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
kadonotakashi | 0:8fdf9a60065b | 547 | |
kadonotakashi | 0:8fdf9a60065b | 548 | #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
kadonotakashi | 0:8fdf9a60065b | 549 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
kadonotakashi | 0:8fdf9a60065b | 550 | |
kadonotakashi | 0:8fdf9a60065b | 551 | #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
kadonotakashi | 0:8fdf9a60065b | 552 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 553 | |
kadonotakashi | 0:8fdf9a60065b | 554 | /* MPU Control Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 555 | #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
kadonotakashi | 0:8fdf9a60065b | 556 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
kadonotakashi | 0:8fdf9a60065b | 557 | |
kadonotakashi | 0:8fdf9a60065b | 558 | #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
kadonotakashi | 0:8fdf9a60065b | 559 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
kadonotakashi | 0:8fdf9a60065b | 560 | |
kadonotakashi | 0:8fdf9a60065b | 561 | #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
kadonotakashi | 0:8fdf9a60065b | 562 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
kadonotakashi | 0:8fdf9a60065b | 563 | |
kadonotakashi | 0:8fdf9a60065b | 564 | /* MPU Region Number Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 565 | #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
kadonotakashi | 0:8fdf9a60065b | 566 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
kadonotakashi | 0:8fdf9a60065b | 567 | |
kadonotakashi | 0:8fdf9a60065b | 568 | /* MPU Region Base Address Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 569 | #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
kadonotakashi | 0:8fdf9a60065b | 570 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
kadonotakashi | 0:8fdf9a60065b | 571 | |
kadonotakashi | 0:8fdf9a60065b | 572 | #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
kadonotakashi | 0:8fdf9a60065b | 573 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
kadonotakashi | 0:8fdf9a60065b | 574 | |
kadonotakashi | 0:8fdf9a60065b | 575 | #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
kadonotakashi | 0:8fdf9a60065b | 576 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
kadonotakashi | 0:8fdf9a60065b | 577 | |
kadonotakashi | 0:8fdf9a60065b | 578 | /* MPU Region Attribute and Size Register Definitions */ |
kadonotakashi | 0:8fdf9a60065b | 579 | #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
kadonotakashi | 0:8fdf9a60065b | 580 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
kadonotakashi | 0:8fdf9a60065b | 581 | |
kadonotakashi | 0:8fdf9a60065b | 582 | #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
kadonotakashi | 0:8fdf9a60065b | 583 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
kadonotakashi | 0:8fdf9a60065b | 584 | |
kadonotakashi | 0:8fdf9a60065b | 585 | #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
kadonotakashi | 0:8fdf9a60065b | 586 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
kadonotakashi | 0:8fdf9a60065b | 587 | |
kadonotakashi | 0:8fdf9a60065b | 588 | #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
kadonotakashi | 0:8fdf9a60065b | 589 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
kadonotakashi | 0:8fdf9a60065b | 590 | |
kadonotakashi | 0:8fdf9a60065b | 591 | #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
kadonotakashi | 0:8fdf9a60065b | 592 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
kadonotakashi | 0:8fdf9a60065b | 593 | |
kadonotakashi | 0:8fdf9a60065b | 594 | #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
kadonotakashi | 0:8fdf9a60065b | 595 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
kadonotakashi | 0:8fdf9a60065b | 596 | |
kadonotakashi | 0:8fdf9a60065b | 597 | #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
kadonotakashi | 0:8fdf9a60065b | 598 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
kadonotakashi | 0:8fdf9a60065b | 599 | |
kadonotakashi | 0:8fdf9a60065b | 600 | #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
kadonotakashi | 0:8fdf9a60065b | 601 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
kadonotakashi | 0:8fdf9a60065b | 602 | |
kadonotakashi | 0:8fdf9a60065b | 603 | #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
kadonotakashi | 0:8fdf9a60065b | 604 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
kadonotakashi | 0:8fdf9a60065b | 605 | |
kadonotakashi | 0:8fdf9a60065b | 606 | #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
kadonotakashi | 0:8fdf9a60065b | 607 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
kadonotakashi | 0:8fdf9a60065b | 608 | |
kadonotakashi | 0:8fdf9a60065b | 609 | /*@} end of group CMSIS_MPU */ |
kadonotakashi | 0:8fdf9a60065b | 610 | #endif |
kadonotakashi | 0:8fdf9a60065b | 611 | |
kadonotakashi | 0:8fdf9a60065b | 612 | |
kadonotakashi | 0:8fdf9a60065b | 613 | /** |
kadonotakashi | 0:8fdf9a60065b | 614 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 615 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
kadonotakashi | 0:8fdf9a60065b | 616 | \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
kadonotakashi | 0:8fdf9a60065b | 617 | Therefore they are not covered by the SC000 header file. |
kadonotakashi | 0:8fdf9a60065b | 618 | @{ |
kadonotakashi | 0:8fdf9a60065b | 619 | */ |
kadonotakashi | 0:8fdf9a60065b | 620 | /*@} end of group CMSIS_CoreDebug */ |
kadonotakashi | 0:8fdf9a60065b | 621 | |
kadonotakashi | 0:8fdf9a60065b | 622 | |
kadonotakashi | 0:8fdf9a60065b | 623 | /** |
kadonotakashi | 0:8fdf9a60065b | 624 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 625 | \defgroup CMSIS_core_bitfield Core register bit field macros |
kadonotakashi | 0:8fdf9a60065b | 626 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
kadonotakashi | 0:8fdf9a60065b | 627 | @{ |
kadonotakashi | 0:8fdf9a60065b | 628 | */ |
kadonotakashi | 0:8fdf9a60065b | 629 | |
kadonotakashi | 0:8fdf9a60065b | 630 | /** |
kadonotakashi | 0:8fdf9a60065b | 631 | \brief Mask and shift a bit field value for use in a register bit range. |
kadonotakashi | 0:8fdf9a60065b | 632 | \param[in] field Name of the register bit field. |
kadonotakashi | 0:8fdf9a60065b | 633 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
kadonotakashi | 0:8fdf9a60065b | 634 | \return Masked and shifted value. |
kadonotakashi | 0:8fdf9a60065b | 635 | */ |
kadonotakashi | 0:8fdf9a60065b | 636 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
kadonotakashi | 0:8fdf9a60065b | 637 | |
kadonotakashi | 0:8fdf9a60065b | 638 | /** |
kadonotakashi | 0:8fdf9a60065b | 639 | \brief Mask and shift a register value to extract a bit filed value. |
kadonotakashi | 0:8fdf9a60065b | 640 | \param[in] field Name of the register bit field. |
kadonotakashi | 0:8fdf9a60065b | 641 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
kadonotakashi | 0:8fdf9a60065b | 642 | \return Masked and shifted bit field value. |
kadonotakashi | 0:8fdf9a60065b | 643 | */ |
kadonotakashi | 0:8fdf9a60065b | 644 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
kadonotakashi | 0:8fdf9a60065b | 645 | |
kadonotakashi | 0:8fdf9a60065b | 646 | /*@} end of group CMSIS_core_bitfield */ |
kadonotakashi | 0:8fdf9a60065b | 647 | |
kadonotakashi | 0:8fdf9a60065b | 648 | |
kadonotakashi | 0:8fdf9a60065b | 649 | /** |
kadonotakashi | 0:8fdf9a60065b | 650 | \ingroup CMSIS_core_register |
kadonotakashi | 0:8fdf9a60065b | 651 | \defgroup CMSIS_core_base Core Definitions |
kadonotakashi | 0:8fdf9a60065b | 652 | \brief Definitions for base addresses, unions, and structures. |
kadonotakashi | 0:8fdf9a60065b | 653 | @{ |
kadonotakashi | 0:8fdf9a60065b | 654 | */ |
kadonotakashi | 0:8fdf9a60065b | 655 | |
kadonotakashi | 0:8fdf9a60065b | 656 | /* Memory mapping of Core Hardware */ |
kadonotakashi | 0:8fdf9a60065b | 657 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
kadonotakashi | 0:8fdf9a60065b | 658 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
kadonotakashi | 0:8fdf9a60065b | 659 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
kadonotakashi | 0:8fdf9a60065b | 660 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
kadonotakashi | 0:8fdf9a60065b | 661 | |
kadonotakashi | 0:8fdf9a60065b | 662 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
kadonotakashi | 0:8fdf9a60065b | 663 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
kadonotakashi | 0:8fdf9a60065b | 664 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
kadonotakashi | 0:8fdf9a60065b | 665 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
kadonotakashi | 0:8fdf9a60065b | 666 | |
kadonotakashi | 0:8fdf9a60065b | 667 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
kadonotakashi | 0:8fdf9a60065b | 668 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
kadonotakashi | 0:8fdf9a60065b | 669 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
kadonotakashi | 0:8fdf9a60065b | 670 | #endif |
kadonotakashi | 0:8fdf9a60065b | 671 | |
kadonotakashi | 0:8fdf9a60065b | 672 | /*@} */ |
kadonotakashi | 0:8fdf9a60065b | 673 | |
kadonotakashi | 0:8fdf9a60065b | 674 | |
kadonotakashi | 0:8fdf9a60065b | 675 | |
kadonotakashi | 0:8fdf9a60065b | 676 | /******************************************************************************* |
kadonotakashi | 0:8fdf9a60065b | 677 | * Hardware Abstraction Layer |
kadonotakashi | 0:8fdf9a60065b | 678 | Core Function Interface contains: |
kadonotakashi | 0:8fdf9a60065b | 679 | - Core NVIC Functions |
kadonotakashi | 0:8fdf9a60065b | 680 | - Core SysTick Functions |
kadonotakashi | 0:8fdf9a60065b | 681 | - Core Register Access Functions |
kadonotakashi | 0:8fdf9a60065b | 682 | ******************************************************************************/ |
kadonotakashi | 0:8fdf9a60065b | 683 | /** |
kadonotakashi | 0:8fdf9a60065b | 684 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
kadonotakashi | 0:8fdf9a60065b | 685 | */ |
kadonotakashi | 0:8fdf9a60065b | 686 | |
kadonotakashi | 0:8fdf9a60065b | 687 | |
kadonotakashi | 0:8fdf9a60065b | 688 | |
kadonotakashi | 0:8fdf9a60065b | 689 | /* ########################## NVIC functions #################################### */ |
kadonotakashi | 0:8fdf9a60065b | 690 | /** |
kadonotakashi | 0:8fdf9a60065b | 691 | \ingroup CMSIS_Core_FunctionInterface |
kadonotakashi | 0:8fdf9a60065b | 692 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
kadonotakashi | 0:8fdf9a60065b | 693 | \brief Functions that manage interrupts and exceptions via the NVIC. |
kadonotakashi | 0:8fdf9a60065b | 694 | @{ |
kadonotakashi | 0:8fdf9a60065b | 695 | */ |
kadonotakashi | 0:8fdf9a60065b | 696 | |
kadonotakashi | 0:8fdf9a60065b | 697 | #ifdef CMSIS_NVIC_VIRTUAL |
kadonotakashi | 0:8fdf9a60065b | 698 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
kadonotakashi | 0:8fdf9a60065b | 699 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
kadonotakashi | 0:8fdf9a60065b | 700 | #endif |
kadonotakashi | 0:8fdf9a60065b | 701 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
kadonotakashi | 0:8fdf9a60065b | 702 | #else |
kadonotakashi | 0:8fdf9a60065b | 703 | /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ |
kadonotakashi | 0:8fdf9a60065b | 704 | /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ |
kadonotakashi | 0:8fdf9a60065b | 705 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
kadonotakashi | 0:8fdf9a60065b | 706 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
kadonotakashi | 0:8fdf9a60065b | 707 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
kadonotakashi | 0:8fdf9a60065b | 708 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
kadonotakashi | 0:8fdf9a60065b | 709 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
kadonotakashi | 0:8fdf9a60065b | 710 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
kadonotakashi | 0:8fdf9a60065b | 711 | /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ |
kadonotakashi | 0:8fdf9a60065b | 712 | #define NVIC_SetPriority __NVIC_SetPriority |
kadonotakashi | 0:8fdf9a60065b | 713 | #define NVIC_GetPriority __NVIC_GetPriority |
kadonotakashi | 0:8fdf9a60065b | 714 | #define NVIC_SystemReset __NVIC_SystemReset |
kadonotakashi | 0:8fdf9a60065b | 715 | #endif /* CMSIS_NVIC_VIRTUAL */ |
kadonotakashi | 0:8fdf9a60065b | 716 | |
kadonotakashi | 0:8fdf9a60065b | 717 | #ifdef CMSIS_VECTAB_VIRTUAL |
kadonotakashi | 0:8fdf9a60065b | 718 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
kadonotakashi | 0:8fdf9a60065b | 719 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
kadonotakashi | 0:8fdf9a60065b | 720 | #endif |
kadonotakashi | 0:8fdf9a60065b | 721 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
kadonotakashi | 0:8fdf9a60065b | 722 | #else |
kadonotakashi | 0:8fdf9a60065b | 723 | #define NVIC_SetVector __NVIC_SetVector |
kadonotakashi | 0:8fdf9a60065b | 724 | #define NVIC_GetVector __NVIC_GetVector |
kadonotakashi | 0:8fdf9a60065b | 725 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
kadonotakashi | 0:8fdf9a60065b | 726 | |
kadonotakashi | 0:8fdf9a60065b | 727 | #define NVIC_USER_IRQ_OFFSET 16 |
kadonotakashi | 0:8fdf9a60065b | 728 | |
kadonotakashi | 0:8fdf9a60065b | 729 | |
kadonotakashi | 0:8fdf9a60065b | 730 | /* The following EXC_RETURN values are saved the LR on exception entry */ |
kadonotakashi | 0:8fdf9a60065b | 731 | #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ |
kadonotakashi | 0:8fdf9a60065b | 732 | #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ |
kadonotakashi | 0:8fdf9a60065b | 733 | #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ |
kadonotakashi | 0:8fdf9a60065b | 734 | |
kadonotakashi | 0:8fdf9a60065b | 735 | |
kadonotakashi | 0:8fdf9a60065b | 736 | /* Interrupt Priorities are WORD accessible only under Armv6-M */ |
kadonotakashi | 0:8fdf9a60065b | 737 | /* The following MACROS handle generation of the register offset and byte masks */ |
kadonotakashi | 0:8fdf9a60065b | 738 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
kadonotakashi | 0:8fdf9a60065b | 739 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
kadonotakashi | 0:8fdf9a60065b | 740 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
kadonotakashi | 0:8fdf9a60065b | 741 | |
kadonotakashi | 0:8fdf9a60065b | 742 | |
kadonotakashi | 0:8fdf9a60065b | 743 | /** |
kadonotakashi | 0:8fdf9a60065b | 744 | \brief Enable Interrupt |
kadonotakashi | 0:8fdf9a60065b | 745 | \details Enables a device specific interrupt in the NVIC interrupt controller. |
kadonotakashi | 0:8fdf9a60065b | 746 | \param [in] IRQn Device specific interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 747 | \note IRQn must not be negative. |
kadonotakashi | 0:8fdf9a60065b | 748 | */ |
kadonotakashi | 0:8fdf9a60065b | 749 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 750 | { |
kadonotakashi | 0:8fdf9a60065b | 751 | if ((int32_t)(IRQn) >= 0) |
kadonotakashi | 0:8fdf9a60065b | 752 | { |
kadonotakashi | 0:8fdf9a60065b | 753 | NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kadonotakashi | 0:8fdf9a60065b | 754 | } |
kadonotakashi | 0:8fdf9a60065b | 755 | } |
kadonotakashi | 0:8fdf9a60065b | 756 | |
kadonotakashi | 0:8fdf9a60065b | 757 | |
kadonotakashi | 0:8fdf9a60065b | 758 | /** |
kadonotakashi | 0:8fdf9a60065b | 759 | \brief Get Interrupt Enable status |
kadonotakashi | 0:8fdf9a60065b | 760 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
kadonotakashi | 0:8fdf9a60065b | 761 | \param [in] IRQn Device specific interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 762 | \return 0 Interrupt is not enabled. |
kadonotakashi | 0:8fdf9a60065b | 763 | \return 1 Interrupt is enabled. |
kadonotakashi | 0:8fdf9a60065b | 764 | \note IRQn must not be negative. |
kadonotakashi | 0:8fdf9a60065b | 765 | */ |
kadonotakashi | 0:8fdf9a60065b | 766 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 767 | { |
kadonotakashi | 0:8fdf9a60065b | 768 | if ((int32_t)(IRQn) >= 0) |
kadonotakashi | 0:8fdf9a60065b | 769 | { |
kadonotakashi | 0:8fdf9a60065b | 770 | return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kadonotakashi | 0:8fdf9a60065b | 771 | } |
kadonotakashi | 0:8fdf9a60065b | 772 | else |
kadonotakashi | 0:8fdf9a60065b | 773 | { |
kadonotakashi | 0:8fdf9a60065b | 774 | return(0U); |
kadonotakashi | 0:8fdf9a60065b | 775 | } |
kadonotakashi | 0:8fdf9a60065b | 776 | } |
kadonotakashi | 0:8fdf9a60065b | 777 | |
kadonotakashi | 0:8fdf9a60065b | 778 | |
kadonotakashi | 0:8fdf9a60065b | 779 | /** |
kadonotakashi | 0:8fdf9a60065b | 780 | \brief Disable Interrupt |
kadonotakashi | 0:8fdf9a60065b | 781 | \details Disables a device specific interrupt in the NVIC interrupt controller. |
kadonotakashi | 0:8fdf9a60065b | 782 | \param [in] IRQn Device specific interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 783 | \note IRQn must not be negative. |
kadonotakashi | 0:8fdf9a60065b | 784 | */ |
kadonotakashi | 0:8fdf9a60065b | 785 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 786 | { |
kadonotakashi | 0:8fdf9a60065b | 787 | if ((int32_t)(IRQn) >= 0) |
kadonotakashi | 0:8fdf9a60065b | 788 | { |
kadonotakashi | 0:8fdf9a60065b | 789 | NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kadonotakashi | 0:8fdf9a60065b | 790 | __DSB(); |
kadonotakashi | 0:8fdf9a60065b | 791 | __ISB(); |
kadonotakashi | 0:8fdf9a60065b | 792 | } |
kadonotakashi | 0:8fdf9a60065b | 793 | } |
kadonotakashi | 0:8fdf9a60065b | 794 | |
kadonotakashi | 0:8fdf9a60065b | 795 | |
kadonotakashi | 0:8fdf9a60065b | 796 | /** |
kadonotakashi | 0:8fdf9a60065b | 797 | \brief Get Pending Interrupt |
kadonotakashi | 0:8fdf9a60065b | 798 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
kadonotakashi | 0:8fdf9a60065b | 799 | \param [in] IRQn Device specific interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 800 | \return 0 Interrupt status is not pending. |
kadonotakashi | 0:8fdf9a60065b | 801 | \return 1 Interrupt status is pending. |
kadonotakashi | 0:8fdf9a60065b | 802 | \note IRQn must not be negative. |
kadonotakashi | 0:8fdf9a60065b | 803 | */ |
kadonotakashi | 0:8fdf9a60065b | 804 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 805 | { |
kadonotakashi | 0:8fdf9a60065b | 806 | if ((int32_t)(IRQn) >= 0) |
kadonotakashi | 0:8fdf9a60065b | 807 | { |
kadonotakashi | 0:8fdf9a60065b | 808 | return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kadonotakashi | 0:8fdf9a60065b | 809 | } |
kadonotakashi | 0:8fdf9a60065b | 810 | else |
kadonotakashi | 0:8fdf9a60065b | 811 | { |
kadonotakashi | 0:8fdf9a60065b | 812 | return(0U); |
kadonotakashi | 0:8fdf9a60065b | 813 | } |
kadonotakashi | 0:8fdf9a60065b | 814 | } |
kadonotakashi | 0:8fdf9a60065b | 815 | |
kadonotakashi | 0:8fdf9a60065b | 816 | |
kadonotakashi | 0:8fdf9a60065b | 817 | /** |
kadonotakashi | 0:8fdf9a60065b | 818 | \brief Set Pending Interrupt |
kadonotakashi | 0:8fdf9a60065b | 819 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
kadonotakashi | 0:8fdf9a60065b | 820 | \param [in] IRQn Device specific interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 821 | \note IRQn must not be negative. |
kadonotakashi | 0:8fdf9a60065b | 822 | */ |
kadonotakashi | 0:8fdf9a60065b | 823 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 824 | { |
kadonotakashi | 0:8fdf9a60065b | 825 | if ((int32_t)(IRQn) >= 0) |
kadonotakashi | 0:8fdf9a60065b | 826 | { |
kadonotakashi | 0:8fdf9a60065b | 827 | NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kadonotakashi | 0:8fdf9a60065b | 828 | } |
kadonotakashi | 0:8fdf9a60065b | 829 | } |
kadonotakashi | 0:8fdf9a60065b | 830 | |
kadonotakashi | 0:8fdf9a60065b | 831 | |
kadonotakashi | 0:8fdf9a60065b | 832 | /** |
kadonotakashi | 0:8fdf9a60065b | 833 | \brief Clear Pending Interrupt |
kadonotakashi | 0:8fdf9a60065b | 834 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
kadonotakashi | 0:8fdf9a60065b | 835 | \param [in] IRQn Device specific interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 836 | \note IRQn must not be negative. |
kadonotakashi | 0:8fdf9a60065b | 837 | */ |
kadonotakashi | 0:8fdf9a60065b | 838 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 839 | { |
kadonotakashi | 0:8fdf9a60065b | 840 | if ((int32_t)(IRQn) >= 0) |
kadonotakashi | 0:8fdf9a60065b | 841 | { |
kadonotakashi | 0:8fdf9a60065b | 842 | NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kadonotakashi | 0:8fdf9a60065b | 843 | } |
kadonotakashi | 0:8fdf9a60065b | 844 | } |
kadonotakashi | 0:8fdf9a60065b | 845 | |
kadonotakashi | 0:8fdf9a60065b | 846 | |
kadonotakashi | 0:8fdf9a60065b | 847 | /** |
kadonotakashi | 0:8fdf9a60065b | 848 | \brief Set Interrupt Priority |
kadonotakashi | 0:8fdf9a60065b | 849 | \details Sets the priority of a device specific interrupt or a processor exception. |
kadonotakashi | 0:8fdf9a60065b | 850 | The interrupt number can be positive to specify a device specific interrupt, |
kadonotakashi | 0:8fdf9a60065b | 851 | or negative to specify a processor exception. |
kadonotakashi | 0:8fdf9a60065b | 852 | \param [in] IRQn Interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 853 | \param [in] priority Priority to set. |
kadonotakashi | 0:8fdf9a60065b | 854 | \note The priority cannot be set for every processor exception. |
kadonotakashi | 0:8fdf9a60065b | 855 | */ |
kadonotakashi | 0:8fdf9a60065b | 856 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
kadonotakashi | 0:8fdf9a60065b | 857 | { |
kadonotakashi | 0:8fdf9a60065b | 858 | if ((int32_t)(IRQn) >= 0) |
kadonotakashi | 0:8fdf9a60065b | 859 | { |
kadonotakashi | 0:8fdf9a60065b | 860 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
kadonotakashi | 0:8fdf9a60065b | 861 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
kadonotakashi | 0:8fdf9a60065b | 862 | } |
kadonotakashi | 0:8fdf9a60065b | 863 | else |
kadonotakashi | 0:8fdf9a60065b | 864 | { |
kadonotakashi | 0:8fdf9a60065b | 865 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
kadonotakashi | 0:8fdf9a60065b | 866 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
kadonotakashi | 0:8fdf9a60065b | 867 | } |
kadonotakashi | 0:8fdf9a60065b | 868 | } |
kadonotakashi | 0:8fdf9a60065b | 869 | |
kadonotakashi | 0:8fdf9a60065b | 870 | |
kadonotakashi | 0:8fdf9a60065b | 871 | /** |
kadonotakashi | 0:8fdf9a60065b | 872 | \brief Get Interrupt Priority |
kadonotakashi | 0:8fdf9a60065b | 873 | \details Reads the priority of a device specific interrupt or a processor exception. |
kadonotakashi | 0:8fdf9a60065b | 874 | The interrupt number can be positive to specify a device specific interrupt, |
kadonotakashi | 0:8fdf9a60065b | 875 | or negative to specify a processor exception. |
kadonotakashi | 0:8fdf9a60065b | 876 | \param [in] IRQn Interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 877 | \return Interrupt Priority. |
kadonotakashi | 0:8fdf9a60065b | 878 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
kadonotakashi | 0:8fdf9a60065b | 879 | */ |
kadonotakashi | 0:8fdf9a60065b | 880 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 881 | { |
kadonotakashi | 0:8fdf9a60065b | 882 | |
kadonotakashi | 0:8fdf9a60065b | 883 | if ((int32_t)(IRQn) >= 0) |
kadonotakashi | 0:8fdf9a60065b | 884 | { |
kadonotakashi | 0:8fdf9a60065b | 885 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
kadonotakashi | 0:8fdf9a60065b | 886 | } |
kadonotakashi | 0:8fdf9a60065b | 887 | else |
kadonotakashi | 0:8fdf9a60065b | 888 | { |
kadonotakashi | 0:8fdf9a60065b | 889 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
kadonotakashi | 0:8fdf9a60065b | 890 | } |
kadonotakashi | 0:8fdf9a60065b | 891 | } |
kadonotakashi | 0:8fdf9a60065b | 892 | |
kadonotakashi | 0:8fdf9a60065b | 893 | |
kadonotakashi | 0:8fdf9a60065b | 894 | /** |
kadonotakashi | 0:8fdf9a60065b | 895 | \brief Set Interrupt Vector |
kadonotakashi | 0:8fdf9a60065b | 896 | \details Sets an interrupt vector in SRAM based interrupt vector table. |
kadonotakashi | 0:8fdf9a60065b | 897 | The interrupt number can be positive to specify a device specific interrupt, |
kadonotakashi | 0:8fdf9a60065b | 898 | or negative to specify a processor exception. |
kadonotakashi | 0:8fdf9a60065b | 899 | VTOR must been relocated to SRAM before. |
kadonotakashi | 0:8fdf9a60065b | 900 | \param [in] IRQn Interrupt number |
kadonotakashi | 0:8fdf9a60065b | 901 | \param [in] vector Address of interrupt handler function |
kadonotakashi | 0:8fdf9a60065b | 902 | */ |
kadonotakashi | 0:8fdf9a60065b | 903 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
kadonotakashi | 0:8fdf9a60065b | 904 | { |
kadonotakashi | 0:8fdf9a60065b | 905 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
kadonotakashi | 0:8fdf9a60065b | 906 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
kadonotakashi | 0:8fdf9a60065b | 907 | } |
kadonotakashi | 0:8fdf9a60065b | 908 | |
kadonotakashi | 0:8fdf9a60065b | 909 | |
kadonotakashi | 0:8fdf9a60065b | 910 | /** |
kadonotakashi | 0:8fdf9a60065b | 911 | \brief Get Interrupt Vector |
kadonotakashi | 0:8fdf9a60065b | 912 | \details Reads an interrupt vector from interrupt vector table. |
kadonotakashi | 0:8fdf9a60065b | 913 | The interrupt number can be positive to specify a device specific interrupt, |
kadonotakashi | 0:8fdf9a60065b | 914 | or negative to specify a processor exception. |
kadonotakashi | 0:8fdf9a60065b | 915 | \param [in] IRQn Interrupt number. |
kadonotakashi | 0:8fdf9a60065b | 916 | \return Address of interrupt handler function |
kadonotakashi | 0:8fdf9a60065b | 917 | */ |
kadonotakashi | 0:8fdf9a60065b | 918 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
kadonotakashi | 0:8fdf9a60065b | 919 | { |
kadonotakashi | 0:8fdf9a60065b | 920 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
kadonotakashi | 0:8fdf9a60065b | 921 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
kadonotakashi | 0:8fdf9a60065b | 922 | } |
kadonotakashi | 0:8fdf9a60065b | 923 | |
kadonotakashi | 0:8fdf9a60065b | 924 | |
kadonotakashi | 0:8fdf9a60065b | 925 | /** |
kadonotakashi | 0:8fdf9a60065b | 926 | \brief System Reset |
kadonotakashi | 0:8fdf9a60065b | 927 | \details Initiates a system reset request to reset the MCU. |
kadonotakashi | 0:8fdf9a60065b | 928 | */ |
kadonotakashi | 0:8fdf9a60065b | 929 | __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) |
kadonotakashi | 0:8fdf9a60065b | 930 | { |
kadonotakashi | 0:8fdf9a60065b | 931 | __DSB(); /* Ensure all outstanding memory accesses included |
kadonotakashi | 0:8fdf9a60065b | 932 | buffered write are completed before reset */ |
kadonotakashi | 0:8fdf9a60065b | 933 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
kadonotakashi | 0:8fdf9a60065b | 934 | SCB_AIRCR_SYSRESETREQ_Msk); |
kadonotakashi | 0:8fdf9a60065b | 935 | __DSB(); /* Ensure completion of memory access */ |
kadonotakashi | 0:8fdf9a60065b | 936 | |
kadonotakashi | 0:8fdf9a60065b | 937 | for(;;) /* wait until reset */ |
kadonotakashi | 0:8fdf9a60065b | 938 | { |
kadonotakashi | 0:8fdf9a60065b | 939 | __NOP(); |
kadonotakashi | 0:8fdf9a60065b | 940 | } |
kadonotakashi | 0:8fdf9a60065b | 941 | } |
kadonotakashi | 0:8fdf9a60065b | 942 | |
kadonotakashi | 0:8fdf9a60065b | 943 | /*@} end of CMSIS_Core_NVICFunctions */ |
kadonotakashi | 0:8fdf9a60065b | 944 | |
kadonotakashi | 0:8fdf9a60065b | 945 | |
kadonotakashi | 0:8fdf9a60065b | 946 | /* ########################## FPU functions #################################### */ |
kadonotakashi | 0:8fdf9a60065b | 947 | /** |
kadonotakashi | 0:8fdf9a60065b | 948 | \ingroup CMSIS_Core_FunctionInterface |
kadonotakashi | 0:8fdf9a60065b | 949 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
kadonotakashi | 0:8fdf9a60065b | 950 | \brief Function that provides FPU type. |
kadonotakashi | 0:8fdf9a60065b | 951 | @{ |
kadonotakashi | 0:8fdf9a60065b | 952 | */ |
kadonotakashi | 0:8fdf9a60065b | 953 | |
kadonotakashi | 0:8fdf9a60065b | 954 | /** |
kadonotakashi | 0:8fdf9a60065b | 955 | \brief get FPU type |
kadonotakashi | 0:8fdf9a60065b | 956 | \details returns the FPU type |
kadonotakashi | 0:8fdf9a60065b | 957 | \returns |
kadonotakashi | 0:8fdf9a60065b | 958 | - \b 0: No FPU |
kadonotakashi | 0:8fdf9a60065b | 959 | - \b 1: Single precision FPU |
kadonotakashi | 0:8fdf9a60065b | 960 | - \b 2: Double + Single precision FPU |
kadonotakashi | 0:8fdf9a60065b | 961 | */ |
kadonotakashi | 0:8fdf9a60065b | 962 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
kadonotakashi | 0:8fdf9a60065b | 963 | { |
kadonotakashi | 0:8fdf9a60065b | 964 | return 0U; /* No FPU */ |
kadonotakashi | 0:8fdf9a60065b | 965 | } |
kadonotakashi | 0:8fdf9a60065b | 966 | |
kadonotakashi | 0:8fdf9a60065b | 967 | |
kadonotakashi | 0:8fdf9a60065b | 968 | /*@} end of CMSIS_Core_FpuFunctions */ |
kadonotakashi | 0:8fdf9a60065b | 969 | |
kadonotakashi | 0:8fdf9a60065b | 970 | |
kadonotakashi | 0:8fdf9a60065b | 971 | |
kadonotakashi | 0:8fdf9a60065b | 972 | /* ################################## SysTick function ############################################ */ |
kadonotakashi | 0:8fdf9a60065b | 973 | /** |
kadonotakashi | 0:8fdf9a60065b | 974 | \ingroup CMSIS_Core_FunctionInterface |
kadonotakashi | 0:8fdf9a60065b | 975 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
kadonotakashi | 0:8fdf9a60065b | 976 | \brief Functions that configure the System. |
kadonotakashi | 0:8fdf9a60065b | 977 | @{ |
kadonotakashi | 0:8fdf9a60065b | 978 | */ |
kadonotakashi | 0:8fdf9a60065b | 979 | |
kadonotakashi | 0:8fdf9a60065b | 980 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
kadonotakashi | 0:8fdf9a60065b | 981 | |
kadonotakashi | 0:8fdf9a60065b | 982 | /** |
kadonotakashi | 0:8fdf9a60065b | 983 | \brief System Tick Configuration |
kadonotakashi | 0:8fdf9a60065b | 984 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
kadonotakashi | 0:8fdf9a60065b | 985 | Counter is in free running mode to generate periodic interrupts. |
kadonotakashi | 0:8fdf9a60065b | 986 | \param [in] ticks Number of ticks between two interrupts. |
kadonotakashi | 0:8fdf9a60065b | 987 | \return 0 Function succeeded. |
kadonotakashi | 0:8fdf9a60065b | 988 | \return 1 Function failed. |
kadonotakashi | 0:8fdf9a60065b | 989 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
kadonotakashi | 0:8fdf9a60065b | 990 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
kadonotakashi | 0:8fdf9a60065b | 991 | must contain a vendor-specific implementation of this function. |
kadonotakashi | 0:8fdf9a60065b | 992 | */ |
kadonotakashi | 0:8fdf9a60065b | 993 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
kadonotakashi | 0:8fdf9a60065b | 994 | { |
kadonotakashi | 0:8fdf9a60065b | 995 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
kadonotakashi | 0:8fdf9a60065b | 996 | { |
kadonotakashi | 0:8fdf9a60065b | 997 | return (1UL); /* Reload value impossible */ |
kadonotakashi | 0:8fdf9a60065b | 998 | } |
kadonotakashi | 0:8fdf9a60065b | 999 | |
kadonotakashi | 0:8fdf9a60065b | 1000 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
kadonotakashi | 0:8fdf9a60065b | 1001 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
kadonotakashi | 0:8fdf9a60065b | 1002 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
kadonotakashi | 0:8fdf9a60065b | 1003 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
kadonotakashi | 0:8fdf9a60065b | 1004 | SysTick_CTRL_TICKINT_Msk | |
kadonotakashi | 0:8fdf9a60065b | 1005 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
kadonotakashi | 0:8fdf9a60065b | 1006 | return (0UL); /* Function successful */ |
kadonotakashi | 0:8fdf9a60065b | 1007 | } |
kadonotakashi | 0:8fdf9a60065b | 1008 | |
kadonotakashi | 0:8fdf9a60065b | 1009 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1010 | |
kadonotakashi | 0:8fdf9a60065b | 1011 | /*@} end of CMSIS_Core_SysTickFunctions */ |
kadonotakashi | 0:8fdf9a60065b | 1012 | |
kadonotakashi | 0:8fdf9a60065b | 1013 | |
kadonotakashi | 0:8fdf9a60065b | 1014 | |
kadonotakashi | 0:8fdf9a60065b | 1015 | |
kadonotakashi | 0:8fdf9a60065b | 1016 | #ifdef __cplusplus |
kadonotakashi | 0:8fdf9a60065b | 1017 | } |
kadonotakashi | 0:8fdf9a60065b | 1018 | #endif |
kadonotakashi | 0:8fdf9a60065b | 1019 | |
kadonotakashi | 0:8fdf9a60065b | 1020 | #endif /* __CORE_SC000_H_DEPENDANT */ |
kadonotakashi | 0:8fdf9a60065b | 1021 | |
kadonotakashi | 0:8fdf9a60065b | 1022 | #endif /* __CMSIS_GENERIC */ |