takashi kadono / Mbed OS Nucleo_446

Color Oled(SSD1331) connect to STMicroelectronics Nucleo-F466

Dependencies:   ssd1331

mbed-os/drivers/QSPI.h@0:8fdf9a60065b, 2018-10-10 (annotated)

Committer:
kadonotakashi
Date:
Wed Oct 10 00:33:53 2018 +0000
Revision:
0:8fdf9a60065b
how to make mbed librry

Who changed what in which revision?

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kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2006-2018 ARM Limited
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 */
kadonotakashi 0:8fdf9a60065b 16 #ifndef MBED_QSPI_H
kadonotakashi 0:8fdf9a60065b 17 #define MBED_QSPI_H
kadonotakashi 0:8fdf9a60065b 18
kadonotakashi 0:8fdf9a60065b 19 #include "platform/platform.h"
kadonotakashi 0:8fdf9a60065b 20
kadonotakashi 0:8fdf9a60065b 21 #if defined (DEVICE_QSPI) || defined(DOXYGEN_ONLY)
kadonotakashi 0:8fdf9a60065b 22
kadonotakashi 0:8fdf9a60065b 23 #include "hal/qspi_api.h"
kadonotakashi 0:8fdf9a60065b 24 #include "platform/PlatformMutex.h"
kadonotakashi 0:8fdf9a60065b 25 #include "platform/SingletonPtr.h"
kadonotakashi 0:8fdf9a60065b 26 #include "platform/NonCopyable.h"
kadonotakashi 0:8fdf9a60065b 27
kadonotakashi 0:8fdf9a60065b 28 #define ONE_MHZ 1000000
kadonotakashi 0:8fdf9a60065b 29
kadonotakashi 0:8fdf9a60065b 30 namespace mbed {
kadonotakashi 0:8fdf9a60065b 31
kadonotakashi 0:8fdf9a60065b 32 /** \addtogroup drivers */
kadonotakashi 0:8fdf9a60065b 33
kadonotakashi 0:8fdf9a60065b 34 /** A QSPI Driver, used for communicating with QSPI slave devices
kadonotakashi 0:8fdf9a60065b 35 *
kadonotakashi 0:8fdf9a60065b 36 * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
kadonotakashi 0:8fdf9a60065b 37 * Most QSPI devices will also require Chip Select which is indicated by ssel.
kadonotakashi 0:8fdf9a60065b 38 *
kadonotakashi 0:8fdf9a60065b 39 * @note Synchronization level: Thread safe
kadonotakashi 0:8fdf9a60065b 40 *
kadonotakashi 0:8fdf9a60065b 41 * Example:
kadonotakashi 0:8fdf9a60065b 42 * @code
kadonotakashi 0:8fdf9a60065b 43 * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
kadonotakashi 0:8fdf9a60065b 44 *
kadonotakashi 0:8fdf9a60065b 45 * #include "mbed.h"
kadonotakashi 0:8fdf9a60065b 46 *
kadonotakashi 0:8fdf9a60065b 47 * #define CMD_WRITE 0x02
kadonotakashi 0:8fdf9a60065b 48 * #define CMD_READ 0x03
kadonotakashi 0:8fdf9a60065b 49 * #define ADDRESS 0x1000
kadonotakashi 0:8fdf9a60065b 50 *
kadonotakashi 0:8fdf9a60065b 51 * // hardware ssel (where applicable)
kadonotakashi 0:8fdf9a60065b 52 * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel
kadonotakashi 0:8fdf9a60065b 53 *
kadonotakashi 0:8fdf9a60065b 54 *
kadonotakashi 0:8fdf9a60065b 55 * int main() {
kadonotakashi 0:8fdf9a60065b 56 * char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
kadonotakashi 0:8fdf9a60065b 57 * char rx_buf[4];
kadonotakashi 0:8fdf9a60065b 58 * int buf_len = sizeof(tx_buf);
kadonotakashi 0:8fdf9a60065b 59 *
kadonotakashi 0:8fdf9a60065b 60 * qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
kadonotakashi 0:8fdf9a60065b 61 * if (result != QSPI_STATUS_OK) {
kadonotakashi 0:8fdf9a60065b 62 * printf("Write failed");
kadonotakashi 0:8fdf9a60065b 63 * }
kadonotakashi 0:8fdf9a60065b 64 * result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
kadonotakashi 0:8fdf9a60065b 65 * if (result != QSPI_STATUS_OK) {
kadonotakashi 0:8fdf9a60065b 66 * printf("Read failed");
kadonotakashi 0:8fdf9a60065b 67 * }
kadonotakashi 0:8fdf9a60065b 68 *
kadonotakashi 0:8fdf9a60065b 69 * }
kadonotakashi 0:8fdf9a60065b 70 * @endcode
kadonotakashi 0:8fdf9a60065b 71 * @ingroup drivers
kadonotakashi 0:8fdf9a60065b 72 */
kadonotakashi 0:8fdf9a60065b 73 class QSPI : private NonCopyable<QSPI> {
kadonotakashi 0:8fdf9a60065b 74
kadonotakashi 0:8fdf9a60065b 75 public:
kadonotakashi 0:8fdf9a60065b 76
kadonotakashi 0:8fdf9a60065b 77 /** Create a QSPI master connected to the specified pins
kadonotakashi 0:8fdf9a60065b 78 *
kadonotakashi 0:8fdf9a60065b 79 * io0-io3 is used to specify the Pins used for Quad SPI mode
kadonotakashi 0:8fdf9a60065b 80 *
kadonotakashi 0:8fdf9a60065b 81 * @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
kadonotakashi 0:8fdf9a60065b 82 * @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
kadonotakashi 0:8fdf9a60065b 83 * @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
kadonotakashi 0:8fdf9a60065b 84 * @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
kadonotakashi 0:8fdf9a60065b 85 * @param sclk QSPI Clock pin
kadonotakashi 0:8fdf9a60065b 86 * @param ssel QSPI chip select pin
kadonotakashi 0:8fdf9a60065b 87 * @param mode Mode specifies the SPI mode(Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
kadonotakashi 0:8fdf9a60065b 88 * default value = 0
kadonotakashi 0:8fdf9a60065b 89 *
kadonotakashi 0:8fdf9a60065b 90 */
kadonotakashi 0:8fdf9a60065b 91 QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
kadonotakashi 0:8fdf9a60065b 92
kadonotakashi 0:8fdf9a60065b 93 /** Configure the data transmission format
kadonotakashi 0:8fdf9a60065b 94 *
kadonotakashi 0:8fdf9a60065b 95 * @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
kadonotakashi 0:8fdf9a60065b 96 * @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
kadonotakashi 0:8fdf9a60065b 97 * @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
kadonotakashi 0:8fdf9a60065b 98 * @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
kadonotakashi 0:8fdf9a60065b 99 * @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
kadonotakashi 0:8fdf9a60065b 100 * @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
kadonotakashi 0:8fdf9a60065b 101 * @param dummy_cycles Number of dummy clock cycles to be used after alt phase
kadonotakashi 0:8fdf9a60065b 102 *
kadonotakashi 0:8fdf9a60065b 103 */
kadonotakashi 0:8fdf9a60065b 104 qspi_status_t configure_format(qspi_bus_width_t inst_width,
kadonotakashi 0:8fdf9a60065b 105 qspi_bus_width_t address_width,
kadonotakashi 0:8fdf9a60065b 106 qspi_address_size_t address_size,
kadonotakashi 0:8fdf9a60065b 107 qspi_bus_width_t alt_width,
kadonotakashi 0:8fdf9a60065b 108 qspi_alt_size_t alt_size,
kadonotakashi 0:8fdf9a60065b 109 qspi_bus_width_t data_width,
kadonotakashi 0:8fdf9a60065b 110 int dummy_cycles);
kadonotakashi 0:8fdf9a60065b 111
kadonotakashi 0:8fdf9a60065b 112 /** Set the qspi bus clock frequency
kadonotakashi 0:8fdf9a60065b 113 *
kadonotakashi 0:8fdf9a60065b 114 * @param hz SCLK frequency in hz (default = 1MHz)
kadonotakashi 0:8fdf9a60065b 115 * @returns
kadonotakashi 0:8fdf9a60065b 116 * Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
kadonotakashi 0:8fdf9a60065b 117 */
kadonotakashi 0:8fdf9a60065b 118 qspi_status_t set_frequency(int hz = ONE_MHZ);
kadonotakashi 0:8fdf9a60065b 119
kadonotakashi 0:8fdf9a60065b 120 /** Read from QSPI peripheral with the preset read_instruction and alt_value
kadonotakashi 0:8fdf9a60065b 121 *
kadonotakashi 0:8fdf9a60065b 122 * @param address Address to be accessed in QSPI peripheral
kadonotakashi 0:8fdf9a60065b 123 * @param rx_buffer Buffer for data to be read from the peripheral
kadonotakashi 0:8fdf9a60065b 124 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
kadonotakashi 0:8fdf9a60065b 125 *
kadonotakashi 0:8fdf9a60065b 126 * @returns
kadonotakashi 0:8fdf9a60065b 127 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kadonotakashi 0:8fdf9a60065b 128 */
kadonotakashi 0:8fdf9a60065b 129 qspi_status_t read(int address, char *rx_buffer, size_t *rx_length);
kadonotakashi 0:8fdf9a60065b 130
kadonotakashi 0:8fdf9a60065b 131 /** Write to QSPI peripheral using custom write instruction
kadonotakashi 0:8fdf9a60065b 132 *
kadonotakashi 0:8fdf9a60065b 133 * @param address Address to be accessed in QSPI peripheral
kadonotakashi 0:8fdf9a60065b 134 * @param tx_buffer Buffer containing data to be sent to peripheral
kadonotakashi 0:8fdf9a60065b 135 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
kadonotakashi 0:8fdf9a60065b 136 *
kadonotakashi 0:8fdf9a60065b 137 * @returns
kadonotakashi 0:8fdf9a60065b 138 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kadonotakashi 0:8fdf9a60065b 139 */
kadonotakashi 0:8fdf9a60065b 140 qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
kadonotakashi 0:8fdf9a60065b 141
kadonotakashi 0:8fdf9a60065b 142 /** Read from QSPI peripheral using custom read instruction, alt values
kadonotakashi 0:8fdf9a60065b 143 *
kadonotakashi 0:8fdf9a60065b 144 * @param instruction Instruction value to be used in instruction phase
kadonotakashi 0:8fdf9a60065b 145 * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
kadonotakashi 0:8fdf9a60065b 146 * @param address Address to be accessed in QSPI peripheral
kadonotakashi 0:8fdf9a60065b 147 * @param rx_buffer Buffer for data to be read from the peripheral
kadonotakashi 0:8fdf9a60065b 148 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
kadonotakashi 0:8fdf9a60065b 149 *
kadonotakashi 0:8fdf9a60065b 150 * @returns
kadonotakashi 0:8fdf9a60065b 151 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kadonotakashi 0:8fdf9a60065b 152 */
kadonotakashi 0:8fdf9a60065b 153 qspi_status_t read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
kadonotakashi 0:8fdf9a60065b 154
kadonotakashi 0:8fdf9a60065b 155 /** Write to QSPI peripheral using custom write instruction, alt values
kadonotakashi 0:8fdf9a60065b 156 *
kadonotakashi 0:8fdf9a60065b 157 * @param instruction Instruction value to be used in instruction phase
kadonotakashi 0:8fdf9a60065b 158 * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
kadonotakashi 0:8fdf9a60065b 159 * @param address Address to be accessed in QSPI peripheral
kadonotakashi 0:8fdf9a60065b 160 * @param tx_buffer Buffer containing data to be sent to peripheral
kadonotakashi 0:8fdf9a60065b 161 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
kadonotakashi 0:8fdf9a60065b 162 *
kadonotakashi 0:8fdf9a60065b 163 * @returns
kadonotakashi 0:8fdf9a60065b 164 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kadonotakashi 0:8fdf9a60065b 165 */
kadonotakashi 0:8fdf9a60065b 166 qspi_status_t write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
kadonotakashi 0:8fdf9a60065b 167
kadonotakashi 0:8fdf9a60065b 168 /** Perform a transaction to write to an address(a control register) and get the status results
kadonotakashi 0:8fdf9a60065b 169 *
kadonotakashi 0:8fdf9a60065b 170 * @param instruction Instruction value to be used in instruction phase
kadonotakashi 0:8fdf9a60065b 171 * @param address Some instruction might require address. Use -1 if no address
kadonotakashi 0:8fdf9a60065b 172 * @param tx_buffer Buffer containing data to be sent to peripheral
kadonotakashi 0:8fdf9a60065b 173 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
kadonotakashi 0:8fdf9a60065b 174 * @param rx_buffer Buffer for data to be read from the peripheral
kadonotakashi 0:8fdf9a60065b 175 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
kadonotakashi 0:8fdf9a60065b 176 *
kadonotakashi 0:8fdf9a60065b 177 * @returns
kadonotakashi 0:8fdf9a60065b 178 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kadonotakashi 0:8fdf9a60065b 179 */
kadonotakashi 0:8fdf9a60065b 180 qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
kadonotakashi 0:8fdf9a60065b 181
kadonotakashi 0:8fdf9a60065b 182 protected:
kadonotakashi 0:8fdf9a60065b 183 /** Acquire exclusive access to this SPI bus
kadonotakashi 0:8fdf9a60065b 184 */
kadonotakashi 0:8fdf9a60065b 185 virtual void lock(void);
kadonotakashi 0:8fdf9a60065b 186
kadonotakashi 0:8fdf9a60065b 187 /** Release exclusive access to this SPI bus
kadonotakashi 0:8fdf9a60065b 188 */
kadonotakashi 0:8fdf9a60065b 189 virtual void unlock(void);
kadonotakashi 0:8fdf9a60065b 190
kadonotakashi 0:8fdf9a60065b 191 public:
kadonotakashi 0:8fdf9a60065b 192 virtual ~QSPI()
kadonotakashi 0:8fdf9a60065b 193 {
kadonotakashi 0:8fdf9a60065b 194 }
kadonotakashi 0:8fdf9a60065b 195
kadonotakashi 0:8fdf9a60065b 196 protected:
kadonotakashi 0:8fdf9a60065b 197 qspi_t _qspi;
kadonotakashi 0:8fdf9a60065b 198
kadonotakashi 0:8fdf9a60065b 199 bool acquire(void);
kadonotakashi 0:8fdf9a60065b 200 static QSPI *_owner;
kadonotakashi 0:8fdf9a60065b 201 static SingletonPtr<PlatformMutex> _mutex;
kadonotakashi 0:8fdf9a60065b 202 qspi_bus_width_t _inst_width; //Bus width for Instruction phase
kadonotakashi 0:8fdf9a60065b 203 qspi_bus_width_t _address_width; //Bus width for Address phase
kadonotakashi 0:8fdf9a60065b 204 qspi_address_size_t _address_size;
kadonotakashi 0:8fdf9a60065b 205 qspi_bus_width_t _alt_width; //Bus width for Alt phase
kadonotakashi 0:8fdf9a60065b 206 qspi_alt_size_t _alt_size;
kadonotakashi 0:8fdf9a60065b 207 qspi_bus_width_t _data_width; //Bus width for Data phase
kadonotakashi 0:8fdf9a60065b 208 qspi_command_t _qspi_command; //QSPI Hal command struct
kadonotakashi 0:8fdf9a60065b 209 unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
kadonotakashi 0:8fdf9a60065b 210 int _hz; //Bus Frequency
kadonotakashi 0:8fdf9a60065b 211 int _mode; //SPI mode
kadonotakashi 0:8fdf9a60065b 212 bool _initialized;
kadonotakashi 0:8fdf9a60065b 213 PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
kadonotakashi 0:8fdf9a60065b 214
kadonotakashi 0:8fdf9a60065b 215 private:
kadonotakashi 0:8fdf9a60065b 216 /* Private acquire function without locking/unlocking
kadonotakashi 0:8fdf9a60065b 217 * Implemented in order to avoid duplicate locking and boost performance
kadonotakashi 0:8fdf9a60065b 218 */
kadonotakashi 0:8fdf9a60065b 219 bool _acquire(void);
kadonotakashi 0:8fdf9a60065b 220 bool _initialize();
kadonotakashi 0:8fdf9a60065b 221
kadonotakashi 0:8fdf9a60065b 222 /*
kadonotakashi 0:8fdf9a60065b 223 * This function builds the qspi command struct to be send to Hal
kadonotakashi 0:8fdf9a60065b 224 */
kadonotakashi 0:8fdf9a60065b 225 inline void _build_qspi_command(int instruction, int address, int alt);
kadonotakashi 0:8fdf9a60065b 226 };
kadonotakashi 0:8fdf9a60065b 227
kadonotakashi 0:8fdf9a60065b 228 } // namespace mbed
kadonotakashi 0:8fdf9a60065b 229
kadonotakashi 0:8fdf9a60065b 230 #endif
kadonotakashi 0:8fdf9a60065b 231
kadonotakashi 0:8fdf9a60065b 232 #endif